Memory array and manufacturing method thereof, memory, electronic device and read-write method

Abstract

The embodiment of the application belongs to the technical field of storage devices, and particularly relates to a storage array and a manufacturing method thereof, a memory, an electronic device and a read-write method. The embodiment of the application aims to solve the problem of slow data reading of the storage array. The storage array, the manufacturing method thereof and the read-write method provided by the embodiment of the application, the device layer comprises first electrode layers, first isolation layers and electrode plates which are arranged in a stack, and the first electrode layers are electrically connected. When data is read, the first electrode layers and the gate columns can be powered, so that the gate columns and each storage transistor formed by each device layer are in a state of readable data. At this time, the data in the storage transistor corresponding to the electrode plate can be read through the electrode plate, without making the gate columns and each storage transistor formed by each device layer in an open state, so that the data reading speed is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of storage device, in particular to a storage array and a manufacturing method thereof, a memory, an electronic device and a read-write method. BACKGROUND

[0002] With the gradual development of storage device technology, the storage array has been gradually widely applied due to its high storage capacity. In the related art, the storage array includes a substrate and a storage string arranged on the substrate, the storage string includes a plurality of storage transistors arranged in sequence along a direction perpendicular to the substrate, the plurality of storage transistors are connected in series, and each storage transistor is used for data storage. However, the plurality of transistors in the storage string are connected in series, and when data is read, all the transistors in the storage string need to be in a conducting state, which results in slow data reading. SUMMARY

[0003] Embodiments of the present application provide a storage array and a manufacturing method thereof, a memory, an electronic device and a read-write method, to solve the problem of slow data reading of the storage array.

[0004] In a first aspect, the embodiments of the present application provide a storage array, including a substrate and a stacked structure arranged on the substrate, the stacked structure including a plurality of device layers stacked, each device layer including a first electrode layer, a first isolation layer and a second electrode layer stacked, the first isolation layer being arranged between the first electrode layer and the second electrode layer; the first electrode layers in each device layer are electrically connected.

[0005] The stacked structure further includes a gate column, the stacked structure is provided with a through hole, the through hole penetrates each stacked structure, and the gate column is arranged in the through hole. The first electrode layer in each device layer serves as a first electrode of a storage transistor, the electrode plate in the device layer serves as a second electrode of the corresponding storage transistor, and the gate column serves as a gate of the corresponding storage transistor. The storage transistor is used for data storage.

[0006] Through the above arrangement, the first electrode layers are electrically connected, so that the gate column and the storage transistors formed by each device layer are connected in parallel. When data is read, power can be supplied to the first electrode layer and the gate column, so that each storage transistor formed by the gate column and each device layer is in a state that can read data. At this time, the data in the storage transistor corresponding to the second electrode layer can be read through the second electrode layer, without the need to make each storage transistor formed by the gate column and each device layer in an open state, thereby improving the data reading speed.

[0007] In some embodiments that can include the above-mentioned embodiments, each device layer further comprises a dielectric layer and a channel layer, and the through hole comprises a sub-through hole penetrating each device layer. The dielectric layer is arranged on the gate pillar corresponding to the sub-through hole, and the channel layer covers the hole wall of the sub-through hole, and the channel layer is in contact with the dielectric layer, the first electrode layer and the second electrode layer. Through the above arrangement, the dielectric layer can store electrons, and when the dielectric layer stores electrons, a smaller voltage applied to the gate pillar and the first electrode layer can make the storage transistor in an open state, at which time a larger current can be detected; when the dielectric layer does not store electrons, a smaller current is obtained when a smaller voltage is applied to the gate pillar and the first electrode layer, and the data reading can be realized by analyzing the current, which is simple in structure and easy to manufacture.

[0008] In some embodiments that can include the above-mentioned embodiments, the dielectric layer covers the entire gate pillar corresponding to the sub-through hole, that is, the dielectric layer is tubular. Such an arrangement can increase the area of the dielectric layer, thereby improving the ability of the dielectric layer to store electrons.

[0009] In some embodiments that can include the above-mentioned embodiments, the channel layer covers the entire hole wall of the through hole, that is, the channel layer is continuously arranged along the hole wall of the through hole, and the channel layer covers the entire hole wall of the through hole (the channel layer is tubular). Such an arrangement can increase the contact area between the channel layer and the first electrode layer, the second electrode layer and the dielectric layer, that is, increase the area of the conductive channel formed by the channel layer and the dielectric layer, so as to improve the opening voltage of the storage transistor, thereby improving the performance of the storage array.

[0010] In some embodiments that can include the above-mentioned embodiments, each device layer further comprises a dielectric layer and a channel layer, and the through hole comprises a sub-through hole penetrating each device layer, and the dielectric layer is arranged on the gate pillar corresponding to the hole wall of the sub-through hole; the first isolation layer has a gap between the hole wall of the sub-through hole, the gap is in communication with the sub-through hole, and the channel layer comprises a first channel layer arranged in the gap, and the first channel layer is in contact with the dielectric layer, the first electrode layer and the second electrode layer.

[0011] Such an arrangement can avoid the conductive channel occupying the space in the through hole, thereby increasing the area of the dielectric layer and improving the electron storage capacity of the dielectric layer.

[0012] In some embodiments that can include the above-mentioned embodiments, the channel layer further comprises a second channel layer arranged on the surface of the first isolation layer facing the second electrode layer, and the second channel layer is in contact with the first channel layer. Such an arrangement can increase the contact area between the channel layer and the second electrode layer, thereby reducing the resistance between the channel layer and the second electrode layer.

[0013] In some embodiments which can comprise the above-mentioned embodiments, the channel layer further comprises a third channel layer disposed on the surface of the first isolation layer facing the first electrode layer, and the third channel layer is in contact with the first channel layer. In this way, the contact area between the channel layer and the first electrode layer can be increased, thereby reducing the resistance between the channel layer and the first electrode layer.

[0014] In some embodiments which can comprise the above-mentioned embodiments, each device layer further comprises a dielectric layer and a channel layer, the through hole comprises a sub-through hole penetrating each device layer; the first isolation layer has a gap between the hole wall of the sub-through hole, the gap is in communication with the through hole, and the extension is disposed on the gate pillar and is disposed in the gap. The extension can be of the same material as the gate pillar, so that the extension and the gate pillar can form an integral structure to reduce the resistance between the extension and the gate pillar.

[0015] The dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is disposed on the gate pillar corresponding to the hole wall of the sub-through hole, and the second dielectric layer is wrapped on the extension. The first dielectric layer and the second dielectric layer are in contact.

[0016] The channel layer comprises a first channel layer and a second channel layer, the first channel layer is disposed between the hole wall of the sub-through hole and the first dielectric layer, and the second channel layer is disposed between the second dielectric layer and the side wall of the gap. The first channel layer and the second channel layer are in contact. In this way, while the first dielectric layer and the first channel layer in the sub-through hole form a conductive channel, the second dielectric layer and the second channel layer in the gap also form a conductive channel, so that the area of the conductive channel can be increased, thereby increasing the opening voltage of the storage transistor to improve the performance of the storage array.

[0017] In some embodiments which can comprise the above-mentioned embodiments, the dielectric layers in adjacent device layers are in contact, that is, the dielectric layers are continuously disposed in a direction parallel to the center line of the gate pillar. In this way, the area of the dielectric layer can be increased, thereby improving the storage capacity of the electrons.

[0018] In some embodiments which can comprise the above-mentioned embodiments, the stack structure further comprises a second isolation layer, and the second isolation layer is a plurality of layers, one second isolation layer is disposed between adjacent device layers in a stacked manner. The second isolation layer can achieve isolation between adjacent device layers.

[0019] In some embodiments which can comprise the above-mentioned embodiments, the second isolation layer is in contact with the dielectric layer, that is, the channel layers on adjacent sub-through holes are isolated by the second isolation layer to avoid mutual influence of the channel layers on adjacent sub-through holes.

[0020] In some embodiments which can include the above-mentioned embodiments, the second electrode layer includes a plurality of second electrode lines arranged at intervals along a direction parallel to the substrate; the through hole penetrates one of the second electrode lines; the stack structure further includes a connection hole penetrating each device layer, a projection of the connection hole on the substrate is located between projections of two adjacent second electrode lines on the substrate in the same device layer; and the connection hole is filled with a conductor, and the conductor is in contact with each first electrode layer. In this way, the electrical connection between each first electrode line corresponding to a storage string can be realized through the conductor, and the structure is simple and easy to manufacture.

[0021] In a second aspect, the embodiments of the present application provide a storage array, including a storage string, a first electrode line and a plurality of second electrode lines. The storage string includes a plurality of storage transistors, and the gates of the storage transistors are electrically connected. The first electrode line is electrically connected to the first electrodes of the storage transistors in the storage string. One of the second electrode lines is electrically connected to the second electrode of one of the storage transistors in the storage string, and data can be written into or read from the corresponding storage transistor through the second electrode line.

[0022] The storage array provided by the embodiments can supply power to the first electrode line and the gates of the storage transistors in the storage string when reading data, so that each of the storage transistors in the storage string is in a state in which data can be read. Thus, the data in the storage transistor corresponding to the second electrode line can be read through the second electrode line without turning on each of the storage transistors in the storage string, thereby improving the data reading speed.

[0023] In a third aspect, the embodiments of the present application provide a storage device, including the storage array in the above-mentioned embodiments and a controller, and the controller is electrically connected to the storage array.

[0024] The storage device provided by the embodiments includes a stack structure in the storage array, and the stack structure includes a plurality of device layers arranged in layers. Each of the device layers includes a first electrode layer, a first isolation layer and a second electrode layer arranged in layers, and the first isolation layer is arranged between the first electrode layer and the second electrode layer. Each of the first electrode layers in the device layers is electrically connected. The stack structure further includes a gate column, and the stack structure is provided with a through hole penetrating the stack structure. The gate column is arranged in the through hole. The first electrode layer in each of the device layers serves as a first electrode of a storage transistor, the second electrode layer in the device layer serves as a second electrode of the corresponding storage transistor, and the gate column serves as a gate of the corresponding storage transistor. The storage transistor is used for storing data.

[0025] Through the above arrangement, each first electrode layer is electrically connected, so that the gate column is in parallel with the storage transistors formed by each device layer. During data reading, the first electrode layer and the gate column can be supplied with power, so that each storage transistor formed by the gate column and each device layer is in a state of readable data. At this time, the data in the storage transistor corresponding to the second electrode layer can be read through the second electrode layer, without the need to make each storage transistor formed by the gate column and each device layer in an open state, thereby improving the data reading speed.

[0026] In a fourth aspect, an electronic device is provided, which includes the memory in the above embodiments and a circuit board, and the memory is arranged on the circuit board.

[0027] The electronic device provided by the embodiment includes a stacked structure in a memory array, the stacked structure includes a plurality of device layers arranged in layers, each device layer includes a first electrode layer, a first isolation layer and a second electrode layer arranged in layers, and the first isolation layer is arranged between the first electrode layer and the second electrode layer; and the first electrode layers in each device layer are electrically connected. The stacked structure further includes a gate column, and a through hole is arranged on the stacked structure, the through hole penetrates through each stacked structure, and the gate column is arranged in the through hole. The first electrode layer in each device layer serves as a first electrode of a storage transistor, the second electrode layer in the device layer serves as a second electrode of the corresponding storage transistor, and the gate column serves as a gate of the corresponding storage transistor, and the storage transistor is used for storing data.

[0028] Through the above arrangement, each first electrode layer is electrically connected, so that the gate column is in parallel with the storage transistors formed by each device layer. During data reading, the first electrode layer and the gate column can be supplied with power, so that each storage transistor formed by the gate column and each device layer is in a state of readable data. At this time, the data in the storage transistor corresponding to the second electrode layer can be read through the second electrode layer, without the need to make each storage transistor formed by the gate column and each device layer in an open state, thereby improving the data reading speed.

[0029] In a fifth aspect, the embodiment of the present application further provides a read-write method for a memory array, the memory array includes a memory string, the memory string includes a plurality of storage transistors, and reading data in the storage transistor includes: applying a first voltage to the gate of each storage transistor in the memory string and the first electrode of each storage transistor; obtaining the current of the second electrode of the storage transistor; and obtaining the data stored in the storage transistor through the current.

[0030] The read-write method provided in the embodiment can apply a first voltage to the gate of each storage transistor and the first electrode of each storage transistor in the storage string before reading data, and each storage transistor in the storage string is in parallel; at this time, each storage transistor in the storage string can be in a state in which data can be read, and the data stored in the storage transistor can be read through the second electrode corresponding to the storage transistor, without the need to make each storage transistor in the storage string in an open state, thereby improving the data reading speed.

[0031] In some embodiments that can include the above-described embodiments, the writing data in the storage transistor includes:

[0032] applying a second voltage to the gate of each storage transistor in the storage string and the second electrode of the storage transistor to be written with data, so that the storage transistor to be written with data is in an open state, to write first data in the storage transistor to be written with data;

[0033] Alternatively, a third voltage smaller than the second voltage is applied to the gate of each storage transistor in the storage string and the second electrode of the storage transistor to be written with data, to write second data in the storage transistor to be written with data.

[0034] The read-write method provided in the embodiment can apply a voltage to the gate of each storage transistor in the storage string when writing data, and each storage transistor in the storage string is in parallel; at this time, data can be written in the storage transistor through the second electrode corresponding to the storage transistor, without the need to make each storage transistor in the storage string in an open state, thereby improving the data writing speed.

[0035] In a sixth aspect, the embodiments of the present application further provide a storage array manufacturing method, including:

[0036] providing a substrate;

[0037] forming a stack structure on the substrate; the stack structure includes a plurality of device layers stacked, each device layer including a first intermediate layer, a first isolation layer and a second intermediate layer stacked, and the first isolation layer is located between the first intermediate layer and the second intermediate layer; the second intermediate layer is provided with a first opening penetrating therethrough, and the first opening is filled with an electrode plate;

[0038] forming a through hole on the stack structure, the through hole penetrating through each stack structure, and the projection of the through hole on the substrate is located within the projection of the electrode plate on the substrate;

[0039] forming a gate column in the through hole;

[0040] The first electrode layer in each device layer is used as a first electrode of a storage transistor, the electrode plate in the device layer is used as a second electrode of the corresponding storage transistor, and the gate pillar is used as a gate electrode of the corresponding storage transistor; and each first electrode layer is electrically connected.

[0041] The storage array is manufactured by the manufacturing method of the storage array in the above embodiment. The stack structure includes a plurality of device layers stacked. Each device layer includes a first electrode layer, a first isolation layer, and an electrode plate stacked. The first isolation layer is between the first electrode layer and the electrode plate. Each first electrode layer is electrically connected. The stack structure is provided with a through hole penetrating each second electrode layer and each first electrode layer. A gate pillar is arranged in the through hole. The first electrode layer in each device layer is used as a first electrode of a storage transistor, the electrode plate in the device layer is used as a second electrode of the corresponding storage transistor, and the gate pillar is used as a gate electrode of the corresponding storage transistor. Since each first electrode layer is electrically connected, the gate pillar is in parallel connection with the storage transistors formed by each device layer. When data is read, the first electrode layer and the gate pillar can be powered, so that each storage transistor formed by each device layer is in a state in which data can be read. At this time, the data in the storage transistor corresponding to the electrode plate can be read through the electrode plate, without the need to make each storage transistor formed by each device layer in an open state, thereby improving the data reading speed.

[0042] In some embodiments that can include the above embodiments, before the gate pillar is formed in the through hole, the method further includes: sequentially forming a channel layer and a dielectric layer on the hole wall of the through hole; the channel layer covers the entire hole wall of the through hole, and the dielectric layer covers the entire channel layer. In this way, the area of the dielectric layer can be increased, thereby improving the ability of the dielectric layer to store electrons. In addition, the area of the conductive channel is also increased, thereby improving the opening voltage of the storage transistor and improving the performance of the storage array.

[0043] In some embodiments that can include the above embodiments, forming the stack structure on the substrate further includes: forming an intermediate isolation layer between adjacent device layers; and after the gate pillar is formed, the method further includes: removing the intermediate isolation layer and the channel layer corresponding to the intermediate isolation layer to form a first void layer, and forming a second isolation layer in the first void layer. In this way, the second isolation layer not only isolates adjacent device layers, but also isolates the channel layer in adjacent device layers.

[0044] In some embodiments that can include the above embodiments, before forming the gate pillar in the through hole, further comprising: forming a dielectric layer on the hole wall of the through hole, the dielectric layer covering the entire hole wall of the through hole; after forming the gate pillar in the through hole, further comprising: forming a connection hole on the stack structure, the connection hole penetrating through each device layer; and removing the first isolation layer through the connection hole to form a second void layer; forming a channel layer on the sidewall of the second void layer, the channel layer covering the corresponding dielectric layer, the electrode plate and the first intermediate layer of the second void layer; forming a third isolation layer in the second void layer.

[0045] In this way, after the first electrode layer is formed, the contact area between the channel layer and the electrode plate, and between the channel layer and the first electrode layer can be increased, thereby reducing the resistance between the channel layer and the electrode plate, and between the channel layer and the first electrode layer. In addition, the channel layer is arranged in the second void layer, which can avoid the channel layer occupying the space of the through hole, increase the area of the dielectric layer in the through hole, and further improve the ability of the dielectric layer to store electrons.

[0046] In some embodiments that can include the above embodiments, before forming the gate pillar in the through hole, further comprising: removing part of the first isolation layer through the through hole to form a gap; forming a first channel layer on the hole wall of the through hole and a second channel layer on the sidewall of the gap, the second channel layer being in contact with the first channel layer; forming a first dielectric layer on the first channel layer and a second dielectric layer on the second channel layer, the first dielectric layer being in contact with the second dielectric layer; forming the gate pillar in the through hole includes: filling the through hole and the gap with a conductive material to form an extension located in the gap and a gate pillar located in the through hole, and the extension being in contact with the gate pillar.

[0047] Through the above arrangement, while the first dielectric layer and the first channel layer in the through hole form a conductive channel, the second dielectric layer and the second channel layer in the gap also form a conductive channel, which can increase the area of the conductive channel and further increase the opening voltage of the storage transistor to improve the performance of the storage array.

[0048] In some embodiments that can include the above embodiments, forming the stack structure on the substrate further comprises: forming a second opening through the first intermediate layer, and filling the second opening with a source plate, and in the same device layer, the projection of the source plate on the substrate completely overlaps the projection of the electrode plate on the substrate. In this way, the through hole penetrates the source plate and the electrode plate whose projections overlap, and the gate pillar and the source plate and the electrode plate form a storage transistor.

[0049] In some embodiments that may include the above embodiments, the first intermediate layer is replaced with a first electrode layer, and the electrical connection of each first electrode layer includes: forming a connecting hole to form a through-stacking structure; removing the first intermediate layer through the connecting hole to form a third void layer; filling the connecting hole and the third void layer with conductive material to form a first electrode layer; and a conductor connecting each first electrode layer. Electrical connection between adjacent first electrode layers can be achieved through the conductor, resulting in a simple structure that is easy to manufacture.

[0050] In some embodiments that may include the above embodiments, after forming the gate pillar in the through-hole, the method further includes: forming a conductive connector in the second intermediate layer, the conductive connector contacting the electrode plate to form a second electrode line. Attached Figure Description

[0051] Figure 1 This is a schematic diagram illustrating the connections between storage transistors in a storage string in related technologies;

[0052] Figure 2 A schematic diagram of the structure of the storage array provided in the embodiments of this application. Figure 1 ;

[0053] Figure 3 A schematic diagram of the structure of the storage array provided in the embodiments of this application. Figure 2 ;

[0054] Figure 4 for Figure 2 A magnified view of a section at point A in the middle;

[0055] Figure 5 A schematic diagram of the structure of the storage array provided in the embodiments of this application. Figure 3 ;

[0056] Figure 6 for Figure 5 A magnified view of a section at point B in the middle;

[0057] Figure 7 A schematic diagram of the structure of the storage array provided in the embodiments of this application. Figure 4 ;

[0058] Figure 8 for Figure 7 A magnified view of a section at point C;

[0059] Figure 9 A flowchart illustrating a method for fabricating a storage array as provided in an embodiment of this application;

[0060] Figure 10 This is a schematic diagram of the structure after the stacked structure is formed in the storage array fabrication method provided in the embodiments of this application;

[0061] Figure 11A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the first process hole;

[0062] Figure 12 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after filling the first insulating block in the first process hole;

[0063] Figure 13 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the through hole;

[0064] Figure 14 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the first opening;

[0065] Figure 15 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the through hole;

[0066] Figure 16 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the gate column;

[0067] Figure 17 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the connecting hole;

[0068] Figure 18 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the third void layer;

[0069] Figure 19 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the first electrode layer and the conductor;

[0070] Figure 20 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the first void layer;

[0071] Figure 21 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the second isolation layer;

[0072] Figure 22 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the second process hole;

[0073] Figure 23 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after forming the conductive connecting body;

[0074] Figure 24 A structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after removing the first insulating block;

[0075] Figure 25 This is a schematic diagram of the structure after forming a conductive interconnect using a first process hole in the storage array fabrication method provided in the embodiments of this application.

[0076] Figure 26 This is a schematic diagram of the structure after the first void layer is formed using the first process hole in the storage array fabrication method provided in the embodiment of this application.

[0077] Figure 27 This is a schematic diagram of the structure after the second isolation layer is formed using the first process hole in the storage array fabrication method provided in the embodiment of this application;

[0078] Figure 28 for Figure 15 Sectional view along the middle AA direction;

[0079] Figure 29 This is a schematic diagram of the structure after the gate pillars are formed in the memory array fabrication method provided in the embodiments of this application;

[0080] Figure 30 This is a schematic diagram of the structure after removing the first isolation layer using a connection hole in the storage array fabrication method provided in the embodiments of this application;

[0081] Figure 31 This is a schematic diagram of the structure after the third isolation layer is formed in the storage array fabrication method provided in the embodiments of this application;

[0082] Figure 32 A schematic diagram of the structure after the formation of the first electrode layer and the conductor in the storage array fabrication method provided in the embodiments of this application;

[0083] Figure 33 This is a schematic diagram of the structure after gaps are formed using through holes in the storage array fabrication method provided in the embodiments of this application;

[0084] Figure 34 This is a schematic diagram of the structure after the channel layer is formed in the storage array fabrication method provided in the embodiments of this application;

[0085] Figure 35 This is a schematic diagram of the structure after the dielectric layer is formed in the storage array fabrication method provided in the embodiments of this application;

[0086] Figure 36 This is a schematic diagram of the structure after the gate pillars are formed in the memory array fabrication method provided in the embodiments of this application;

[0087] Figure 37 A circuit diagram of a storage array provided in an embodiment of this application;

[0088] Figure 38 A flowchart illustrating the read / write method provided in an embodiment of this application.

[0089] Explanation of reference numerals: 10: substrate; 20: stacked structure; 201: device layer; 202: second electrode layer; 203: first isolation layer; 204: first electrode layer; 205: through hole; 206: second isolation layer; 207: dielectric layer; 208: channel layer; 209: gate pillar; 210: third isolation layer; 2021: second electrode line; 2022: electrode plate; 2023: conductive connecting body; 2024: first isolation block; 2031: gap; 2032: gap; 2041: connecting hole; 2042: conductor; 2043: source plate; 2044: second isolation block; 2051: sub-through hole; 2071: first dielectric layer; 2072: second dielectric layer; 2081: first channel layer; 2082: second channel layer; 2083: third channel layer; 2091: extension; 301: first intermediate layer; 302: second intermediate layer; 303: intermediate isolation layer; 304: first process hole; 305: first insulating block; 306: through hole; 307: second process hole; 308: second gap layer; 3011: third gap layer; 3021: first opening; 3031: first gap layer; 3071: second insulating block. DETAILED DESCRIPTION

[0090] Figure 1 For a schematic diagram of connections between each storage transistor in a storage string in the related art, please refer to Figure 1 , a storage array (NAND flash memory) includes a storage string, the storage string includes a plurality of storage transistors 101 arranged in sequence, each storage transistor 101 is used for data storage. The plurality of storage transistors 101 are connected in series, so that Figure 1The shown orientation is an example, from bottom to top, the drain of the first storage transistor 101 is connected with the source line (SL) through the ground select transistor 102, the source of the first storage transistor 101 is connected with the drain of the second storage transistor 101, the source of the second storage transistor 101 is connected with the drain of the third storage transistor 101, and so on; the source of the storage transistor 101 at the top end is connected with the word line (BL1) through the BL select transistor 103, and the gate of each storage transistor 101 is connected with a gate line (WL). When reading the data in any storage transistor 101, all the storage transistors 101 in the storage string need to be in the on state, and then the data is read through the corresponding gate line (WL) of the storage transistor 101. Since the conductive channel in the storage transistor 101 is generally composed of semiconductor materials such as polysilicon and oxide semiconductor, the mobility of the conductive channel is low, and the transmission current is small, which leads to a long time required to turn on all the storage transistors 101 in the storage string, and further leads to slow reading of the data in the storage array.

[0091] To this end, the embodiment of the present application provides a storage array and a manufacturing method thereof, a memory, an electronic device and a read-write method. The substrate of the storage array is provided with a stack structure, the stack structure includes a plurality of device layers stacked, each device layer includes a first electrode layer, a first isolation layer and a second electrode layer stacked, each first electrode layer is electrically connected, the stack structure is provided with a through hole, the first electrode layer in each device layer serves as a first electrode of a storage transistor, the second electrode layer in the device layer serves as a second electrode of the corresponding storage transistor, and the gate pillar serves as a gate of the corresponding storage transistor. That is, the storage transistor includes a gate pillar, a first electrode layer in a device layer and a second electrode layer in the device layer; among the storage transistors formed by the gate pillar and each device layer, each first electrode layer is electrically connected, and the gate pillar serves as the gate of each storage transistor. That is, the storage transistors formed by the gate pillar and each device layer are connected in parallel, and when reading data, all the storage transistors do not need to be turned on, thereby improving the reading speed of the data.

[0092] To make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0093] The electronic device provided by the embodiment of the present application has a data storage function, and the electronic device can include a central processing unit (CPU), a power management device, etc. The electronic device includes a circuit board and a memory disposed on the circuit board, and the memory is used for storing data. It can be understood that the circuit board can also be provided with other electronic devices, and the present embodiment does not limit this.

[0094] The memory includes a storage array and a controller, the controller is electrically connected with the storage array, and the controller is used for accessing the storage array to write data into the storage array or read data from the storage array.

[0095] Figure 2 The structure of the storage array provided by the embodiment of the present application Figure 1 Please refer to Figure 2 The embodiment of the present application provides a storage array, which includes a substrate 10 and a stacked structure 20 disposed on the substrate 10, wherein the substrate 10 is in a plate shape, and the material of the substrate 10 can include silicon, germanium, etc. The present embodiment does not limit the material of the substrate 10. The stacked structure 20 includes a plurality of device layers 201 stacked, each device layer 201 includes a first electrode layer 204, a first isolation layer 203 and a second electrode layer 202 stacked, the first isolation layer 203 is disposed between the first electrode layer 204 and the second electrode layer 202, and the first electrode layer 204 can be located on the side of the first isolation layer 203 close to the substrate 10.

[0096] The first electrode layer 204 can include a plurality of first electrode lines 2043 arranged in parallel and spaced apart along the direction parallel to the substrate 10, and the second electrode layer 202 can include a plurality of second electrode lines 2021 arranged in parallel and spaced apart along the direction parallel to the substrate 10, and the projection of the first electrode line 2043 on the substrate 10 is perpendicular to the projection of the second electrode line 2021 on the substrate 10. The material of the first electrode line 2043 and the second electrode line 2021 can include one or more of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium-tin oxide (In-Ti-O ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag). The first isolation layer 203 is used to isolate the first electrode line and the second electrode line, and the first isolation layer 203 is an insulating layer. The material of the first isolation layer 203 can include silicon oxide (SIO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), etc.

[0097] It can be understood that the first isolation blocks 2024 can be arranged between the adjacent second electrode lines 2021 to realize isolation between the adjacent second electrode lines 2021. Similarly, the second isolation blocks 2044 can be arranged between the adjacent first electrode lines 2043 to realize isolation between the adjacent first electrode lines 2043 through the second isolation blocks 2044. For example, the first isolation blocks 2024 and the second isolation blocks 2044 can be made of the same material as the first isolation layer 203, and the first isolation blocks 2024 and the second isolation blocks 2044 can also be made of other insulating materials, which are not limited in the embodiment.

[0098] The stack structure 20 further comprises a plurality of second isolation layers 206, one of which is arranged between the adjacent device layers 201, and isolation between the adjacent device layers 201 can be realized through the second isolation layers 206. For example, the second isolation layers 206 can be made of the same material as the first isolation layer 203, and the second isolation layers 206 can also be made of other insulating materials, which are not limited in the embodiment.

[0099] Continuing to refer to Figure 2 In the embodiment, the stack structure 20 further comprises a gate pillar 209, and the stack structure 20 is provided with a through hole 205, the through hole 205 penetrates the stack structure 20, and the gate pillar 209 is arranged in the through hole 205. The first electrode layer 204 in each device layer 201 serves as a first electrode of a storage transistor 101, the second electrode layer 201 in the device layer 201 serves as a second electrode of the corresponding storage transistor 101, and the gate pillar 209 serves as a gate of the corresponding storage transistor 101, and the storage transistor 101 is used for storing data. That is, the gate pillar 209 and each device layer 201 form a storage transistor 101, and in one device layer 201, the first electrode layer 204 serves as a first electrode of the storage transistor 101, the second electrode layer 201 serves as a second electrode of the storage transistor 101, and the gate pillar 209 serves as a gate of the storage transistor 101. The gate pillar 209 is a conductive pillar, for example, the gate pillar 209 can be made of the same material as the first electrode line 2043 and the second electrode line 2021, and the gate pillar 209 can also be made of other conductive materials, which are not limited in the embodiment.

[0100] In the implementation where the second electrode layer 202 includes a plurality of second electrode lines 2021, the first electrode layer 204 includes a plurality of first electrode lines 2043, and the second electrode lines 2021 are perpendicular to the first electrode lines 2043, the projection of one second electrode line 2021 and one first electrode line 2043 in the same device layer 201 on the substrate 10 has an overlapping region, and the projection of the through hole 205 on the substrate 10 is located in the overlapping region; that is, the through hole 205 penetrates the overlapping portion of the second electrode line 2021 and the first electrode line 2043. Correspondingly, the second electrode line 2021 serves as the second electrode of a storage transistor 101, the first electrode line 2043 serves as the first electrode of the storage transistor 101, and the gate pillar 209 serves as the gate of the storage transistor 101, where the second electrode can be the drain of the storage transistor 101, the first electrode can be the source of the storage transistor 101, and the gate pillar 209 is the gate of the storage transistor 101; or, the second electrode is the source of the storage transistor 101, the first electrode is the drain of the storage transistor 101, and the gate pillar 209 is the gate of the storage transistor 101.

[0101] In the above implementation, the structures of each device layer 201 are substantially the same, the through hole 205 penetrates each device layer 201, and correspondingly, each storage transistor 101 formed between the gate pillar 209 and each device layer 201 constitutes a storage string, that is, each storage transistor 101 in the storage string is arranged in sequence along a direction substantially perpendicular to the substrate 10.

[0102] The through hole 205 can be a plurality of, and correspondingly, in the same device layer 201, each second electrode line 2021 and each first electrode line 2043 in the overlapping region of the projection on the substrate 10 is correspondingly provided with a through hole 205, and each through hole 205 is provided with a gate pillar 209. In this way, each gate pillar 209 and each device layer 201 constitute a storage string, thereby improving the storage capacity of the storage array.

[0103] The storage array provided by the embodiment has the first electrode layer 204 in each device layer 201 electrically connected, that is, the first electrode layers 204 in the same storage string are electrically connected, and in this way, the sources of the storage transistors 101 in the same storage string are electrically connected. At the same time, the gate pillar 209 serves as the gate of each storage transistor 101 in the same storage string, that is, the gates of the storage transistors 101 in the same storage string are electrically connected, so that the storage transistors 101 in the same storage string are connected in parallel. When reading data, power can be supplied to the first electrode layer 204 and the gate pillar 209, so that each storage transistor 101 in the storage string where the gate pillar 209 is located is in a state where data can be read, and at this time, the data in the storage transistor corresponding to the second electrode layer 202 can be read through the second electrode layer 202.

[0104] Continue to refer to Figure 2 In some embodiments, within the same device layer 201, the first electrode layer 204 includes a plurality of first electrode lines 2043 arranged parallel to and spaced apart along a direction parallel to the substrate 10, and the second electrode layer 202 includes a plurality of second electrode lines 2021 arranged parallel to and spaced apart along a direction parallel to the substrate 10; a through-hole 205 passes through one of the second electrode lines 2021; the stacked structure 20 also includes a connection hole 2041 passing through each device layer 201, the projection of the connection hole 2041 on the substrate 10 being located between the projections of two adjacent second electrode lines 2021 in the same device layer 201 on the substrate 10; the connection hole 2041 is filled with a conductor 2042, and the conductor 2042 contacts each of the first electrode lines 2043 in the same memory string. That is, the connection hole 2041 passes through each of the first electrode lines 2043 corresponding to the memory string, and the formed conductor 2042 can realize the electrical connection between each of the first electrode lines 2043 corresponding to the memory string. This configuration is simple in structure and easy to manufacture.

[0105] It is understandable that the material of the conductor 2042 can be the same as that of the first electrode line 2043. After the conductor 2042 comes into contact with each of the first electrode lines 2043, the conductor 2042 can form an integral structure with each of the first electrode lines 2043. This can reduce the resistance between the conductor 2042 and each of the first electrode lines 2043, thereby improving the performance of the storage array.

[0106] In a storage array implementation comprising multiple storage strings, the same first electrode line 2043 can correspond to multiple storage strings, meaning the same first electrode line can be passed through by multiple through-holes 205. Correspondingly, a connecting hole 2041 can be provided between two adjacent through-holes 205, and each connecting hole 2041 is filled with a conductor 2042. This configuration, using multiple conductors 2042 to achieve electrical connections between the first electrode lines 2043 corresponding to the same storage string, improves voltage uniformity on the first electrode lines 2043, thereby enhancing the performance of the storage array.

[0107] Figure 3 A schematic diagram of the structure of the storage array provided in the embodiments of this application. Figure 2 Please refer to Figure 3 In other embodiments, the first electrode layer 204 within the same device layer 201 can be a whole layer structure. Correspondingly, the first electrode layers 204 within different device layers 201 can be electrically connected through an external circuit (not shown). This embodiment does not limit the electrical connection method between each first electrode layer 204.

[0108] The memory array provided in this embodiment has a stacked structure 20 comprising multiple stacked device layers 201. Each device layer 201 includes a first electrode layer 204, a first isolation layer 203, and a second electrode layer 202 stacked together. The first isolation layer 203 is located between the first electrode layer 204 and the second electrode layer 202, and the first electrode layers 204 are electrically connected to each other. A through-hole 205 is provided on the stacked structure 20, which penetrates each second electrode layer 202 and each first electrode layer 204. A gate post 209 is disposed within the through-hole 205. The first electrode layer 204 in each device layer 201 serves as the first electrode of a memory transistor 101, the second electrode layer 202 in the same device layer 201 serves as the second electrode of the corresponding memory transistor 101, and the gate post 209 serves as the gate of the corresponding memory transistor 101. Since the first electrode layers 204 are electrically connected, the gate pillar 209 and the storage transistors 101 formed by the device layers 201 are connected in parallel. When reading data, power can be supplied to the first electrode layers 204 and the gate pillar 209, so that the gate pillar 209 and the storage transistors 101 formed by the device layers 201 are all in a data-readable state. At this time, the data in the storage transistor 101 corresponding to the second electrode layer 202 can be read through the second electrode layer 202, without having to keep the gate pillar 209 and the storage transistors 101 formed by the device layers 201 in the on state, thus improving the data reading speed.

[0109] Figure 4 for Figure 2 Please refer to the enlarged view of part A in the middle. Figure 4 In this embodiment, each device layer 201 further includes a dielectric layer 207 and a channel layer 208. The via 205 includes a sub-via 2051 penetrating each device layer 201. That is, the sub-vias 2051 penetrating the device layer 201 are connected sequentially to form a via 205. The dielectric layer 207 is disposed on the gate pillar 209 corresponding to the sub-via 2051. The channel layer 208 is in contact with the dielectric layer 207, the first electrode layer 204, and the second electrode layer 202. The storage transistor 101 further includes a dielectric layer 207 and a channel layer 208 that is in contact with the dielectric layer 207, the first electrode layer 204, and the second electrode layer 202. With the above configuration, the dielectric layer 207 can store electrons. When electrons are stored in the dielectric layer 207, applying a small voltage to the gate post 209 and the first electrode layer 204 will turn on the storage transistor 101, at which time a large current can be detected. When no electrons are stored in the dielectric layer 207, applying a small voltage to the gate post 209 and the first electrode layer 204 will make it difficult for the storage transistor 101 to turn on, and the current obtained will be small. Data can be read by analyzing the current. The structure is simple and easy to manufacture.

[0110] It can be understood that the medium layer 207 is used for storing electrons, and the medium layer 207 can include silicon oxide layers (SiO x ), silicon nitride layers (SiN x ), and silicon oxide layers (SiO x ) arranged in a stack. Alternatively, the medium layer 207 is composed of one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), and the like insulating materials.

[0111] Of course, the medium layer 207 can also be hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum (Al) doped hafnium oxide (HfO2), silicon (Si) doped hafnium oxide (HfO2), zirconium (Zr) doped hafnium oxide (HfO2), lanthanum (La) doped hafnium oxide (HfO2), yttrium (Y) doped hafnium oxide (HfO2), and the like ferroelectric materials, or the medium layer 207 is a material based on the ferroelectric material and doped with other elements, or the medium layer 207 is a combination of one or more of the above materials.

[0112] The working process of the storage array provided by the embodiment is as follows:

[0113] When reading data, a first voltage can be applied to the gate column 209 and the first electrode layer 204. If the data stored in the storage transistor 101 is “1”, at this time, the medium layer 207 stores electrons, under the joint action of the first voltage and the electrons, the storage transistor 101 can be in an open state, at this time, the second electrode layer 202 connected through the storage transistor 101 can obtain a first current; if the data stored in the storage transistor 101 is “0”, the medium layer 207 does not store electrons, and the storage transistor 101 is difficult to open, at this time, the second electrode layer 202 connected through the storage transistor 101 can obtain a second current, and the second current is less than the first current. By analyzing the first current and the second current, the data stored in the storage transistor 101 can be obtained, and the reading of the data is realized.

[0114] When the memory transistor 101 is writing data, a second voltage can be applied to the gate pillar 209 and the second electrode layer 202 connected with the memory transistor 101, so that the memory transistor 101 is in an open state. Under the action of the second voltage, electrons are injected into the dielectric layer 207 and remain in the dielectric layer 207. At this time, the data stored in the memory transistor 101 can be "1". If the second voltage is applied to the gate pillar 209 and the third voltage is applied to the second electrode layer 202 connected with the memory transistor 101, the third voltage is lower than the second voltage. At this time, the electrons will not be injected into the dielectric layer 207, and the data stored in the memory transistor 101 can be "0". It can be understood that when writing data, the voltage is applied to the gate pillar 209, and the memory transistors 101 are connected in parallel. At this time, data can be written into the memory transistor 101 through the corresponding second electrode layer 202 of the memory transistor 101, without the need to make each memory transistor in the memory string in an open state, thereby improving the data writing speed.

[0115] In some implementations, the dielectric layer 207 can cover the entire gate pillar 209 corresponding to the sub-hole 2051, that is, the dielectric layer 207 is continuously arranged along the center line direction of the sub-gate pillar 209, and the dielectric layer 207 covers the entire gate pillar 209 (the dielectric layer 207 is in a tubular shape). Such an arrangement can increase the area of the dielectric layer 207, thereby improving the electron storage capacity of the dielectric layer 207.

[0116] In some implementations, the dielectric layers 207 in adjacent device layers 201 are in contact, for example, the dielectric layers 207 in adjacent device layers 201 can be an integral structure. Such an arrangement can further increase the area of the dielectric layer 207, thereby improving the electron storage capacity of the dielectric layer 207 and improving the performance of the memory array layer. Each dielectric layer 207 can also cover the entire gate pillar 209, that is, each dielectric layer 207 forms a continuous tube. Such an arrangement can further increase the area of the dielectric layer 207.

[0117] In this embodiment, the channel layer 208 is in contact with the first electrode layer 204, the second electrode layer 202, and the dielectric layer 207. The structure and arrangement position of the channel layer 208 can be various, which will be introduced in multiple scenarios as follows:

[0118] Scenario one

[0119] Continuing to refer to Figure 4In this scenario, the channel layer 208 covers the wall of the sub-via 2051, and the dielectric layer 207 covers the gate pillar 209 corresponding to the sub-via 2051, thereby achieving contact between the channel layer 208 and the second electrode layer 202, the first electrode layer 204, and the dielectric layer 207. With this configuration, the channel layer 208 and the dielectric layer 207 can be sequentially formed on the wall of the sub-via 2051 during fabrication, simplifying the fabrication of the memory array.

[0120] The channel layer 208 can cover the entire wall of the sub-via 2051, meaning the channel layer 208 is tubular within the sub-via 2051. Correspondingly, the dielectric layer 207 can cover the entire sidewall of the gate pillar 209, meaning the dielectric layer 207 is also tubular. This increases the contact area between the channel layer 208 and the first electrode layer 204, the second electrode layer 202, and the dielectric layer 207, thus increasing the area of ​​the conductive channel formed by the channel layer 208 and the dielectric layer 207. This improves the turn-on voltage of the storage transistor 101, thereby enhancing the performance of the storage array.

[0121] In the implementation of the stacked structure 20 including the second isolation layer 206, the dielectric layers 207 in adjacent device layers 201 are in contact. In this case, each dielectric layer 207 forms a tube covering the entire gate pillar 209, thereby increasing the area of ​​the dielectric layer 207 and improving its electronic storage capacity. Correspondingly, the second isolation layer 206 can be in contact with the dielectric layer 207. That is, the channel layers 208 on adjacent sub-vias 2051 are isolated by the second isolation layer 206 to prevent the channel layers 208 on adjacent sub-vias 2051 from interfering with each other.

[0122] Scene 2

[0123] Figure 5 A schematic diagram of the structure of the storage array provided in the embodiments of this application. Figure 3 , Figure 6 for Figure 5 Please refer to the enlarged view of section B in the middle. Figure 5 and Figure 6 The difference between this scenario and scenario one is that there is a gap 2031 between the first isolation layer 203 and the wall of the sub-via 2051. The gap 2031 is connected to the sub-via 2051. That is, the sidewall of the sub-via 2051 corresponding to the first isolation layer 203 is recessed into the first isolation layer 203 to form the gap 2031. The channel layer 208 includes a first channel layer 2081 disposed in the gap 2031 to achieve contact between the channel layer 208 and the second electrode layer 202, the first electrode layer 204, and the dielectric layer 207.

[0124] In this way, the conductive channel can avoid occupying the space in the through hole 205, and the area of the dielectric layer 207 can be increased, and the electronic storage capacity of the dielectric layer 207 can be improved.

[0125] In the above implementation, the channel layer 208 further includes a second channel layer 2082 arranged on the surface of the first isolation layer 203 facing the second electrode layer 202, and the second channel layer 2082 is in contact with the first channel layer 2081; that is, the second channel layer 2082 is arranged between the second electrode layer 202 and the first isolation layer 203, and the second channel layer 2082 is in contact with the second electrode layer 202. In this way, the contact area between the channel layer 208 and the second electrode layer 202 can be increased, and the resistance between the channel layer 208 and the second electrode layer 202 can be reduced.

[0126] For example, the first channel layer 2081 and the second channel layer 2082 can be made of the same material, so that after the first channel layer 2081 and the second channel layer 2082 are in contact, the first channel layer 2081 and the second channel layer 2082 form an integrated structure, so as to reduce the resistance between the first channel layer 2081 and the second channel layer 2082.

[0127] In some embodiments, the channel layer 208 further includes a third channel layer 2083 arranged on the surface of the first isolation layer 203 facing the first electrode layer 204, and the third channel layer 2083 is in contact with the first channel layer 2081; that is, the third channel layer 2083 is arranged between the first electrode layer 204 and the first isolation layer 203, and the third channel layer 2083 is in contact with the first electrode layer 204. In this way, the contact area between the channel layer 208 and the first electrode layer 204 can be increased, and the resistance between the channel layer 208 and the first electrode layer 204 can be reduced.

[0128] In the implementation in which the channel layer 208 includes the first channel layer 2081, the second channel layer 2082, and the third channel layer 2083, the first channel layer 2081, the second channel layer 2082, and the third channel layer 2083 can be made of the same material, so that after the first channel layer 2081 is in contact with the second channel layer 2082 and the third channel layer 2083, the first channel layer 2081, the second channel layer 2082, and the third channel layer 2083 form an integrated structure, so as to reduce the resistance between the first channel layer 2081 and the second channel layer 2082 and the third channel layer 2083.

[0129] Scenario three

[0130] Figure 7 Structure of the storage array provided by the embodiments of the present application Figure 4 , Figure 8 For Figure 7 Please refer to the local enlarged view at C in FIG.Figure 7 and Figure 8 The difference between this scenario and scenarios one and two is that the first isolation layer 203 has a gap 2032 between the hole wall of the sub-via hole 2051 and the first isolation layer 203, the gap 2032 is in communication with the through hole 205, that is, the hole wall corresponding to the sub-via hole 2051 and the first isolation layer 203 is recessed to form a gap 2032 to the first isolation layer 203. The gate pillar 209 is provided with an extension 2091, and the extension 2091 is arranged in the gap 2032.

[0131] The extension 2091 is composed of a conductive material, and the extension 2091 can be of the same material as the gate pillar 209, for example, so that the extension 2091 and the gate pillar 209 can form an integrated structure to reduce the resistance between the extension 2091 and the gate pillar 209. Of course, the material of the extension 2091 can also be different from that of the gate pillar 209, and the present embodiment does not limit this, as long as the electrical connection between the extension 2091 and the gate pillar 209 is ensured.

[0132] The dielectric layer 207 includes a first dielectric layer 2071 and a second dielectric layer 2072, the first dielectric layer 2071 is located on the gate pillar 209 corresponding to the sub-via hole 2051, and the second dielectric layer 2072 is wrapped on the extension 2091; that is, the second dielectric layer 2072 is located between the extension 2091 and the second electrode layer 202, between the extension 2091 and the first isolation layer 203, and between the extension 2091 and the first electrode layer 204. The first dielectric layer 2071 and the second dielectric layer 2072 are in contact. The material of the first dielectric layer 2071 and the second dielectric layer 2072 can be the same, for example, so that the first dielectric layer 2071 and the second dielectric layer 2072 can form an integrated structure after being in contact, so as to increase the area of the dielectric layer 207 and improve the electronic storage capacity of the dielectric layer 207.

[0133] The channel layer 208 includes a first channel layer 2081 and a second channel layer 2082. The first channel layer 2081 is arranged between the hole wall of the sub-via hole 2051 and the first dielectric layer 2071. The second channel layer 2082 is arranged between the second dielectric layer 2072 and the side wall of the gap 2032. That is, the second channel layer 2082 is located between the second dielectric layer 2072 and the second electrode layer 202, between the second dielectric layer 2072 and the first isolation layer 203, and between the second dielectric layer 2072 and the first electrode layer 204. The first channel layer 2081 and the second channel layer 2082 are in contact. In this way, the first dielectric layer 2071 and the first channel layer 2081 in the sub-via hole 2051 form a conductive channel, and the second dielectric layer 2072 and the second channel layer 2082 in the gap 2032 also form a conductive channel. In this way, the area of the conductive channel can be increased, and the opening voltage of the storage transistor can be increased, thereby improving the performance of the storage array.

[0134] It can be understood that, in the implementation where the second electrode layer 202 includes a plurality of second electrode lines 2021 arranged in parallel and spaced apart, the width of the gap 2032 along the direction perpendicular to the second electrode lines 2021 can be greater than or equal to the width of the second electrode lines 2021, so that the gap 2032 has a large enough space to accommodate more second dielectric layers 2072 and second channel layers 2082. Similarly, the width of the gap 2032 along the direction parallel to the second electrode lines can be greater than or equal to the width of the first electrode lines 2043 (as shown in FIG. 2B), so that the gap 2032 has a large enough space to accommodate more second dielectric layers 2072 and second channel layers 2082. Figure 2

[0135] Continuing to refer to Figure 8 In the implementation where the stack structure 20 includes the second isolation layer 206, the first dielectric layer 2071 can also cover the gate pillar 209 between adjacent device layers 201, so as to increase the area of the first dielectric layer 2071 and improve the electronic storage capacity of the dielectric layer 207. Correspondingly, the second isolation layer 206 can be in contact with the first dielectric layer 2071, that is, the first channel layers 2081 on adjacent sub-via holes 2051 are isolated by the second isolation layer 206, so as to avoid mutual influence of the first channel layers 2081 on adjacent sub-via holes 2051.

[0136] The embodiment provides a storage array manufacturing method which can be used to manufacture the storage array in the first embodiment.

[0137] Figure 9 The flowchart of the storage array manufacturing method provided by the embodiment is shown in FIG. 2E. Figure 9 The storage array manufacturing method provided by the embodiment includes the following steps.

[0138] ​S101: Form a stack structure on a substrate.

[0139] Figure 10 For the structure schematic diagram of the stack structure provided in the storage array manufacturing method of the embodiment of the present application, please refer to Figure 10 The substrate 10 is the basis of the entire storage array, and the substrate 10 can be in the form of a plate. The material of the substrate 10 can include silicon, germanium, etc. The stack structure 20 includes a plurality of device layers 201 stacked. Each device layer 201 includes a first intermediate layer 301, a first isolation layer 203, and a second intermediate layer 302 stacked. The first isolation layer 203 is located between the first intermediate layer 301 and the second intermediate layer 302. The second intermediate layer 302 can be located on the side of the first isolation layer 203 away from the substrate 10. The second intermediate layer 302 is provided with a first opening 3021 (as shown in Figure 11 ) penetrating through the second intermediate layer 302. The first opening 3021 is filled with an electrode plate 2022.

[0140] In some implementations, the method of manufacturing the stack structure 20 on the substrate 10 can include: alternately forming the first intermediate layer 301, the first isolation layer 203, and the second intermediate layer 302 on the substrate 10 to form a plurality of device layers 201 stacked. That is, first, a first intermediate layer 301 is formed on the substrate 10. Then, a first isolation layer 203 is formed on the first intermediate layer 301. Then, a second intermediate layer 302 is formed on the first isolation layer 203 to complete the manufacturing of one device layer 201. After that, the above steps are repeated to sequentially form a plurality of device layers 201 stacked.

[0141] After each device layer 201 is formed, an intermediate isolation layer 303 can be formed on the device layer 201, and then the next device layer 201 is manufactured. That is, the intermediate isolation layer 303 is arranged between adjacent device layers 201 to isolate the adjacent device layers 201.

[0142] Figure 11 For the structure schematic diagram of the stack structure provided in the storage array manufacturing method of the embodiment of the present application after the first process hole is formed, please refer to Figure 11 After each device layer 201 is manufactured, a first process hole 304 can be formed on the stack structure 20. The first process hole 304 penetrates through the stack structure 20. Then, a first insulating block 305 (as shown in Figure 12 ) is filled in the first process hole 304. The first insulating block 305 can connect each film layer in the stack structure 20 to improve the connection force between each film layer in the stack structure 20.

[0143] Figure 13 For the structure schematic diagram of the stack structure provided in the storage array manufacturing method of the embodiment of the present application after the via hole is formed, please refer to Figure 13After the first insulating block 305 is formed, a via hole 306 can be formed on the stack structure 20, the via hole 306 penetrates the stack structure 20, and a projection of the via hole 306 on the substrate 10 is located outside a projection of the first insulating block 305 on the substrate 10. Figure 14 For a structure schematic diagram of the storage array manufacturing method provided in the embodiment of the present application after the first opening is formed, please refer to Figure 14 Part of the second intermediate layer 302 is removed through the via hole 306 to form a first opening 3021 on the second intermediate layer 302. Figure 15 For a structure schematic diagram of the storage array manufacturing method provided in the embodiment of the present application after the through hole is formed, please refer to Figure 15 Then, a conductive material is filled in the via hole 306 and the first opening 3021 to form an electrode plate 2022 in the first opening 3021.

[0144] After the electrode plate 2022 is formed, still referring to Figure 9 The storage array manufacturing method in the embodiment further includes:

[0145] S102: Form a through hole on the stack structure, the through hole penetrates the stack structure, and a projection of the through hole on the substrate is located within a projection of the electrode plate on the substrate.

[0146] Still referring to Figure 15 It can be understood that Figure 14 The projection of the via hole 306 on the substrate 10 can be located within the projection of the through hole 205 on the substrate 10, so that the conductive material in the via hole 306 can be removed in the process of forming the through hole 205 to avoid the connection between the electrode plates 2022. For example, the projection of the through hole 205 on the substrate 10 can completely coincide with the projection of the via hole 306 on the substrate 10; or the projection area of the through hole 205 on the substrate 10 is greater than the projection area of the via hole 306 on the substrate 10, so that the conductive material in the via hole 306 can be completely removed to avoid the residual conductive material in the via hole 306.

[0147] After the through hole 205 is formed, still referring to Figure 9 The storage array manufacturing method in the embodiment further includes:

[0148] S103: Form a gate column in the through hole.

[0149] S104: Replace the first intermediate layer with a first electrode layer, the first electrode layer in each device layer as a first electrode of a storage transistor, the electrode plate in the device layer as a second electrode of the corresponding storage transistor, and the gate column as a gate of the corresponding storage transistor; each first electrode layer is electrically connected.

[0150] Figure 16This is a schematic diagram of the structure after the gate pillars are formed in the memory array fabrication method provided in the embodiments of this application, as shown in the figure. Figure 16 As shown, after the gate pillar 209 is formed, the first electrode layer in each device layer 201 serves as the first electrode of a storage transistor 101, the electrode plate 2022 in the device layer 201 serves as the second electrode of the corresponding storage transistor 101, and the gate pillar 209 serves as the gate of the corresponding storage transistor 101. This storage transistor is used for data storage. Specifically, the gate pillar 209 can be the gate of the storage transistor, the first electrode can be the source of the storage transistor, and the second electrode can be the drain of the storage transistor; or the gate pillar 209 can be the gate of the storage transistor, the first electrode can be the drain of the storage transistor, and the second electrode can be the source of the storage transistor.

[0151] The memory array fabricated by the memory array fabrication method provided in this embodiment includes a stacked structure 20 comprising multiple stacked device layers 201. Each device layer 201 includes a stacked first electrode layer, a first isolation layer 203, and an electrode plate 2022. The first isolation layer 203 is located between the first electrode layer and the electrode plate 2022, and the first electrode layers are electrically connected to each other. A through-hole 205 is provided on the stacked structure 20, which penetrates each second electrode layer 202 and each first electrode layer. A gate post 209 is disposed within the through-hole 205. The first electrode layer in each device layer 201 serves as the first electrode of a memory transistor 101, the electrode plate 2022 in the device layer 201 serves as the second electrode of the corresponding memory transistor 101, and the gate post 209 serves as the gate of the corresponding memory transistor 101. Since the first electrode layers are electrically connected, the gate pillar 209 and the storage transistors formed by the device layers 201 are connected in parallel. When reading data, power can be supplied to the first electrode layers and the gate pillar 209, so that the gate pillar 209 and the storage transistors formed by the device layers 201 are all in a data-readable state. At this time, the data in the storage transistor corresponding to the electrode plate 2022 can be read through the electrode plate 2022, without having to turn on the gate pillar 209 and the storage transistors formed by the device layers 201, thus improving the data reading speed.

[0152] In this embodiment, before forming the gate pillar 209, a channel layer 208 and a dielectric layer 207 are further formed to form a conductive channel. Depending on the structure and location of the channel layer 208, the memory array fabrication method in this embodiment can have the following fabrication scenarios:

[0153] Scene 1

[0154] Continue to refer to Figure 16Before forming the gate pillar 209 in the through hole 205, the method further comprises: sequentially forming the channel layer 208 and the dielectric layer 207 on the hole wall of the through hole 205; the channel layer 208 covers the whole hole wall of the through hole 205, and the dielectric layer 207 covers the whole channel layer 208. That is, the channel layer 208 and the dielectric layer 207 are both in a tubular shape in the through hole 205. In this way, the area of the dielectric layer 207 can be increased, and the ability of the dielectric layer 207 to store electrons can be improved. In addition, the area of the conductive channel is also increased, and the opening voltage of the storage transistor is improved, and the performance of the storage array is improved.

[0155] It can be understood that the dielectric layer 207 is used to store electrons, and the dielectric layers 207 in adjacent device layers can be in contact and form an integrated structure, and the corresponding dielectric layer 207 can cover the whole through hole 205, that is, the dielectric layer 207 covers the whole gate pillar 209. In this way, the electron storage capacity of the dielectric layer 207 can be further improved.

[0156] In the above implementation, when the gate pillar 209 is formed, the channel layer 208 and the dielectric layer 207 are sandwiched between the gate pillar 209 and the hole wall of the through hole 205, and the channel layer 208 is located between the dielectric layer 207 and the hole wall of the through hole 205. The gate pillar 209, the dielectric layer 207, the channel layer 208, the electrode plate 2022, and the first electrode layer 204 constitute a storage transistor.

[0157] Figure 17 For the structure schematic diagram of the storage array provided by the embodiment of the present application after forming the connecting hole, please refer to Figure 17 In the embodiment, the first intermediate layer 301 is replaced by the first electrode layer, and each first electrode layer is electrically connected, comprising: forming a connecting hole 2041 penetrating the stacked structure 20, and the projection of the connecting hole 2041 on the substrate 10 is located outside the projection of the electrode plate 2022 on the substrate 10. Figure 18 For the structure schematic diagram of the storage array provided by the embodiment of the present application after forming the third gap layer, please refer to Figure 18 Then, the first intermediate layer 301 is removed through the connecting hole 2041 to form the third gap layer 3011. Figure 19 For the structure schematic diagram of the storage array provided by the embodiment of the present application after forming the first electrode layer and the conductive body, please refer to Figure 19 After that, conductive material is filled in the connecting hole 2041 and the third gap layer 3011 to form the first electrode layer 204 located in the third gap layer and the conductive body 2042 connecting each first electrode layer 204. The electrical connection between adjacent first electrode layers 204 can be realized through the conductive body 2042, which is simple in structure and easy to manufacture.

[0158] In the implementation manner in which the intermediate isolation layer 303 is formed between the adjacent device layers 201, after the gate pillar 209 is formed, the method further includes: Figure 20 For the structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after the first void layer is formed, please refer to Figure 20 The intermediate isolation layer 303 and the channel layer 208 corresponding to the intermediate isolation layer 303 are removed to form the first void layer 3031. The first void layer 3031 can break the channel layer 208 between the adjacent device layers 201, thereby avoiding the connection of the channel layer 208 between the adjacent device layers 201. Figure 21 For the structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after the second isolation layer is formed, please refer to Figure 21 Then, the second isolation layer 206 is formed in the first void layer 3031. The second isolation layer 206 can isolate the adjacent device layers 201 and isolate the channel layer 208 in the adjacent device layers 201.

[0159] In some embodiments, before the first intermediate layer 301 is removed, the intermediate isolation layer 303 can be removed through the connection hole 2041. Then, the second isolation layer 206 is filled into the first void layer 3031 through the connection hole 2041. It can be understood that part of the insulating material will be filled in the connection hole 2041 in the process of forming the second isolation layer 206. Accordingly, before the first intermediate layer 301 is removed, the insulating material in the connection hole 2041 can be removed to avoid affecting the subsequent process.

[0160] In the above implementation manner, after the conductive body 2042 and the first electrode layer 204 are formed, the storage array manufacturing method further includes forming a conductive connecting body in the second intermediate layer 302, and the conductive connecting body is in contact with the electrode plate 2022 to form a second electrode line. The second electrode line can realize the reading and writing of data. For example, the material of the conductive connecting body and the electrode plate 2022 can be the same, so that after the conductive connecting body is formed, the conductive connecting body and the electrode plate 2022 form an integrated structure, so as to reduce the resistance between the conductive connecting body and the electrode plate 2022.

[0161] In the present scenario, a plurality of electrode plates 2022 are arranged on the second intermediate layer 302 in each device layer 201, and a through hole 205 is arranged on each electrode plate 2022. A gate pillar 209 is arranged in each through hole 205. Such arrangement can increase the number of storage transistors, thereby improving the storage capacity of the storage array.

[0162] Figure 22 For the structure schematic diagram of the storage array manufacturing method provided by the embodiment of the present application after the second process hole is formed, please refer to Figure 22For example, after the formation of the conductive body 2042 and the first electrode layer 204, a second process hole 307 can be formed on the first insulating block 305, the second process hole 307 penetrates to the substrate 10, and the projection of the second process hole 307 on the substrate 10 is located within the projection of the first process hole 304 on the substrate 10. The second process hole 307 extends in a direction parallel to the substrate 10 and penetrates to the second intermediate layer 302 between the adjacent electrode plates 2022.

[0163] Figure 23 For the structure after the formation of the conductive connecting body in the storage array manufacturing method provided by the embodiment of the present application, please refer to Figure 23 After the formation of the second process hole 307, the second intermediate layer 302 outside the electrode plate 2022 can be removed through the second process hole 307, that is, the second intermediate layer 302 between the adjacent electrode plates 2022 is removed, and the conductive connecting body 2023 is formed in the second intermediate layer 302, that is, the conductive connecting body 2023 is located between the adjacent electrode plates 2022, and the conductive connecting body 2023 is in contact with the electrode plate 2022 to form the second electrode line. After the formation of the second electrode line, the second insulating block 3071 can be filled in the second process hole 307 to seal the second process hole 307.

[0164] Figure 24 For the structure after the removal of the first insulating block in the storage array manufacturing method provided by the embodiment of the present application, as shown in Figure 24 In this scenario, after the formation of the gate pillar 209, the first insulating block 305 can also be removed to expose the first process hole 304. Figure 25 For the structure after the formation of the conductive connecting body by using the first process hole in the storage array manufacturing method provided by the embodiment of the present application, as shown in Figure 25 After that, the second intermediate layer 302 between the adjacent electrode plates 2022 is removed through the first process hole 304, and the conductive connecting body 2023 is formed between the adjacent electrode plates 2022, and the conductive connecting body 2023 is in contact with the electrode plate 2022 to form the second electrode line.

[0165] Figure 26 For the structure after the formation of the first void layer by using the first process hole in the storage array manufacturing method provided by the embodiment of the present application, as shown in Figure 26 After that, the intermediate isolation layer 303 and the channel layer 208 corresponding to the intermediate isolation layer 303 can be removed through the first process hole 304 to form the first void layer 3031, so that the channel layer 208 between the adjacent device layers 201 is disconnected. Figure 27 For the structure after the formation of the second isolation layer by using the first process hole in the storage array manufacturing method provided by the embodiment of the present application, as shown in Figure 27As shown, after the first process hole 304, the second isolation layer 206 is formed in the first void layer 3031, and the second isolation layer 206 is in contact with the dielectric layer 207 corresponding to the first void layer 3031, so as to realize the isolation of the channel layer 208 in the device layer 201 through the second isolation layer 206.

[0166] After the second isolation layer 206 is formed, the first intermediate layer 301 can also be removed through the first process hole 304 to form a third void layer, and then the first electrode layer 204 is formed in the third void layer. The first electrode layer 204 can be an integral layer structure, and correspondingly, each first electrode layer 204 can be electrically connected through the peripheral circuit.

[0167] In the above implementation, in the process of forming the stack structure 20, the second opening is formed on the first intermediate layer 301, and the source plate is filled in the second opening. In the same device layer 201, the projection of the source plate on the substrate 10 is completely overlapped with the projection of the electrode plate 2022 on the substrate 10. In this way, the through hole 205 penetrates the source plate and the electrode plate 2022 whose projections are overlapped, and the gate pillar 209 and the source plate and the electrode plate 2022 constitute a storage transistor.

[0168] It can be understood that after the second isolation layer 206 is formed, the first intermediate layer 301 outside the source plate is removed through the first process hole 304 to form a third void layer, and then a conductive material is formed in the third void layer, and the conductive material is in contact with the source plate to form the first electrode layer 204.

[0169] Scenario two

[0170] Figure 28 For Figure 15 The cross-sectional view of A-A direction, as shown in Figure 29 The difference between this scenario and scenario one is that, after the through hole 205 is formed, and before the gate pillar 209 is formed, it includes:

[0171] Figure 29 The structure schematic diagram provided by the storage array manufacturing method of the embodiment of the present application after the gate pillar is formed, as shown in Figure 30 The dielectric layer 207 is formed on the hole wall of the through hole 205, and the dielectric layer 207 covers the hole wall of the entire through hole 205; that is, the dielectric layer 207 is in a tubular shape in the through hole 205, and the dielectric layer 207 is in direct contact with the hole wall of the through hole 205. Then the gate pillar 209 is formed in the through hole 205, the dielectric layer 207 is located between the gate pillar 209 and the hole wall of the through hole 205, and the dielectric layer 207 is in contact with the gate pillar 209.

[0172] After that, a connection hole 2041 is formed on the stack structure 20, the connection hole 2041 penetrating through each device layer 201, and the projection of the connection hole 2041 on the substrate 10 is located outside the projection of the electrode plate 2022 on the substrate 10. Figure 30 The structure diagram after the first isolation layer is removed by the connection hole in the storage array manufacturing method provided in the embodiment of the present application is shown in FIG. 8. Figure 31 The first isolation layer 203 is removed through the connection hole 2041 to form a second void layer 308. Figure 31 The structure diagram after the third isolation layer is formed in the storage array manufacturing method provided in the embodiment of the present application is shown in FIG. 9. Figure 32 A channel layer 208 is formed on the sidewall of the second void layer 308, and the channel layer 208 covers the corresponding dielectric layer 207, the electrode plate 2022 and the first intermediate layer 301 of the second void layer 308. After the channel layer 208 is formed, the third isolation layer 210 can be formed in the second void layer 308 through the connection hole 2041, and the third isolation layer 210 fills the second void layer 308.

[0173] Correspondingly, the channel layer 208 formed at this time includes a first channel layer 2081 in contact with the dielectric layer 207, a second channel layer 2082 in contact with the electrode plate 2022, and a third channel layer 2083 in contact with the first intermediate layer 301, and the first channel layer 2081, the second channel layer 2082 and the third channel layer 2083 are integrated structures. In this way, after the first electrode layer 204 is formed, the contact area between the channel layer 208 and the electrode plate 2022 and between the channel layer 208 and the first electrode layer 204 can be increased, thereby reducing the resistance between the channel layer 208 and the electrode plate 2022 and between the channel layer 208 and the first electrode layer 204. In addition, the channel layer 208 is arranged in the second void layer 308, which can avoid the channel layer 208 occupying the space of the through hole 205, increase the area of the dielectric layer 207 in the through hole 205, and further improve the storage capacity of the dielectric layer 207.

[0174] Figure 32 The structure diagram after the first electrode layer and the conductor are formed in the storage array manufacturing method provided in the embodiment of the present application is shown in FIG. 10. Figure 5 In this scenario, the projection of the connection hole 2041 on the substrate 10 is located outside the projection of the electrode plate 2022 on the substrate 10, and the first intermediate layer 301 can be removed through the connection hole 2041 after the third isolation layer 210 is formed to form a third void layer. Then, a conductive material is filled in the connection hole 2041 and the third void layer to form the first electrode layer 204 and the conductor 2042 connecting the first electrode layers 204. The electrical connection between adjacent first electrode layers 204 can be realized through the conductor 2042, which is simple in structure and easy to manufacture.

[0175] It can be understood that when the third isolation layer 210 is formed, part of the insulating material will fill in the connection hole 2041, and accordingly the insulating material in the connection hole 2041 can be removed before the first intermediate layer 301 is removed, so as to avoid the influence of the insulating material on the subsequent process.

[0176] After that, a conductive connecting body can be formed to connect adjacent electrode plates 2022 (for specific steps, please refer to scenario one), thereby forming a storage array as shown in Figure 33 .

[0177] Scenario three

[0178] Figure 33 The structure schematic diagram after the gap is formed by the through hole in the storage array manufacturing method provided by the embodiment of the present application, please refer to Figure 34 The difference between the present scenario and scenarios one and two is that before the gate pillar 209 is formed in the through hole 205, part of the first isolation layer 203 is removed through the through hole 205 to form a gap 2032 extending in the first isolation layer 203. Figure 34 The structure schematic diagram after the channel layer is formed in the storage array manufacturing method provided by the embodiment of the present application, please refer to Figure 35 After that, the first channel layer 2081 is formed on the hole wall of the through hole 205, and the second channel layer 2082 is formed on the side wall of the gap 2032, the first channel layer 2081 and the second channel layer 2082 are in contact, and the first channel layer 2081 and the second channel layer 2082 constitute the channel layer 208.

[0179] It can be understood that the material of the first channel layer 2081 and the second channel layer 2082 can be the same, so that the first channel layer 2081 and the second channel layer 2082 can be formed at the same time, thereby simplifying the manufacturing difficulty of the storage array. In addition, after the first channel layer 2081 and the second channel layer 2082 are formed, the first channel layer 2081 and the second channel layer 2082 are in contact to form an integrated structure, which can reduce the resistance between the first channel layer 2081 and the second channel layer 2082.

[0180] Figure 35 The structure schematic diagram after the dielectric layer is formed in the storage array manufacturing method provided by the embodiment of the present application, please refer to Figure 36After the first channel layer 2081 and the second channel layer 2082 are formed, the first dielectric layer 2071 is formed on the first channel layer 2081, and the second dielectric layer 2072 is formed on the second channel layer 2082, and the first dielectric layer 2071 and the second dielectric layer 2072 are in contact. That is, the first dielectric layer 2071 covers the first channel layer 2081, and the second dielectric layer 2072 covers the second channel layer 2082. The materials of the first dielectric layer 2071 and the second dielectric layer 2072 can be the same, so that the first dielectric layer 2071 and the second dielectric layer 2072 can be formed at the same time, and after the first dielectric layer 2071 and the second dielectric layer 2072 are formed, the first dielectric layer 2071 and the second dielectric layer 2072 are in contact to form an integrated structure.

[0181] Figure 36 The structure diagram after the gate pillar is formed in the storage array manufacturing method provided by the embodiment of the present application is shown in FIG. 8. After the first channel layer 2081 and the second channel layer 2082 are formed, the first dielectric layer 2071 is formed on the first channel layer 2081, and the second dielectric layer 2072 is formed on the second channel layer 2082, and the first dielectric layer 2071 and the second dielectric layer 2072 are in contact. That is, the first dielectric layer 2071 covers the first channel layer 2081, and the second dielectric layer 2072 covers the second channel layer 2082. The materials of the first dielectric layer 2071 and the second dielectric layer 2072 can be the same, so that the first dielectric layer 2071 and the second dielectric layer 2072 can be formed at the same time, and after the first dielectric layer 2071 and the second dielectric layer 2072 are formed, the first dielectric layer 2071 and the second dielectric layer 2072 are in contact to form an integrated structure. Figure 7

[0182] Through the above setting, while the first dielectric layer 2071 and the first channel layer 2081 in the through hole 205 form a conductive channel, the second dielectric layer 2072 and the second channel layer 2082 in the gap 2032 also form a conductive channel, so that the area of the conductive channel can be increased, and the opening voltage of the storage transistor can be increased, so as to improve the performance of the storage array.

[0183] After that, the first intermediate layer 301 is replaced by the first electrode layer 204, and a conductive connector is formed to connect adjacent electrode plates 2022 (the specific steps can refer to scene one and scene two), and then a storage array as shown in FIG. 9 is formed. Figure 37

[0184] Figure 37 The circuit diagram of the storage array provided by the embodiment of the present application is shown in FIG. 10. Figure 38 ​​As shown, the embodiment of the present application further provides a storage array, which comprises a storage string 100, the storage string 100 comprises a plurality of storage transistors 101 arranged in sequence, and the gates of the storage transistors 101 are electrically connected. Exemplarily, the gates of the storage transistors 101 can be connected through a gate line WL, of course, the embodiment is not limited thereto, and the gates of the storage transistors 101 can also be electrically connected through other structures.

[0185] The storage array in the embodiment further comprises a first electrode line 2043 and a plurality of second electrode lines 2021, the first electrode line 2043 is electrically connected with the first electrodes in the storage transistors 101 in the storage string 100. One second electrode line 2021 is electrically connected with the second electrode of one storage transistor 101 in the storage string 100, so that data can be written into or read from the corresponding storage transistor 101 through the second electrode line 2021.

[0186] Exemplarily, the first electrode can be the source of the storage transistors 101, and correspondingly, the second electrode can be the drain of the storage transistors 101. Alternatively, the first electrode can be the drain of the storage transistors 101, and correspondingly, the second electrode can be the source of the storage transistors 101.

[0187] In the above implementation manner, the storage string 100 can be multiple, and the multiple storage strings 100 can improve the data storage capacity of the storage array.

[0188] The storage array provided by the embodiment is characterized in that the gates of the storage transistors 101 in the storage string 100 are electrically connected, the first electrode line 2043 is electrically connected with the first electrodes of the storage transistors 101 in the storage string 100, and each second electrode line 2021 is electrically connected with the second electrode of one storage transistor 101 in the storage string 100; when data is read, the first electrode line 2043 and the gates of the storage transistors 101 in the storage string 100 can be supplied with power, so that the storage transistors 101 in the storage string 100 are all in a state in which data can be read, and then the data in the storage transistor 101 corresponding to the second electrode line 2021 can be read through the second electrode line 2021, without the need to turn on the storage transistors 101 in the storage string 100, thereby improving the data reading speed.

[0189] The embodiment of the present application further provides a read-write method for a storage array, wherein the storage array comprises a storage string, the storage string comprises a plurality of storage transistors, and each storage transistor is used for storing data. It can be understood that the storage array further comprises a substrate, and the plurality of storage transistors in the storage string can be arranged in a direction substantially perpendicular to the substrate. The storage string can be multiple, so as to improve the data storage capacity of the storage array.

[0190] The storage array in the embodiment can be the storage array in the above embodiment, and can also be another storage array, which is not limited in the embodiment.

[0191] Figure 38 The flowchart of the read-write method provided in the embodiment of the application is shown in ​ The read-write method provided in the embodiment comprises the following steps:

[0192] S201: A first voltage is applied to the gate of each storage transistor in the storage string and the first electrode of each storage transistor.

[0193] For example, the first electrode can be the source electrode or the drain electrode of the storage transistor, which is not limited in the embodiment.

[0194] After that, the read-write method in the embodiment further comprises the following steps:

[0195] S202: The current of the second electrode of the storage transistor is obtained.

[0196] In some implementations, the first electrode is the source electrode of the storage transistor, and correspondingly, the second electrode is the drain electrode of the storage transistor; in other implementations, the first electrode is the drain electrode of the storage transistor, and correspondingly, the second electrode is the source electrode of the storage transistor.

[0197] After that, the read-write method in the embodiment further comprises the following steps:

[0198] S203: The data stored in the storage transistor is obtained by the current.

[0199] It can be understood that if the current is greater than a preset value, the storage transistor is in an open state; by analyzing the current, the data stored in the storage transistor can be obtained.

[0200] For example, if the data stored in the storage transistor is "1", the storage transistor stores an electron in the medium layer, and under the action of the first voltage and the electron, the storage transistor is in an open state, and the current obtained at this time is greater than the preset value. If the data stored in the storage transistor is "0", the storage transistor does not store an electron in the medium layer, and under the action of the first voltage, the storage transistor cannot be opened, and the current obtained at this time is less than the preset value. By analyzing the current, the data stored in the storage transistor can be obtained.

[0201] Alternatively, if the data stored in the storage transistor can be "0", the medium layer of the storage transistor stores an electron, under the action of the first voltage and the electron, the storage transistor is in an open state, and the current obtained at this time is greater than the preset value. If the data stored in the storage transistor is "1", the medium layer of the storage transistor does not store an electron, and under the action of the first voltage, the storage transistor cannot be opened, and the current obtained at this time is less than the preset value.

[0202] The read-write method provided in the embodiment can apply a first voltage to the gate of each storage transistor in the storage string and the first electrode of each storage transistor before reading data, and each storage transistor in the storage string is connected in parallel. At this time, each storage transistor in the storage string can be in a state in which data can be read, and the data stored in the storage transistor can be read through the second electrode corresponding to the storage transistor, without the need to make each storage transistor in the storage string in an open state, thereby improving the data reading speed.

[0203] In the embodiment, writing data into the storage transistor includes: applying a second voltage to the gate of each storage transistor in the storage string and the second electrode of the storage transistor to be written with data, so that the storage transistor to be written with data is in an open state, to write first data into the storage transistor to be written with data; or applying a third voltage to the gate of each storage transistor in the storage string and the second electrode of the storage transistor to be written with data, the third voltage being less than the second voltage, to write second data into the storage transistor to be written with data.

[0204] For example, when writing data, a second voltage can be applied to the gate and the second electrode of the storage transistor, so that the storage transistor is in an open state, and under the action of the second voltage, an electron is injected into the medium layer of the storage transistor and remains in the medium layer, to store first data in the storage transistor. If the second voltage is applied to the gate and the third voltage is applied to the second electrode of the storage transistor, the third voltage is lower than the second voltage, and at this time, the electron will not be injected into the medium layer, to store second data in the storage transistor.

[0205] It can be understood that the first data can be "1", and the second data can be "0" accordingly; or the first data can be "0", and the second data can be "1" accordingly.

[0206] Through the above setting, when writing data, a voltage is applied to the gate of each storage transistor in the storage string, and each storage transistor in the storage string is connected in parallel. At this time, data can be written into the storage transistor through the second electrode corresponding to the storage transistor, without the need to make each storage transistor in the storage string in an open state, thereby improving the data writing speed.

[0207] It should be noted that in the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "connected", "connected" should be understood in a broad sense, for example, it can be fixedly connected, or integrally connected; it can also be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or the communication inside two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0208] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage array, characterized in that, include: Base; A stacked structure disposed on the substrate, the stacked structure comprising a plurality of device layers stacked together; Each of the device layers includes a first electrode layer, a first isolation layer, and a second electrode layer stacked together, wherein the first isolation layer is located between the first electrode layer and the second electrode layer, and each of the first electrode layers is electrically connected. A gate pillar is provided in the stacked structure, and a through hole is provided in the stacked structure. The through hole passes through the stacked structure and the gate pillar passes through the through hole. The first electrode layer in each device layer serves as the first electrode of a storage transistor, the second electrode layer in the device layer serves as the second electrode of the corresponding storage transistor, and the gate pillar serves as the gate of the corresponding storage transistor. The stacked structure also includes a connection hole penetrating each of the device layers, the connection hole being filled with a conductor, and the conductor being in contact with each of the first electrode layers.

2. The storage array according to claim 1, characterized in that, Each of the device layers further includes a dielectric layer and a channel layer. The via includes a sub-via that penetrates each of the device layers. The dielectric layer is disposed on the gate pillar corresponding to the wall of the sub-via. The channel layer covers the wall of the sub-via. The channel layer is in contact with the dielectric layer, the first electrode layer, and the second electrode layer.

3. The storage array according to claim 2, characterized in that, The channel layer covers the entire wall of the sub-through hole.

4. The storage array according to claim 1, characterized in that, Each of the device layers further includes a dielectric layer and a channel layer, and the via includes a sub-via that penetrates each of the device layers, wherein the dielectric layer is disposed on the gate pillar corresponding to the wall of the sub-via; There is a gap between the first isolation layer and the wall of the sub-through hole, and the gap communicates with the sub-through hole. The channel layer includes a first channel layer disposed in the gap, and the first channel layer is in contact with the dielectric layer, the first electrode layer and the second electrode layer.

5. The storage array according to claim 4, characterized in that, The channel layer further includes a second channel layer, which is disposed on the surface of the first insulating layer facing the second electrode layer, and the second channel layer is in contact with the first channel layer.

6. The storage array according to claim 4 or 5, characterized in that, The channel layer further includes a third channel layer, which is disposed on the surface of the first isolation layer facing the first electrode layer, and the third channel layer is in contact with the first channel layer.

7. The storage array according to claim 1, characterized in that, Each of the device layers further includes a dielectric layer and a channel layer, and the via includes a sub-via penetrating each of the device layers; There is a gap between the first isolation layer and the wall of the sub-via, the gap is in communication with the sub-via, and an extension is provided on the gate post, the extension being disposed within the gap; The dielectric layer includes: a first dielectric layer disposed on the gate pillar corresponding to the hole wall of the sub-via, and a second dielectric layer wrapped around the extension, wherein the first dielectric layer and the second dielectric layer are in contact; The channel layer includes: a first channel layer located between the sub-through hole wall and the first medium layer, and a second channel layer located between the second medium layer and the gap sidewall, wherein the first channel layer and the second channel layer are in contact.

8. The storage array according to any one of claims 2-7, characterized in that, The dielectric layer in the adjacent device layer is in contact.

9. The storage array according to claim 8, characterized in that, The stacked structure further includes a second isolation layer, which may be multiple, with one second isolation layer disposed between adjacent device layers; the second isolation layer is in contact with the dielectric layer.

10. The storage array according to any one of claims 1-9, characterized in that, The second electrode layer includes a plurality of second electrode lines spaced apart along a direction parallel to the substrate; the through hole penetrates one of the second electrode lines; The projection of the connection hole on the substrate lies between the projections of two adjacent second electrode lines on the substrate within the same device layer.

11. A storage array, characterized in that, include: A memory string, the memory string comprising a plurality of memory transistors, wherein the gates of each memory transistor are electrically connected; A plurality of first electrode lines, each of the first electrode lines being electrically connected to a first electrode of one of the storage transistors; Multiple second electrode lines, one of which is electrically connected to the second electrode of one of the storage transistors; A conductor, which is spaced apart from the storage string, and the conductor is in contact with each of the first electrode lines.

12. A memory, characterized in that, include: The storage array according to any one of claims 1-11; A controller, which is electrically connected to the storage array.

13. An electronic device, characterized in that, include: The memory according to claim 12; A circuit board, on which the memory is disposed.

14. A read / write method for a storage array according to any one of claims 1-11, the storage array comprising a storage string, the storage string comprising a plurality of storage transistors, characterized in that, Reading data from the storage transistor includes: A first voltage is applied to the gate of each of the storage transistors in the memory string and to the first electrode of each of the storage transistors; Obtain the current of the second electrode of the storage transistor; The data stored in the storage transistor is obtained through the current.

15. The read / write method according to claim 14, characterized in that, Writing data into the storage transistor includes: A second voltage is applied to the gate of each of the storage transistors in the memory string and the second electrode of the storage transistor containing the data to be written, so that the storage transistor containing the data to be written is turned on, so as to write the first data into the storage transistor containing the data to be written. Alternatively, a third voltage, less than the second voltage, is applied to the gate of each of the storage transistors in the memory string and the second electrode of the storage transistor to be written, so as to write the second data into the storage transistor to be written.

16. A method for manufacturing a storage array, characterized in that, include: A stacked structure is formed on a substrate; the stacked structure includes multiple device layers stacked together, each device layer including a first intermediate layer, a first isolation layer and a second intermediate layer stacked together, the first isolation layer being located between the first intermediate layer and the second intermediate layer; the second intermediate layer is provided with a first opening penetrating therethrough, and the first opening is filled with an electrode plate; A through hole is formed on the stacked structure, the through hole penetrating each of the stacked structures, and the projection of the through hole on the substrate is located within the projection of the electrode plate on the substrate; A gate post is formed within the through-hole; The first intermediate layer is replaced with a first electrode layer, and the first electrode layer in each device layer serves as a first electrode of a storage transistor, the electrode plate in the device layer serves as a second electrode of the corresponding storage transistor, and the gate pillar serves as the gate of the corresponding storage transistor. Each of the first electrode layers is electrically connected; The first intermediate layer is replaced with a first electrode layer, and the electrical connection of each first electrode layer includes: forming a connection hole through the stacked structure, removing the first intermediate layer through the connection hole to form a third void layer, filling the connection hole and the third void layer with a conductive material to form a first electrode layer and a conductor connecting each first electrode layer.

17. The method for manufacturing a storage array according to claim 16, characterized in that, Before forming the gate post within the through-hole, the following is also included: A channel layer and a dielectric layer are sequentially formed on the wall of the through hole; the channel layer covers the entire wall of the through hole, and the dielectric layer covers the entire channel layer.

18. The method for manufacturing a storage array according to claim 17, characterized in that, Forming a stacked structure on the substrate further includes: forming an intermediate isolation layer between adjacent device layers; After forming the gate pillar, the method further includes: removing the intermediate isolation layer and the channel layer corresponding to the intermediate isolation layer to form a first void layer, and forming a second isolation layer within the first void layer.

19. The method for manufacturing a storage array according to claim 16, characterized in that, Before forming the gate post within the through-hole, the following is also included: A dielectric layer is formed on the wall of the through hole, and the dielectric layer covers the entire wall of the through hole; After forming the gate post within the through-hole, the method further includes: A connection hole is formed on the stacked structure, the connection hole penetrating each of the device layers; and a first isolation layer is removed through the connection hole to form a second void layer; A channel layer is formed on the sidewall of the second void layer, and the channel layer covers the dielectric layer, the electrode plate and the first intermediate layer corresponding to the second void layer; A third isolation layer is formed within the second void layer.

20. The method for manufacturing a storage array according to claim 16, characterized in that, Before forming the gate post within the through-hole, the following is also included: A portion of the first insulating layer is removed through the through-hole to form a gap; A first channel layer is formed on the wall of the through hole, and a second channel layer is formed on the side wall of the gap, wherein the second channel layer is in contact with the first channel layer. A first dielectric layer is formed on the first channel layer, and a second dielectric layer is formed on the second channel layer, wherein the first dielectric layer is in contact with the second dielectric layer; Forming a gate post within the through-hole includes filling the through-hole and the gap with a conductive material to form an extension within the gap and the gate post within the through-hole, wherein the extension contacts the gate post.

21. The method for manufacturing a storage array according to claim 16, characterized in that, Forming a stacked structure on the substrate further includes: forming a second opening through the first intermediate layer, filling the second opening with a source plate, wherein in the same device layer, the projection of the source plate on the substrate completely coincides with the projection of the electrode plate on the substrate.

22. The method for manufacturing a storage array according to any one of claims 16-21, characterized in that, After forming the gate post within the through-hole, the method further includes: A conductive connector is formed in the second intermediate layer, and the conductive connector contacts the electrode plate to form a second electrode line.

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