Configuration update method and apparatus for chip and chip

Abstract

The application relates to the technical field of chip configuration updating, and discloses a configuration updating method for a chip, the chip comprising a memory and a memory protection unit, the memory protection unit comprising a configuration register, the configuration register being configured to store physical address information and corresponding permission information of one or more regions of the memory; the method comprising: obtaining target physical address information and corresponding target permission information that need to be updated, and updated updated physical address information and corresponding updated permission information; and updating the target physical address information and the corresponding target permission information into the updated physical address information and the corresponding updated permission information. The method can simultaneously update the physical address information and the corresponding permission information stored by the memory protection unit, and realizes that different access permissions can take effect simultaneously when multiple cores simultaneously access the same memory. The application further discloses a configuration updating device for a chip and the chip.

Description

Technical Field

[0001] This application relates to the field of chip configuration update technology, and for example to a method, apparatus and chip for updating chip configuration. Background Technology

[0002] Currently, most memory in chips (such as automotive electronic chips) is designed with an MPU (memory protection unit) mechanism, which allows different CPUs (Central Processing Units) or DMA (Direct Memory Access) access permissions to be configured for the same memory block.

[0003] When multiple cores need to access memory, related technologies can easily lead to the CPU entering an abnormal state. The reason is that the MPU (Multi-Core Processing Unit) mechanism takes effect during multi-core memory access. Since the physical address range protected by the MPU and the corresponding permission information need to be configured separately, it's easy for the upper or lower limit of the physical address range to be configured before the entire physical address range is configured, and then the previous MPU permission happens to restrict the current memory region from being writable—that is, the MPU protection mechanism does not take effect as expected. In this case, the CPU detects illegal access and directly enters an unrecoverable abnormal state.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a configuration update method, apparatus, and chip for a chip, which can simultaneously update the physical address information and corresponding permission information stored in the memory protection unit. This enables different access permissions to take effect simultaneously when multiple cores access the same memory, thereby improving the stability of multi-core memory access.

[0007] In some embodiments, the chip includes memory and a memory protection unit. The memory protection unit includes a configuration register configured to store physical address information and corresponding permission information of one or more regions of memory. The configuration update method for the chip includes: obtaining target physical address information and corresponding target permission information to be updated, as well as updated physical address information and corresponding updated permission information; and updating the target physical address information and corresponding target permission information to the updated physical address information and corresponding updated permission information.

[0008] Optionally, obtaining the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information, includes: upon receiving an update instruction for the physical address information and the corresponding permission information of the memory, parsing the update instruction to obtain the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information.

[0009] Optionally, the physical address information and the corresponding permission information belong to the same update instruction; updating the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information includes: rewriting the target physical address information and the corresponding target permission information into the same instruction as update the physical address information and the corresponding update permission information.

[0010] Optionally, before updating the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information, the method further includes: unlocking the configuration register so that the configuration register can be updated.

[0011] Optionally, the memory includes a password register.

[0012] Optionally, unlocking the configuration register includes writing a valid password to the password register to unlock the configuration register.

[0013] Optionally, after updating the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information, the following steps are included: disabling the configuration register from being updated.

[0014] Optionally, preventing the configuration register from being updated includes writing an invalid password into the password register to prevent the configuration register from being updated.

[0015] In some embodiments, the configuration update device for the chip includes an acquisition module configured to acquire target physical address information to be updated and corresponding target permission information, as well as updated physical address information and corresponding update permission information; and an update module configured to update the target physical address information and corresponding target permission information to updated physical address information and corresponding update permission information.

[0016] In some embodiments, the configuration update apparatus for a chip includes a processor and a memory storing program instructions, the processor being configured to execute the configuration update method for a chip as described above when the program instructions are executed.

[0017] In some embodiments, the chip includes: a chip body including memory and a memory protection unit; wherein the memory protection unit includes a configuration register configured to store physical address information and corresponding permission information of one or more regions of memory; and the configuration update device for the chip described above is installed on the chip body.

[0018] The configuration update method, apparatus, and chip for chips provided in this disclosure can achieve the following technical effects:

[0019] By storing the physical address information of memory and its corresponding permission information in the same configuration register, updating the configuration information of the memory protection unit allows for simultaneous modification of the physical address range protected by the memory protection unit and the read / write permissions for that physical address range. This ensures that the protected physical address range and corresponding access permissions take effect simultaneously, resolving the issue in related technologies where the categorized configuration of physical address information and corresponding permission information during memory protection unit configuration changes leads to unexpected MPU protection mechanisms taking effect, causing the processor to enter an unrecoverable abnormal state. Furthermore, by simultaneously updating the physical address information and corresponding permission information stored in the memory protection unit, different access permissions can take effect simultaneously when multiple cores access the same memory, improving the stability of multi-core memory access.

[0020] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0022] Figure 1 This is a schematic diagram of the implementation environment for the chip configuration update method;

[0023] Figure 2 This is a schematic diagram of a configuration update method for a chip provided in an embodiment of this disclosure;

[0024] Figure 3 This is a schematic diagram of another configuration update method for a chip provided in an embodiment of this disclosure;

[0025] Figure 4 This is a schematic diagram of another configuration update method for a chip provided in an embodiment of this disclosure;

[0026] Figure 5 This is a schematic diagram of a configuration update device for a chip provided in an embodiment of this disclosure;

[0027] Figure 6 This is a schematic diagram of another configuration update device for a chip provided in an embodiment of this disclosure;

[0028] Figure 7 This is a structural block diagram of a chip provided in an embodiment of this disclosure. Detailed Implementation

[0029] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0030] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0031] Unless otherwise stated, the term "multiple" means two or more.

[0032] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0033] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0034] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0036] Currently, when there is a need for multi-core memory access, the CPU is prone to entering an abnormal state. The reason is that the MPU mechanism takes effect under multi-core memory access conditions. Since the physical address range protected by the MPU and the corresponding permission information need to be configured separately, it's easy for the upper or lower limit of the physical address range to be configured, but before the entire physical address range can be configured, the previous MPU permission might restrict the current memory region from being writable, meaning the MPU protection mechanism doesn't take effect as expected. In this case, the CPU detects illegal out-of-bounds access and directly enters an unrecoverable abnormal state.

[0037] In view of this, the present disclosure provides a configuration update method for a chip, which can simultaneously update the physical address information and corresponding permission information stored in the memory protection unit, so that different access permissions can take effect simultaneously when multiple cores access the same memory.

[0038] Figure 1 This is a schematic diagram of the implementation environment of an embodiment of this disclosure. For example... Figure 1 As shown, the implementation environment may include memory, a memory protection unit, and a control unit.

[0039] The memory protection unit includes configuration registers. These registers contain information storage units located within a subset of bytes of the memory protection unit. These information storage units are configured to store the physical address information and corresponding access permissions for one or more memory regions. The memory protection unit defines the attributes of the memory regions and the access permissions to the memory.

[0040] The physical address information and corresponding permission information represent the physical address range of the memory region and the permissions granted to that physical address range. Permissions include read, write, and execute permissions.

[0041] It should be noted that in related technologies, physical address information and corresponding permission information are stored in different registers; that is, physical address information is stored in the address register (e.g., the physical address information is located in the first 2 bits of the address register), and permission information is stored in the permission register (e.g., the permission information is located in the first 2 bits of the permission register). In this embodiment, the physical address information and corresponding permission information are stored in the same register, namely the configuration register (e.g., the physical address information and corresponding permission information are located in the information storage unit of the configuration register, and the information storage unit is located in the first 4 bits of the configuration register). This allows for simultaneous updating of both the physical address information and the corresponding permission information when updating the physical address information and the corresponding permission information.

[0042] The control unit, including the processor, is configured as a configuration update method for the control chip.

[0043] Optionally, the memory includes a password register, configured to either write a valid password to unlock the configuration register or write an invalid password to lock the configuration register.

[0044] Optionally, the memory also includes a verification register. The verification register is configured to store a preset valid password.

[0045] Optionally, the memory also includes a comparator. The comparator is configured to compare whether the write password written to the password register matches the preset valid password stored in the verification register. If they match, the write password written to the password register is determined to be a valid password; if they do not match, the password written to the password register is determined to be an invalid password.

[0046] Optionally, the default valid password is represented as a series of binary bits, and the password written in the password register is also represented as a series of binary bits.

[0047] Optionally, the memory also includes logic gates configured to logically evaluate each bit of the preset valid password and the written password. When a logic gate outputs a high level, it indicates that the corresponding bit of the written password matches the corresponding bit of the preset valid password; when a logic gate outputs a low level, it indicates that the corresponding bit of the written password does not match the corresponding bit of the preset valid password. If all bits of the written password match the corresponding bits of the preset valid password, a valid password is determined to be written into the password register; if any bit of the written password does not match the corresponding bit of the preset valid password, an invalid password is determined to be written into the password register.

[0048] Alternatively, the chip can be an automotive electronic chip.

[0049] Combination Figure 1The implementation environment shown in this disclosure provides a configuration update method for a chip, such as... Figure 2 As shown, the configuration update method includes:

[0050] S201, the processor obtains the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information.

[0051] It is understandable that the configuration information before the update includes the target physical address information and the corresponding target permission information. The configuration information after the update includes the updated physical address information and the corresponding updated permission information.

[0052] S202, the processor updates the target physical address information and the corresponding target permission information to update the physical address information and the corresponding updated permission information.

[0053] The chip configuration update method provided in this disclosure stores the physical address information and corresponding permission information of the memory in the same configuration register. This allows for simultaneous modification of the physical address range protected by the memory protection unit and the read / write permissions for that range when updating the configuration information of the memory protection unit. This ensures that the protected physical address range and corresponding access permissions take effect simultaneously, solving the problem in related technologies where the categorized configuration of physical address information and corresponding permission information during memory protection unit configuration changes leads to unexpected MPU protection mechanisms taking effect, causing the processor to enter an unrecoverable abnormal state. Furthermore, by simultaneously updating the physical address information and corresponding permission information stored in the memory protection unit, different access permissions can take effect simultaneously when multiple cores access the same memory, improving the stability of multi-core memory access.

[0054] Optionally, the processor obtains the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding updated permission information, by: upon receiving an update instruction for the physical address information and the corresponding permission information of memory, the processor parses the update instruction to obtain the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding updated permission information.

[0055] In this disclosed embodiment, the received update instruction is parsed to understand and execute it, thereby obtaining the address and access permissions of the memory region to be updated, as well as the address and access permissions of the updated memory region. In this way, by simultaneously updating the physical address information and the corresponding permission information, the unexpected MPU protection mechanism is prevented from taking effect, effectively managing and scheduling system memory resources, thus enabling correct and secure memory access during multi-core memory access.

[0056] Optionally, the physical address information and the corresponding permission information belong to the same update instruction. Since the processor executes one instruction sequentially within one clock cycle, setting the physical address information and the corresponding permission information to the same update instruction allows the processor to update both the physical address information and the corresponding permission information simultaneously.

[0057] Optionally, the processor updates the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information by rewriting the target physical address information and the corresponding target permission information into the same entry.

[0058] In this disclosed embodiment, by rewriting the target physical address information and the corresponding target permission information into the same entry as updated physical address information and the corresponding updated permission information, the target physical address information and the corresponding target permission information are simultaneously updated to updated physical address information and the corresponding updated permission information. This allows for the simultaneous modification of the physical address range protected by the memory protection unit and the read / write permissions for that physical address range, ensuring that the physical address range protected by the memory protection unit and the corresponding access permissions are both effective simultaneously.

[0059] Optionally, before the processor updates the target physical address information and the corresponding target permission information to update the updated physical address information and the corresponding updated permission information, the processor further includes: unlocking the configuration register so that the configuration register can be updated.

[0060] Combination Figure 3 As shown, this disclosure provides another method for configuring and updating a chip, including:

[0061] S301, the processor obtains the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information.

[0062] S302, the processor unlocks the configuration register so that the configuration register can be updated.

[0063] S303, the processor updates the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information.

[0064] In this disclosed embodiment, by unlocking the configuration register, the physical address information and corresponding permission information of the configuration register can be updated. In this way, when it is allowed to change the physical address information and corresponding permission information, the target physical address information and the corresponding target permission information can be updated simultaneously to update the physical address information and the corresponding update permission information, thus avoiding accidental updates to the information in the configuration register.

[0065] Optionally, the processor unlocking the configuration register includes: the processor providing an enable signal to the configuration register to unlock it. This allows the physical address information and corresponding permission information of the configuration register to be updated.

[0066] Optionally, the processor unlocking the configuration register includes: the processor writing a valid password to the password register to unlock the configuration register.

[0067] For example, the valid password to be written to the password register is determined as follows: The write password to the password register is determined. The write password is compared with a preset valid password. If the write password matches the preset valid password, the valid password is determined to be written to the password register.

[0068] For example, the valid password to be written to the password register is determined as follows: The write password to be written to the password register is determined. A logical judgment is performed on each bit of the write password to ensure it corresponds to a preset valid password, and the logical judgment result is obtained. Based on the logical judgment result, the valid password is determined to be written to the password register.

[0069] For example, logical judgment is performed on each bit of the written password as the corresponding bit value of the preset valid password, and the logical judgment result includes: when the logic gate outputs a high level, it is determined that the bit value of the written password matches the corresponding bit value of the preset valid password.

[0070] For example, determining to write a valid password into the password register based on the logical judgment result includes: determining that a valid password is written into the password register when all bit values ​​of the written password match the corresponding bit values ​​of the preset valid password.

[0071] Here, "valid password" represents the correct password. "Preset valid password" represents the preset correct password.

[0072] In this disclosed embodiment, a valid password is written into the password register to unlock the configuration register, thereby allowing the physical address information and corresponding permission information in the configuration register to be modified. This ensures that, while allowing modification of the physical address information and corresponding permission information, the target physical address information and corresponding target permission information are simultaneously updated to update the physical address information and corresponding update permission information, preventing accidental updates to the information in the configuration register.

[0073] Combination Figure 4 As shown, this disclosure provides another method for configuring and updating a chip, including:

[0074] S401, the processor obtains the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information.

[0075] S402, the processor unlocks the configuration register so that the configuration register can be updated.

[0076] S403, the processor updates the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information.

[0077] S404, the processor configuration register is prevented from being updated.

[0078] In this disclosed embodiment, by disabling the updating of the physical address information and corresponding permission information of the configuration register, it is possible to avoid accidental updates to the information in the configuration register after the physical address information and corresponding permission information have been changed.

[0079] Optionally, preventing the configuration register from being updated by the processor includes: the processor providing an enable signal to lock the configuration register, thereby preventing the configuration register from being updated. This prevents the physical address information and corresponding permission information of the configuration register from being updated, avoiding accidental modification of these information.

[0080] Optionally, preventing the configuration register from being updated by the processor includes writing an invalid password into the password register to prevent the configuration register from being updated.

[0081] For example, determining whether to write an invalid password to the password register is done as follows: Determine the write password to be written to the password register. Compare the write password with a preset valid password. If the write password does not match the preset valid password, determine that an invalid password has been written to the password register.

[0082] For example, the invalid password to be written to the password register is determined as follows: The write password to be written to the password register is determined. A logical judgment is performed on each bit of the write password that corresponds to a preset valid password, and the logical judgment result is obtained. Based on the logical judgment result, it is determined that an invalid password is written to the password register.

[0083] For example, a logical judgment is performed on each bit of the written password, which is the corresponding bit value of the preset valid password. The logical judgment result includes: when the logic gate outputs a low level, it is determined that the bit value of the written password does not match the corresponding bit value of the preset valid password.

[0084] For example, determining that an invalid password is written to the password register based on the logical judgment result includes: if the bit value of the written password does not match the corresponding bit value of the preset valid password, determining that an invalid password is written to the password register.

[0085] Invalid password means an incorrect password.

[0086] In this disclosed embodiment, by writing an invalid password into the password register, the physical address information and corresponding permission information in the configuration register are prevented from being changed. This avoids accidental updates to the information in the configuration register.

[0087] Combination Figure 5 As shown, this embodiment of the disclosure provides a configuration update device 200 for a chip, including an acquisition module 21 and an update module 22. The acquisition module 21 is configured to acquire target physical address information to be updated and corresponding target permission information, as well as updated physical address information and corresponding update permission information. The update module 22 is configured to update the target physical address information and corresponding target permission information to updated physical address information and corresponding update permission information.

[0088] The configuration update device 200 for chips provided in this embodiment can simultaneously update the physical address information and corresponding permission information stored in the memory protection unit, so that different access permissions can take effect at the same time when multiple cores access the same memory.

[0089] Combination Figure 6As shown, this disclosure provides a configuration update device 300 for a chip, including a processor 600 and a memory 601. Optionally, the device may further include a communication interface 602 and a bus 603. The processor 600, communication interface 602, and memory 601 can communicate with each other via the bus 603. The communication interface 602 can be used for information transmission. The processor 600 can call logical instructions in the memory 601 to execute the configuration update method for the chip described in the above embodiment.

[0090] Furthermore, the logic instructions in the aforementioned memory 601 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0091] The memory 601, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 600 executes functional applications and data processing by running the program instructions / modules stored in the memory 601, thereby implementing the configuration update method for the chip described in the above embodiments.

[0092] The memory 601 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 601 may include high-speed random access memory and may also include non-volatile memory.

[0093] Combination Figure 7 As shown, this disclosure provides a chip 1, including a chip body 100 and the aforementioned configuration update device 200 (300) for the chip. The table-building device 200 (300) for Flash memory is mounted on the chip body 100. The mounting relationship described herein is not limited to placement inside the chip body 100, but also includes mounting connections with other components of the chip 1, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the configuration update device 200 (300) for the chip can be adapted to any feasible chip body to achieve other feasible embodiments.

[0094] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described configuration update method for a chip.

[0095] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0096] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0097] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0098] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0099] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A configuration update method for a chip, characterized in that, The chip includes memory and a memory protection unit. The memory protection unit includes a configuration register, which is configured to store the physical address information and corresponding access information of one or more memory regions. The method includes: Obtain the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information; obtaining the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information, includes: upon receiving an update instruction for the physical address information and the corresponding permission information in memory, parsing the update instruction to obtain the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information; the physical address information and the corresponding permission information belong to the same update instruction; Update the target physical address information and the corresponding target permission information to the updated physical address information and the corresponding updated permission information; update the target physical address information and the corresponding target permission information to the updated physical address information and the corresponding updated permission information, including: rewriting the target physical address information and the corresponding target permission information into the same entry as the updated physical address information and the corresponding updated permission information.

2. The configuration update method according to claim 1, characterized in that, Before updating the target physical address information and the corresponding target permission information to update the physical address information and the corresponding update permission information, it also includes: Unlock the configuration register so that it can be updated.

3. The configuration update method according to claim 2, characterized in that, The memory includes a password register and an unlock configuration register, including: Write a valid password into the password register to unlock the configuration register.

4. The configuration update method according to claim 2, characterized in that, After updating the target physical address information and the corresponding target permission information to update the physical address information and the corresponding updated permission information, the following is included: Configuration registers cannot be updated.

5. The configuration update method according to claim 4, characterized in that, Prevent configuration registers from being updated, including: Write an invalid password into the password register to prevent the configuration register from being updated.

6. A configuration update apparatus for a chip, characterized in that, include: The acquisition module is configured to obtain the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information. Obtaining the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information, includes: upon receiving an update instruction for the physical address information and the corresponding permission information in memory, parsing the update instruction to obtain the target physical address information to be updated and the corresponding target permission information, as well as the updated physical address information and the corresponding update permission information; the physical address information and the corresponding permission information belong to the same update instruction; The update module is configured to update the target physical address information and the corresponding target permission information to update the updated physical address information and the corresponding updated permission information; updating the target physical address information and the corresponding target permission information to update the updated physical address information and the corresponding updated permission information includes: rewriting the target physical address information and the corresponding target permission information into the same entry as the updated physical address information and the corresponding updated permission information.

7. A configuration update apparatus for a chip, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform the configuration update method for a chip as described in any one of claims 1 to 5 when executing the program instructions.

8. A chip, characterized in that, include: The chip body includes memory and a memory protection unit; wherein, the memory protection unit includes a configuration register, which is configured to store the physical address information and corresponding permission information of one or more regions of memory; and, The configuration update device for a chip as described in claim 6 or 7 is installed on the chip body.

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