Phase-locked loop hundred picosecond level clock regulation method, device and system and storage medium
By using carrier phase observation and phase-locked loop (PLL) technology, combined with second-order PLL for frequency and phase control, the dependence of BeiDou time receivers on real-time precision orbit and clock difference products has been resolved, achieving high-precision clock control at the picosecond level and improving the stability and accuracy of time and frequency synchronization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIHANG UNIV
- Filing Date
- 2024-01-29
- Publication Date
- 2026-07-14
AI Technical Summary
Existing BeiDou time receivers rely heavily on real-time precision orbit and clock difference products for high-precision time and frequency applications, resulting in poor accuracy of OCXO crystal oscillators and difficulty in achieving picosecond-level clock control.
By employing carrier phase observation combined with phase-locked loop (PLL) technology, and through carrier phase differential time transmission, precise satellite orbit and clock bias calculations are used, combined with a second-order PLL for precise frequency and phase control, reducing reliance on real-time precision orbit and clock bias products, and achieving picosecond-level clock control.
It achieves high-precision clock control, reduces time transmission errors, has real-time performance and scalability, lowers costs, avoids dependence on real-time precision tracks and clock difference products, and improves the stability and accuracy of time and frequency synchronization.
Smart Images
Figure CN117826570B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-precision clock control and time-frequency synchronization technology for Global Navigation Satellite System (GNSS), and in particular to a phase-locked loop (PLL) method, device, system, and storage medium for controlling a picosecond-level clock. Background Technology
[0002] Clock control generally includes two methods: phase modulation and frequency modulation. Phase modulation refers to directly changing the phase of the local clock to a preset phase value. However, frequent phase modulation can lead to discontinuities in the phase of the clock output signal and cause frequency jumps, reducing clock stability. In contrast, frequency modulation avoids phase jumps by slowly changing the frequency of the clock output signal, ensuring clock phase stability. Based on the effects of phase modulation and frequency modulation on the clock, there is usually a large clock difference between the crystal clock and the time reference when the crystal clock is first powered on. Therefore, coarse phase adjustment can be used to quickly converge the clock difference, bringing the phase of the local clock closer to the reference signal. When the clock difference is small, fine frequency adjustment is used to slowly converge the clock difference phase while minimizing disruption to the clock's own frequency stability. This control strategy can balance the requirements of clock accuracy and stability.
[0003] The BeiDou Navigation Satellite System (BDS) provides all-weather, full-frequency global positioning, navigation, and timing services. In the timing field, using BeiDou receivers offers advantages such as high accuracy, low cost, and stability, leading to their increasingly widespread application. When using BeiDou timing receivers for high-precision time and frequency applications, precise control of the crystal oscillator is required using a clock control model. The accuracy of one-way timing from a BeiDou receiver depends on the accuracy of the satellite ephemeris product. For pseudorange point positioning technology, the accuracy of the receiver clock bias calculated using broadcast ephemeris is approximately 20 nanoseconds. Therefore, existing methods for achieving accurate timing have the following drawbacks: clock control is highly dependent on real-time precise orbit and clock bias products; and the accuracy of using BeiDou shared broadcast ephemeris to control the OCXO crystal oscillator is poor. Summary of the Invention
[0004] This invention addresses the aforementioned problems in the prior art. Therefore, there is a need for a phase-locked loop (PLL) method, apparatus, system, and storage medium for picosecond-level clock control, combining precise single-point positioning technology based on carrier phase observations. The accuracy of the receiver clock bias calculated using precise satellite orbits and clock bias is approximately 0.2 nanoseconds. In high-precision data processing, carrier phase differential observations not only eliminate errors such as ephemeris residuals and atmospheric residuals but also restore the integer characteristics of double-difference integer ambiguities, enabling rapid picosecond-level time and frequency services. Utilizing carrier phase differential time transfer, the receiver receives observation information from the reference station at the network end, avoiding the drawbacks of relying on precise satellite orbits and clock bias products.
[0005] According to a first aspect of the present invention, a method for controlling a picosecond-level clock in a phase-locked loop is provided, the method comprising:
[0006] Based on the receiver clock difference between epochs of the oscillator clock:
[0007]
[0008] In the formula, "[·]" indicates rounding to the nearest integer, y(i) represents the clock adjustment amount of epoch i, and t epoch Let z represent the time interval between adjacent epochs, and z be the minimum digital adjustment of the voltage-controlled crystal oscillator. During initialization, the receiver clock bias estimated by the DPT time transfer is expressed as:
[0009] dt r (i)=t tran (i)+dt r ′(i) (2)
[0010] Among them, dt r (i) is the receiver clock bias estimated during initialization, t tran (i) is the error during DPT initialization, dt r ′(i) is the receiver clock bias;
[0011] After the initial estimation of the receiver clock bias, the receiver crystal oscillator is adjusted via frequency control. During the oscillation process, an expected time length T0 is added. The expected change in the receiver clock bias is obtained by setting the expected time length T0 for frequency compensation, as shown in equation (3).
[0012]
[0013] The corresponding clock control amount is:
[0014]
[0015] During the real-time control of the local crystal oscillator, iterative calculations are performed for each epoch to ensure that the crystal oscillator clock after DPT convergence is locked to the time-frequency reference using equation (4).
[0016] The frequency deviation between the reference time and the controlled crystal oscillator is obtained. A digital-to-analog converter (DAC) is used to convert the digital frequency deviation into a corresponding voltage adjustment value. This voltage adjustment value is then used to adjust the crystal oscillator in real time. The frequency adjustment range is:
[0017] f A =f0±Δf (5)
[0018] Where f0 is the nominal frequency value of the OCXO crystal oscillator; ±Δf is the adjustable upper and lower bounds of the deviation between the actual operating frequency and the nominal frequency of the OCXO crystal oscillator;
[0019] The estimated adjustment value for the minimum frequency deviation is:
[0020]
[0021] In the formula, V max The maximum adjustable voltage value, V min V is the adjustable minimum voltage value, and f is the adjustable voltage range. max f is the adjustable maximum frequency value. min The minimum adjustable frequency value can be converted into a voltage regulation value through equation (6).
[0022] Furthermore, the method also includes:
[0023] The steady-state phase difference is calculated using the following formula:
[0024]
[0025] in For steady-state phase difference, E(s) is the error propagation function, and θ is the error transfer function. i (s) is the input signal;
[0026] A second-order ring consists of an integrator and a constant term, i.e.
[0027]
[0028] In the formula, τ1 represents the coefficient of the integrator, and τ2 represents the coefficient of the constant term;
[0029] The loop transfer function H(s) and the error transfer function E(s) are expressed as follows:
[0030]
[0031]
[0032] In the formula, K1 represents the coefficient of the digital-to-analog converter in the second-order phase-locked loop circuit, K2 represents the coefficient of the ocxo in the second-order phase-locked loop circuit, and s represents the variable of the Laplace transform in the principle of automatic control.
[0033] Rewriting the denominators in equations (8) and (9) in normalized form, we get:
[0034]
[0035] In the formula ω n Let ζ represent the characteristic frequency of the loop, and ζ represent the damping coefficient; using equation (10), the transfer function H(s) and error transfer function E(s) of the loop are expressed as:
[0036]
[0037] Based on the superposition of various noises, the power spectral density S of the output noise of the second-order phase-locked loop is... o (f) is represented as:
[0038] S o (f)=S ref (f)+S DAC (f)+S OCXO (f) (12)
[0039] Among them, S ref (f) and S OCXO (f) represents the power spectral density of the precision time-transfer noise and the power spectral density of the oscillator's free oscillation, respectively. DAC (f) represents the power spectral density of phase jitter noise introduced by the digital-to-analog conversion module. The parameters of the second-order phase-locked loop are determined by quantizing the noise through digital-to-analog conversion and modeling the noise.
[0040] The damping coefficient ζ is determined based on its effectiveness in suppressing input noise.
[0041] The characteristic frequency ω is determined based on the total output phase variance. n .
[0042] Furthermore, the damping coefficient ζ was determined to be 0.707.
[0043] Furthermore, the characteristic frequency ω is determined based on the total output phase variance. n ,include:
[0044] Based on the principle of minimizing the total output phase variance of the system, the equivalent noise bandwidth B of the second-order phase-locked loop is determined. n for:
[0045]
[0046] Bandwidth B nTake the intersection frequency f c The characteristic frequency ω is obtained through equation (14). n :
[0047]
[0048] According to a second technical solution of the present invention, a picosecond-level clock control device for a phase-locked loop is provided. The device includes a precise clock control module, which is configured to:
[0049] Based on the receiver clock difference between epochs of the oscillator clock:
[0050]
[0051] In the formula, "[·]" indicates rounding to the nearest integer, y(i) represents the clock adjustment amount of epoch i, and t epoch Let z represent the time interval between adjacent epochs, and z be the minimum digital adjustment of the voltage-controlled crystal oscillator. During initialization, the receiver clock bias estimated by the DPT time transfer is expressed as:
[0052] dt r (i)=t tran (i)+dt r ′(i) (2)
[0053] Among them, dt r (i) is the receiver clock bias estimated during initialization, t tran (i) is the error during DPT initialization, dt r ′(i) is the receiver clock bias;
[0054] After the initial estimation of the receiver clock bias, the receiver crystal oscillator is adjusted via frequency control. During the oscillation process, an expected time length T0 is added. The expected change in the receiver clock bias is obtained by setting the expected time length T0 for frequency compensation, as shown in equation (3).
[0055]
[0056] The corresponding clock control amount is:
[0057]
[0058] During the real-time control of the local crystal oscillator, iterative calculations are performed for each epoch to ensure that the crystal oscillator clock after DPT convergence is locked to the time-frequency reference using equation (4).
[0059] The frequency deviation between the reference time and the controlled crystal oscillator is obtained. A digital-to-analog converter (DAC) is used to convert the digital frequency deviation into a corresponding voltage adjustment value. This voltage adjustment value is then used to adjust the crystal oscillator in real time. The frequency adjustment range is:
[0060] f A =f0±Δf (5)
[0061] Where f0 is the nominal frequency value of the OCXO crystal oscillator; ±Δf is the adjustable upper and lower bounds of the deviation between the actual operating frequency and the nominal frequency of the OCXO crystal oscillator;
[0062] The estimated adjustment value for the minimum frequency deviation is:
[0063]
[0064] In the formula, V max The maximum adjustable voltage value, V min V is the adjustable minimum voltage value, and f is the adjustable voltage range. max f is the adjustable maximum frequency value. min The minimum adjustable frequency value can be converted into a voltage regulation value through equation (6).
[0065] Furthermore, the device also includes a crystal oscillator clock control module, which is configured to:
[0066] The steady-state phase difference is calculated using the following formula:
[0067]
[0068] in For steady-state phase difference, E(s) is the error propagation function, and θ is the error transfer function. i (s) is the input signal;
[0069] A second-order ring consists of an integrator and a constant term, i.e.
[0070]
[0071] In the formula, τ1 represents the coefficient of the integrator, and τ2 represents the coefficient of the constant term;
[0072] The loop transfer function H(s) and the error transfer function E(s) are expressed as follows:
[0073]
[0074]
[0075] In the formula, K1 represents the coefficient of the digital-to-analog converter in the second-order phase-locked loop circuit, K2 represents the coefficient of the ocxo in the second-order phase-locked loop circuit, and s represents the variable of the Laplace transform in the principle of automatic control.
[0076] Rewriting the denominators in equations (8) and (9) in normalized form, we get:
[0077]
[0078] In the formula ω n Let ζ represent the characteristic frequency of the loop, and ζ represent the damping coefficient; using equation (10), the transfer function H(s) and error transfer function E(s) of the loop are expressed as:
[0079]
[0080] Based on the superposition of various noises, the power spectral density S of the output noise of the second-order phase-locked loop is... o (f) is represented as:
[0081] S o (f)=S ref (f)+S DAC (f)+S OCXO (f) (12)
[0082] Among them, S ref (f) and S OCXO (f) represents the power spectral density of the precision time-transfer noise and the power spectral density of the oscillator's free oscillation, respectively. DAC (f) represents the power spectral density of phase jitter noise introduced by the digital-to-analog conversion module. The parameters of the second-order phase-locked loop are determined by quantizing the noise through digital-to-analog conversion and modeling the noise.
[0083] The damping coefficient ζ is determined based on its effectiveness in suppressing input noise.
[0084] The characteristic frequency ω is determined based on the total output phase variance. n .
[0085] Furthermore, the damping coefficient ζ was determined to be 0.707.
[0086] Furthermore, the crystal oscillator clock control module is further configured as follows:
[0087] Based on the principle of minimizing the total output phase variance of the system, the equivalent noise bandwidth B of the second-order phase-locked loop is determined. n for:
[0088]
[0089] Bandwidth B n Take the intersection frequency f cThe characteristic frequency ω is obtained through equation (14). n :
[0090]
[0091] According to a third technical solution of the present invention, a phase-locked loop picosecond-level clock control system is provided, the system comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the method described above.
[0092] According to a fourth technical solution of the present invention, a non-transitory computer-readable storage medium storing instructions is provided, which, when executed by a processor, performs the method described above.
[0093] The phase-locked loop picosecond-level clock control method, apparatus, system, and storage medium according to various embodiments of the present invention have at least the following technical effects:
[0094] (1) The present invention has good usability: the carrier phase single difference time transfer can accurately transfer a high-precision time and frequency reference source, thereby greatly reducing the impact of the error introduced by the time transfer on clock control.
[0095] (2) Real-time performance: This method can perform real-time and precise crystal clock control in the time synchronization / timing receiver, and can reproduce the time and frequency results consistent with the reference clock in real time at the terminal.
[0096] (3) High scalability: This method can meet the time and frequency synchronization of hundreds of picoseconds in different baseline scenarios, with low cost and high mobility.
[0097] (4) This invention avoids the dependence on real-time precision track and clock difference products when controlling the crystal oscillator clock, and also solves the problem of poor accuracy of OCXO crystal oscillator when using Beidou co-broadcast ephemeris control. Attached Figure Description
[0098] In drawings that are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. The same reference numerals with or without letter suffixes may indicate different instances of similar parts. The drawings generally illustrate various embodiments by way of example rather than limitation and, together with the description and claims, serve to explain embodiments of the invention. Where appropriate, the same reference numerals are used in all drawings to refer to the same or similar parts. Such embodiments are illustrative and not intended to be exhaustive or exclusive embodiments of the apparatus or method.
[0099] Figure 1 A block diagram of a clock precision control structure based on DPT time transfer according to an embodiment of the present invention is shown.
[0100] Figure 2 A schematic diagram of a second-order phase-locked loop OCXO crystal oscillator clock control circuit according to an embodiment of the present invention is shown.
[0101] Figure 3 A structural diagram of a phase-locked loop picosecond-level clock control device according to an embodiment of the present invention is shown.
[0102] Figure 4 Another structural diagram of a phase-locked loop picosecond-level clock control device according to an embodiment of the present invention is shown. Detailed Implementation
[0103] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and specific examples, but this is not intended to limit the present invention. If there is no necessary sequential relationship between the various steps described herein, the order in which they are described as examples should not be considered a limitation. Those skilled in the art should understand that the order can be adjusted, as long as it does not disrupt the logical consistency between them and render the entire process impossible.
[0104] Explanation of technical terms:
[0105] DPT stands for Differential Precise Time Transfer, which refers to the BeiDou differential precision time transfer.
[0106] DAC: Digital-to-Analog Converter.
[0107] OCXO: The full English name is Oven Controlled Crystal Oscillator; a thermostatic crystal oscillator is also known as a thermostatic crystal oscillator.
[0108] This invention provides a picosecond-level clock control method using a phase-locked loop (PLL). This method enables precise clock control, which is crucial for achieving high-precision time-frequency synchronization. OCXOs (Optical Characteristic Crystal Oscillators) offer high short-term stability, while BeiDou differential precision time transfer provides high long-term stability. By combining these two methods, the time-frequency output of the time synchronization terminal can achieve high stability in both the short and long term.
[0109] The clock precision control structure based on BeiDou Differential Precise Time Transfer (DPT) is shown in the diagram below. Figure 1As shown, the precision clock controller, as a crucial component, receives the clock error parameters from the BeiDou differential precise time transfer solution. By analyzing and processing these parameters, it can accurately estimate clock drift and deviation. Then, based on the estimated clock state, the controller generates corresponding control quantities, which are converted into voltage quantities and applied to the temperature-controlled crystal oscillator (OCXO) to regulate the crystal oscillator's frequency. Therefore, the precision clock controller can achieve precise control of the clock frequency, ensuring it remains consistent with the reference time introduced by the DPT. The regulated clock state will be reflected in the BeiDou differential precise time transfer solution of the next epoch, achieving closed-loop control and ultimately outputting a high-precision time and frequency signal consistent with the reference clock.
[0110] In the case of real-time transmission of reference time information using DPT time-frequency transfer, the clock adjustment amount is calculated using the current clock difference value and relative frequency deviation. Simultaneously, to ensure that over-adjustment does not occur when the clock difference is small, and to achieve rapid convergence when the clock difference is large, the receiver clock difference is estimated through precise time transfer, and then the inter-epoch receiver clock difference of the oscillator clock is obtained.
[0111]
[0112] In the formula, "[·]" indicates rounding to the nearest integer, y(i) represents the clock adjustment amount of epoch i, and t epoch Let z represent the time interval between adjacent epochs, and z be the minimum digital adjustment of the voltage-controlled crystal oscillator. During initialization, the receiver clock bias estimated by the DPT time transfer consists of the following two terms.
[0113] dt r (i)=t tran (i)+dt r ′(i) (2)
[0114] Among them, dt r (i) is the receiver clock bias estimated during initialization, t tran (i) is the error during DPT initialization, dt r ′(i) is the receiver clock bias, and the two terms on the right side of equation (2) cannot be separated. At the first epoch, the receiver clock bias estimated by DPT may have a large deviation value dt. r(0), which is a rough time difference between the reference clock and the receiver oscillator clock. After the first estimation of the receiver clock bias, the receiver crystal oscillator is adjusted by frequency control. In fact, directly constraining the oscillator usually results in excessive local clock jitter and divergence. In order for the crystal oscillator to lock the reference time better, it is necessary to ensure that the receiver clock bias and the amount of clock bias change are stable near 0, that is, the crystal oscillator clock time and the time-frequency reference source time are consistent. Therefore, an expected time length T0 is added during the oscillation process. Therefore, the expected amount of clock bias change of the receiver can also be obtained by setting the expected time length T0 of frequency compensation, as shown in equation (3).
[0115]
[0116] The corresponding clock control amount is
[0117]
[0118] During the real-time control of the local crystal oscillator, iterative calculations are performed for each epoch to ensure that the crystal clock after DPT convergence is locked to the time-frequency reference using equation (4). Furthermore, t in equation (2) tran (i) After the DPT converges, it tends to 0, at which point the receiver clock error has been accurately estimated.
[0119] After obtaining the reference time and the frequency deviation of the controlled crystal oscillator, a digital-to-analog converter (DAC) is used to convert the digital frequency deviation into a corresponding voltage adjustment value, which is then used to adjust the crystal oscillator in real time. In the actual operation of the OCXO crystal oscillator, its frequency adjustment range is...
[0120] f A =f0±Δf (5)
[0121] Where f0 is the nominal frequency of the OCXO crystal oscillator; ±Δf is the adjustable upper and lower bounds of the deviation between the actual operating frequency and the nominal frequency of the OCXO crystal oscillator. The DAC mainly performs the digital-to-analog conversion of the frequency deviation to obtain the analog control voltage of the temperature-controlled crystal oscillator. The accuracy of its digital-to-analog conversion directly affects the control accuracy. The DAC voltage control bit of this invention is 16 bits, corresponding to an output voltage of 0-5V. The following formula gives the relationship between the control voltage of the OCXO crystal oscillator clock and the output frequency of the crystal oscillator clock, and estimates the adjustment value of the minimum frequency deviation.
[0122]
[0123] In the formula, V max The maximum adjustable voltage value, V min V is the adjustable minimum voltage value, and f is the adjustable voltage range. max f is the adjustable maximum frequency value. minThis is the adjustable minimum frequency value. Equation (6) can be used to convert the frequency deviation into a voltage regulation value.
[0124] In some embodiments, based on the clock frequency control process described in detail above, this embodiment uses a second-order phase-locked loop for clock discipline, as follows:
[0125] In phase-locked loop clock control, three common input signals θ i These are phase step, frequency step, and frequency ramp input, respectively. Assuming the original phase is represented as ω0t, a phase step input suddenly adds a quantity θ0 to the original phase, changing the phase to ω0t+θ0, while the frequency remains unchanged. A frequency step input adds Δωt to the original phase, changing the phase to ω0t+Δωt; in effect, the frequency changes abruptly by Δω. A frequency ramp input adds a frequency acceleration component α to the original frequency, changing the phase... The design of the loop filter has a significant impact on the performance of the phase-locked loop (PLL). The selection of its design parameters directly affects the PLL's stability, tracking capability, and noise suppression ability. In PLL control, the steady-state response is typically used to evaluate the PLL's ability to track the input signal after reaching stable tracking, and to determine if there is any stability deviation. Steady-state response analysis can be directly performed using the Laplace final value theorem.
[0126]
[0127] in Let E(s) be the steady-state phase difference, and E(s) be the error propagation function. When the steady-state phase difference... When the value is 0, the loop can track and lock onto the input signal; otherwise, a stable deviation or even loss of lock may occur. In this case, the circuit principle of the second-order phase-locked loop is as follows: Figure 2 As shown, the second-order ring consists of an integrator and a constant term, i.e.
[0128]
[0129] In the formula, τ1 represents the coefficient of the integrator, and τ2 represents the coefficient of the constant term.
[0130] The loop transfer function H(s) and the error transfer function E(s) can be obtained as follows:
[0131]
[0132]
[0133] In the formula, K1 represents the coefficient of the digital-to-analog converter in the second-order phase-locked loop circuit, K2 represents the coefficient of the ocxo in the second-order phase-locked loop circuit, and s represents the variable of the Laplace transform in the principle of automatic control.
[0134] In cybernetics, the denominators in the above two equations can be written in a normalized expression, i.e.
[0135]
[0136] In the above formula, ω n This represents the characteristic frequency of the loop, and its physical meaning lies in relation to θ. i The change in θ(t) will cause the output of the second-order phase-locked loop, θ1(t), to produce a transient response, which resembles a damped oscillation. The angular frequency of this damped oscillation is ω. n The corresponding damping coefficient is ζ. According to control theory, when ζ is very small, the transient response requires a large overshoot to reach steady state, i.e., underdamped; while when ζ is very large, because the system is excessively damped, although there will be no overshoot, the system requires a longer time to reach steady state, i.e., overdamped.
[106] Using equation (10), the loop transfer function H(s) and error transfer function E(s) can be written as follows:
[0137]
[0138] In phase-locked loop (PLL) design, a common practice is to determine the loop bandwidth setting by directly measuring the intersection of the phase noise power spectra of the input signal and the voltage-controlled crystal oscillator (VCO) signal, thereby achieving better output phase noise performance. However, directly setting the loop bandwidth to the intersection frequency of the power spectra does not guarantee optimal phase noise performance. Based on the superposition of various noises, the power spectral density S of the output noise of a second-order PLL is... o (f) as follows.
[0139] S o (f)=S ref (f)+S DAC (f)+S OCXO (f) (12)
[0140] Among them, S ref (f) and S OCXO (f) represents the power spectral density of precision time-transfer noise (including phase jitter noise of the reference clock) and the power spectral density of oscillator free oscillation, respectively. DAC (f) represents the power spectral density of the phase jitter noise introduced by the DAC module. By accurately modeling the noise through DAC quantization, the parameters of the second-order phase-locked loop can be accurately determined.
[0141] According to equation (11), it can be found that the damping coefficient ζ and the characteristic frequency ω n These are the two most important parameters in a second-order phase-locked loop (PLL), and all the performance characteristics of the loop are related to these parameters ζ and ω. nClosely related. The damping coefficient determines the speed at which the tracking loop adjusts to changes in the external input. The most typical example is whether the clock phase adjustment amplitude can keep up with the change in the input clock difference phase when the input is a unit step excitation, i.e., the loop transient response during a unit step excitation.
[0142] First, the optimal input noise suppression is achieved when ζ = 0.707. For the characteristic frequency ω... n The determination of the equivalent noise bandwidth B of the second-order phase-locked loop adopts the principle of minimizing the total output phase variance of the system. n for
[0143]
[0144] The power spectral density is analyzed based on the DPT time-transmitted noise (including the phase jitter noise of the reference clock), the jitter noise of the crystal oscillator's free oscillation, and the DAC phase jitter noise. The bandwidth B... n Take the intersection frequency f c The characteristic frequency ω is obtained by the following formula. n
[0145]
[0146] This invention also provides a phase-locked loop (PLL) clock control device with a picosecond-level clock speed, such as... Figure 3 As shown, the device 300 includes a clock precision control module 301, which is configured to:
[0147] Based on the receiver clock difference between epochs of the oscillator clock:
[0148]
[0149] In the formula, "[·]" indicates rounding to the nearest integer, y(i) represents the clock adjustment amount of epoch i, and t epoch Let z represent the time interval between adjacent epochs, and z be the minimum digital adjustment of the voltage-controlled crystal oscillator. During initialization, the receiver clock bias estimated by the DPT time transfer is expressed as:
[0150] dt r (i)=t tran (i)+dt r ′(i) (2)
[0151] Among them, dt r (i) is the receiver clock bias estimated during initialization, t tran (i) is the error during DPT initialization, dt r ′(i) is the receiver clock bias;
[0152] After the initial estimation of the receiver clock bias, the receiver crystal oscillator is adjusted via frequency control. During the oscillation process, an expected time length T0 is added. The expected change in the receiver clock bias is obtained by setting the expected time length T0 for frequency compensation, as shown in equation (3).
[0153]
[0154] The corresponding clock control amount is:
[0155]
[0156] During the real-time control of the local crystal oscillator, iterative calculations are performed for each epoch to ensure that the crystal oscillator clock after DPT convergence is locked to the time-frequency reference using equation (4).
[0157] The frequency deviation between the reference time and the controlled crystal oscillator is obtained. A digital-to-analog converter (DAC) is used to convert the digital frequency deviation into a corresponding voltage adjustment value. This voltage adjustment value is then used to adjust the crystal oscillator in real time. The frequency adjustment range is:
[0158] f A =f0±Δf (5)
[0159] Where f0 is the nominal frequency value of the OCXO crystal oscillator; ±Δf is the adjustable upper and lower bounds of the deviation between the actual operating frequency and the nominal frequency of the OCXO crystal oscillator;
[0160] The estimated adjustment value for the minimum frequency deviation is:
[0161]
[0162] In the formula, V max The maximum adjustable voltage value, V min V is the adjustable minimum voltage value, and f is the adjustable voltage range. max f is the adjustable maximum frequency value. min The minimum adjustable frequency value can be converted into a voltage regulation value through equation (6).
[0163] In some embodiments, such as Figure 4 As shown, the device further includes a crystal oscillator clock control module 302, which is configured to:
[0164] The steady-state phase difference is calculated using the following formula:
[0165]
[0166] in For steady-state phase difference, E(s) is the error propagation function, and θ is the error transfer function. i(s) is the input signal;
[0167] A second-order ring consists of an integrator and a constant term, i.e.
[0168]
[0169] In the formula, τ1 represents the coefficient of the integrator, and τ2 represents the coefficient of the constant term;
[0170] The loop transfer function H(s) and the error transfer function E(s) are expressed as follows:
[0171]
[0172]
[0173] In the formula, K1 represents the coefficient of the digital-to-analog converter in the second-order phase-locked loop circuit, K2 represents the coefficient of the ocxo in the second-order phase-locked loop circuit, and s represents the variable of the Laplace transform in the principle of automatic control.
[0174] Rewriting the denominators in equations (8) and (9) in normalized form, we get:
[0175]
[0176] In the formula ω n Let ζ represent the characteristic frequency of the loop, and ζ represent the damping coefficient; using equation (10), the transfer function H(s) and error transfer function E(s) of the loop are expressed as:
[0177]
[0178] Based on the superposition of various noises, the power spectral density S of the output noise of the second-order phase-locked loop is... o (f) is represented as:
[0179] S o (f)=S ref (f)+S DAC (f)+S OCXO (f) (12)
[0180] Among them, S ref (f) and S OCXO (f) represents the power spectral density of the precision time-transfer noise and the power spectral density of the oscillator's free oscillation, respectively. DAC (f) represents the power spectral density of phase jitter noise introduced by the digital-to-analog conversion module. The parameters of the second-order phase-locked loop are determined by quantizing the noise through digital-to-analog conversion and modeling the noise.
[0181] The damping coefficient ζ is determined based on its effectiveness in suppressing input noise.
[0182] The characteristic frequency ω is determined based on the total output phase variance. n .
[0183] Furthermore, the damping coefficient ζ was determined to be 0.707.
[0184] Furthermore, the crystal oscillator clock control module 302 is further configured as follows:
[0185] Based on the principle of minimizing the total output phase variance of the system, the equivalent noise bandwidth B of the second-order phase-locked loop is determined. n for:
[0186]
[0187] Bandwidth B n Take the intersection frequency f c The characteristic frequency ω is obtained through equation (14). n :
[0188]
[0189] It should be noted that the device described in this embodiment belongs to the same technical concept as the previously described method, and can achieve the same technical effect, so it will not be repeated here.
[0190] Furthermore, although exemplary embodiments have been described herein, their scope includes any and all embodiments based on the invention that have equivalent elements, modifications, omissions, combinations (e.g., schemes involving intersections of various embodiments), adaptations, or alterations. Elements in the claims will be interpreted broadly based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of this application, and such examples will be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered illustrative only, and the true scope and spirit are indicated by the following claims and the full scope of their equivalents.
[0191] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. Other embodiments can be used by those skilled in the art when reading the above description. Furthermore, in the above detailed description, various features may be grouped together to simplify the invention. This should not be construed as an intention that a feature of an unclaimed invention is necessary for any claim. Rather, the subject matter of the invention may be less than all the features of a particular embodiment of the invention. Thus, the following claims are incorporated herein by reference as examples or embodiments, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.
Claims
1. A method for controlling a picosecond-level clock using a phase-locked loop, characterized in that, The method includes: Based on the receiver clock difference between epochs of the oscillator clock: In the formula, This indicates rounding to the nearest integer. Represents the epoch Clock control amount, Indicates the time interval between adjacent epochs. For the minimum digital adjustment of the voltage-controlled crystal oscillator, the receiver clock bias estimated by the DPT time transfer during initialization is expressed as: in, It is the receiver clock bias estimated during initialization. This is the error during DPT initialization. It is the receiver clock bias; After the initial estimation of the receiver clock bias, the receiver crystal oscillator is adjusted via frequency control, adding a predetermined time length during the oscillation process. By setting the expected duration of frequency compensation The expected clock bias change of the receiver is obtained by calculation as shown in equation (3): The corresponding clock control amount is: During the real-time control of the local crystal oscillator, iterative calculations are performed for each epoch to ensure that the crystal oscillator clock after DPT convergence is locked to the time-frequency reference using equation (4). The frequency deviation between the reference time and the controlled crystal oscillator is obtained. A digital-to-analog converter (DAC) is used to convert the digital frequency deviation into a corresponding voltage adjustment value. This voltage adjustment value is then used to adjust the crystal oscillator in real time. The frequency adjustment range is: in This refers to the nominal frequency value of the OCXO crystal oscillator; These are the adjustable upper and lower bounds for the deviation between the actual operating frequency and the nominal frequency of the OCXO crystal oscillator. The estimated adjustment value for the minimum frequency deviation is: In the formula, The maximum adjustable voltage value, The minimum adjustable voltage value. For adjustable voltage range, The maximum adjustable frequency value. The minimum adjustable frequency value can be converted into a voltage regulation value through equation (6).
2. The method according to claim 1, characterized in that, The method further includes: The steady-state phase difference is calculated using the following formula: in For steady-state phase difference, For the error propagation function, For input clock signal; A second-order ring consists of an integrator and a constant term, i.e. In the formula, Represents the coefficients of the integrator. The coefficient of the constant term. The variable representing the Laplace transform in the principles of automatic control; Loop transfer function and error transfer function They are represented as follows: In the formula, This represents the coefficients of the digital-to-analog converter in a second-order phase-locked loop circuit. The coefficients representing the ocxo in a second-order phase-locked loop circuit Rewriting the denominators in equations (8) and (9) in normalized form, we get: In the formula Indicates the characteristic frequency of the loop. The damping coefficient is represented by equation (10); the transfer function of the loop is given by equation (10). and error transfer function Represented as: Based on the superposition of various noises, the power spectral density of the output noise of the second-order phase-locked loop is... Represented as: in, and These are represented as the precision time-transfer noise power spectral density and the oscillator free oscillation power spectral density, respectively. This represents the power spectral density of phase jitter noise introduced by the digital-to-analog conversion module. The noise model is quantized through digital-to-analog conversion to determine the parameters of the second-order phase-locked loop. The damping coefficient is determined based on its effectiveness in suppressing input noise. ; The characteristic frequency is determined based on the total output phase variance. .
3. The method according to claim 2, characterized in that, Determined damping coefficient .
4. The method according to claim 2, characterized in that, The characteristic frequency is determined based on the total output phase variance. ,include: Based on the principle of minimizing the total output phase variance of the system, the equivalent noise bandwidth of the second-order phase-locked loop is determined. for: bandwidth Take the intersection frequency The characteristic frequency is obtained through equation (14). : 。 5. A phase-locked loop clock control device with a picosecond-level range, characterized in that, The device includes a clock precision control module, which is configured to: Based on the receiver clock difference between epochs of the oscillator clock: In the formula, Represents the epoch Clock control amount, Indicates the time interval between adjacent epochs. For the minimum digital adjustment of the voltage-controlled crystal oscillator, the receiver clock bias estimated by the DPT time transfer during initialization is expressed as: in, It is the receiver clock bias estimated during initialization. This is the error during DPT initialization. It is the receiver clock bias; After the initial estimation of the receiver clock bias, the receiver crystal oscillator is adjusted via frequency control, adding a predetermined time length during the oscillation process. By setting the expected duration of frequency compensation The expected clock bias change of the receiver is obtained by calculation as shown in equation (3): The corresponding clock control amount is: During the real-time control of the local crystal oscillator, iterative calculations are performed for each epoch to ensure that the crystal oscillator clock after DPT convergence is locked to the time-frequency reference using equation (4). The frequency deviation between the reference time and the controlled crystal oscillator is obtained. A digital-to-analog converter (DAC) is used to convert the digital frequency deviation into a corresponding voltage adjustment value. This voltage adjustment value is then used to adjust the crystal oscillator in real time. The frequency adjustment range is: in This refers to the nominal frequency value of the OCXO crystal oscillator; These are the adjustable upper and lower bounds for the deviation between the actual operating frequency and the nominal frequency of the OCXO crystal oscillator. The estimated adjustment value for the minimum frequency deviation is: In the formula, The maximum adjustable voltage value, The minimum adjustable voltage value. For adjustable voltage range, The maximum adjustable frequency value. The minimum adjustable frequency value can be converted into a voltage regulation value through equation (6).
6. The apparatus according to claim 5, characterized in that, The device further includes a crystal clock control module, which is configured to: The steady-state phase difference is calculated using the following formula: in For steady-state phase difference, For the error propagation function, For input signals; A second-order ring consists of an integrator and a constant term, i.e. In the formula, Represents the coefficients of the integrator. The coefficient of the constant term. The variable representing the Laplace transform in the principles of automatic control; Loop transfer function and error transfer function They are represented as follows: In the formula, This represents the coefficients of the digital-to-analog converter in a second-order phase-locked loop circuit. The coefficients representing the ocxo in a second-order phase-locked loop circuit Rewriting the denominators in equations (8) and (9) in normalized form, we get: In the formula Indicates the characteristic frequency of the loop. The damping coefficient is represented by equation (10); the transfer function of the loop is given by equation (10). and error transfer function Represented as: Based on the superposition of various noises, the power spectral density of the output noise of the second-order phase-locked loop is... Represented as: in, and These are represented as the precision time-transfer noise power spectral density and the oscillator free oscillation power spectral density, respectively. This represents the power spectral density of phase jitter noise introduced by the digital-to-analog conversion module. The noise model is quantized through digital-to-analog conversion to determine the parameters of the second-order phase-locked loop. The damping coefficient is determined based on its effectiveness in suppressing input noise. ; The characteristic frequency is determined based on the total output phase variance. .
7. The apparatus according to claim 6, characterized in that, Determined damping coefficient .
8. The apparatus according to claim 6, characterized in that, The crystal oscillator clock control module is further configured as follows: Based on the principle of minimizing the total output phase variance of the system, the equivalent noise bandwidth of the second-order phase-locked loop is determined. for: bandwidth Take the intersection frequency The characteristic frequency is obtained through equation (14). : 。 9. A phase-locked loop (PLL) clock control system operating at the picosecond level, characterized in that: The system includes: Memory, used to store computer programs; A processor for executing the computer program to implement the method as described in any one of claims 1 to 4.
10. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, perform the method according to any one of claims 1 to 4.