Printed circuit board defect determination method, apparatus, and electronic device
By combining X-ray imaging and printed circuit board decoding networks, the accuracy problem of defect detection in small-batch, multi-batch printed circuit boards was solved, achieving efficient defect detection, improving recall rate and reducing false detection rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-12-19
- Publication Date
- 2026-07-28
AI Technical Summary
Existing technologies are insufficient for efficiently and accurately detecting defects in small batches of printed circuit boards, especially when the defect database is inadequate, resulting in high false positive rates and low recall rates.
X-ray imaging technology is used to acquire images of printed circuit boards. Combined with a trained printed circuit board decoding network, the first type of defects are determined by design parameters and optimal estimation parameters. The second type of defects are then discovered by subtracting the fitted image from the first type of defect. Finally, the final defects of the printed circuit board are determined by combining the results.
It improved the recall rate of defect detection for small-batch, multi-batch printed circuit boards, reduced the false detection rate, and improved product quality and production efficiency.
Smart Images
Figure CN117830236B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of printed circuit board inspection technology, specifically relating to a method, apparatus, and electronic equipment for determining defects in printed circuit boards. Background Technology
[0002] A printed circuit board (PCB) is a fundamental component of electronic devices. It consists of insulating and conductive materials with printed circuit patterns used to connect and support electronic components. PCBs are widely used in electronic devices such as computers, mobile phones, televisions, and audio equipment. With the widespread application of PCBs, PCB defect detection technology has emerged. PCB defect detection technology is a series of technologies developed to ensure the quality and reliability of PCBs. As electronic devices evolve and demands increase, PCB manufacturing becomes increasingly complex, and PCB defects include various types such as cold solder joints, excessive or insufficient solder, short circuits, broken solder joints, misaligned solder joints, component displacement, stains, white spots, and blistering. These defects can lead to malfunctions, performance degradation, or even complete failure of the PCB. Therefore, developing efficient and accurate PCB defect detection technology is crucial for ensuring product quality and improving production efficiency.
[0003] In existing technologies, whether using electrical, acoustic, or image-based detection methods, most advanced detection methods rely on machine learning. However, these methods depend on high-quality, large-scale defect libraries, making it difficult to handle defect detection in large batches of small-volume printed circuit boards. Therefore, defect detection in small batches of printed circuit boards has become an urgent problem to be solved. Summary of the Invention
[0004] To address the aforementioned problems in the prior art, the present invention provides a method, apparatus, and electronic device for determining defects in printed circuit boards.
[0005] According to a first aspect of the present invention, a method for determining defects in a printed circuit board is provided, the method comprising:
[0006] A test image of the printed circuit board to be tested is acquired; wherein the test image is obtained based on X-rays; a first type of defect of the printed circuit board to be tested is determined based on the design parameters and optimal estimation parameters of the printed circuit board to be tested; wherein the design parameters characterize the various parameters in the design of the printed circuit board to be tested; and the optimal estimation parameters are obtained based on a trained printed circuit board decoding network.
[0007] The optimal estimation parameters and the first pixel position of each pixel in the image to be tested are input into the trained printed circuit board decoding network to obtain the fitted image of the printed circuit board to be tested.
[0008] Subtracting the fitted image from the image to be tested yields the second type of defect in the printed circuit board to be tested.
[0009] The final defects of the printed circuit board under test are determined based on the first type of defect and the second type of defect.
[0010] Optionally, determining the first type of defect of the printed circuit board under test based on the design parameters and optimal estimation parameters of the image under test includes:
[0011] The design parameters are input into the trained printed circuit board decoding network for iteration;
[0012] If the similarity between the printed circuit board image corresponding to the estimated parameters obtained in the current iteration and the image under test is greater than the similarity threshold, the estimated parameters obtained in the current iteration are taken as the optimal estimated parameters; wherein, the design parameters and the optimal estimated parameters respectively include the parameters of the bare board, components and solder joints in the circuit board under test;
[0013] The first type of defect is determined based on the design parameters and the optimal estimation parameters.
[0014] Optionally, the trained printed circuit board decoding network includes a trained bare board decoding network, various trained device decoding networks, and various trained solder joint decoding networks; before determining the first type of defect of the printed circuit board under test based on the design parameters and optimal estimation parameters of the printed circuit board under test, the method further includes:
[0015] An initial bare-board decoding network is constructed based on the printed circuit board under test;
[0016] A first sample set corresponding to the bare board in the printed circuit board under test is obtained; wherein, the first sample set includes a first parameter obtained based on the bare board image corresponding to the preprocessed printed circuit board, each second pixel position in the bare board image corresponding to the preprocessed printed circuit board under test, and a first label of the bare board image corresponding to the preprocessed printed circuit board under test; the first label is used to characterize the transmittance of each second pixel position in the bare board image corresponding to the preprocessed printed circuit board under test.
[0017] The first sample set is input into the initial bare-plate decoding network for training to obtain a fitted bare-plate image;
[0018] Based on the first sample set, the fitted bare-plate image, and the first loss function, determine whether the initial bare-plate decoding network has reached the first convergence condition;
[0019] If the first convergence condition is not met, adjust the parameters in the initial bare-plate decoding network and train again based on the first sample set until the first convergence condition is met.
[0020] When the first convergence condition is met, the bare-metal decoding network of the current training round is used as the trained bare-metal decoding network.
[0021] Optionally, the method further includes:
[0022] Construct an initial device decoding network corresponding to each type of device in the printed circuit board under test based on the printed circuit board under test;
[0023] A second sample set corresponding to various devices in the printed circuit board under test is obtained; wherein, the second sample set includes a second parameter obtained from the device images corresponding to various preprocessed printed circuit boards under test, the third pixel positions in the device images corresponding to various preprocessed printed circuit boards under test, and the second labels of the device images corresponding to various preprocessed printed circuit boards under test; the second labels are used to characterize the transmittance of each third pixel position in the device images corresponding to various preprocessed printed circuit boards under test.
[0024] The second sample set corresponding to each type of device in the printed circuit board under test is input into the initial device decoding network corresponding to each type of device for training, and the fitted device images of each type are obtained.
[0025] Based on the second sample set, the images of the various types of fitted devices, and the second loss function, determine whether the initial device decoding network corresponding to each type of device has reached the second convergence condition.
[0026] If the second convergence condition is not met, adjust the parameters in the initial device decoding network corresponding to each type of device, and train again based on the second sample set until the second convergence condition is met.
[0027] When the second convergence condition is met, the device decoding network corresponding to each type of device in the current training round is taken as the trained device decoding network for each type.
[0028] Optionally, the method further includes:
[0029] Construct an initial solder joint decoding network corresponding to various solder joints in the printed circuit board under test based on the printed circuit board under test;
[0030] A third sample set corresponding to various solder joints in the printed circuit board under test is obtained; wherein, the third sample set includes a third parameter, a fourth parameter obtained from the solder joint images corresponding to various preprocessed printed circuit boards under test, the fourth pixel position in each of the solder joint images of various preprocessed printed circuit boards under test, and a third label for the solder joint images corresponding to various preprocessed printed circuit boards under test; the third label is used to characterize the transmittance of each fourth pixel position in the solder joint images corresponding to various preprocessed printed circuit boards under test; the fourth parameter is obtained from the solder joint images of various preprocessed printed circuit boards under test and the solder joint coding network;
[0031] The third sample set corresponding to each type of solder joint in the printed circuit board under test is input into the initial solder joint decoding network corresponding to each type of solder joint for training, so as to obtain various fitted solder joint images.
[0032] Based on the third sample set, the various types of fitted solder joint images, and the third loss function, determine whether the initial solder joint decoding network corresponding to each type of solder joint has reached the third convergence condition.
[0033] If the third convergence condition is not met, adjust the parameters in the initial solder joint decoding network corresponding to each type of solder joint, and train again based on the third sample set until the third convergence condition is met.
[0034] When the third convergence condition is met, the solder joint decoding network corresponding to each type of solder joint in the current training round is taken as the trained solder joint decoding network for each type.
[0035] Optionally, determining the first type of defect based on the design parameters and the optimal estimation parameters includes:
[0036] The range of interpretable parameters corresponding to the bare board, various components, and various solder joints of the printed circuit board under test is determined based on the design parameters.
[0037] The range of unexplainable parameters corresponding to various solder joints of the printed circuit board under test is obtained based on the third sample set and the solder joint coding network.
[0038] The first type of defect is determined based on the range of interpretable parameters corresponding to the bare board, various components, and various solder joints of the printed circuit board under test, the range of non-interpretable parameters corresponding to various solder joints of the printed circuit board under test, and the optimal estimated parameters.
[0039] Optionally, the trained printed circuit board decoding network is constructed as follows:
[0040]
[0041] Where F(x,y,{θ)comp1,n},{θ comp2,j,k},{θ comp3,l,m},{η comp3,l,m}) represents the trained printed circuit board decoding network, x, y represent the first pixel position of each pixel in the image under test, and θ comp1,n The interpretable parameter θ characterizes the bare board type n of the printed circuit board under test. comp2,j,k The interpretable parameter θ characterizes the k-th device in the j-th type of device in the printed circuit board under test. comp3,l,m The interpretable parameter η characterizes the m-th solder joint of type l in the printed circuit board under test. comp3,l,m The uninterpretable parameter characterizes the m-th solder joint (there are m of each type) in the l-th type of solder joints in the printed circuit board under test.
[0042] Optionally, the method further includes:
[0043] The pre-built model library is used to query the bare board, various components, and various solder joints of the printed circuit board under test, and the corresponding pre-trained bare board decoding network, various pre-trained component decoding network, and various pre-trained solder joint decoding network. The pre-built model library is composed of different pre-trained printed circuit board decoding networks obtained each time the printed circuit board is defect-determined.
[0044] When at least one of the trained bare board decoding networks, trained device decoding networks, and trained solder joint decoding networks corresponding to the bare board, various devices, and various solder joints of the printed circuit board under test is found in the constructed model library, the trained printed circuit board decoding network is constructed using the found decoding network.
[0045] If no trained bare board decoding network, trained device decoding network, or trained solder joint decoding network is found in the constructed model library for the bare board of the printed circuit board under test, the trained but not found decoding network obtained after the defects of the printed circuit board under test are determined is added to the constructed model library.
[0046] According to a second aspect of the present invention, a printed circuit board defect determination apparatus is provided, the apparatus comprising:
[0047] The first image acquisition module is used to acquire a test image of the printed circuit board under test; wherein the test image is obtained based on X-rays;
[0048] The first determining module is used to determine a first type of defect of the printed circuit board under test based on the design parameters and optimal estimation parameters of the printed circuit board under test; wherein, the design parameters characterize the various parameters when designing the printed circuit board under test; and the optimal estimation parameters are obtained based on a trained printed circuit board decoding network.
[0049] The second image acquisition module is used to input the optimal estimation parameters and the first pixel position of each pixel of the image to be tested into the trained printed circuit board decoding network to obtain the fitted image of the printed circuit board to be tested.
[0050] The second determining module is used to determine a second type of defect in the printed circuit board under test based on the fitted image and the image to be tested.
[0051] The third determining module is used to determine the final defects of the printed circuit board under test based on the first type of defects and the second type of defects.
[0052] According to a third aspect of the present disclosure, a printed circuit board defect determination apparatus is provided, comprising: a processor; and a memory for storing processor-executable instructions;
[0053] The processor is configured to execute the executable instructions to implement the steps of the printed circuit board defect determination method according to any embodiment of the first aspect described above.
[0054] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:
[0055] In the above technical solution, a test image of the printed circuit board (PCB) to be tested is acquired; the first type of defect of the PCB to be tested is determined based on the design parameters and optimal estimation parameters of the PCB to be tested; wherein, the design parameters characterize the various parameters when designing the PCB to be tested; the optimal estimation parameters are obtained based on a trained PCB decoding network; the optimal estimation parameters and the first pixel position of each pixel in the test image are input into the trained PCB decoding network to obtain a fitted image of the PCB to be tested; the fitted image is subtracted from the test image to obtain the second type of defect of the PCB to be tested; the final defect of the PCB to be tested is determined based on the first and second type defects. Through the above technical solution, using the trained PCB decoding network and the constructed PCB model obtained from the PCB to be tested as support, it can be applied to the defect detection scenario of small-batch, multi-batch PCBs. The detected first and second type defects of the PCBs complement and corroborate each other, eliminating falsely judged PCB defects while determining the final defect of the PCB, thus improving the recall rate of defects in small-batch, multi-batch PCBs and reducing the false detection rate of defects in small-batch, multi-batch PCBs, thereby improving the product quality and production efficiency of PCBs. Attached Figure Description
[0056] Figure 1 This is a flowchart illustrating a method for determining defects in a printed circuit board according to an exemplary embodiment.
[0057] Figure 2 This is a flowchart illustrating another method for determining defects in a printed circuit board according to an exemplary embodiment.
[0058] Figure 3 This is a flowchart illustrating another method for determining defects in a printed circuit board according to an exemplary embodiment.
[0059] Figure 4 This is a flowchart illustrating yet another method for determining defects in a printed circuit board, according to an exemplary embodiment.
[0060] Figure 5 This is a block diagram illustrating a printed circuit board defect determination apparatus according to an exemplary embodiment.
[0061] Figure 6 This is a block diagram of an electronic device for a method of determining defects in a printed circuit board, according to an exemplary embodiment. Detailed Implementation
[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.
[0063] To facilitate understanding of the present invention, a brief description of the prior art and the inventive concept of the present invention will be provided first.
[0064] Current printed circuit board (PCB) defect detection methods can be broadly categorized into electrical, acoustic, and image-based methods. Image-based methods primarily use visible light, infrared, and X-rays to image the PCB and then visually compare the images to identify defects. Initially, image-based PCB defect detection methods relied heavily on manual inspection. Their main advantage was ease of implementation, but their major drawbacks included uncontrollable human error, high manpower consumption, and low efficiency. Due to increased PCB production and ever-increasing demands for PCB inspection accuracy, machine vision-based PCB defect detection methods have gained significant attention.
[0065] Machine vision-based methods for detecting defects in printed circuit boards (PCBs) can be broadly categorized into three types: morphological analysis-based methods, template comparison-based methods, and deep learning-based methods. Morphological analysis-based methods typically detect defects by checking if the shape and size parameters of various components on the PCB conform to standards. However, they cannot accurately identify defects in overly complex, non-parameterized sections of the PCB, such as complex contamination. Template comparison-based methods involve fabricating a qualified PCB template and comparing its image with the PCB to be inspected. Areas showing significant errors are considered potential defect locations and further assessed manually. However, template comparison-based methods are sensitive to differences in component placement and irregular solder joint shapes, especially when components with large dimensional variations exist on the PCB, leading to numerous false positives. Consequently, they often consume significant post-processing time in many scenarios. In deep learning-based methods, for mass-producible printed circuit board (PCB) products, a sufficiently representative database of good and defective PCB samples is typically built using manual annotation. A deep network with sufficient representational power is then used to statistically model the PCB or its regions. This model is then used to inspect the entire PCB or specific regions to identify potential defects. Existing common AI-based methods heavily rely on large-scale PCB defect databases. This is unsuitable for the scenario of inspecting small batches of PCBs in massive, unloaded, and spaceborne equipment. Therefore, this invention proposes a method for determining PCB defects to address this technical problem.
[0066] Figure 1 This is a flowchart illustrating a method for determining defects in a printed circuit board according to an exemplary embodiment, such as... Figure 1 As shown, the method includes the following steps.
[0067] In S101, a test image of the printed circuit board to be tested is acquired; wherein the test image is obtained based on X-rays.
[0068] Understandably, the image to be tested can be obtained from multiple images taken of the printed circuit board under test. Since X-ray images can penetrate multi-layered structures and have extremely high resolution, they provide good imaging results. Therefore, this invention chooses X-rays to acquire images of the printed circuit board under test. After acquiring multiple images of the printed circuit board under test, these images need to be preprocessed to obtain the preprocessed image as the image to be tested for the printed circuit board. This image to be tested includes the bare board image of the printed circuit board under test, images of various components, and images of various solder joints. Therefore, this image to be tested can be segmented to obtain various solder joint images.
[0069] For example, a multi-image averaging method can be used to preprocess multiple initial images of the printed circuit board under test (PCB). The image to be tested for the PCB can then be determined based on the average of these initial images. The image to be tested for the PCB can be obtained using the following formula:
[0070] g(a,b)=f(a,b)+h(a,b)
[0071]
[0072]
[0073] Where t represents the number of images of the printed circuit board under test acquired, g(a,b) represents a single image of the printed circuit board under test acquired, f(a,b) represents a noise-free image of the printed circuit board under test, and h(a,b) represents the noise level of the image of the printed circuit board under test. Here, P represents the average image of the printed circuit board under test, and P is the number of images of the printed circuit board under test captured. This represents the expected average image of the printed circuit board under test (PCB). f(a,b), i.e., a noise-free image of the PCB under test, can be chosen as the test image.
[0074] It is worth mentioning that the individual solder joint images after cutting can also be processed using the above preprocessing method to obtain various solder joint images. Furthermore, the methods for preprocessing bare board images, various device images, various solder joint images, and the initial image of the printed circuit board under test are not limited to the above methods, and this invention does not impose any limitations on them.
[0075] In S102, the first type of defect of the printed circuit board under test is determined based on the design parameters and optimal estimation parameters of the printed circuit board under test; wherein, the design parameters characterize the various parameters when designing the printed circuit board under test; the optimal estimation parameters are obtained based on the trained printed circuit board decoding network.
[0076] It is understandable that the design parameters of the printed circuit board under test (PCB) include the design parameters of each component (bare PCB, various devices, and various solder joints). These design parameters are those used during the PCB design process. The design parameters of the bare PCB and various devices are interpretable parameters, while the design parameters of various solder joints require description of non-interpretable parameters. Therefore, the design parameters of various solder joints include both interpretable and non-interpretable parameters. Interpretable parameters can include the size, shape, and placement of devices, X-ray intensity, and the shape, size, and spacing of pads (the metal areas on the PCB used for soldering electronic devices), as well as the shape and size of solder joints. For solder joints, interpretable parameters, such as the location, size, and thickness, are insufficient to fully characterize the transmittance distribution, such as variations in the transmittance distribution. In such cases, a series of additional parameters can be used to describe the transmittance. Because the physical meaning of these parameters is not explicitly known, they are called "non-interpretable parameters." The optimal estimated parameters characterize the actual parameters of the printed circuit board (PCB) under test. Correspondingly, the optimal estimated parameters also include interpretable and non-interpretable parameters of the PCB bare board, various components, and various solder joints. Typically, there is a certain discrepancy between the design parameters and the actual parameters of the PCB. This invention takes this discrepancy into account and sets a reasonable range of difference between the optimal estimated parameters and the design parameters. However, when the difference between certain parameters in the optimal estimated parameters and the design parameters exceeds a certain threshold, the first type of defect in the PCB under test is determined based on these parameters. Therefore, the first type of defect is a parameter-level defect, namely, abnormal parameter defects in the bare board, components, and solder joints of the PCB under test. The trained PCB decoding network can employ autoencoders, recurrent neural networks, convolutional neural networks, generative adversarial networks, etc.
[0077] In S103, the optimal estimated parameters and the first pixel position of each pixel in the image to be tested are input into the trained printed circuit board decoding network to obtain the fitted image of the printed circuit board to be tested.
[0078] Understandably, the optimal estimated parameters are the actual parameters of the printed circuit board under test obtained iteratively from the trained printed circuit board decoding network. Therefore, the optimal estimated parameters can be input into the trained printed circuit board decoding network. It's worth noting that the fitted image of the printed circuit board under test is actually composed of the transmittance at each pixel location. Therefore, when inputting into the trained printed circuit board decoding network, the first pixel location also needs to be input. For example, inputting the first pixel location, along with the optimal estimated parameters such as device placement orientation, size, and X-ray intensity, into the trained printed circuit board decoding network generates the transmittance of the device image at that pixel location (transmittance typically ranges from 0 to 1, being a real number).
[0079] In S104, the fitted image is subtracted from the image to be tested to obtain the second type of defect of the printed circuit board to be tested.
[0080] Understandably, after identifying the first type of defect in the printed circuit board under test (PCB), it is necessary to further determine whether the PCB might have defects other than those specified in the parameters, or to determine whether the identified first type of defect is a false positive. Therefore, a trained PCB decoding network is used to identify the second type of defect in the PCB. The trained PCB decoding network can construct an idealized fitted image based on the parameters of the PCB, and then the second type of defect in the PCB is confirmed by comparing the fitted image with the actual image.
[0081] For example, the fitted image can be compared with the image to be tested. The fitted image, which represents the ideal transmittance distribution, is subtracted from the image to be tested, which represents the actual transmittance distribution. Since there is a certain error between the idealized fitted image and the actual image to be tested, when the difference in transmittance between the fitted image and the image to be tested exceeds a certain threshold, it can be considered that the transmittance in the fitted image and the image to be tested is abnormal. The second type of defect of the printed circuit board under test can be identified based on the pixel position of the abnormal transmittance. The second type of defect is essentially a non-parametric defect, such as contamination on the printed circuit board, bridging between solder joints, etc.
[0082] In S105, the final defects of the printed circuit board under test are determined based on the first type of defect and the second type of defect.
[0083] It is worth mentioning that when determining the final defects of the circuit board under test based on the first type of defects and the second type of defects, there may be conflicts between the first type of defects and the second type of defects. In this case, manual judgment can be made. Furthermore, when the first type of defects and the second type of defects are used to complement and verify each other, some misjudged defects in the first type of defects and the second type of defects may be eliminated, and it may also be possible to detect that the circuit board under test has both the first type of defects and the second type of defects.
[0084] For example, when the first type of defect of the printed circuit board under test is a short circuit at the solder joint, and the second type of defect is that the printed circuit board is covered with stains, the final defect of the printed circuit board under test, as determined by the first and second type of defects, may be that the printed circuit board is covered with stains and the solder joint is short-circuited. When the first type of defect of the printed circuit board under test is a broken solder joint, and the second type of defect is that the printed circuit board is defect-free, the final defect of the printed circuit board under test, as determined by the first and second type of defects, may be that the printed circuit board is defect-free.
[0085] In the above technical solution, a test image of the printed circuit board (PCB) to be tested is acquired; the first type of defect of the PCB to be tested is determined based on the design parameters and optimal estimation parameters of the PCB to be tested; wherein, the design parameters characterize the various parameters when designing the PCB to be tested; the optimal estimation parameters are obtained based on a trained PCB decoding network; the optimal estimation parameters and the first pixel position of each pixel in the test image are input into the trained PCB decoding network to obtain a fitted image of the PCB to be tested; the fitted image is subtracted from the test image to obtain the second type of defect of the PCB to be tested; the final defect of the PCB to be tested is determined based on the first and second type defects. Through the above technical solution, using the trained PCB decoding network and the constructed PCB model obtained from the PCB to be tested as support, it can be applied to the defect detection scenario of small-batch, multi-batch PCBs. The detected first and second type defects of the PCBs complement and corroborate each other, eliminating falsely judged PCB defects while determining the final defect of the PCB, thus improving the recall rate of defects in small-batch, multi-batch PCBs and reducing the false detection rate of defects in small-batch, multi-batch PCBs, thereby improving the product quality and production efficiency of PCBs.
[0086] Optionally, Figure 2 This is a flowchart illustrating another method for determining defects in a printed circuit board according to an exemplary embodiment, such as... Figure 2 As shown, S102 may include:
[0087] In S1021, the design parameters are input into the trained printed circuit board decoding network for iteration.
[0088] In S1022, if the similarity between the printed circuit board image corresponding to the estimated parameters obtained in the current iteration and the image to be tested is greater than the similarity threshold, the estimated parameters obtained in the current iteration are taken as the optimal estimated parameters; wherein, the design parameters and the optimal estimated parameters respectively include the parameters of the bare board, devices and solder joints in the circuit board to be tested.
[0089] In S1023, the first type of defect is determined based on the design parameters and the optimal estimated parameters.
[0090] Understandably, design parameters can be used as initial parameters input to the trained PCB decoding network. The interpretable parameters for the bare board, components, and solder joints of the PCB under test can be directly adopted from the design parameters; while the uninterpretable parameters for solder joints can be initially set to 0. Using high-dimensional optimization algorithms such as gradient descent or particle swarm optimization, the initial parameters obtained from the design parameters are iterated until the similarity between the image output by the trained PCB decoding network based on the iterated design parameters and the image under test is greater than a similarity threshold. The similarity can be calculated using methods such as the reciprocal of the mean squared error. Since the design parameters and optimal estimated parameters respectively include parameters for the bare board, components, and solder joints of the PCB under test, the design parameters and optimal estimated parameters are compared. Parameters with excessively large differences between the design parameters and optimal estimated parameters are identified as Type I defects. For example, if the solder joint size in the design parameters is 50 micrometers and the solder joint size in the optimal estimated parameters is 200 micrometers, the difference in solder joint size is too large, and the PCB can be considered to have a defect of abnormal solder joint size.
[0091] Optionally, the trained printed circuit board decoding network includes a trained bare board decoding network, various trained device decoding networks, and various trained solder joint decoding networks. Before step S102, the printed circuit board defect determination method may further include:
[0092] Step a. Construct an initial bare-board decoding network based on the printed circuit board under test;
[0093] Step b. Obtain the first sample set corresponding to the bare board in the printed circuit board to be tested; wherein, the first sample set includes the first parameter obtained from the bare board image corresponding to the preprocessed printed circuit board, the second pixel position in the bare board image corresponding to the preprocessed printed circuit board to be tested, and the first label of the bare board image corresponding to the preprocessed printed circuit board to be tested; the first label is used to characterize the transmittance of each second pixel position in the bare board image corresponding to the preprocessed printed circuit board to be tested;
[0094] Step c. Input the first sample set into the initial bare-plate decoding network for training to obtain the fitted bare-plate image;
[0095] Step d. Determine whether the initial bare-plate decoding network has reached the first convergence condition based on the first sample set, the fitted bare-plate image, and the first loss function;
[0096] Step e. If the first convergence condition is not met, adjust the parameters in the initial bare-metal decoding network and train again based on the first sample set until the first convergence condition is met.
[0097] Step f. When the first convergence condition is met, the bare-metal decoding network of the current training round is used as the trained bare-metal decoding network.
[0098] It is understandable that steps a to f are the training process for the initial bare board decoding network in the initial printed circuit board decoding network, and the first sample set of the initial bare board decoding network is {(x i1 ,y i1 ,θ comp1 ;v i1 )},x i1 ,y i1 Let θ be the coordinates of each second pixel position. comp1 The first parameter, the first label v i1 For x i1 ,y i1 The transmittance at the location. Preprocessing of the bare board image corresponding to the printed circuit board under test can employ denoising, image enhancement, histogram equalization, etc., such as image averaging for noise reduction of multiple images; this invention is not limited to these methods. The initial bare board decoding network is iteratively trained using the first sample set. In each iteration, the transmittance value of the output in the current training round and the error of the first label are calculated using the first sample set, the fitted bare board image, and the first loss function. Based on this error, the first loss function is established, and optimization algorithms such as gradient descent and backpropagation are used to adjust the parameters in the bare board decoding network of the current training round until the first convergence condition is met. When the first convergence condition is met, the bare board decoding network of the current training round is considered the trained bare board decoding network. This first convergence condition can be that the loss value of the current training round is less than a set threshold or that the training round has reached the maximum number of iterations. During iterative training, the loss function used can be a cross-entropy loss function, etc., and is not limited to these methods.
[0099] Optionally, the printed circuit board defect determination method further includes:
[0100] Step g. Construct an initial device decoding network corresponding to each type of device in the printed circuit board under test (PCB).
[0101] Step h. Obtain the second sample set corresponding to various devices in the printed circuit board under test; wherein, the second sample set includes the second parameters obtained from the device images corresponding to various preprocessed printed circuit boards under test, the third pixel positions in the device images corresponding to various preprocessed printed circuit boards under test, and the second labels of the device images corresponding to various preprocessed printed circuit boards under test; the second labels are used to characterize the transmittance of each third pixel position in the device images corresponding to various preprocessed printed circuit boards under test.
[0102] Step i. Input the second sample set corresponding to each type of device in the printed circuit board under test into the initial device decoding network corresponding to each type of device for training, and obtain the fitted device images for each type of device;
[0103] Step j. Determine whether the initial device decoding network corresponding to each type of device has reached the second convergence condition based on the second sample set, the images of various fitted devices, and the second loss function;
[0104] Step k. If the second convergence condition is not met, adjust the parameters in the initial device decoding network corresponding to each type of device, and train again based on the second sample set until the second convergence condition is met.
[0105] Step 1. When the second convergence condition is met, the device decoding network corresponding to each type of device in the current training round is taken as the trained device decoding network for each type.
[0106] It is understandable that steps g to l are the training process for the initial device decoding network in the initial printed circuit board decoding network, and each type of device has a corresponding trained device decoding network. The second sample set of the initial device decoding network corresponding to each type of device is {(x i2 ,y i2 ,θ comp2 ;v i2 )},x i2 ,y i2 Let θ be the coordinates of each third pixel position. comp2 The second parameter, the second label v i2 For x i2 ,y i2 The transmittance at that location. The remaining training process is the same as in steps a to f, and will not be repeated here.
[0107] Optionally, the printed circuit board defect determination method further includes:
[0108] Step m. Construct an initial solder joint decoding network corresponding to various solder joints in the printed circuit board under test;
[0109] Step n. Obtain the third sample set corresponding to various types of solder joints in the printed circuit board under test; wherein, the third sample set includes the third parameter, the fourth parameter, the fourth pixel position in the solder joint image of the preprocessed printed circuit board under test, and the third label of the solder joint image of the preprocessed printed circuit board under test; the third label is used to characterize the transmittance of each fourth pixel position in the solder joint image of the preprocessed printed circuit board under test; the fourth parameter is obtained based on the solder joint image and solder joint coding network of the preprocessed printed circuit board under test.
[0110] Step o. Input the third sample set corresponding to each type of solder joint in the printed circuit board under test into the initial solder joint decoding network corresponding to each type of solder joint for training, and obtain the fitted solder joint images of each type;
[0111] Step p. Based on the third sample set, various fitted solder joint images, and the third loss function, determine whether the initial solder joint decoding network corresponding to each type of solder joint has reached the third convergence condition;
[0112] Step q. If the third convergence condition is not met, adjust the parameters in the initial solder joint decoding network corresponding to each type of solder joint, and train again based on the third sample set until the third convergence condition is met.
[0113] Step r. When the third convergence condition is met, the solder joint decoding network corresponding to each type of solder joint in the current training round is used as the trained solder joint decoding network for each type.
[0114] It is understandable that steps m to r constitute the training process of the initial solder joint decoding network. Each type of solder joint has a corresponding pre-trained solder joint decoding network. The third sample set of the initial solder joint decoding network corresponding to each type of solder joint is {(x... i3 ,y i3 ,θ comp3 ,η comp3 ;v i3 )},x i3 ,y i3 Let θ be the coordinates of each fourth pixel position. comp3 η is the third parameter. comp3 The fourth parameter, the third label v i3 For x i3 ,y i3The transmittance at the point. First, obtain pre-processed solder joint images of the printed circuit board (PCB) under test. Then, solder a chip simulation sample onto the bare PCB to obtain an image composed of the first layer of chip simulation sample, the second layer of bare board, and the third layer of solder joints. This PCB image is I (pre-processed image), the chip simulation sample image is I1 (pre-processed image), and the bare board image is I2 (pre-processed image). Then, the solder joint image is: I3 = I. / I1. / I2. This solder joint image contains a large number of similar solder joints. Repeat the above operation to obtain a large number of pre-processed solder joint images of various types of PCBs under test. Segment the obtained solder joint images of each type into images containing only a single solder joint, then remove defective solder joint images, and manually annotate the interpretable parameters of each solder joint. Finally, obtain a set of single-type solder joint images with interpretable parameters. These sets of single-type solder joint images with interpretable parameters constitute the third sample set of the solder joint decoding network for this type of solder joint. The initial solder joint decoding network corresponding to each type of solder joint is iteratively trained using a third sample set. Images of each type of solder joint are input into the encoding network to obtain the fourth parameter (non-interpretable parameter) for each type of solder joint. In each iteration, the transmittance value and the error of the third label in the current training round are calculated using the third sample set, the fitted solder joint images, and the third loss function. Based on this error, a third loss function is established. Gradient descent and other optimization algorithms are used, along with backpropagation (BP) and other methods, to adjust the parameters in the solder joint decoding network corresponding to each type of solder joint in the current training round until the third convergence condition is met. When the third convergence condition is met, the solder joint decoding network corresponding to each type of solder joint in the current training round is used as the trained solder joint decoding network for each type of solder joint. The third convergence condition can be that the loss value in the current training round is less than a set threshold or that the training round has reached the maximum number of iterations. During iterative training, the loss function used can be any loss function, such as the cross-entropy loss function; no restrictions are placed here.
[0115] Optionally, Figure 3 This is a flowchart illustrating another method for determining defects in a printed circuit board according to an exemplary embodiment, such as... Figure 3 As shown, S1023 may include:
[0116] In S10231, the range of interpretable parameters corresponding to the bare board, various components, and various solder joints of the printed circuit board under test is determined based on the design parameters.
[0117] In S10232, the range of uninterpretable parameters corresponding to various solder joints of the printed circuit board under test is obtained based on the third sample set and the solder joint coding network.
[0118] In S10233, the first type of defect is determined based on the range of interpretable parameters corresponding to the bare board of the printed circuit board under test, various components and various solder joints, the range of non-interpretable parameters corresponding to various solder joints of the printed circuit board under test, and the optimal estimated parameters.
[0119] It is understandable that steps S10231 to S10233 determine the interpretable parameter ranges for the bare board, various components, and various solder joints of the printed circuit board under test (PCB), as well as the non-interpretable parameter ranges for the various solder joints. Since non-interpretable parameters cannot be represented like interpretable parameters, the encoding network used when training the solder joint decoding network for each type of solder joint is needed to obtain the non-interpretable parameter ranges for each type of solder joint. Specifically, the interpretable parameter ranges for the bare board, various components, and various solder joints of the PCB, and the non-interpretable parameter ranges for the various solder joints of the PCB are compared with the optimal estimated parameters to determine the first type of defect. Therefore, the first type of defect may simultaneously include defects in the bare board, components, and solder joints.
[0120] Alternatively, the trained printed circuit board decoding network can be constructed as follows:
[0121]
[0122] Where F(x,y,{θ) comp1,n},{θ comp2,j,k},{θ comp3,l,m},{η comp3,l,m}) represents the trained printed circuit board decoding network, x, y represent the first pixel position of each pixel in the image under test, and θ comp1,n The interpretable parameter θ represents the bare board type n of the printed circuit board under test. comp2,j,k θ represents the interpretable parameter characterizing the k-th device of the j-th type in the printed circuit board under test. comp3,l,m η is an interpretable parameter characterizing the m-th solder joint of type l in the printed circuit board under test. comp3,l,m Uninterpretable parameters characterizing the m-th solder joint of the l-th type in the printed circuit board under test.
[0123] Optionally, Figure 4 This is a flowchart illustrating yet another method for determining defects in a printed circuit board according to an exemplary embodiment, such as... Figure 4 As shown, the method for determining defects in printed circuit boards may further include:
[0124] In S106, the trained bare board decoding network, trained device decoding network, and trained solder joint decoding network corresponding to the bare board, various components, and various solder joints of the printed circuit board under test are queried from the constructed model library; wherein, the constructed model library is composed of different trained printed circuit board decoding networks obtained each time the printed circuit board is defect-determined.
[0125] In S107, when at least one of the trained bare board decoding networks, trained device decoding networks, and trained solder joint decoding networks corresponding to the bare board of the printed circuit board to be tested, various devices, and various solder joints is found in the built model library, the trained printed circuit board decoding network is constructed using the found decoding network.
[0126] In S108, if no trained bare board decoding network, various device decoding network, or various solder joint decoding network corresponding to the bare board of the printed circuit board under test, is found in the built model library, the trained but not found decoding network obtained after the defects of the printed circuit board under test are determined is added to the built model library.
[0127] It is understood that S106 to S108 are extensions of the present invention. As defects in various printed circuit boards (PCBs) are continuously identified, a model library can be constructed using the trained bare board decoding network, various trained device decoding networks, and various trained solder joint decoding networks used in each defect identification of the PCB under test. This model library stores the decoding networks trained over a historical period for various bare boards, devices, and solder joints. When identifying defects in a new PCB under test, the model library can be searched using the bare boards, devices, and solder joints in the PCB under test. For trained decoding networks that can be found, they can be directly used to construct the PCB decoding network required for this defect identification. For trained decoding networks that cannot be found, they can be added to the constructed model library after the defect identification of the current PCB is completed, thus continuously expanding the constructed model library.
[0128] The above technical solution utilizes a pre-trained printed circuit board (PCB) decoding network constructed from trained bare board decoding networks, various pre-trained device decoding networks, and various pre-trained solder joint decoding networks. Combined with optimal estimation parameters and the first pixel position of the image under test, the final defects of the PCB under test are comprehensively determined. A model library is built to store the pre-trained PCB decoding networks used in historical defect determinations, facilitating direct retrieval when inspecting similar bare boards, devices, or solder joints. This approach can, to some extent, avoid misjudgments during PCB defect determination, improve the accuracy of defect detection on the PCB under test, and provide convenience for subsequent PCB defect determination.
[0129] Figure 5 This is a block diagram illustrating a printed circuit board defect determination apparatus according to an exemplary embodiment. (Refer to...) Figure 5The printed circuit board defect determination device 500 may include such a device.
[0130] The first image acquisition module 501 is used to acquire a test image of the printed circuit board to be tested; wherein the test image is obtained based on X-rays.
[0131] The first determining module 502 is used to determine the first type of defect of the printed circuit board under test based on the design parameters and optimal estimation parameters of the printed circuit board under test; wherein, the design parameters characterize the various parameters when designing the printed circuit board under test; and the optimal estimation parameters are obtained based on the trained printed circuit board decoding network.
[0132] The second image acquisition module 503 is used to input the optimal estimated parameters and the first pixel position of each pixel in the image to be tested into the trained printed circuit board decoding network to obtain a fitted image of the printed circuit board to be tested.
[0133] The second determining module 504 is used to subtract the fitted image from the image to be tested to obtain the second type of defect of the printed circuit board to be tested.
[0134] The third determination module 505 is used to determine the final defects of the printed circuit board under test based on the first type of defects and the second type of defects.
[0135] In the above technical solution, a test image of the printed circuit board (PCB) to be tested is acquired; the first type of defect of the PCB to be tested is determined based on the design parameters and optimal estimation parameters of the PCB to be tested; wherein, the design parameters characterize the various parameters when designing the PCB to be tested; the optimal estimation parameters are obtained based on a trained PCB decoding network; the optimal estimation parameters and the first pixel position of each pixel in the test image are input into the trained PCB decoding network to obtain a fitted image of the PCB to be tested; the fitted image is subtracted from the test image to obtain the second type of defect of the PCB to be tested; the final defect of the PCB to be tested is determined based on the first and second type defects. Through the above technical solution, using the trained PCB decoding network and the constructed PCB model obtained from the PCB to be tested as support, it can be applied to the defect detection scenario of small-batch, multi-batch PCBs. The detected first and second type defects of the PCBs complement and corroborate each other, eliminating falsely judged PCB defects while determining the final defect of the PCB, thus improving the recall rate of defects in small-batch, multi-batch PCBs and reducing the false detection rate of defects in small-batch, multi-batch PCBs, thereby improving the product quality and production efficiency of PCBs.
[0136] For details on the specific processing procedures of each module of the device, please refer to the relevant content in the first section, which will not be repeated here.
[0137] Figure 6This is a block diagram illustrating an electronic device for a printed circuit board defect determination method according to an exemplary embodiment, such as... Figure 6 As shown, it includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604.
[0138] The memory is used to store computer programs;
[0139] When the processor executes the program stored in the memory, it implements the steps of any of the printed circuit board defect determination methods described above in the embodiments of the present invention.
[0140] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.
[0141] The communication interface is used for communication between the aforementioned electronic devices and other devices.
[0142] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.
[0143] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0144] The method provided in this invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.
[0145] It is understood that in this invention, "multiple" refers to two or more, and other quantifiers are similar. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. The singular forms "a," "the," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.
[0146] It is further understood that the terms "first," "second," etc., are used to describe various types of information, but this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another, and do not indicate a specific order or degree of importance. In fact, the expressions "first," "second," etc., are completely interchangeable. For example, without departing from the scope of this invention, a first parameter can also be referred to as a second parameter, and similarly, a second parameter can also be referred to as a first parameter.
[0147] It is further understood that although the operations are described in a specific order in the accompanying drawings in the embodiments of the present invention, this should not be construed as requiring these operations to be performed in the specific order or serial order shown, or requiring all the operations shown to obtain the desired result. In certain environments, multitasking and parallel processing may be advantageous.
[0148] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.
Claims
1. A method for determining defects in a printed circuit board, characterized in that, include: Acquire a test image of the printed circuit board to be tested; wherein the test image is obtained based on X-rays; The first type of defect of the printed circuit board under test is determined based on the design parameters and optimal estimation parameters of the printed circuit board under test; wherein, the design parameters characterize the various parameters when designing the printed circuit board under test; the optimal estimation parameters are obtained based on the trained printed circuit board decoding network; the trained printed circuit board decoding network includes a trained bare board decoding network, various trained device decoding networks, and various trained solder joint decoding networks. The optimal estimation parameters and the first pixel position of each pixel in the image to be tested are input into the trained printed circuit board decoding network to obtain the fitted image of the printed circuit board to be tested. Subtracting the fitted image from the image to be tested yields the second type of defect in the printed circuit board to be tested. The final defects of the printed circuit board under test are determined based on the first type of defect and the second type of defect; The method further includes: Construct an initial solder joint decoding network corresponding to various solder joints in the printed circuit board under test based on the printed circuit board under test; A third sample set corresponding to various solder joints in the printed circuit board under test is obtained; wherein, the third sample set includes a third parameter, a fourth parameter obtained from the solder joint images corresponding to various preprocessed printed circuit boards under test, the fourth pixel position in each of the solder joint images of various preprocessed printed circuit boards under test, and a third label for the solder joint images corresponding to various preprocessed printed circuit boards under test; the third label is used to characterize the transmittance of each fourth pixel position in the solder joint images corresponding to various preprocessed printed circuit boards under test; the fourth parameter is obtained from the solder joint images of various preprocessed printed circuit boards under test and the solder joint coding network; The third sample set corresponding to each type of solder joint in the printed circuit board under test is input into the initial solder joint decoding network corresponding to each type of solder joint for training, so as to obtain various fitted solder joint images. Based on the third sample set, the various types of fitted solder joint images, and the third loss function, determine whether the initial solder joint decoding network corresponding to each type of solder joint has reached the third convergence condition. If the third convergence condition is not met, adjust the parameters in the initial solder joint decoding network corresponding to each type of solder joint, and train again based on the third sample set until the third convergence condition is met. When the third convergence condition is met, the solder joint decoding network corresponding to each type of solder joint in the current training round is taken as the trained solder joint decoding network for each type. Determining the first type of defect based on the design parameters and the optimal estimation parameters includes: The range of interpretable parameters corresponding to the bare board, various components, and various solder joints of the printed circuit board under test is determined based on the design parameters. The range of unexplainable parameters corresponding to various solder joints of the printed circuit board under test is obtained based on the third sample set and the solder joint coding network. The first type of defect is determined based on the range of interpretable parameters corresponding to the bare board, various components, and various solder joints of the printed circuit board under test, the range of non-interpretable parameters corresponding to various solder joints of the printed circuit board under test, and the optimal estimated parameters. The trained printed circuit board decoding network is constructed as follows: in, Characterize the trained printed circuit board decoding network. The first pixel position characterizing each pixel in the image under test. The bare board type of the printed circuit board under test is characterized as follows: Interpretable parameters at time Characterizing the first in the printed circuit board under test The first type of device Interpretable parameters of each device, Characterizing the first in the printed circuit board under test In the first type of solder joint Interpretable parameters for each solder joint Characterizing the first in the printed circuit board under test In the first type of solder joint Unexplained parameters of a solder joint.
2. The method for determining defects in printed circuit boards according to claim 1, characterized in that, The process of determining the first type of defect of the printed circuit board under test based on the design parameters and optimal estimation parameters of the image under test includes: The design parameters are input into the trained printed circuit board decoding network for iteration; If the similarity between the printed circuit board image corresponding to the estimated parameters obtained in the current iteration and the image to be tested is greater than the similarity threshold, the estimated parameters obtained in the current iteration are taken as the optimal estimated parameters; wherein, the design parameters and the optimal estimated parameters respectively include the parameters of the bare board, components and solder joints in the printed circuit board to be tested; The first type of defect is determined based on the design parameters and the optimal estimation parameters.
3. The method for determining defects in printed circuit boards according to claim 1, characterized in that, Before determining the first type of defect of the printed circuit board under test based on its design parameters and optimal estimation parameters, the method further includes: An initial bare-board decoding network is constructed based on the printed circuit board under test; A first sample set corresponding to the bare board in the printed circuit board under test is obtained; wherein, the first sample set includes a first parameter obtained based on the bare board image corresponding to the preprocessed printed circuit board, each second pixel position in the bare board image corresponding to the preprocessed printed circuit board under test, and a first label of the bare board image corresponding to the preprocessed printed circuit board under test; the first label is used to characterize the transmittance of each second pixel position in the bare board image corresponding to the preprocessed printed circuit board under test. The first sample set is input into the initial bare-plate decoding network for training to obtain a fitted bare-plate image; Based on the first sample set, the fitted bare-plate image, and the first loss function, determine whether the initial bare-plate decoding network has reached the first convergence condition; If the first convergence condition is not met, adjust the parameters in the initial bare-plate decoding network and train again based on the first sample set until the first convergence condition is met. When the first convergence condition is met, the bare-metal decoding network of the current training round is used as the trained bare-metal decoding network.
4. The method for determining defects in printed circuit boards according to claim 3, characterized in that, The method further includes: Construct an initial device decoding network corresponding to each type of device in the printed circuit board under test based on the printed circuit board under test; A second sample set corresponding to various devices in the printed circuit board under test is obtained; wherein, the second sample set includes a second parameter obtained from the device images corresponding to various preprocessed printed circuit boards under test, the third pixel positions in the device images corresponding to various preprocessed printed circuit boards under test, and the second labels of the device images corresponding to various preprocessed printed circuit boards under test; the second labels are used to characterize the transmittance of each third pixel position in the device images corresponding to various preprocessed printed circuit boards under test. The second sample set corresponding to each type of device in the printed circuit board under test is input into the initial device decoding network corresponding to each type of device for training, and the fitted device images of each type are obtained. Based on the second sample set, the images of the various types of fitted devices, and the second loss function, determine whether the initial device decoding network corresponding to each type of device has reached the second convergence condition. If the second convergence condition is not met, adjust the parameters in the initial device decoding network corresponding to each type of device, and train again based on the second sample set until the second convergence condition is met. When the second convergence condition is met, the device decoding network corresponding to each type of device in the current training round is taken as the trained device decoding network for each type.
5. The method for determining defects in printed circuit boards according to claim 1, characterized in that, The method further includes: The pre-built model library is used to query the bare board, various components, and various solder joints of the printed circuit board under test, and the corresponding pre-trained bare board decoding network, various pre-trained component decoding network, and various pre-trained solder joint decoding network. The pre-built model library is composed of different pre-trained printed circuit board decoding networks obtained each time the printed circuit board is defect-determined. When at least one of the trained bare board decoding networks, trained device decoding networks, and trained solder joint decoding networks corresponding to the bare board, various devices, and various solder joints of the printed circuit board under test is found in the constructed model library, the trained printed circuit board decoding network is constructed using the found decoding network. If no trained bare board decoding network, trained device decoding network, or trained solder joint decoding network is found in the constructed model library for the bare board of the printed circuit board under test, the trained but not found decoding network obtained after the defects of the printed circuit board under test are determined is added to the constructed model library.
6. A device for determining defects in printed circuit boards, characterized in that, include: A first image acquisition module is used to acquire a test image of the printed circuit board under test (PCB); wherein the test image is obtained based on X-rays; a first determination module is used to determine a first type of defect of the PCB based on the design parameters and optimal estimation parameters of the PCB; wherein the design parameters characterize various parameters in the design of the PCB; the optimal estimation parameters are obtained based on a trained PCB decoding network; the trained PCB decoding network includes a trained bare board decoding network, various trained device decoding networks, and various trained solder joint decoding networks; The second image acquisition module is used to input the optimal estimation parameters and the first pixel position of each pixel of the image to be tested into the trained printed circuit board decoding network to obtain the fitted image of the printed circuit board to be tested. The second determining module is used to determine a second type of defect in the printed circuit board under test based on the fitted image and the image to be tested. The third determining module is used to determine the final defects of the printed circuit board under test based on the first type of defects and the second type of defects; The device further includes: The network construction module is used to construct an initial solder joint decoding network corresponding to various solder joints in the printed circuit board under test based on the printed circuit board under test. The sample acquisition module is used to acquire a third sample set corresponding to various types of solder joints in the printed circuit board under test. The third sample set includes a third parameter and a fourth parameter obtained from solder joint images of various preprocessed printed circuit boards under test, the fourth pixel position in each of the solder joint images of various preprocessed printed circuit boards under test, and a third label for the solder joint images of various preprocessed printed circuit boards under test. The third label is used to characterize the transmittance of each fourth pixel position in the solder joint images of various preprocessed printed circuit boards under test. The fourth parameter is obtained from the solder joint images of various preprocessed printed circuit boards under test and the solder joint coding network. The training module is used to input the third sample set corresponding to various solder joints in the printed circuit board under test into the initial solder joint decoding network corresponding to various solder joints for training, so as to obtain various fitted solder joint images. The judgment module is used to determine whether the initial solder joint decoding network corresponding to each type of solder joint has reached the third convergence condition based on the third sample set, the various types of fitted solder joint images, and the third loss function. The adjustment module is used to adjust the parameters in the initial solder joint decoding network corresponding to each type of solder joint when the third convergence condition is not met, and to train again based on the third sample set until the third convergence condition is met. The network determination module is used to use the solder joint decoding network corresponding to each type of solder joint in the current training round as the trained solder joint decoding network when the third convergence condition is met. The first determining module is further configured to determine the range of interpretable parameters corresponding to the bare board, various components and various solder joints of the printed circuit board under test based on the design parameters; The range of unexplainable parameters corresponding to various solder joints of the printed circuit board under test is obtained based on the third sample set and the solder joint coding network. The first type of defect is determined based on the range of interpretable parameters corresponding to the bare board, various components, and various solder joints of the printed circuit board under test, the range of non-interpretable parameters corresponding to various solder joints of the printed circuit board under test, and the optimal estimated parameters. The trained printed circuit board decoding network is constructed as follows: in, Characterize the trained printed circuit board decoding network. The first pixel position characterizing each pixel in the image under test. The bare board type of the printed circuit board under test is characterized as follows: Interpretable parameters at time Characterizing the first in the printed circuit board under test The first type of device Interpretable parameters of each device, Characterizing the first in the printed circuit board under test In the first type of solder joint Interpretable parameters for each solder joint Characterizing the first in the printed circuit board under test In the first type of solder joint Unexplained parameters of a solder joint.
7. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to execute the executable instructions to implement the steps of the printed circuit board defect determination method according to any one of claims 1 to 5.