Display device

Abstract

A display device includes: pixel circuits disposed on a plurality of pixels, a plurality of flip-flop circuits disposed on a shift register, and a reset element disposed on the plurality of flip-flop circuits, wherein the reset element is an n-channel transistor, the pixel circuits having a light-emitting element, a light-emitting power supply, and a switching element, wherein the light-emitting element is disconnected from the light-emitting power supply during the period when the light-emitting power supply is rising.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2022-161675, filed on October 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to display devices. Background Technology

[0004] A reset circuit has been developed to set the potential of the liquid crystal layer of the display device to a specified potential, and a reset circuit to reset the shift register. Summary of the Invention

[0005] The purpose of this embodiment is to provide a display device that prevents unwanted light emission and improves display quality.

[0006] One embodiment of the display device includes:

[0007] Multiple pixels;

[0008] Pixel circuits are respectively provided in the plurality of pixels;

[0009] Multiple scan lines connected to the plurality of pixels;

[0010] Multiple signal lines connected to the plurality of pixels;

[0011] Scan line drive circuit connected to the plurality of scan lines;

[0012] Signal line driving circuit connected to the plurality of pixels;

[0013] The shift register is located in the scan line driving circuit;

[0014] Multiple flip-flop circuits are provided in the shift register; and

[0015] Reset elements are respectively provided in the plurality of flip-flop circuits.

[0016] The reset element is an n-channel transistor.

[0017] The pixel circuit includes a light-emitting element, a light-emitting power supply, and a switching element, wherein the light-emitting element is disconnected from the light-emitting power supply during a period when the light-emitting power supply is rising. Additionally, a display device according to one embodiment includes:

[0018] Multiple pixels;

[0019] Pixel circuits are respectively provided in the plurality of pixels;

[0020] Multiple scan lines connected to the plurality of pixels;

[0021] Multiple signal lines connected to the plurality of pixels;

[0022] Scan line drive circuit connected to the plurality of scan lines;

[0023] Signal line driving circuit connected to the plurality of pixels;

[0024] The shift register is located in the scan line driving circuit;

[0025] Multiple flip-flop circuits are provided in the shift register; and

[0026] Reset elements connected to the plurality of trigger circuits respectively,

[0027] The reset element is a NAND gate.

[0028] The pixel circuit has a light-emitting element, a light-emitting power supply, and a switching element, wherein the light-emitting element is disconnected from the light-emitting power supply during the period when the light-emitting power supply is rising. Attached Figure Description

[0029] Figure 1 This is a top view showing an example of the schematic configuration of the display device according to the embodiment.

[0030] Figure 2 This is a circuit diagram representing a pixel circuit.

[0031] Figure 3 This is a circuit diagram representing a pixel circuit.

[0032] Figure 4 This is a circuit diagram representing a pixel circuit.

[0033] Figure 5 This is a circuit diagram representing a pixel circuit.

[0034] Figure 6 This is a circuit diagram showing the configuration of a shift register for comparison.

[0035] Figure 7 This is the timing diagram of the shift register for the comparison example.

[0036] Figure 8 This is a timing diagram showing the sequence of power-on for the pixel circuit of the comparative example.

[0037] Figure 9 It indicates that the process is being carried out. Figure 8 A block diagram outlining the operation of the shift register.

[0038] Figure 10 This is a circuit diagram illustrating the configuration of the shift register in the implementation method.

[0039] Figure 11 This is a timing diagram of the shift register in the implementation method.

[0040] Figure 12 This is a diagram illustrating an example of the configuration of the display device in the embodiment.

[0041] Figure 13 This is the timing diagram of the shift register that constitutes Example 1. Detailed Implementation

[0042] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, the disclosed content is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the present invention. Additionally, in order to make the description clearer, the drawings may schematically represent the width, thickness, shape, etc., of various parts compared to the actual embodiment; however, this is merely an example and does not limit the interpretation of the present invention. Furthermore, in this specification and the various drawings, elements that are the same as those already described are labeled with the same reference numerals, and detailed descriptions are sometimes appropriately omitted.

[0043] The embodiments described in this specification are not the usual embodiments, but rather embodiments that illustrate the same or corresponding special technical features of the present invention. Hereinafter, a display device according to one embodiment will be described in detail with reference to the accompanying drawings.

[0044] In this embodiment, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but they may also intersect at an angle other than 90 degrees. The direction of the arrow pointing towards the tip of the third direction Z is defined as up or above, and the direction opposite to the direction of the arrow pointing towards the tip of the third direction Z is defined as down or below. Furthermore, the first direction X, the second direction Y, and the third direction Z are respectively referred to as the X direction, the Y direction, and the Z direction.

[0045] Furthermore, when designated as "a second component above the first component" or "a second component below the first component," the second component can either be connected to the first component or located separately from it. In the latter case, a third component may be sandwiched between the first and second components. On the other hand, when designated as "a second component above the first component" or "a second component below the first component," the second component is connected to the first component.

[0046] Furthermore, assuming an observation position for viewing the display device is located at the tip of an arrow pointing from the third direction Z, the view from this position towards the XY plane defined by the first direction X and the second direction Y is called a top view. A cross-section of the display device viewed in the XZ plane defined by the first direction X and the third direction Z, or in the YZ plane defined by the second direction Y and the third direction Z, is called a sectional view.

[0047] [Implementation Method]

[0048] Figure 1 This is a top view illustrating an example of the schematic configuration of the display device according to an embodiment. Figure 1 In the display device DSP shown, a display area DA, a peripheral area FA surrounding the display area DA, a scan line drive circuit GDV (scan line drive circuit GDV1 and scan line drive circuit GDV2) disposed in the peripheral area FA, and a signal line drive circuit SDV are provided on the substrate SUB 1.

[0049] The display area DA contains multiple pixels PX, which are configured in a matrix. Each pixel PX is located at the intersection of a scan line GL and a signal line SL. Each pixel PX is connected to its corresponding scan line GL and signal line SL.

[0050] The peripheral area FA refers to the area outside the display area DA. The peripheral area FA includes scan line drive circuits GDV (scan line drive circuits GDV1 and GDV2), signal line drive circuits SDV, and a wiring substrate FPC connected via terminals not shown. Figure 1 In the example shown, scan lines GL extend from scan line driver circuit GDV. Odd-numbered scan lines GL are connected to scan line driver circuit GDV1. Even-numbered scan lines GL are connected to scan line driver circuit GDV2. Alternatively, the scan line driver circuit may not be divided into two circuits; all scan lines GL may be connected to a single scan line driver circuit. Signal lines SL extend from signal line driver circuit SDV. Driver elements CTL are disposed on the wiring substrate FPC. Examples of driver elements CTL include driver ICs.

[0051] Image signals and various control signals are supplied from outside the display device DSP via the wiring board (FPC). The image signals are input to multiple pixels (PX) via drive elements (CTLs). The various drive signals are input to the scan line drive circuit (GDV) and the signal line drive circuit (SDV) via the drive elements (CTLs). The pixels (PX) emit light based on the image signals and various control signals.

[0052] Figure 1The scan line driving circuit GDV and signal line driving circuit SDV shown each have a shift register. The shift register is configured, for example, by connecting multiple flip-flop circuits together. In this embodiment, the display device DSP, having m scan lines GL and n signal lines SL, is configured to have m × n pixels PX. For example, the shift register of the scan line driving circuit GDV has m (m-level) flip-flop circuits. These m flip-flop circuits are each connected to the scan line GL.

[0053] The operation of this shift register is explained below. First, a start pulse (start signal) is input to the first-stage flip-flop circuit. If each stage of the flip-flop circuit outputs a pulse, this pulse is supplied as a gate signal to the scan line GL. Simultaneously, the pulse is input as a carry signal to the next stage of the flip-flop circuit. Thus, each stage of the flip-flop outputs pulses sequentially, starting from the first stage.

[0054] Figures 2 to 5 This is a circuit diagram representing a pixel circuit. In Figure 2 In this structure, pixel circuits PC, located in multiple pixels PX, include transistors TRS (which function as switching elements), transistors TRI (which function as current control transistors), and light-emitting elements ELM (which are organic electroluminescent (EL) light-emitting elements).

[0055] A light-emitting signal EM is input to the gate of transistor TRS. A high-potential power supply ELVDD is connected to either the source or drain of transistor TRS. The source or drain of transistor TRI is connected to the other end of the transistor TRS. The light-emitting signal EM is equivalent to the gate signal supplied to the scan line GL described above.

[0056] The gate of transistor TRI is connected to other components of the pixel circuit PC. One of the sources or drains of transistor TRI is connected to the other of the source or drain of transistor TRS. The other of the source or drain of transistor TRI is connected to the anode of the light-emitting element ELM. The cathode of the light-emitting element ELM is connected to the low-potential power supply ELVSS.

[0057] The transistor TRS functions as a switching element that connects the high-potential power supply ELVDD and the low-potential power supply ELVSS to the light-emitting element ELM. Figures 3 to 5 It shows that Figure 2 The transistor TRS is rewritten as the pixel circuit PC of the switching element SWT.

[0058] In driving the light-emitting element (ELM) to emit light, the first step is to raise (start up, activate) the high-potential power supply ELVDD and the low-potential power supply ELVSS. The high-potential power supply ELVDD and the low-potential power supply ELVSS are, for example, 5V and 0V power supplies, respectively. Raising the high-potential power supply ELVDD and the low-potential power supply ELVSS means fixing their potentials so that the potential difference between them is 5V.

[0059] At this time, with the switching element SWT set to the off state, i.e., not electrically connected, the high-potential power supply ELVDD and the low-potential power supply ELVSS rise (refer to...). Figure 3 In addition, in this embodiment, the high-potential power supply ELVDD and the low-potential power supply ELVSS are sometimes referred to together simply as "power supply," "EL power supply," or "light-emitting power supply." Furthermore, the rise of the high-potential power supply ELVDD and the low-potential power supply ELVSS is also simply referred to as "the rise of the power supply."

[0060] Consider the case where the transistor TRS, acting as the switching element SWT, is a p-channel transistor. When the input light signal EM to the switching element SWT is high (H), the switching element SWT is in the off state (disconnected state) (refer to...). Figure 4 On the other hand, when the light emission signal EM is low (L), the switching element SWT becomes in the on state (connected state) (see reference). Figure 5 ).

[0061] As described above, in order for the light-emitting element ELM of this embodiment to emit light, it is necessary to raise the high-potential power supply ELVDD and the low-potential power supply ELVSS. During the raising of these power supplies (power supplies ELVDD and ELVSS), if a low-level (L) signal is input to the switching element SWT, the power supply is connected to the light-emitting element ELM. Therefore, the light-emitting element ELM may cause unnecessary light emission.

[0062] Therefore, during the rise of the high-potential power supply ELVDD and the low-potential power supply ELVSS, it is necessary to keep the signal input to the switching element SWT at a high level (H).

[0063] Figure 6 This is a circuit diagram showing the configuration of a shift register for comparison. Figure 6 The shift register SRr shown contains a flip-flop circuit FF_i at the i-th stage (where i is a natural number satisfying 1≤i≤(m-1)) and a flip-flop circuit FF_i+1 at the (i+1)-th stage.

[0064] The trigger circuit FF_i has a NOR gate (or NOT gate) NR_i, a transistor TRRr_i, an inverter INV_i, a transistor TMP_i, a transistor TMN_i, and a transistor TRF_i.

[0065] In addition, Figure 6 In the diagram, no lines are used to connect the nodes to make them easier to understand, but nodes NDa_i are connected to each other. Similarly, nodes NDb_i are connected to each other.

[0066] One input terminal of the NOR gate NR_i is connected to node INP_i. The other input terminal of the NOR gate NR_i is connected to either the source or drain of transistor TMP_i, either the source or drain of transistor TMN_i, either the source or drain of transistor TRF_i, and node OTP_i. The output terminal of the NOR gate NR_i is connected to either the source or drain of transistor TRRr_i, the input terminal of inverter INV_i, and node NDb_i.

[0067] Transistor TRRr_i is a p-channel transistor. One of the source or drain terminals of transistor TRRr_i is connected to the output terminal of NOR gate NR_i, the input terminal of inverter INV_i, and node NDb_i. The other terminal of transistor TRRr_i is connected to the high-potential power supply VGH. A reset signal RST is input to the gate of transistor TRRr_i. Transistor TRRr_i acts as a reset element.

[0068] Transistor TMP_i is a p-channel transistor. One of the sources or drains of transistor TMP_i is connected to the other end of the input terminal of NOR gate NR_i, one of the sources or drains of transistor TMN_i, one of the sources or drains of transistor TRF_i, and node OTP_i. The other end of the source or drain of transistor TMP_i is connected to the other end of the source or drain of transistor TMN_i and is connected to the input clock signal CLK. The gate of transistor TMP_i is connected to node NDb_i.

[0069] Transistor TMN_i is an n-channel transistor. One of the sources or drains of transistor TMN_i is connected to one of the sources or drains of transistor TMP_i, the other end of the input terminal of NOR gate NR_i, one of the sources or drains of transistor TRF_i, and node OTP_i. The other end of the source or drain of transistor TMN_i is connected to the other end of the source or drain of transistor TMP_i and is connected to the input clock signal CLK. The gate of transistor TMN_i is connected to node NDa_i.

[0070] The sources and drains of transistors TMN_i and TMP_i are connected to each other to form a transmission gate.

[0071] Transistor TRF_i is an n-channel transistor. One of the sources or drains of transistor TRF_i is connected to one of the sources or drains of transistor TMN_i, one of the sources or drains of transistor TMP_i, the other end of the input terminal of NOR gate NR_i, and node OTP_i. The other end of the source or drain of transistor TRF_i is connected to the low-potential power supply VGL. The gate of transistor TRF_i is connected to node NDb_i.

[0072] Node INP_i is the input terminal of the flip-flop circuit FF_i. The carry signal is input to node INP_i from the output terminal (node ​​OTP_i-1, not shown) of the previous stage flip-flop circuit (flip-flop circuit FF_i-1, not shown).

[0073] Node OTP_i is the output terminal of the flip-flop circuit FF_i. The carry signal is output from node OTP_i to the input terminal (node ​​INP_i+1) of the next stage flip-flop circuit FF_i+1.

[0074] The light emission signal EMi is output from the output terminal of the inverter INV_i via node NDa_i. As described above, if the light emission signal EMi is input to the pixel circuit PC of pixel PX, the light emission element ELM emits light.

[0075] The flip-flop circuit FF_i+1 in the (i+1)th stage has a NOR gate NR_i+1, a transistor TRRr_i+1, an inverter INV_i+1, a transistor TMP_i+1, a transistor TMN_i+1, a transistor TRF_i+1, and an inverter INE_i+1.

[0076] As above, no lines are used to connect the nodes in the diagram for ease of understanding, but nodes NDa_i+1 are connected to each other. Similarly, nodes NDb_i+1 are connected to each other.

[0077] One input terminal of the NOR gate NR_i+1 is connected to node INP_i+1. The other input terminal of the NOR gate NR_i+1 is connected to the output terminal of inverter INE_i+1 and node OTP_i+1. The output terminal of the NOR gate NR_i+1 is connected to either the source or drain of transistor TRRr_i+1, the input terminal of inverter INV_i+1, and node NDb_i+1.

[0078] Transistor TRRr_i+1 is a p-channel transistor. One of the source or drain terminals of transistor TRRr_i+1 is connected to the output terminal of NOR gate NR_i+1, the input terminal of inverter INV_i+1, and node NDb_i+1. The other of the source or drain terminal of transistor TRRr_i+1 is connected to a high-potential power supply VGH. A reset signal RST is input to the gate of transistor TRRr_i+1. Transistor TRRr_i+1 acts as a reset element.

[0079] Transistor TMP_i+1 is a p-channel transistor. One of the sources or drains of transistor TMP_i+1 is connected to the input terminal of inverter INE_i+1, one of the sources or drains of transistor TMN_i+1, and one of the sources or drains of transistor TRF_i+1. The other source or drain of transistor TMP_i+1 is connected to the other source or drain of transistor TMN_i+1 and is connected to the input clock signal CLK. The gate of transistor TMP_i+1 is connected to node NDb_i+1.

[0080] Transistor TMN_i+1 is an n-channel transistor. One of the sources or drains of transistor TMN_i+1 is connected to the input terminal of inverter INE_i+1, one of the sources or drains of transistor TMP_i+1, and one of the sources or drains of transistor TRF_i+1. The other source or drain of transistor TMN_i+1 is connected to the other source or drain of transistor TMP_i+1 and is connected to the input clock signal CLK. The gate of transistor TMN_i+1 is connected to node NDa_i+1.

[0081] The sources and drains of transistors TMN_i+1 and TMP_i+1 are connected to each other to form a transmission gate.

[0082] Transistor TRF_i+1 is an n-channel transistor. One of the sources or drains of transistor TRF_i+1 is connected to the input terminal of inverter INE_i+1, one of the sources or drains of transistor TMN_i+1, and one of the sources or drains of transistor TMP_i+1. The other of the sources or drains of transistor TRF_i+1 is connected to the high-potential power supply VGH. The gate of transistor TRF_i is connected to node NDb_i+1.

[0083] The input terminals of inverter INE_i+1 are connected to either the source or drain of transistor TRF_i+1, either the source or drain of transistor TMN_i+1, and either the source or drain of transistor TMP_i+1. The output terminals of inverter INE_i+1 are connected to the other input terminal of NOR gate NR_i+1 and node OTP_i+1.

[0084] The output terminal of the inverter INV_i+1 outputs the light-emitting signal EMi+1 via node NDa_i+1. As described above, if the light-emitting signal EMi+1 is input to the pixel circuit PC of pixel PX, the light-emitting element ELM emits light.

[0085] Node INP_i+1 is the input terminal of the flip-flop circuit FF_i+1. The carry signal is input to node INP_i+1 from the output terminal (node ​​OTP_i) of the previous stage flip-flop circuit FF_i.

[0086] Node OTP_i+1 is the output terminal of the flip-flop circuit FF_i+1. A carry signal is output from node OTP_i+1 to the input terminal (node ​​INP_i+2, not shown) of the next stage flip-flop circuit (flip-flop circuit FF_i+2, not shown). Furthermore, if flip-flop circuit FF_i+1 is the final stage (i+1 = m), there is no subsequent stage flip-flop circuit.

[0087] The circuit configuration of flip-flop circuit FF_i is, for example, a flip-flop circuit used for odd-numbered stages. The circuit configuration of flip-flop circuit FF_i+1 is, for example, a flip-flop circuit used for even-numbered stages.

[0088] Figure 7 This is the timing diagram of the shift register for the comparison example.

[0089] After the power supply signal PSL rises, that is, after it changes from low level (L) to high level (H), the reset signal RST changes from low level (L) to high level (H). The period from the rise of the power supply signal PSL to the change of the reset signal RST to high level (H) is defined as the reset period PRSr.

[0090] Furthermore, before the power supply signal PSL rises, the light emission signal EM may be in either a high level (H) or a low level (L) state. In the comparative example, the light emission signal EM before the power supply signal PSL rises (in... Figure 7 The potential of the light-emitting signals EM1 to EM4 is set to uncertain (recorded as "uncertain").

[0091] If a low-level (L) reset signal RST is input to transistor TRRr_i, transistor TRRr_i becomes on. The source and drain of transistor TRRr_i become the same potential as the high-potential power supply VGH (high level (H)). The input terminal of inverter INV_i, connected to either the source or drain of transistor TRRr_i, also becomes high level (H). Because the input terminal becomes high level (H), inverter INV_i outputs a low-level (L) light-emitting signal EMi from its output terminal.

[0092] When the light emission signal EMi is at a low level (L), such as Figure 5 As shown, the light-emitting element ELM is connected to the high-potential power supply ELVDD and the low-potential power supply ELVSS. In all trigger circuits FF, the same operation as trigger circuit FF_i is performed. Therefore, during the reset period PRSr, the light-emitting elements ELM of all pixels PX are connected to the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0093] Even after the PRS ends during the reset period, all light-emitting signals EM remain at a low level (L). That is, the light-emitting element ELM remains connected to both the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0094] After the reset period PRSr, the clock signal CLK is input to the other side of the source or drain of transistor TMN in all flip-flop circuits FF, and to the other side of the source or drain of transistor TMP. Then, the start pulse STP is input to node INP_1, which is the input terminal of flip-flop circuit FF_1. That is, the start pulse STP changes from low level (L) to high level (H).

[0095] After the initial pulse STP changes to a high level (H), the light-emitting signal EM1 changes from a low level (L) to a high level (H) at the timing of the rising clock signal CLK. If the light-emitting signal EM1 becomes high (H), then... Figure 4 As shown, the light-emitting element ELM is disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0096] The high-potential power supply ELVDD and the low-potential power supply ELVSS are connected to the light-emitting element ELM from the rise of the reset signal RST until the rise of the initial start pulse STP. In the comparative example, the period from the rise of the reset signal RST to the rise of the initial start pulse STP is defined as the power rise period PSPr. During the power rise period PSPr, the high-potential power supply ELVDD and the low-potential power supply ELVSS rise.

[0097] The high-potential power supply ELVDD and the low-potential power supply ELVSS are, for example, 5V and 0V, as described above. That is, as long as the potential difference between the high-potential power supply ELVDD and the low-potential power supply ELVSS is 5V, it is sufficient. Even when the light-emitting element ELM is connected to both the high-potential power supply ELVDD and the low-potential power supply ELVSS, as long as the gate potential of the transistor TRI, which acts as the current control transistor in the pixel circuit PC, is at the cutoff potential, no current flows, and therefore the light-emitting element ELM does not emit light.

[0098] However, the gate potential of the current-controlled transistor TRI is in an uncertain state immediately after the power supply rises, and there is a possibility that the current-controlled transistor may not be in the off state and current may still flow. In this case, the light-emitting element ELM will emit unwanted light.

[0099] Even if Figure 6 The shift register SRr shown can also suppress unwanted light emission by fixing the start pulse of the first frame to a high level (H) when the power supply rises. Its operation is explained below.

[0100] Figure 8 This is a timing diagram showing the sequence of power-on for the pixel circuit of the comparative example. Figure 9 It indicates that the process is being carried out. Figure 8 A block diagram outlining the operation of the shift register. In the first frame, the start pulse ST P is fixed at a high level (H).

[0101] First, a start pulse STP is input to the first-stage flip-flop circuit FF_1 of the shift register SR. Flip-flop circuit FF_1 outputs a light-emitting signal EM1 and outputs a pulse (carry signal) to the second-stage flip-flop circuit FF_2. Since the start pulse STP is high (H), the light-emitting signal EM1 also becomes high (H). The light-emitting signal EM1 is input to the pixel circuit PC of each pixel PX in the first row (first stage) via the scan line GL. Consequently, the light-emitting signal EM1 is input to the switching element SWT of each pixel PX in the first row, and the switching element SWT becomes off. Therefore, the light-emitting element ELM of each pixel PX in the first row is disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0102] The second-stage trigger circuit FF_2, which has been input with the aforementioned pulse (carry signal), outputs the light-emitting signal EM2 and also outputs a pulse (carry signal) to the third-stage trigger circuit FF_2. Similar to the pixels PX in the first row, the light-emitting elements ELM of each pixel PX in the second row are disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0103] From the third level to the final level (m level), the same operation as described above is performed, and the light-emitting elements ELM of all pixels PX are disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS. At this time, the switching elements SWT of all pixels PX are maintained at a high level (H) by the light-emitting signals EM (light-emitting signals EM1 to EMm).

[0104] The EL power supply rises when the individual light-emitting elements (ELMs) of all pixels (PX) are disconnected from the EL power supply (EL power supply ELVDD and EL power supply ELVSS). At the end of this rise, the start pulse STP changes from high (H) to low (L). The second frame begins from here.

[0105] A low-level (L) start pulse STP is input to the first-stage trigger circuit FF_1. This causes the light-emitting signal EM1 to go low (L). The switching element SWT of each pixel PX connected to the first-stage (first row) scan line GL becomes active. The high-potential power supply ELVDD and the low-potential power supply ELVSS are connected to the light-emitting element ELM of each pixel PX in the first row, illuminating the light-emitting element ELM.

[0106] The trigger circuit FF_1 receives a low-level (L) start pulse STP and outputs a pulse (carry signal) to the second-stage trigger circuit FF_2. The switching element SWT of each pixel PX connected to the second-stage (second row) scan line GL becomes on. The high-potential power supply ELVDD and the low-potential power supply ELVSS are connected to the light-emitting element ELM of each pixel PX in the second row, and the light-emitting element ELM is lit.

[0107] From level 3 to the final level (level m), the same action as described above is performed, and the light-emitting elements (ELMs) of all pixels PX are illuminated. This concludes the action for the second frame.

[0108] In the first frame, the start pulse STP is maintained at a high level (H) until the light-emitting elements (ELMs) of all pixels PX are off. In the second frame, the start pulse STP is maintained at a low level (L) until the light-emitting elements (ELMs) of all pixels PX are lit. However, from the third frame onwards, the start pulse STP is output as a pulse at the beginning of each frame.

[0109] exist Figure 8 as well as Figure 9 In the operation of the shift register shown, during the rise of the high-potential power supply ELVDD and the low-potential power supply ELVSS, the light-emitting elements (ELMs) of all pixels PX are disconnected from the power supply. Therefore, unexpected light emission from the ELMs is prevented.

[0110] However, in Figure 8 as well as Figure 9 The operation of the shift register shown requires the start pulse STP to be kept high (H) for one frame. Additionally, the rise of the high-level power supply ELVDD and the low-level power supply ELVSS also requires one frame. This complex operation demands a high degree of control, complicating the system. Furthermore, there are concerns about increased manufacturing costs for display devices with such shift registers.

[0111] In this embodiment, a reset element is provided in the shift register, and the output of the shift register is also set to cut off. Therefore, the light-emitting elements (ELMs) of all pixels (PXs) can be disconnected from the power supply simply by applying a reset signal to this reset element.

[0112] Figure 10 This is a circuit diagram illustrating the configuration of the shift register in the implementation method. Figure 10 The shift register SR shown contains a flip-flop circuit FF_i at the i-th stage (where i is a natural number satisfying 1≤i≤(m-1)) and a flip-flop circuit FF_i+1 at the (i+1)-th stage.

[0113] The trigger circuit FF_i has a NOR gate NR_i, a transistor TRR_i, an inverter INV_i, a transistor TMP_i, a transistor TMN_i, and a transistor TRF_i.

[0114] In addition, Figure 10 In the diagram, no lines are used to connect the nodes to make them easier to understand, but nodes NDa_i are connected to each other. Similarly, nodes NDb_i are connected to each other.

[0115] One input terminal of the NOR gate NR_i is connected to node INP_i. The other input terminal of the NOR gate NR_i is connected to either the source or drain of transistor TMP_i, either the source or drain of transistor TMN_i, either the source or drain of transistor TRF_i, and node OTP_i. The output terminal of the NOR gate NR_i is connected to either the source or drain of transistor TRR_i, the input terminal of inverter INV_i, and node NDb_i.

[0116] Transistor TRR_i is an n-channel transistor. One of the source or drain terminals of transistor TRR_i is connected to the output terminal of NOR gate NR_i, the input terminal of inverter INV_i, and node NDb_i. The other of the source or drain terminal of transistor TRR_i is connected to the low-potential power supply VGL. A reset signal RST is input to the gate of transistor TRR_i. Transistor TRR_i acts as a reset element.

[0117] Transistor TMP_i is a p-channel transistor. One of the sources or drains of transistor TMP_i is connected to the other end of the input terminal of NOR gate NR_i, one of the sources or drains of transistor TMN_i, one of the sources or drains of transistor TRF_i, and node OTP_i. The other end of the source or drain of transistor TMP_i is connected to the other end of the source or drain of transistor TMN_i and is connected to the input clock signal CLK. The gate of transistor TMP_i is connected to node NDb_i.

[0118] Transistor TMN_i is an n-channel transistor. One of the sources or drains of transistor TMN_i is connected to one of the sources or drains of transistor TMP_i, the other end of the input terminal of NOR gate NR_i, one of the sources or drains of transistor TRF_i, and node OTP_i. The other end of the source or drain of transistor TMN_i is connected to the other end of the source or drain of transistor TMP_i and is connected to the input clock signal CLK. The gate of transistor TMN_i is connected to node NDa_i.

[0119] The sources and drains of transistors TMN_i and TMP_i are connected to each other to form a transmission gate.

[0120] Transistor TRF_i is an n-channel transistor. One of the sources or drains of transistor TRF_i is connected to one of the sources or drains of transistor TMN_i, one of the sources or drains of transistor TMP_i, the other end of the input terminal of NOR gate NR_i, and node OTP_i. The other end of the source or drain of transistor TRF_i is connected to the low-potential power supply VGL. The gate of transistor TRF_i is connected to node NDb_i.

[0121] Node INP_i is the input terminal of the flip-flop circuit FF_i. The carry signal is input to node INP_i from the output terminal (node ​​OTP_i-1, not shown) of the previous stage flip-flop circuit (flip-flop circuit FF_i-1, not shown).

[0122] Node OTP_i is the output terminal of the flip-flop circuit FF_i. The carry signal is output from node OTP_i to the input terminal (node ​​INP_i+1) of the next stage flip-flop circuit FF_i+1.

[0123] The light emission signal EMi is output from the output terminal of the inverter INV_i via node NDa_i. As described above, if the light emission signal EMi is input to the pixel circuit PC of pixel PX, the light emission element ELM emits light.

[0124] The flip-flop circuit FF_i+1 in the (i+1)th stage has a NOR gate NR_i+1, a transistor TRR_i+1, an inverter INV_i+1, a transistor TMP_i+1, a transistor TMN_i+1, a transistor TRF_i+1, and an inverter INE_i+1.

[0125] As above, no lines are used to connect the nodes in the diagram for ease of understanding, but nodes NDa_i+1 are connected to each other. Similarly, nodes NDb_i+1 are connected to each other.

[0126] One input terminal of the NOR gate NR_i+1 is connected to node INP_i+1. The other input terminal of the NOR gate NR_i+1 is connected to the output terminal of inverter INE_i+1 and node OTP_i+1. The output terminal of the NOR gate NR_i+1 is connected to either the source or drain of transistor TRR_i+1, the input terminal of inverter INV_i+1, and node NDb_i+1.

[0127] Transistor TRR_i+1 is an n-channel transistor. One of the source or drain terminals of transistor TRR_i+1 is connected to the output terminal of NOR gate NR_i+1, the input terminal of inverter INV_i+1, and node NDb_i+1. The other of the source or drain terminal of transistor TRR_i+1 is connected to the low-potential power supply VGL. A reset signal RST is input to the gate of transistor TRR_i+1. Transistor TRR_i+1 acts as a reset element.

[0128] Transistor TMP_i+1 is a p-channel transistor. One of the sources or drains of transistor TMP_i+1 is connected to the input terminal of inverter INE_i+1, one of the sources or drains of transistor TMN_i+1, and one of the sources or drains of transistor TRF_i+1. The other source or drain of transistor TMP_i+1 is connected to the other source or drain of transistor TMN_i+1 and is connected to the input clock signal CLK. The gate of transistor TMP_i+1 is connected to node NDb_i+1.

[0129] Transistor TMN_i+1 is an n-channel transistor. One of the sources or drains of transistor TMN_i+1 is connected to the input terminal of inverter INE_i+1, one of the sources or drains of transistor TMP_i+1, and one of the sources or drains of transistor TRF_i+1. The other source or drain of transistor TMN_i+1 is connected to the other source or drain of transistor TMP_i+1 and is connected to the input clock signal CLK. The gate of transistor TMN_i+1 is connected to node NDa_i+1.

[0130] The sources and drains of transistors TMN_i+1 and TMP_i+1 are connected to each other to form a transmission gate.

[0131] Transistor TRF_i+1 is an n-channel transistor. One of the sources or drains of transistor TRF_i+1 is connected to the input terminal of inverter INE_i+1, one of the sources or drains of transistor TMN_i+1, and one of the sources or drains of transistor TMP_i+1. The other of the sources or drains of transistor TRF_i+1 is connected to the high-potential power supply VGH. The gate of transistor TRF_i is connected to node NDb_i+1.

[0132] The input terminals of inverter INE_i+1 are connected to either the source or drain of transistor TRF_i+1, either the source or drain of transistor TMN_i+1, and either the source or drain of transistor TMP_i+1. The output terminals of inverter INE_i+1 are connected to the other input terminal of NOR gate NR_i+1 and node OTP_i+1.

[0133] The output terminal of the inverter INV_i+1 outputs the light-emitting signal EMi+1 via node NDa_i+1. As described above, when the light-emitting signal EMi+1 is input to the pixel circuit PC of pixel PX, the light-emitting element ELM emits light.

[0134] Node INP_i+1 is the input terminal of the flip-flop circuit FF_i+1. The carry signal is input to node INP_i+1 from the output terminal (node ​​OTP_i) of the previous stage flip-flop circuit FF_i.

[0135] Node OTP_i+1 is the output terminal of the flip-flop circuit FF_i+1. A carry signal is output from node OTP_i+1 to the input terminal (node ​​INP_i+2, not shown) of the next stage flip-flop circuit (flip-flop circuit FF_i+2, not shown). Furthermore, if flip-flop circuit FF_i+1 is the final stage (i+1 = m), there is no subsequent stage flip-flop circuit.

[0136] The circuit configuration of flip-flop circuit FF_i is, for example, a flip-flop circuit used for odd-numbered stages. The circuit configuration of flip-flop circuit FF_i+1 is, for example, a flip-flop circuit used for even-numbered stages.

[0137] Figure 11 This is a timing diagram of the shift register in the implementation method. First, the power supply signal PSL rises, that is, it changes from a low level (L) to a high level (H).

[0138] A reset signal RST is input at the timing when the power supply signal PSL changes from low (L) to high (H). The reset signal RST changes from low (L) to high (H). The period from the high (H) reset signal RST until the next change to low (L) is defined as the reset period PRS.

[0139] If a high-level (H) reset signal RST is input to transistor TRR_i, transistor TRR_i becomes on. The source and drain of transistor TRR_i become the same potential as the low-level power supply VGL (low level (L)). The input terminal of inverter INV_i, connected to either the source or drain of transistor TRR_i, also becomes low level (L). Because the input terminal becomes low level (L), inverter INV_i outputs a high-level (H) light-emitting signal EMi from its output terminal.

[0140] When the light emission signal EMi is at a high level (H), such as Figure 4 As shown, the light-emitting element ELM is disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS. In all trigger circuits FF, the same operation as in trigger circuit FF_i is performed. Therefore, the light-emitting elements ELM of all pixels PX are disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS during the reset period PRS.

[0141] Even after the PRS ends during the reset period, all light-emitting signals EM are maintained at a high level (H). That is, the light-emitting element ELM is kept disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0142] After the reset period PRS, the clock signal CLK is input to the other side of the source or drain of transistor TMN in all flip-flop circuits FF, and to the other side of the source or drain of transistor TMP. Then, the start pulse STP is input to node INP_1, which is the input terminal of flip-flop circuit FF_1. That is, the start pulse STP changes from low level (L) to high level (H).

[0143] At the timing of the initial pulse STP's descent, i.e., the change from high level (H) to low level (L), the light-emitting signal EM1 changes from high level (H) to low level (L). If the light-emitting signal EM1 becomes low level (L), then as... Figure 5 As shown, the light-emitting element ELM is connected to a high-potential power supply ELVDD and a low-potential power supply ELVSS. Therefore, the pixel PX connected to the scan line GL in the first row (first level) emits light.

[0144] If a carry signal is output from the first-stage flip-flop circuit FF_1 to the second-stage flip-flop circuit FF_2, then flip-flop circuit FF_2 will operate in the same way as flip-flop circuit FF_1. This process is repeated sequentially from the third-stage flip-flop circuit FF_3 to the final-stage flip-flop circuit FF_m.

[0145] After the light-emitting signal EM1 changes from high level (H) to low level (L), the light-emitting signals EM2 to EMm change from high level (H) to low level (L) sequentially during the timing of the clock signal CLK falling (changing from high level (H) to low level (L)).

[0146] After the reset signal RST is input until the initial start pulse STP falls, the high-level power supply ELVDD and the low-level power supply ELVSS are disconnected from the light-emitting element ELM. The period from the input reset signal RST to the fall of the initial start pulse STP is defined as the power rise period PSP. The rise of the high-level power supply ELVDD and the low-level power supply ELVSS must be completed within the power rise period PSP.

[0147] In this embodiment, during the power-up phase of the PSP, the light-emitting element ELM is disconnected from both the high-potential power supply ELVDD and the low-potential power supply ELVSS. Therefore, unwanted light emission is not generated. This results in a display device DSP with improved light emission quality.

[0148] <Example 1>

[0149] Figure 12 This diagram illustrates other configuration examples of the display device in the embodiment. Figure 12 In the example shown, with Figure 10 The difference between the example shown and the one described is that the shift register is connected to a NAND gate, i.e., a NAND gate.

[0150] exist Figure 12 In the shift register SR shown, the output terminal of the inverter INV_i in the flip-flop circuit FF_i is connected to the NAND gate NND_i via node NDa_i. One side of the input terminal of the NAND gate NND_i is connected to the output terminal of the inverter INV_i as described above. The other side of the input terminal of the NAND gate NND_i is connected to the other side of the input terminal of the NAND gate NND_i in other stages via wiring LR. Figure 12 In this circuit, the other end of the input terminal of NAND gate NND_i is connected to NAND gate NND_i+1 via wiring LR. An LED signal EMi is output from the output terminal of NAND gate NND_i. A reset signal RST is input to wiring LR.

[0151] exist Figure 12 In the shift register SR shown, the NAND gates NAND (NND_i and NAND_i+1) and the wiring LR, other than the structure, are... Figure 6 The same. A NAND gate (NND) is equivalent to a reset element connected to a flip-flop circuit (FF).

[0152] Figure 13 This is the timing diagram of the shift register that constitutes Example 1. (And...) Figure 11 Similarly, after the power supply signal PSL changes from low level (L) to high level (H), the reset signal RST changes from low level (L) to high level (H). The period from the rise of the power supply signal PSL to the change of the reset signal RST to high level (H) is defined as the reset period PRS.

[0153] In addition, with Figure 11 Similarly, before the power supply signal PSL rises, the light emission signal EM may be in either a high level (H) or a low level (L) state. In this configuration example, the light emission signal EM before the power supply signal PSL rises (in... Figure 13 The potential of the light-emitting signals EM1 to EM4 is set to uncertain (recorded as "uncertain").

[0154] If a low-level (L) reset signal RST is input to transistor TRRr_i, transistor TRRr_i becomes on. The source and drain of transistor TRRr_i become the same potential as the high-potential power supply VGH (high level (H)). The input terminal of inverter INV_i, connected to either the source or drain of transistor TRRr_i, also becomes high level (H). Because the potentials of both input terminals become high level (H), inverter INV_i outputs a low-level (L) signal from its output terminal.

[0155] A low-level (L) signal is input to one of the input terminals of the NAND gate NND_i from the output terminal of the inverter INV_i. Conversely, a low-level (L) reset signal RST is input to the other input terminal of the NAND gate NND_i. Because low-level (L) signals are input to both input terminals, the NAND gate NND_i outputs a high-level (H) LED signal EMi. Figure 13 The diagram shows that the light-emitting signals EM1 to EM4 are at a high level (H).

[0156] When the light emission signal EMi is at a high level (H), such as Figure 4As shown, the light-emitting element ELM is disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS. In all trigger circuits FF, the same operation as in trigger circuit FF_i is performed. Therefore, the light-emitting elements ELM of all pixels PX are disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS during the reset period PRS.

[0157] When the reset signal RST changes from low level (L) to high level (H), a high level (H) signal is input to both input terminals of the NAND gate NND_i. Therefore, the LED signal EMi output from the output terminal of the NAND gate NND_i changes to low level (L). Since the LED signal EMi becomes low level (L), therefore... Figure 5 As shown, the light-emitting element ELM is connected to the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0158] The rise of the high-potential power supply ELVDD and the low-potential power supply ELVSS only needs to occur during the same period as the reset period PRS. That is, in this configuration example, the reset period PRS and the power rise period PSP can be simultaneous. In this configuration example, the rise of the high-potential power supply ELVDD and the low-potential power supply ELVSS also occurs during the period when the high-potential power supply ELVDD and the low-potential power supply ELVSS are disconnected from the light-emitting element ELM. Therefore, it is possible to obtain a display device DSP that does not produce unwanted light emission and improves the light emission quality.

[0159] After the reset period PRS and the power-up period PSP end, the clock signal CLK is input to the pixel circuit PC. Then, the start pulse STP is sequentially input from the flip-flop circuit FF_1 of the shift register SR.

[0160] After the start pulse STP is input, the light-emitting signal EM1 changes from low level (L) to high level (H) at the timing of the rise of the clock signal CLK. Since the light-emitting signal EM1 becomes high level (H), the light-emitting element ELM is disconnected from the high-potential power supply ELVDD and the low-potential power supply ELVSS.

[0161] At the timing of the next clock signal CLK rising, the light-emitting signal EM1 changes from high level (H) to low level (L). Thus, the light-emitting element ELM is connected to the high-potential power supply ELVDD and the low-potential power supply ELVSS. Therefore, the light-emitting element ELM emits light.

[0162] In this configuration example, it is preferable to set the potential within the pixel circuit PC in a manner that avoids unnecessary light emission when connected to the pixel circuit PC and the high-potential power supply ELVDD and the low-potential power supply ELVSS, after the reset period RST and before the start pulse STP is input.

[0163] After the light-emitting signal EM1 changes from low level (L) to high level (H), the light-emitting signal EM2 changes from low level (L) to high level (H) when the clock signal CLK falls. The light-emitting signal EM2 changes from high level (H) to low level (L) when the next clock signal CLK falls.

[0164] By repeating the above description, the light-emitting element ELM of the pixel PX connected to the scan line GL emits light according to the change of the light-emitting signal EM at each level (each scan line GL).

[0165] In this configuration example, it also achieves the same effect as in the implementation method.

[0166] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

Claims

1. A display device comprising: Multiple pixels; Pixel circuits are respectively provided in the plurality of pixels; Multiple scan lines connected to the plurality of pixels; Multiple signal lines connected to the plurality of pixels; Scan line drive circuit connected to the plurality of scan lines; Signal line driving circuit connected to the plurality of pixels; The shift register is located in the scan line driving circuit; Multiple flip-flop circuits are provided in the shift register; as well as Reset elements are respectively provided in the plurality of flip-flop circuits. The reset element is an n-channel transistor. The pixel circuit includes a light-emitting element, a light-emitting power supply, and a switching element. The light-emitting power source includes a high-potential power source and a low-potential power source. The high-potential power supply, the switching element, the light-emitting element, and the low-potential power supply are connected in series. A light-emitting signal is output from each of the plurality of trigger circuits, and the light-emitting element emits light when the light-emitting signal is input to the switching element. When the power signal changes from low to high, the reset signal changes from low to high. When a high-level reset signal is input to the reset element, the reset element is set to the ON state. When the reset element is set to the ON state, each of the plurality of trigger circuits outputs a high-level light-emitting signal. When the light-emitting signal is high, the light-emitting element is disconnected from both the high-potential power supply and the low-potential power supply. When the light-emitting element is disconnected from the high-potential power supply and the low-potential power supply, the high-potential power supply and the low-potential power supply are activated.

2. The display device as claimed in claim 1, wherein, The light-emitting element is an organic electroluminescent element.

3. The display device as claimed in claim 1, wherein, The trigger circuit includes a NOR gate (i.e., a NOR gate), a transmission gate, and an inverter. The source or drain of the n-channel transistor is connected to the output terminal of the NOR gate and the input terminal of the inverter. The other end of the source or drain of the n-channel transistor is connected to a low-potential power supply. A reset signal is input to the gate of the n-channel transistor. The inverter outputs a light-emitting signal to the pixel circuit from its output terminal.

4. The display device as claimed in claim 1, wherein, During the period when the light-emitting power supply rises, the reset signal input to the gate of the n-channel transistor is at a low level.

5. A display device comprising: Multiple pixels; Pixel circuits are respectively provided in the plurality of pixels; Multiple scan lines connected to the plurality of pixels; Multiple signal lines connected to the plurality of pixels; Scan line drive circuit connected to the plurality of scan lines; Signal line driving circuit connected to the plurality of pixels; The shift register is located in the scan line driving circuit; Multiple flip-flop circuits are provided in the shift register; and Reset elements connected to the plurality of trigger circuits respectively, The reset element is a NAND gate, i.e., a NOT gate. The pixel circuit includes a light-emitting element, a light-emitting power supply, and a switching element. The light-emitting power source includes a high-potential power source and a low-potential power source. The high-potential power supply, the switching element, the light-emitting element, and the low-potential power supply are connected in series. A light-emitting signal is output from each of the plurality of trigger circuits, and the light-emitting element emits light when the light-emitting signal is input to the switching element. When the power signal changes from low to high, the reset signal changes from low to high. When a high-level reset signal is input to the reset element, the reset element is set to the ON state. When the reset element is set to the ON state, each of the plurality of trigger circuits outputs a high-level light-emitting signal. When the light-emitting signal is high, the light-emitting element is disconnected from both the high-potential power supply and the low-potential power supply. When the light-emitting element is disconnected from the high-potential power supply and the low-potential power supply, the high-potential power supply and the low-potential power supply are activated.

6. The display device as claimed in claim 5, wherein, The light-emitting element is an organic electroluminescent element.

7. The display device as claimed in claim 5, wherein, It also has wiring for reset signal input. The trigger circuit includes a NOR gate (i.e., a NOR gate), a transmission gate, and an inverter. One of the input terminals of the NAND gate is connected to the output terminal of the inverter. The other end of the input terminal of the NAND gate is connected to the wiring. The output terminal of the NAND gate outputs a light-emitting signal to the pixel circuit.

8. The display device as claimed in claim 7, wherein, During the period when the light-emitting power is rising, the reset signal input to the other side of the input terminal of the NAND gate via the wiring is at a low level.

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