Source-drain interconnection method for semiconductor structure, semiconductor structure, device and equipment

Abstract

The present application provides a source-drain interconnection method, semiconductor structure, device and equipment of a semiconductor structure, the method comprising: forming an active structure on a semiconductor substrate; forming a first semiconductor structure based on a first active structure; forming a second semiconductor structure based on a second active structure; performing a gate cut-off process on a first gate structure of the first semiconductor structure and a second gate structure of the second semiconductor structure to form a gate cut-off structure; performing photolithography on a first interlayer dielectric layer of the first semiconductor structure and a second interlayer dielectric layer of the second semiconductor structure based on self-alignment to a photolithography region of the gate cut-off structure to form a first deep groove; depositing metal in the first deep groove to form an interconnection through-hole structure, the interconnection through-hole structure connecting a first source-drain metal in the first semiconductor structure and a second source-drain metal in the second semiconductor structure. Through the present application, self-alignment during source-drain interconnection can be achieved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a source-drain interconnection method of a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When a stacked transistor is fabricated using a conventional sequential method, there is a problem that metal etching cannot achieve self-alignment. Summary of the invention

[0004] The present application provides a source-drain interconnection method of a semiconductor structure, a semiconductor structure, a device and an apparatus to achieve self-alignment during source-drain interconnection.

[0005] In a first aspect, an embodiment of the present application provides a source-drain interconnection method for a semiconductor structure, the method comprising: forming an active structure on a semiconductor substrate, the active structure comprising a first active structure and a second active structure; forming a first semiconductor structure based on the first active structure; forming a second semiconductor structure based on the second active structure; self-aligning the first semiconductor structure and the first semiconductor structure in a direction perpendicular to the channel; performing a gate cut-off process on a first gate structure of the first semiconductor structure and a second gate structure of the second semiconductor structure to form a gate cut-off structure; based on the self-alignment to the lithography area of ​​the gate cut-off structure, performing photolithography on a first interlayer dielectric layer of the first semiconductor structure and a second interlayer dielectric layer of the second semiconductor structure to form a first deep trench; depositing metal in the first deep trench to form an interconnection through-hole structure, the interconnection through-hole structure connecting a first source-drain metal in the first semiconductor structure and a second source-drain metal in the second semiconductor structure.

[0006] In some possible implementations, forming a first semiconductor structure based on the first active structure includes: sequentially forming a first source-drain structure, a first interlayer dielectric layer, a first gate structure, and a first source-drain metal based on the first active structure.

[0007] In some possible embodiments, based on the first active structure, a first source-drain structure, a first interlayer dielectric layer, a first gate structure and a first source-drain metal are formed in sequence, including: etching a portion of the first active structure to form the first source-drain structure; depositing semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; forming a first gate structure on both sides of the first source-drain structure; and etching a first portion of the first interlayer dielectric layer to form a first source-drain metal.

[0008] In some possible implementations, forming a second semiconductor structure based on the second active structure includes: sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second gate structure based on the second active structure.

[0009] In some possible embodiments, based on the second active structure, a second source-drain structure, a second interlayer dielectric layer, and a second gate structure are formed in sequence, including: etching a portion of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; and forming a second gate structure on both sides of the second source-drain structure.

[0010] In some possible embodiments, after performing photolithography on the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure based on the photolithography area of ​​the self-aligned gate cut-off structure to form a first deep trench, the method further includes: etching a second portion of the second interlayer dielectric layer of the second semiconductor structure to form a second source and drain metal.

[0011] In some possible implementations, before forming the second semiconductor structure based on the second active structure, the method further includes: bonding the first semiconductor structure to a carrier wafer; flipping the wafer and removing the semiconductor substrate.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, including: a first semiconductor structure; a second semiconductor structure, the second semiconductor structure is self-aligned with the first semiconductor structure in a direction perpendicular to the channel; a gate cut-off structure, the gate cut-off structure is located on both sides of a first active structure of the first semiconductor structure and a second active structure of the second semiconductor structure; an interconnection through-hole structure; the interconnection through-hole structure is self-aligned to the gate cut-off structure, the first source and drain metal of the first semiconductor structure is connected to the second source and drain metal of the second semiconductor structure through the interconnection through-hole structure, and the interconnection through-hole structure passes through a first interlayer dielectric layer of the first semiconductor structure and a second interlayer dielectric layer of the second semiconductor structure.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, based on the self-alignment to the lithography area of ​​the gate cut-off structure, the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure are photolithographically processed to form a first deep groove, and metal is deposited in the first deep groove to form a preparation process for an interconnection through-hole structure, which can make the interconnection through-hole structure self-aligned.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 This is a schematic diagram of a first implementation process of the source-drain interconnection method of the semiconductor structure in the embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0020] Figure 3 A schematic diagram of a structure of an interconnected through-hole structure in an embodiment of the present application;

[0021] FIG. 4A to FIG. 4G A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0022] Figure 5 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0023] Figure 6 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0025] The above pictures:

[0026] 10. semiconductor structure; 11. first semiconductor structure; 111. first active structure; 112. first source-drain structure; 113. first source-drain metal; 114. first interlayer dielectric layer; 115. first gate structure; 116. first spacer; 117. first metal interconnect layer; 12. second semiconductor structure; 121. second active structure; 122. second source-drain structure; 123. second source-drain metal; 124. second interlayer dielectric layer; 125. second gate structure ; 126, second spacer; 127, second metal interconnection layer; 13, interconnection through-hole structure; 14, shallow trench isolation layer; 15, first insulating layer; 16, carrier wafer; 17, gate cut-off structure; 18, anti-reflection layer; 19, photoresist layer; 180, new anti-reflection layer; 190, new photoresist layer; 21, semiconductor substrate; 22, fin structure; 23, shallow trench isolation structure; 241, first dummy gate structure; 242, second dummy gate structure; 30, first deep trench. DETAILED DESCRIPTION

[0027] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0028] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0029] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0030] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0031] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection line. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: metal etching cannot achieve self-alignment. Furthermore, this will increase the demand for alignment accuracy, and it is easy to etch the interlayer dielectric layer at the edge of the device when an alignment error occurs, thereby causing a short circuit in adjacent devices.

[0032] In order to solve the above technical problems, an embodiment of the present application provides a source-drain interconnection method for a semiconductor structure to achieve self-alignment during source-drain interconnection.

[0033] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0034] In one embodiment, the semiconductor structure may include at least two transistors, for example, a first semiconductor structure and a second semiconductor structure. The first semiconductor structure and the second semiconductor structure are arranged opposite to each other. The first active structure in the first semiconductor structure and the second active structure in the second semiconductor structure are formed by the same process. In this case, it can be understood that the first active structure and the second active structure are self-aligned.

[0035] In the embodiment of the present application, the first semiconductor structure and the second semiconductor structure in the semiconductor structure may be transistors of the same type, such as any one of the following: a fin field effect transistor, a full-surround gate transistor, and a planar transistor.

[0036] Figure 2 The semiconductor structure composed of fin field effect transistors is combined below Figure 2 The structure of the semiconductor structure shown is used to illustrate the preparation method provided in the embodiment of the present application.

[0037] Figure 1 This is a schematic diagram of the first implementation process of the source-drain interconnection method of the semiconductor structure in the embodiment of the present application, see Figure 1 As shown, the source-drain interconnection method of the semiconductor structure may include:

[0038] S101, forming an active structure on a semiconductor substrate, wherein the active structure includes a first active structure and a second active structure.

[0039] Among them, the semiconductor substrate in the embodiment of the present application can be a silicon (Si) substrate, or a silicon-on-insulator (SOI) substrate. Of course, it can also be a substrate made of other semiconductor materials, and the embodiment of the present application does not make specific limitations on this.

[0040] It is understandable that when the type of semiconductor structure is different, the arrangement of the substrate is also different accordingly. For example, when the semiconductor structure is a fin field effect transistor or a planar transistor, the semiconductor substrate can be a single-layer structure, that is, a substrate made of one semiconductor material; when the semiconductor structure is a full-surround gate transistor, the semiconductor substrate can be a stacked structure, that is, a stacked layer obtained by stacking Si material and silicon germanium (SiGe) material.

[0041] In some embodiments, when the semiconductor structure is a fin field effect transistor, the above S101 may include: etching the semiconductor substrate to form a plurality of fin structures; the upper half of the fin structure is a first active structure, and the lower half of the fin structure is a second active structure.

[0042] In other embodiments, when the semiconductor structure is a full-surround gate transistor, the above S101 may include: etching the semiconductor substrate to form a columnar structure, wherein the semiconductor substrate is formed by alternately deposited silicon layers and silicon germanium layers; the upper half of the columnar structure is a first active structure, and the lower half of the columnar structure is a second active structure.

[0043] In some other embodiments, when the semiconductor structure is a planar transistor, the above S101 may include: etching the semiconductor substrate to form a block structure; the upper half of the block structure is the first active structure, and the lower half of the block structure is the second active structure.

[0044] In the embodiment of the present application, since the semiconductor structure includes two transistors (i.e., the first semiconductor structure and the second semiconductor structure), and the first active structure of the first semiconductor structure and the second active structure of the second semiconductor structure are formed by the same etching process, a larger etching depth can be used when etching the semiconductor substrate. For example, the height of the fin-shaped structure (which may also be a columnar structure or a block structure) obtained by etching can be greater than 100nm. It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0045] In some embodiments, after the active structure, the method may further include: filling oxide above the active structure to form a shallow trench isolation (STI) structure. The height of the shallow trench isolation structure is greater than the height of the active structure.

[0046] In the embodiment of the present application, the oxide forming the shallow trench isolation structure may be any of the following: silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ) or silicon oxycarbide (SiCO), etc.

[0047] In some embodiments, after forming the shallow trench isolation structure, the method may further include: performing a chemical-mechanical planarization (CMP) process on the shallow trench isolation structure.

[0048] In an embodiment of the present application, chemical mechanical planarization is performed on the shallow trench isolation structure, so that when the shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the shallow trench isolation structure in different areas are the same, thereby making the top heights of the exposed active structures the same.

[0049] In some embodiments, after forming the shallow trench isolation structure, the method may further include: removing a portion of the shallow trench isolation structure by etching to expose the first active structure.

[0050] It is understandable that in order to perform subsequent preparation of the first semiconductor structure on the first active structure, such as preparing the first source-drain structure, the upper half of the shallow trench isolation structure can be etched first to expose the first active structure for subsequent preparation processes.

[0051] It should be noted that the etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application.

[0052] In the embodiment of the present application, the solvent used for etching the shallow trench isolation structure may be: DHF solution or BOE solution. The solvent used in the etching process in the embodiment of the present application may be selected according to actual conditions and is not limited to the above DHF solution or BOE solution.

[0053] In some embodiments, after the first active structure is exposed, ion implantation may be performed at the connection between the first active structure and the second active structure to form an electrical isolation layer, wherein the electrical isolation layer is used to electrically isolate the first active structure from the second active structure.

[0054] The ions implanted include P-type ions, N-type ions or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), antimony (Sb).

[0055] S102 , forming a first semiconductor structure based on the first active structure.

[0056] It is understandable that the first semiconductor structure can be formed based on the exposed first active structure according to standard steps of semiconductor manufacturing process.

[0057] In some embodiments, the above S102 may include: based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer, a first gate structure, and a first source-drain metal.

[0058] The first interlayer dielectric layer wraps the first active structure, the first source-drain structure and the first source-drain metal.

[0059] It can be understood that the removal of the shallow trench isolation structure and the exposure of the first active structure can provide a gate region and a source-drain groove of the first semiconductor structure. The source-drain epitaxial growth is performed in the source-drain groove of the first semiconductor structure to obtain a first source-drain structure. The semiconductor material is deposited above the first active structure to obtain a first interlayer dielectric layer. The semiconductor material is deposited in the gate region of the first semiconductor structure to obtain a first pseudo-gate structure of the first semiconductor structure. The first pseudo-gate structure is removed and a metal material is deposited in the gate region to obtain a first gate structure. The metal material is deposited above the first source-drain structure to obtain a first source-drain metal.

[0060] In some embodiments, the method of forming the first dummy gate structure may include: photolithographically opening a gate region of the first semiconductor structure, and depositing a semiconductor material (such as polysilicon) in the gate region to form a first dummy gate structure of the first semiconductor structure.

[0061] In some embodiments, after forming the first dummy gate structure, spacers may be formed on both sides of the first dummy gate structure.

[0062] In some possible embodiments, the above-mentioned sequential formation of the first source-drain structure, the first interlayer dielectric layer, the first gate structure and the first source-drain metal based on the first active structure may include: etching a portion of the first active structure to form the first source-drain structure; depositing semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; forming a first gate structure on both sides of the first source-drain structure; and etching a first portion of the first interlayer dielectric layer to form a first source-drain metal.

[0063] In some embodiments, etching a portion of the first active structure to form a first source-drain structure may include: removing a portion of the first active structure by etching to provide a source-drain groove of the first semiconductor structure. Using the spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the first semiconductor structure, and then forming the first source-drain structure on the strained material by a heavy doping process.

[0064] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0065] In some embodiments, depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide (SiO 2 )), forming a first interlayer dielectric layer; the first interlayer dielectric layer can cover the first active structure and the first source-drain structure.

[0066] In some embodiments, forming a first gate structure on both sides of the first source-drain structure may include: removing the first dummy gate structure by etching to expose the gate region of the first semiconductor structure, and depositing a metal material on the gate region of the first semiconductor structure to form a first gate structure of the first semiconductor structure. The gate region of the first semiconductor structure is located on both sides of the first source-drain structure.

[0067] In some embodiments, etching the first portion of the first interlayer dielectric layer to form the first source-drain metal may include: etching the portion of the first interlayer dielectric layer located above the first source-drain structure (i.e., the first portion of the first interlayer dielectric layer) until the upper surface of the first source-drain structure is exposed to form a first source-drain metal groove. A metal material may be deposited in the first source-drain metal groove to obtain the first source-drain metal.

[0068] In some embodiments, after S102, the method further includes: bonding the first semiconductor structure to a carrier wafer; flipping the wafer and removing the semiconductor substrate.

[0069] It is understandable that after forming the first interlayer dielectric layer of the first semiconductor structure, a post-process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be performed on the first interlayer dielectric layer to form the first metal interconnect layer of the first semiconductor structure. An insulating material (such as silicon oxide) is deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer is bonded to a carrier wafer; the first semiconductor structure bonded to the carrier wafer is flipped over so that the semiconductor substrate is placed upward, and then the semiconductor substrate is removed by etching.

[0070] In the embodiment of the present application, the first semiconductor structure is bonded to the carrier wafer, which can provide physical support for the flipped first semiconductor structure after flipping the wafer, and effectively prevent the first semiconductor structure from being broken by external force during the preparation of the second semiconductor structure.

[0071] In some embodiments, after removing the semiconductor substrate, the method may further include: removing a portion of the shallow trench isolation structure by etching to expose the second active structure.

[0072] It is understandable that in order to perform subsequent preparation of the second semiconductor structure on the second active structure, such as preparing a second source-drain structure, the lower half of the shallow trench isolation structure can be etched first to expose the second active structure for subsequent preparation processes.

[0073] It should be noted that when etching the lower half of the shallow trench isolation structure, a shallow trench isolation structure of a certain thickness may be retained, and the retained shallow trench isolation structure may be used to isolate the first semiconductor structure from the second semiconductor structure.

[0074] S103 , forming a second semiconductor structure based on the second active structure.

[0075] The first semiconductor structure and the second semiconductor structure are self-aligned in a direction perpendicular to the channel.

[0076] It is understandable that the second semiconductor structure can be formed based on the exposed second active structure according to standard steps of semiconductor manufacturing process.

[0077] In some embodiments, the above S103 may include: based on the second active structure, sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second gate structure.

[0078] The second interlayer dielectric layer wraps the second active structure and the second source-drain structure.

[0079] It can be understood that the removal of the shallow trench isolation structure and the exposure of the second active structure can provide a gate region and a source-drain groove of the second semiconductor structure. The source-drain epitaxial growth is performed in the source-drain groove of the second semiconductor structure to obtain a second source-drain structure. The semiconductor material is deposited above the second active structure to obtain a second interlayer dielectric layer. The semiconductor material is deposited in the gate region of the second semiconductor structure to obtain a second pseudo-gate structure of the second semiconductor structure. The second pseudo-gate structure is removed, and a metal material is deposited in the gate region of the second semiconductor structure to obtain a second gate structure.

[0080] In some embodiments, the method of forming the second dummy gate structure may include: photolithographically opening a gate region of the second semiconductor structure, and depositing a semiconductor material (such as polysilicon) in the gate region to form a first dummy gate structure of the second semiconductor structure.

[0081] In some embodiments, after forming the second dummy gate structure, spacers may be formed on both sides of the second dummy gate structure.

[0082] In some possible embodiments, the above-mentioned formation of a second source-drain structure, a second interlayer dielectric layer, and a second gate structure in sequence based on the second active structure may include: etching a portion of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; and forming a second gate structure on both sides of the second source-drain structure.

[0083] In some embodiments, etching a portion of the second active structure to form a second source-drain structure may include: removing a portion of the second active structure by etching to provide a source-drain groove of the second semiconductor structure. Using the spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the second semiconductor structure, and then forming the second source-drain structure on the strained material by a heavy doping process.

[0084] In some embodiments, depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide) above the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source-drain structure.

[0085] It should be noted that the first interlayer dielectric layer and the second interlayer dielectric layer in the embodiment of the present application may be formed of the same material or different materials, and the embodiment of the present application does not specifically limit this.

[0086] In some embodiments, forming a second gate structure on both sides of the second source-drain structure may include: removing the second dummy gate structure by etching to expose the gate region of the second semiconductor structure, and depositing a metal material on the gate region of the second semiconductor structure to form a second gate structure of the second semiconductor structure. The gate region of the second semiconductor structure is located on both sides of the second source-drain structure.

[0087] In the embodiment of the present application, the metal material of the first gate structure and the second gate structure can be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0088] In the embodiment of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0089] In some embodiments, before preparing the first gate structure, the method may further include: depositing a semiconductor material on the surface of the first active structure to form a first gate dielectric layer of the first semiconductor structure, wherein the first gate dielectric layer is used to isolate the first active structure from the first gate structure.

[0090] In the embodiment of the present application, the preparation method of the second gate dielectric layer of the second semiconductor structure is the same as the preparation method of the first gate dielectric layer, which is not described in detail in the embodiment of the present application.

[0091] It should be noted that the materials used to prepare the first gate dielectric layer and the second gate dielectric layer may be the same or different, and this embodiment of the present application does not specifically limit this.

[0092] S104 , performing a gate cutting process on the first gate structure of the first semiconductor structure and the second gate structure of the second semiconductor structure to form a gate cutting structure.

[0093] It can be understood that gate cutting can be performed at the edges of the first gate structure and the second gate structure, that is, at both ends along the extension direction of the first gate structure and the second gate structure, to form a gate cutting structure. The gate cutting structure is located on both sides of the active structure.

[0094] S105 , based on the self-alignment to the photolithography region of the gate cut-off structure, photolithography is performed on the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure to form a first deep trench.

[0095] It can be understood that the first deep groove formed by photolithography of a portion of the first interlayer dielectric layer and a portion of the second interlayer dielectric layer (i.e., the portion corresponding to the photolithography area in the semiconductor structure) is close to the edge of the gate cut-off structure and has self-alignment. In addition, due to the selectivity of etching, the etching will stop at the surface of the first source-drain metal, and the gate cut-off structure, the second source-drain structure and the first source-drain structure will not be etched.

[0096] S106, depositing metal in the first deep trench to form an interconnection via structure.

[0097] The interconnected via structure connects the first source-drain metal in the first semiconductor structure and the second source-drain metal in the second semiconductor structure.

[0098] It can be understood that the first deep trench is directly etched downward from the top of the second interlayer dielectric layer, along the edge of the gate cut-off structure and the edge of the second source-drain structure, to the second interlayer dielectric layer and the first interlayer dielectric layer until the first source-drain metal is exposed, and the etching is stopped, so that the two ends of the first deep trench are connected to the first source-drain metal and the second source-drain metal; then, a metal material is deposited in the first deep trench to form an interconnection through-hole structure, and the interconnection through-hole structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer. Since the first deep trench is self-aligned to the gate cut-off structure, accordingly, the interconnection through-hole structure formed by depositing the metal material in the first deep trench is also self-aligned.

[0099] In some embodiments, the method further includes: etching a second portion of the second interlayer dielectric layer to form a second source / drain metal.

[0100] It should be noted that, in the embodiment of the present application, the interconnection via structure may be formed after the second source-drain metal is formed, or the second source-drain metal may be formed after the interconnection via structure is formed, or the second source-drain metal and the interconnection via structure may be formed simultaneously. The embodiment of the present application does not specifically limit the order of forming the second source-drain metal and the interconnection via structure.

[0101] In some embodiments, etching the second portion of the second interlayer dielectric layer to form the second source-drain metal may include: etching the portion of the second interlayer dielectric layer located above the second source-drain structure (i.e., the second portion of the second interlayer dielectric layer) until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove. Depositing a metal material in the second source-drain metal groove may obtain the second source-drain metal.

[0102] In some embodiments, before executing S105 , the method may further include: depositing an anti-reflective material on the second interlayer dielectric layer to form an anti-reflective coating (BARC); and depositing a semiconductor material on the anti-reflective layer to form a photoresist layer.

[0103] In the embodiment of the present application, the main components of the anti-reflection material used in the anti-reflection layer may include but are not limited to: cross-linked resin, thermal acid generator, surfactant, etc., or may be other anti-reflection materials, which is not specifically limited in the embodiment of the present application.

[0104] It can be understood that when the second interlayer dielectric layer includes an anti-reflection layer and a photoresist layer, before executing the above S105, the following steps are also included: etching a portion of the anti-reflection layer and a portion of the photoresist layer to expose the area corresponding to the photolithography area in the second interlayer dielectric layer. Similarly, before etching the second portion of the second interlayer dielectric layer to form the second source and drain metal, the following steps can be included: etching a portion of the anti-reflection layer and a portion of the photoresist layer to expose the area corresponding to the second source and drain metal groove in the second interlayer dielectric layer.

[0105] In one example, when the second interlayer dielectric layer includes an anti-reflective layer and a photoresist layer above the second source-drain structure, the method for forming the interconnected via structure and the second source-drain metal may include the following steps: sequentially etching a portion of the photoresist layer and the anti-reflective layer above the second source-drain structure to expose a portion of the second interlayer dielectric layer; then, etching a portion of the second interlayer dielectric layer located above the second source-drain structure (i.e., a second portion of the second interlayer dielectric layer) until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove; depositing an anti-reflective material in the second source-drain metal groove and at a position where the anti-reflective layer is etched away to form a new anti-reflective layer. ; re-depositing photoresist at the position where the photoresist layer is etched away to form a new photoresist layer; then, etching a portion of the new photoresist layer and a portion of the new anti-reflection layer until the upper surface of the second source-drain structure is exposed, and a second source-drain metal groove is formed again; then, according to the pre-set self-aligned to the gate cut-off structure of the lithography area, along the edge of the gate cut-off structure and the edge of the first source-drain structure, the second interlayer dielectric layer and the first interlayer dielectric layer are photolithographically processed to form a first deep groove; depositing the same metal material in the second source-drain metal groove and the first deep groove to form a second source-drain metal and an interconnection through-hole structure.

[0106] It can be understood that the second source-drain metal and the interconnection through-hole structure are formed in the same process, the prepared second source-drain metal and the interconnection through-hole structure are interconnected, and use the same metal material. It can be understood that the second source-drain metal and the interconnection through-hole structure are an integral structure.

[0107] In an embodiment of the present application, the gate cut-off structure is used as an etching stop layer to etch a first deep groove, and then a metal material is deposited in the first deep groove to form an interconnection through-hole structure. The interconnection through-hole structure can be self-aligned, and there is no need to align it during the etching of the first deep groove, thereby simplifying the preparation process.

[0108] In some possible implementations, the interconnection via structure is located on one side of the active structure; or, the interconnection via structure is located on both sides of the active structure.

[0109] It can be understood that the interconnected through-hole structure can be located on one side of the active structure (either the left or right side, the embodiment of the present application does not specifically limit this), and the interconnected through-hole structure can also be located on both sides of the active structure at the same time, that is, two interconnected through-hole structures are formed on both sides of the active structure.

[0110] In some possible implementations, during layout design, the width of the interconnected via structure can be designed to be large enough, so that the area of ​​the interconnected via structure can be larger and the resistance of the first source-drain structure and the second source-drain structure when interconnected can be smaller.

[0111] In some embodiments, after S106, the method may further include: performing a back-end process (such as interconnect line dielectric deposition, metal line formation, lead pad formation, etc.) on the second interlayer dielectric layer to form a second metal interconnect layer of the second semiconductor structure.

[0112] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first semiconductor structure and the second semiconductor structure as fin field effect transistors as an example. Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 2 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view shows the fin structure, gate structure, source-drain structure, gate cut-off structure, source-drain metal and interconnection via structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., BB' direction).

[0113] See also Figure 2As shown, the semiconductor structure 10 includes a first semiconductor structure 11 and a second semiconductor structure 12, and the active structure in the semiconductor structure 10 is a plurality of fin-shaped structures. The fin-shaped structure is divided into two parts, which are respectively recorded as the first part and the second part. The first part is used as the first active structure 111 in the first semiconductor structure 11, and the second part is used as the second active structure 121 in the second semiconductor structure 12. The first source-drain metal 113 in the first semiconductor structure 11 and the second source-drain metal 123 in the second semiconductor structure 12 are interconnected through an interconnection through-hole structure 13. A shallow trench isolation layer 14 is provided between the first semiconductor structure 11 and the second semiconductor structure 12, and the shallow trench isolation layer 14 is used to isolate the first semiconductor structure 11 and the second semiconductor structure 12. In the AA' direction, both sides of the fin-shaped structure have a gate cut-off structure. The interconnection through-hole structure 13 is located between the edge of the gate cut-off structure and the edge of the second source-drain metal.

[0114] Figure 3 A schematic diagram of the structure of the interconnected through-hole structure in an embodiment of the present application. Figure 3 The figure shows a disassembled schematic diagram of the interconnection via structure 13, the first source-drain metal 113 and the second source-drain metal 123, see Figure 3 As shown, the interconnection via structure 13 is led out from the second source-drain metal 123 and extends to the first source-drain metal 113. Two ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123 respectively.

[0115] In the embodiment of the present application, the first active structure 111 of the first semiconductor structure 11 and the second active structure 121 of the second semiconductor structure 12 are formed by the same etching process, so that the first semiconductor structure 11 and the second semiconductor structure 12 can be self-aligned.

[0116] In combination with the above preparation method, Figure 2 The preparation process of the semiconductor structure shown is described. Figure 2 The semiconductor structure shown can be FIG. 4A to FIG. 4G The process shown is prepared FIG. 4A to FIG. 4G It is a schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application.

[0117] In one example, taking the first semiconductor structure 11 and the second semiconductor structure 12 as fin field effect transistors as an example, a first preparation process of the source-drain interconnected semiconductor structure 10 may include the following steps:

[0118] The first step: providing a semiconductor substrate 21 (such as a Si substrate) (see Figure 4A (a) in the figure.

[0119] Step 2: Etching the semiconductor substrate 21 to form a plurality of fin structures 22 (see Figure 4A (b) in the figure.

[0120] Step 3: Fill the fin structure 22 with oxide to form a shallow trench isolation structure 23 (see Figure 4A (c) in the figure). The height of the shallow trench isolation structure 23 is greater than the height of the fin-shaped structure 22, and can cover a plurality of fin-shaped structures 22. Then, the shallow trench isolation structure 23 is subjected to chemical mechanical planarization.

[0121] Step 4: Using standard steps, a portion of the shallow trench isolation structure 23 is etched to expose the first portion of the fin structure 22 (ie, the first active structure 111) (see Figure 4B (a) in the figure.

[0122] Step 5: Etch the first portion of the fin structure 22 to form source and drain grooves of the first semiconductor structure 11. Then, photolithography is performed to open the gate region of the first semiconductor structure 11, and polysilicon is deposited at the gate region to form a first dummy gate structure 241. First spacers 116 are formed on both sides of the first dummy gate structure 241 (see FIG. Figure 4B (b) in the figure.

[0123] Step 6: epitaxially grow source and drain in the source and drain grooves of the first semiconductor structure 11 to form a first source and drain structure 112. Then, a semiconductor material is deposited on the first active structure 111 to form a first interlayer dielectric layer 114 (see Figure 4B (c) in the figure.

[0124] Step 7: Remove a portion of the first interlayer dielectric layer 114 by etching to form a first source-drain metal groove, and deposit a metal material in the first source-drain metal groove to form a first source-drain metal 113. (See Figure 4C (a) in the figure.

[0125] Step 8: Remove the first dummy gate structure 241 and deposit metal in the gate region of the first semiconductor structure to form a first gate structure 115. Then, a back-end process is performed on the first interlayer dielectric layer 114 to form a first metal interconnect layer 117 (see Figure 4C (b) in the figure.

[0126] Step 9: Deposit oxide on the first metal interconnect layer 117 to form a first insulating layer 15, and bond the first insulating layer 15 to the carrier wafer 16. Next, the first semiconductor structure 11 bonded to the carrier wafer 16 is flipped over so that the semiconductor substrate 21 is placed upward (see Figure 4C (c) in the figure.

[0127] Step 10: Remove the semiconductor substrate 21 by etching, and etch the shallow trench isolation structure 23 to expose the second portion of the fin structure 22 (see Figure 4D (a) in the figure.

[0128] It should be noted that when etching the shallow trench isolation structure 23 , the etching depth is controlled to retain a certain thickness of the shallow trench isolation structure 23 to serve as the shallow trench isolation layer 14 . The shallow trench isolation layer 14 is used to isolate the first semiconductor structure 11 from the second semiconductor structure 12 .

[0129] Step 11: Form a second source-drain structure 122, a second dummy gate structure 242, a second spacer 126 and a second interlayer dielectric layer 124 on the second portion of the fin structure 22 (see Figure 4D (b) in (the specific preparation process can refer to the fifth and sixth steps).

[0130] Step 12: Remove the second dummy gate structure 242 and deposit metal in the gate region of the second semiconductor structure to form a second gate structure 125 (see Figure 4D (c) in (see step 8 for the specific preparation process).

[0131] Step 13: Perform a gate cutting process on the first gate structure 115 and the second gate structure 125 to form a gate cutting structure 17 (see Figure 4E (a) in the figure.

[0132] Step 14: Deposit an anti-reflection material on the second interlayer dielectric layer 124 to form an anti-reflection layer 18; then deposit a photoresist on the anti-reflection layer 18 to form a photoresist layer 19 (see Figure 4E (b) in the figure.

[0133] Step 15: Etch the photoresist layer 19, the anti-reflection layer 18, and a portion of the second interlayer dielectric layer 124 to form a second source-drain metal groove (see Figure 4E (c) in the figure.

[0134] Step 16: Deposit anti-reflection material in the second source-drain metal groove, and at the same time, re-deposit anti-reflection material at the etched portion of the anti-reflection layer 18 to form a new anti-reflection layer 180; re-deposit photoresist at the portion where the photoresist layer 19 is removed to form a new photoresist layer 190; the new photoresist layer 190 has no photoresist deposited in the area between the edge of the gate cut-off structure 17 and the edge of the second source-drain structure 122, forming a gap, the gap corresponding to the photolithography area self-aligned to the gate cut-off structure, for subsequent etching of the first deep groove 30 (see Figure 4F (a) in the figure.

[0135] Step 17: Etch the second interlayer dielectric layer 124 and the first interlayer dielectric layer 114 downward along the gap of the new photoresist layer 190 to form a first deep trench 30. The first deep trench penetrates the second interlayer dielectric layer 124 and the first interlayer dielectric layer 114 and is connected to the first source and drain metal 113 (see Figure 4F (b) in the figure.

[0136] In step 18, the anti-reflective material in the second source-drain metal groove is removed by etching until the second source-drain metal groove is exposed (see Figure 4F (c) in the figure.

[0137] Step 19: After removing the new photoresist layer 190 and the new anti-reflection layer 180, a metal material is deposited in the second source-drain metal groove and the first deep trench 30 to form a second source-drain metal 123 and an interconnection through-hole structure 13 (see Figure 4G (a) in the figure.

[0138] Step 20: Forming a second metal interconnection layer (see Figure 4G (b) in (see step 8 for the specific preparation process).

[0139] At this point, the semiconductor structure 10 is completed by the first preparation method, in which the first semiconductor structure 11 and the second semiconductor structure 12 are fin field effect transistors, and the first source-drain metal 113 and the second source-drain metal 123 are interconnected through the interconnection via structure 13 .

[0140] In the embodiment of the present application, during the etching of the first deep groove 30, the gate cut-off structure 17, the second source-drain structure 122, the first source-drain structure 112 and the first source-drain metal 113 will not be etched, so while keeping the area of ​​the first deep groove 30 relatively large, it can be offset to the left or right to a certain extent during etching to form first deep grooves 30 of different shapes.

[0141] In some embodiments, when the etching process of the first deep trench 30 is shifted to the left, the semiconductor structure formed is as follows: Figure 5 As shown, Figure 5 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Figure 5 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view shows the fin structure, gate structure, source-drain structure, gate cut-off structure, source-drain metal and interconnection via structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., BB' direction).

[0142] In some other embodiments, when the etching process of the first deep trench 30 is shifted to the right, the semiconductor structure formed is as follows: Figure 6 As shown, Figure 6 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Figure 6 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view shows the fin structure, gate structure, source-drain structure, gate cut-off structure, source-drain metal and interconnection via structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., BB' direction).

[0143] It should be noted that the offset of etching will not affect the self-alignment performance of the interconnection through-hole structure 13 .

[0144] In the above FIG. 4A to FIG. 4G In the preparation process shown, a first deep trench is first formed by etching, and then a second source-drain metal groove is formed by etching, and the second source-drain metal and the interconnection through-hole structure are formed by the same process; it should be noted that the embodiment of the present application does not limit the preparation order of the first deep trench and the second source-drain metal groove, nor does it limit the preparation order of the second source-drain metal and the interconnection through-hole structure.

[0145] Figure 7 Schematic diagram of the second preparation process of the semiconductor structure in the embodiment of the present application. Figure 2 The semiconductor structure shown can be Figure 7 The process shown is prepared Figure 7 Shows a difference from FIG. 4A to FIG. 4G Preparation process.

[0146] In one example, taking the first semiconductor structure 11 and the second semiconductor structure 12 as fin field effect transistors as an example, the second preparation process of the source-drain interconnected semiconductor structure 10 may include the following steps:

[0147] Among them, the first to fifteenth steps of the second preparation process of the source-drain interconnected semiconductor structure 10 are the same as the first to fifteenth steps of the first preparation process mentioned above. The specific process can be referred to the above embodiment, and the embodiment of the present application will not be repeated here.

[0148] Step 16: Remove the photoresist layer 19 and the anti-reflection layer 18, and deposit a metal material in the second source-drain metal groove to form a second source-drain metal 123 (see Figure 7 (a) in the figure.

[0149] Step 17: Deposit anti-reflection material to form a new anti-reflection layer 180; deposit photoresist to form a new photoresist layer 190; and etch down the new photoresist layer 190, the new anti-reflection layer 180, the second interlayer dielectric layer 124 and a portion of the first interlayer dielectric layer 114 in the area between the edge of the gate cut-off structure 17 and the edge of the second source-drain structure 122 to form a first deep trench 30. When the first deep trench 30 is connected to the first source-drain metal 113, the etching is stopped (see Figure 7 (b) in the figure.

[0150] Step 18: After removing the new photoresist layer 190 and the new anti-reflection layer 180, a metal material is deposited in the first deep trench 30 to form an interconnection via structure 13. A back-end process is performed on the second interlayer dielectric layer 124 to form a second metal interconnection layer 127 (see Figure 7 (c) in the figure) (For details, please refer to the twentieth step in the first preparation process of the semiconductor structure).

[0151] At this point, the semiconductor structure 10 is completed by the second preparation method, in which the first semiconductor structure 11 and the second semiconductor structure 12 are fin field effect transistors, and the first source-drain metal 113 and the second source-drain metal 123 are interconnected through the interconnection via structure 13 .

[0152] In the embodiment of the present application, the interconnection through-hole structure 13 in the semiconductor structure 10 connects the first source-drain metal 113 of the first semiconductor structure 11 and the second source-drain metal 123 of the second semiconductor structure 12, thereby realizing the interconnection between the first source-drain structure 112 of the first semiconductor structure 11 and the second source-drain structure 122 of the second semiconductor structure 12.

[0153] Furthermore, based on the self-alignment to the lithography area of ​​the gate cut-off structure 17, the first interlayer dielectric layer 114 of the first semiconductor structure 11 and the second interlayer dielectric layer 124 of the second semiconductor structure 12 are photolithographically processed to form a first deep groove 30, and metal is deposited in the first deep groove 30 to form an interconnection through-hole structure 13. The preparation process can make the interconnection through-hole structure 13 self-aligned.

[0154] Furthermore, since the interconnection through-hole structure 13 is self-aligned, the requirement for alignment accuracy can be reduced, and etching of the interlayer dielectric layer at the edge of the device can be avoided when alignment errors occur, thereby reducing the occurrence of short circuits between adjacent devices.

[0155] Furthermore, the self-aligned semiconductor structure 10 provided in the embodiment of the present application can be inspected using an inspection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure 10 provided in the embodiment of the present application can be inspected by TEM slicing to inspect the interconnection between the first source-drain metal 113 and the second source-drain metal 123.

[0156] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 5 and Figure 6 The semiconductor structure shown will not be described in detail here.

[0157] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 5 and Figure 6 The semiconductor structure shown will not be described in detail here.

[0158] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0159] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A source-drain interconnection method for a semiconductor structure, characterized in that: The method comprises: forming an active structure on a semiconductor substrate, the active structure comprising a first active structure and a second active structure; Based on the first active structure, forming a first semiconductor structure; Based on the second active structure, a second semiconductor structure is formed; the first semiconductor structure and the second semiconductor structure are self-aligned in a direction perpendicular to the channel; Performing a gate cut-off process on the first gate structure of the first semiconductor structure and the second gate structure of the second semiconductor structure to form a gate cut-off structure; Based on self-alignment to the photolithography region of the gate cut-off structure, photolithography is performed on the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure to form a first deep trench; Depositing metal in the first deep trench to form an interconnection via structure; the interconnection via structure connects a first source-drain metal in the first semiconductor structure and a second source-drain metal in the second semiconductor structure; Among them, based on the self-alignment to the lithography area of ​​the gate cut-off structure, the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure are photolithographically processed to form a first deep groove, including: from the top of the second interlayer dielectric layer, the second interlayer dielectric layer and the first interlayer dielectric layer are etched downward along the edge of the gate cut-off structure and the edge of the second source and drain structure of the second semiconductor structure until the first source and drain metal is exposed, and the etching is stopped to form the first deep groove.

2. The method according to claim 1, characterized in that The forming of a first semiconductor structure based on the first active structure comprises: Based on the first active structure, a first source-drain structure, a first interlayer dielectric layer, the first gate structure and the first source-drain metal are formed in sequence.

3. The method according to claim 2, characterized in that The step of sequentially forming the first source-drain structure, the first interlayer dielectric layer, the first gate structure and the first source-drain metal based on the first active structure includes: Etching a portion of the first active structure to form the first source-drain structure; Depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; forming a first gate structure on both sides of the first source-drain structure; A first portion of the first interlayer dielectric layer is etched to form the first source / drain metal.

4. The method according to claim 1, characterized in that: The forming of a second semiconductor structure based on the second active structure comprises: Based on the second active structure, the second source-drain structure, the second interlayer dielectric layer and the second gate structure are formed in sequence.

5. The method according to claim 4, characterized in that The second source-drain structure, the second interlayer dielectric layer and the second gate structure are sequentially formed based on the second active structure, including: Etching a portion of the second active structure to form the second source-drain structure; Depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; A second gate structure is formed on both sides of the second source-drain structure.

6. The method according to claim 1, characterized in that After performing photolithography on the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure based on self-alignment to the photolithography region of the gate cut-off structure to form a first deep trench, the method further includes: A second portion of the second interlayer dielectric layer of the second semiconductor structure is etched to form the second source-drain metal.

7. The method according to claim 1, characterized in that Before forming a second semiconductor structure based on the second active structure, the method further includes: bonding the first semiconductor structure to a carrier wafer; The semiconductor substrate is flipped and removed.

8. A semiconductor structure, characterized in that: include: a first semiconductor structure; a second semiconductor structure, the second semiconductor structure being self-aligned with the first semiconductor structure in a direction perpendicular to the channel; a gate cut-off structure, the gate cut-off structure being located on both sides of a first active structure of the first semiconductor structure and a second active structure of the second semiconductor structure; Interconnecting via structures; The interconnection via structure is self-aligned to the gate cut-off structure, the first source-drain metal of the first semiconductor structure is connected to the second source-drain metal of the second semiconductor structure through the interconnection via structure, and the interconnection via structure passes through the first interlayer dielectric layer of the first semiconductor structure and the second interlayer dielectric layer of the second semiconductor structure.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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