Solar cell and its preparation method

Abstract

This application relates to a solar cell and a method for manufacturing the same. A solar cell includes a silicon wafer, a passivated contact structure disposed on the back surface of the silicon wafer, and an electrode pattern; the passivated contact structure includes a first silicon oxide layer and a doped polysilicon layer that are disposed in a first region and are sequentially stacked in a direction gradually away from the silicon wafer; a second silicon oxide layer and a doped silicide layer that are disposed in a second region and are sequentially stacked in a direction gradually away from the silicon wafer; wherein, the first region is the region where the electrode pattern is located, the second region includes at least the remaining region of the solar cell except the region where the electrode pattern is located, and the electrode pattern forms an ohmic contact with the doped polysilicon layer. The above-mentioned solar cell is beneficial to further improve the photoelectric conversion efficiency of the cell.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and particularly to a solar cell and a preparation method thereof. Background Art

[0002] In the current passivation contact structure of solar cells, the polycrystalline silicon layer has serious parasitic absorption of light. Growing an overly thick polycrystalline silicon layer on the entire surface of the silicon wafer will significantly reduce the light utilization rate of the cell, thereby reducing the short-circuit current of the cell. How to effectively reduce the recombination in metal and non-metal regions while ensuring the light utilization rate of the cell and improving the cell efficiency has become an urgent problem to be solved. Summary of the Invention

[0003] Based on this, it is necessary to provide a solar cell and a preparation method thereof that can improve the light utilization rate and cell efficiency.

[0004] In a first aspect, this application provides a solar cell, including a silicon wafer, a passivation contact structure disposed on the back surface of the silicon wafer, and an electrode pattern;

[0005] The passivation contact structure includes a first silicon oxide layer and a doped polycrystalline silicon layer that are disposed in a first region and are sequentially stacked in a direction gradually away from the silicon wafer; a second silicon oxide layer and a doped silicide layer that are disposed in a second region and are sequentially stacked in a direction gradually away from the silicon wafer;

[0006] Wherein, the first region is the region where the electrode pattern is located, the second region includes at least the remaining region of the solar cell except the region where the electrode pattern is located, and the electrode pattern forms an ohmic contact with the doped polycrystalline silicon layer.

[0007] In some embodiments, the second region further includes: the region where the electrode pattern is located;

[0008] The second silicon oxide layer and the doped silicide layer further extend to cover the side of the doped polycrystalline silicon layer away from the silicon wafer.

[0009] In some embodiments, the thickness of the doped polycrystalline silicon layer is greater than the thickness of the doped silicide layer.

[0010] In some embodiments, the thickness of the doped polycrystalline silicon layer is 30 nm to 200 nm.

[0011] In some embodiments, the thickness of the doped silicide layer is 10 nm to 80 nm.

[0012] In some embodiments, the doping concentration of the doping element in the doped polycrystalline silicon layer is 6E19 cm -3 ~7E20 cm-3 。

[0013] In some embodiments, the doping concentration of the doping element in the doped silicide layer is 1E19 cm -3 ~7E20 cm -3 。

[0014] In some embodiments, the thickness of the first silicon oxide layer is < 3 nm.

[0015] In some embodiments, the thickness of the second silicon oxide layer is < 3 nm.

[0016] In some embodiments, the silicide in the doped silicide layer includes one or more of silicon carbide, silicon oxide, and silicon nitride.

[0017] In a second aspect, the present application further provides a method for manufacturing a solar cell, including the following steps:

[0018] Form a passivated contact structure on the back surface of the silicon wafer; the passivated contact structure includes a first silicon oxide layer and a doped polysilicon layer that are sequentially stacked in a direction gradually away from the silicon wafer and are disposed in a first region; a second silicon oxide layer and a doped silicide layer that are sequentially stacked in a direction gradually away from the silicon wafer and are disposed in a second region; wherein, the first region is the region where the electrode pattern is located, and the second region includes at least the remaining region of the solar cell except the region where the electrode pattern is located;

[0019] Form the electrode pattern in the first region of the passivated contact structure, and the electrode pattern forms an ohmic contact with the doped polysilicon layer.

[0020] In some embodiments, the second region includes the remaining region of the solar cell except the region where the electrode pattern is located, and the preparation of the passivated contact structure includes the following steps:

[0021] Form the first silicon oxide layer on the back surface of the silicon wafer;

[0022] Form the doped polysilicon layer on the surface of the first silicon oxide layer on the side away from the silicon wafer;

[0023] Remove the first silicon oxide layer and the doped polysilicon layer in the remaining region except the region where the electrode pattern is located;

[0024] In the remaining region except the region where the electrode pattern is located, sequentially form the second silicon oxide layer and the doped silicide layer that are stacked in a direction gradually away from the silicon wafer.

[0025] In some of these embodiments, the second region further includes the region where the electrode pattern is located, and the preparation of the passivation contact structure further includes the following steps:

[0026] While sequentially forming the stacked second silicon oxide layer and the doped silicide layer in the remaining regions except the region where the electrode pattern is located, the second silicon oxide layer and the doped silicide layer are also formed on the side of the doped polysilicon layer away from the silicon wafer, so that the second silicon oxide layer and the doped silicide layer extend to cover the region where the electrode pattern is located.

[0027] The present application provides a solar cell, including a silicon wafer, a passivation contact structure disposed on the back surface of the silicon wafer, and an electrode pattern. In the passivation contact structure, a doped polysilicon layer is disposed in the region where the electrode pattern is located. The doped polysilicon layer is beneficial to reducing the contact resistance of the electrode, improving the fill factor and energy conversion efficiency of the battery. Further, at least in the remaining regions except the region where the electrode pattern is located, a doped silicide layer is provided. The doped silicide layer is beneficial to reducing the parasitic absorption of light and increasing the back reflectivity, thereby being beneficial to further improving the photoelectric conversion efficiency of the battery. Description of the Drawings

[0028] Figure 1 It is a schematic structural diagram of a solar cell in an embodiment.

[0029] 1: Solar cell; 10: Silicon wafer; 20: Passivation contact structure; 21: First silicon oxide layer; 22: Doped polysilicon layer; 23: Second silicon oxide layer; 24: Doped silicide layer; 30: Antireflection film layer; 40: Electrode pattern. Detailed Embodiments

[0030] For ease of understanding the present application, the present application will be described more comprehensively below in conjunction with embodiments and drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used in the present application have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the related listed items.

[0032] In the traditional technology, the passivation contact structure in a solar cell usually includes a polysilicon layer to reduce the recombination of metal and non-metal regions. However, the polysilicon layer has serious parasitic absorption of light. If a thick polysilicon layer is grown on the entire surface of the silicon wafer, the light utilization rate of the cell will be significantly reduced. To overcome the above problems, some studies have replaced the polysilicon layer in the passivation contact structure with a silicide thin film. Although the silicide thin film can reduce the parasitic absorption of light compared with the polysilicon layer, the contact resistance between the silicide thin film and the electrode is higher than that of the polysilicon layer, resulting in relatively low fill factor and energy conversion efficiency of the solar cell.

[0033] As Figure 1 shown, to solve the above problems, the present application provides a solar cell 1, including a silicon wafer 10, a passivation contact structure 20 disposed on the back surface of the silicon wafer 10, and an electrode pattern 40;

[0034] The passivation contact structure 20 includes a first silicon oxide layer 21 and a doped polysilicon layer 22 that are disposed in a first region and stacked in sequence in a direction gradually away from the silicon wafer 10; a second silicon oxide layer 23 and a doped silicide layer 24 that are disposed in a second region and stacked in sequence in a direction gradually away from the silicon wafer 10;

[0035] wherein, the first region is the region where the electrode pattern 40 is located, the second region at least includes the remaining regions of the solar cell 1 except the region where the electrode pattern 40 is located, and the electrode pattern 40 forms an ohmic contact with the doped polysilicon layer 22.

[0036] The present application provides a solar cell 1, including a silicon wafer 10, a passivation contact structure 20 disposed on the back surface of the silicon wafer 10, and an electrode pattern 40. In the passivation contact structure 20, a doped polysilicon layer 22 is disposed in the region where the electrode pattern 40 is located. The doped polysilicon layer 22 is beneficial to reducing the recombination of metal and non-metal regions, reducing the contact resistance of the electrode, and improving the fill factor and energy conversion efficiency of the cell. Further, at least in the remaining regions except the region where the electrode pattern 40 is located, a doped silicide layer 24 is disposed. The doped silicide layer 24 is beneficial to reducing the parasitic absorption of light and increasing the back reflectivity, thereby being beneficial to further improving the photoelectric conversion efficiency of the cell.

[0037] For the solar cell 1 provided by the present application, a doped polysilicon layer 22 is disposed in the region where the electrode pattern 40 is located, so that there is a lower contact resistance between the electrode and the passivation contact structure 20, while in the remaining regions except the region where the electrode pattern 40 is located, a doped silicide layer 24 is disposed to replace the doped polysilicon layer 22, avoiding a thick doped polysilicon layer 22 on the entire back surface of the silicon wafer 10, which is beneficial to reducing the parasitic absorption of light and increasing the back reflectivity.

[0038] In some of these embodiments, the second region further includes: the region where the electrode pattern 40 is located;

[0039] The second silicon oxide layer 23 and the doped silicide layer 24 also extend to cover the side of the doped polysilicon layer 22 away from the silicon wafer 10.

[0040] On the side of the doped polysilicon layer 22 away from the silicon wafer 10 in the region where the electrode pattern 40 is located, the second silicon oxide layer 23 and the doped silicide layer 24 are also covered, but it does not affect the formation of an ohmic contact between the electrode pattern 40 and the doped polysilicon layer 22, and can further improve the back reflectivity of the battery.

[0041] In some of these embodiments, the thickness of the doped polysilicon layer 22 is greater than the thickness of the doped silicide layer 24. Using a doped polysilicon layer 22 with a higher thickness is beneficial to reducing the contact resistance and forming a good ohmic contact between the electrode pattern 40 and the doped polysilicon layer 22.

[0042] In some of these embodiments, the thickness of the doped polysilicon layer 22 is 30 nm to 200 nm. Within the above thickness range, the doped polysilicon layer 22 can play a good conductive role, which is beneficial to reducing the contact resistance of the electrode pattern 40, and the adverse effect of the parasitic absorption of light by the doped polysilicon layer 22 is controlled within an appropriate range. It can be understood that the thickness of the doped polysilicon layer 22 can be, for example, but not limited to, 30 nm, 60 nm, 80 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.

[0043] In some of these embodiments, the thickness of the doped silicide layer 24 is 10 nm to 80 nm. Within the above thickness range, the doped silicide layer 24 can effectively overcome the problem of light parasitic absorption of the doped polysilicon layer 22, thereby improving the back reflectivity and the utilization rate of light. At the same time, it also avoids the influence of the excessive thickness of the doped silicide layer 24 on the contact resistance with the electrode, which is beneficial to improving the fill factor and conversion efficiency of the battery. It can be understood that the thickness of the doped silicide layer 24 can be, for example, but not limited to, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc.

[0044] In some of these embodiments, the doping concentration of the doping element in the doped polysilicon layer 22 is 6E19 cm -3 ~7E20 cm -3 . Within the above doping concentration range of the doping element, it can ensure a lower contact resistance and form a good ohmic contact between the electrode and the doped polysilicon layer 22. It can be understood that the doping concentration of the doping element in the doped polysilicon layer 22 can be, for example, but not limited to, 6E19 cm -3 、7E19 cm -3 、8E19 cm-3 , 9E19 cm -3 , 1E20 cm -3 , 2E20 cm -3 , 3E20 cm -3 , 4E20 cm -3 , 5E20 cm -3 , 6E20 cm -3 , 7E20 cm -3 and so on.

[0045] Understandably, the doping element in the doped polysilicon layer 22 can be phosphorus doping or boron doping.

[0046] In some of the embodiments, the doping concentration of the doping element in the doped silicide layer 24 is 1E19 cm -3 ~7E20 cm -3 . The doping element within the above doping concentration range can have a better effect of reducing the recombination of metal and non-metal, and is also beneficial to improving the back reflectivity. Understandably, the doping concentration of the doping element in the doped silicide layer 24 can be, for example, but not limited to, 1E19 cm -3 , 2E19 cm -3 , 3E19 cm -3 , 4E19 cm -3 , 5E20 cm -3 , 6E19 cm -3 , 7E19 cm -3 , 8E19 cm -3 , 9E19 cm -3 , 1E20 cm -3 , 2E20 cm -3 , 3E20 cm -3 , 4E20 cm -3 , 5E20 cm -3 , 6E20 cm -3 , 7E20 cm -3 and so on.

[0047] Understandably, the doping element in the doped silicide layer 24 can be phosphorus doping or boron doping.

[0048] In some of the embodiments, the thickness of the first silicon oxide layer 21 < 3 nm. The first silicon oxide layer 21 is beneficial to promoting charge transfer and improving the battery efficiency. Understandably, the thickness of the first silicon oxide layer 21 can be, for example, but not limited to, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, and so on.

[0049] In some of these embodiments, the thickness of the second silicon oxide layer 23 is < 3 nm. The second silicon oxide layer 23 and the first silicon oxide layer 21 have similar functions, both being conducive to promoting charge transfer and improving the battery efficiency. Understandably, the thickness of the second silicon oxide layer 23 can be, for example, but not limited to, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, etc.

[0050] In some of these embodiments, the silicide in the doped silicide layer 24 includes one or more of silicon carbide, silicon oxide, and silicon nitride. Appropriate silicides can be selected according to actual needs.

[0051] In some of these embodiments, the solar cell 11 further includes an antireflection film layer 3030, and the antireflection film layer 3030 is disposed on the surface of the doped silicide layer 24 on the side away from the back surface of the silicon wafer 10. The antireflection film layer 30 is conducive to further reducing the back reflectance of light and improving light absorption and light utilization.

[0052] Furthermore, the antireflection film layer 30 can be, for example, a stack of alumina and silicon nitride, or can be only a silicon nitride stack.

[0053] In some of these embodiments, the material of the electrode pattern 40 can be, for example, but not limited to, silver, silver-aluminum, etc.

[0054] In a second aspect, the present application also provides a method for manufacturing a solar cell 1, including the following steps S100 and step S300.

[0055] Step S100: Form a passivated contact structure 20 on the back surface of the silicon wafer 10; the passivated contact structure 20 includes a first silicon oxide layer 21 and a doped polysilicon layer 22 that are disposed in a first region and stacked in sequence in a direction gradually away from the silicon wafer 10; a second silicon oxide layer 23 and a doped silicide layer 24 that are disposed in a second region and stacked in sequence in a direction gradually away from the silicon wafer 10; wherein, the first region is the region where the electrode pattern 40 is located, and the second region includes at least the remaining region of the solar cell 1 other than the region where the electrode pattern 40 is located.

[0056] Step S300: Form an electrode pattern 40 in the first region of the passivated contact structure 20, and the electrode pattern 40 forms an ohmic contact with the doped polysilicon layer 22.

[0057] In some of these embodiments, the second region includes the remaining region of the solar cell 1 other than the region where the electrode pattern 40 is located, and the preparation of the passivated contact structure 20 includes the following steps S110 to step S140.

[0058] Step S110: Form a first silicon oxide layer 21 on the back surface of the silicon wafer 10.

[0059] Furthermore, the thickness of the first silicon oxide layer 21 is < 3 nm.

[0060] Further, a first silicon oxide layer 21 is formed by a thermal oxidation method.

[0061] Step S120: A doped polysilicon layer 22 is formed on the surface of the first silicon oxide layer 21 on the side away from the silicon wafer 10.

[0062] Further, the thickness of the doped polysilicon layer 22 is 30 nm to 200 nm. It can be understood that the thickness of the doped polysilicon layer 22 can be, for example, but not limited to, 30 nm, 60 nm, 80 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, and so on.

[0063] Further, the doping concentration of the doping element in the doped polysilicon layer 22 is 6E19 cm -3 ~7E20 cm -3 . It can be understood that the doping concentration of the doping element in the doped polysilicon layer 22 can be, for example, but not limited to, 6E19 cm -3 、7E19 cm -3 、8E19 cm -3 、9E19 cm -3 、1E20 cm -3 、2E20 cm -3 、3E20 cm -3 、4E20 cm -3 、5E20 cm -3 、6E20 cm -3 、7E20 cm -3 and so on.

[0064] Further, the doped polysilicon layer 22 is formed by a low-pressure chemical vapor deposition method (LPCVD) or a plasma-enhanced chemical vapor deposition method (PECVD).

[0065] Step S130: Remove the first silicon oxide layer 21 and the doped polysilicon layer 22 in the remaining regions except for the region where the electrode pattern 40 is located.

[0066] Further, step 130 includes steps S131 to S132.

[0067] Step S131: After step S120, a mask is formed on the surface of the doped polysilicon layer 22 in the region where the electrode pattern 40 is located on the side away from the silicon wafer 10. Further, the mask can be, for example, but not limited to, a PSG film, a silicon oxide film, and so on.

[0068] Step S132: Remove the doped polysilicon layer 22 in the regions other than the region where the electrode pattern 40 is located by local etching. After the etching is completed, etch with HF solution to remove the mask on the region where the electrode pattern 40 is located, and retain the doped polysilicon layer 22 on the region where the electrode pattern 40 is located. During the process, the first silicon oxide layer 21 on the regions other than the region where the electrode pattern 40 is located will also be etched away. Therefore, a new layer of silicon oxide layer needs to be fabricated in this region subsequently.

[0069] Step S140: In the regions other than the region where the electrode pattern 40 is located, sequentially form a stacked second silicon oxide layer 23 and a doped silicide layer 24 in a direction gradually away from the silicon wafer 10.

[0070] Further, the thickness of the second silicon oxide layer 23 < 3 nm.

[0071] Further, the second silicon oxide layer 23 is formed by plasma enhanced chemical vapor deposition (PECVD).

[0072] Further, the thickness of the doped polysilicon layer 22 is greater than the thickness of the doped silicide layer 24.

[0073] Further, the thickness of the doped silicide layer 24 is 10 nm to 80 nm. It can be understood that the thickness of the doped silicide layer 24 can be, for example, but not limited to, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc.

[0074] Further, the doping concentration of the doping element in the doped silicide layer 24 is 1E19 cm -3 ~7E20 cm -3 . It can be understood that the doping concentration of the doping element in the doped silicide layer 24 can be, for example, but not limited to, 1E19 cm -3 、2E19 cm -3 、3E19 cm -3 、4E19 cm -3 、5E20 cm -3 、6E19 cm -3 、7E19 cm -3 、8E19 cm -3 、9E19 cm -3 、1E20 cm -3 、2E20 cm -3 、3E20 cm -3 、4E20 cm -3 、5E20 cm -3 、6E20 cm -3 、7E20 cm -3 and so on.

[0075] Further, the silicide in the doped silicide layer 24 includes one or more of silicon carbide, silicon oxide, and silicon nitride.

[0076] Further, the doped silicide layer 24 is formed by plasma enhanced chemical vapor deposition (PECVD).

[0077] Further, the silicide includes silicon carbide, the doped silicide layer 24 is n-type doped, and the reaction gases include silane, phosphine, hydrogen, and methane.

[0078] Further, the silicide includes silicon carbide, the doped silicide layer 24 is p-type doped, and the reaction gases include silane, borane, hydrogen, and methane.

[0079] Further, the silicide includes silicon oxide, the doped silicide layer 24 is n-type doped, and the reaction gases include silane, phosphine, and hydrogen, and also include carbon dioxide or nitrous oxide.

[0080] Further, the silicide includes silicon oxide, the doped silicide layer 24 is p-type doped, and the reaction gases include silane, borane, and hydrogen, and also include carbon dioxide or nitrous oxide.

[0081] Further, the silicide includes silicon nitride, the doped silicide layer 24 is n-type doped, and the reaction gases include silane, phosphine, hydrogen, and ammonia.

[0082] Further, the silicide includes silicon nitride, the doped silicide layer 24 is p-type doped, and the reaction gases include silane, borane, hydrogen, and ammonia.

[0083] In some embodiments, the second region further includes the region where the electrode pattern 40 is located, and the preparation step S140 of the passivation contact structure 20 further includes the following step S141.

[0084] Step S141: While sequentially forming the stacked second silicon oxide layer 23 and doped silicide layer 24 in the remaining regions except the region where the electrode pattern 40 is located, the second silicon oxide layer 23 and doped silicide layer 24 are also formed on the side of the doped polysilicon layer 22 away from the silicon wafer 10, so that the second silicon oxide layer 23 and doped silicide layer 24 extend to cover the region where the electrode pattern 40 is located.

[0085] In some embodiments, the manufacturing method of the solar cell 1 further includes step S200.

[0086] Step S200: Form an antireflection film layer 30 on the surface of the doped silicide layer 24 on the side away from the back surface of the silicon wafer 10.

[0087] Further, the antireflection film layer 30 can be, for example, a stack of alumina and silicon nitride, or can be only a silicon nitride stack.

[0088] Further, an antireflection film layer 30 is formed by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0089] In some embodiments, the steps of step S300 include step S310.

[0090] Step S310: Print electrode paste in the corresponding area of the electrode pattern 40 on the surface of the antireflection film layer 30 away from the back surface of the silicon wafer 10. After sintering, the electrode paste burns through the antireflection film layer 30, the doped silicide layer 24, and the second silicon oxide layer 23 to form an electrode pattern 40 in ohmic contact with the doped polysilicon layer 22.

[0091] Further, screen printing technology is used to print the electrode paste.

[0092] Further, the electrode paste can be, for example, but not limited to, silver, silver-aluminum, etc.

[0093] The solar cell 1 provided by the preparation method of the present application uses a doped polysilicon layer 22 in the area where the electrode pattern 40 is located, which is beneficial to reducing the contact resistance. And at least in the remaining areas except the area where the electrode pattern 40 is located, a doped silicide layer 24 is provided, which can reduce the parasitic absorption of light and improve the back reflectivity. The combination of the two can improve the fill factor and photoelectric conversion efficiency of the battery. Further, the solar cell 1 provided by the present application can improve the conversion efficiency by 0.2%.

[0094] The following are specific embodiments.

[0095] Embodiment 1

[0096] A preparation method of a solar cell 1 includes the following steps:

[0097] (1) Clean the n-type silicon wafer 10.

[0098] (2) Prepare a first silicon oxide layer 21 on the back surface of the silicon wafer 10 by thermal oxidation. The thickness of the first silicon oxide layer 21 is 1.5 nm.

[0099] (3) Prepare a doped polysilicon layer 22 on the surface of the first silicon oxide layer 21 away from the silicon wafer 10 by plasma enhanced chemical vapor deposition (PECVD). The doping element of the doped polysilicon layer 22 is phosphorus doping, and the thickness is 150 nm.

[0100] (4) Form a layer of PSG film as a mask on the surface of the doped polysilicon layer 22 away from the silicon wafer 10 in the area where the electrode pattern 40 is located.

[0101] (5) Remove the doped polysilicon layer 22 in the regions other than the region where the electrode pattern 40 is located by local etching. After the etching is completed, etch with HF solution to remove the mask located on the region where the electrode pattern 40 is located, and retain the doped polysilicon layer 22 on the region where the electrode pattern 40 is located. During the process, the first silicon oxide layer 21 in the regions other than the region where the electrode pattern 40 is located will also be etched away.

[0102] (6) Use plasma enhanced chemical vapor deposition (PECVD) with nitrous oxide as the reaction gas to prepare a second silicon oxide layer 23 with a thickness of 1.5 nm on the surfaces of the regions other than the region where the electrode pattern 40 is located and on the surface of the doped polysilicon layer 22 in the region where the electrode pattern 40 is located and away from the side of the silicon wafer 10.

[0103] (7) Use plasma enhanced chemical vapor deposition (PECVD) with silane, borane, hydrogen, and methane as the reaction gases to deposit a doped silicide layer 24 on the surface of the second silicon oxide layer 23 away from the side of the silicon wafer 10. The silicide is silicon carbide, and the doping element is phosphorus doping. The thickness of the formed doped silicide layer 24 is 20 nm.

[0104] (8) Use plasma enhanced chemical vapor deposition (PECVD) to deposit a silicon nitride stack on the surface of the doped silicide layer 24 away from the back side of the silicon wafer 10 to form an antireflection film layer 30 with a thickness of 80 nm.

[0105] (10) Print silver paste by screen printing on the region where the electrode pattern 40 is located on the surface of the antireflection film layer away from the back side of the silicon wafer 10. After sintering, the silver paste burns through the antireflection film layer 30, the doped silicide layer 24, and the second silicon oxide layer 23 to form the electrode pattern 40 in ohmic contact with the doped polysilicon layer 22.

[0106] Comparative Example 1

[0107] A method for manufacturing a solar cell, comprising the following steps:

[0108] (1) Clean the n-type silicon wafer.

[0109] (2) Prepare a first silicon oxide layer on the back side of the silicon wafer by thermal oxidation, and the thickness of the first silicon oxide layer is 1.5 nm.

[0110] (3) Use plasma enhanced chemical vapor deposition (PECVD) to prepare a doped polysilicon layer on the surface of the first silicon oxide layer away from the silicon wafer. The doping element of the doped polysilicon layer is phosphorus doping, and the thickness is 150 nm.

[0111] (4) A silicon nitride stack is deposited on the surface of the doped polysilicon layer away from the back side of the silicon wafer by plasma enhanced chemical vapor deposition (PECVD) to form an antireflection film layer with a thickness of 80 nm.

[0112] (5) Silver paste is printed in the area of the electrode pattern on the surface of the antireflection film layer away from the back side of the silicon wafer by screen printing. After sintering, the silver paste burns through the antireflection film layer to form an electrode pattern in ohmic contact with the doped polysilicon layer.

[0113] Comparative Example 2

[0114] A method for preparing a solar cell includes the following steps:

[0115] (1) Clean the n-type silicon wafer.

[0116] (2) Prepare a first silicon oxide layer on the back side of the silicon wafer by thermal oxidation with a thickness of 1.5 nm.

[0117] (3) Using plasma enhanced chemical vapor deposition (PECVD) with silane, borane, hydrogen, and methane as reaction gases, deposit a doped silicide layer on the surface of the first silicon oxide layer away from the silicon wafer. The silicide is silicon carbide, and the doping element is phosphorus doping. The formed doped silicide layer has a thickness of 150 nm.

[0118] (4) A silicon nitride stack is deposited on the surface of the doped silicide layer away from the back side of the silicon wafer by plasma enhanced chemical vapor deposition (PECVD) to form an antireflection film layer with a thickness of 80 nm.

[0119] (5) Silver paste is printed in the area of the electrode pattern on the surface of the antireflection film layer away from the back side of the silicon wafer by screen printing. After sintering, the silver paste burns through the antireflection film layer and directly contacts the doped silicide layer.

[0120] Perform electrical performance tests on the solar cells prepared in Example 1 and Comparative Examples 1 - 2. The test results are shown in the following table.

[0121] Table 1 Performance test results of solar cells

[0122]

[0123] As can be seen from Table 1, compared with Comparative Examples 1 and 2, the solar cell of Example 1 has higher open circuit voltage (Voc), short circuit current (Isc), fill factor (FF), and conversion efficiency (Eta).

[0124] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope described in this specification.

[0125] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A solar cell, characterized in that, It includes a silicon wafer, a passivation contact structure disposed on the back surface of the silicon wafer, and an electrode pattern; The passivation contact structure includes a first silicon oxide layer and a doped polysilicon layer that are disposed in a first region and stacked in sequence in a direction gradually away from the silicon wafer; a second silicon oxide layer and a doped silicide layer that are disposed in a second region and stacked in sequence in a direction gradually away from the silicon wafer; Wherein, the region where the electrode pattern is located is on the first region, the second region is the remaining region of the solar cell except the region where the electrode pattern is located, the electrode pattern forms an ohmic contact with the doped polysilicon layer, and the second silicon oxide layer and the doped silicide layer also extend to cover the side of the doped polysilicon layer away from the silicon wafer.

2. The solar cell according to claim 1, characterized in that, The thickness of the doped polysilicon layer is greater than the thickness of the doped silicide layer.

3. The solar cell according to claim 2, characterized in that, The thickness of the doped polysilicon layer is 30 nm to 200 nm.

4. The solar cell according to claim 2, characterized in that, The thickness of the doped silicide layer is 10 nm to 80 nm.

5. The solar cell according to any one of claims 1, 3 to 4, characterized in that The doping concentration of the doping element in the doped polysilicon layer is 6E19 cm -3 ~7E20 cm -3 .

6. The solar cell according to any one of claims 1, 3 to 4, characterized in that, The doping concentration of the doping element in the doped silicide layer is 1E19 cm -3 ~7E20 cm -3 .

7. The solar cell according to any one of claims 1, 3 to 4, characterized in that The thickness of the first silicon oxide layer < 3 nm.

8. The solar cell according to any one of claims 1, 3 to 4, characterized in that, The thickness of the second silicon oxide layer < 3 nm.

9. The solar cell according to any one of claims 1, 3 to 4, characterized in that The silicide in the doped silicide layer includes one or more of silicon carbide, silicon oxide, and silicon nitride.

10. A method for preparing a solar cell, characterized in that, It includes the following steps: Form a passivation contact structure on the back surface of the silicon wafer; the passivation contact structure includes a first silicon oxide layer and a doped polysilicon layer that are disposed in a first region and stacked in sequence in a direction gradually away from the silicon wafer; a second silicon oxide layer and a doped silicide layer that are disposed in a second region and stacked in sequence in a direction gradually away from the silicon wafer; wherein, the region where the electrode pattern is located is on the first region, and the second region is the remaining region of the solar cell except the region where the electrode pattern is located; Form the electrode pattern in the first region of the passivation contact structure, the electrode pattern forms an ohmic contact with the doped polysilicon layer, and the second silicon oxide layer and the doped silicide layer also extend to cover the side of the doped polysilicon layer away from the silicon wafer.

11. The method for preparing a solar cell according to claim 10, wherein The second region is the remaining region of the solar cell except the region where the electrode pattern is located, and the preparation of the passivation contact structure includes the following steps: Form the first silicon oxide layer on the back surface of the silicon wafer; Form the doped polysilicon layer on the surface of the first silicon oxide layer away from the silicon wafer; Remove the first silicon oxide layer and the doped polysilicon layer in the regions other than the first region; In the regions other than the region where the electrode pattern is located, form the second silicon oxide layer and the doped silicide layer stacked in sequence in a direction gradually away from the silicon wafer, and the second silicon oxide layer and the doped silicide layer also extend to cover the side of the doped polysilicon layer away from the silicon wafer.

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