Power management based on limiting hardware enforced power control

Abstract

Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. In particular, a power manager circuit in an integrated circuit (e.g., a system on a chip) can modify power budgets of various components in the integrated circuit to reduce the amount of power control caused by external signaling indicating voltage regulator overload (e.g., voltage droop).

Description

BACKGROUND TECHNICAL FIELD

[0001] Embodiments described herein relate to power management in integrated circuits, and more specifically, to a trigger circuit for controlling power delivery to an integrated circuit. BRIEF DESCRIPTION OF DRAWINGS

[0002] The features and advantages of the methods and apparatuses of the embodiments described in this disclosure will be more fully understood with reference to the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0003] Figure 1 is a block diagram of one embodiment of a system including a system on a chip (SOC) coupled to a memory and a power management unit (PMU).

[0004] Figure 2 is a block diagram of one embodiment of a PMU.

[0005] Figure 3 is a block diagram of another embodiment of a PMU.

[0006] Figure 4 is a block diagram of one embodiment of a global power control circuit.

[0007] Figure 5 is a block diagram of one embodiment of a memory controller pipeline.

[0008] Figure 6 is a block diagram of one embodiment of a rate limiter subcomponent.

[0009] Figure 7 is a block diagram of another embodiment of a system on a chip (SOC).

[0010] Figure 8 is a block diagram of one embodiment of a power management mechanism.

[0011] Figure 9 is a timing diagram illustrating a power control window.

[0012] Figure 10 is a flow diagram illustrating one embodiment of operating a power management processor.

[0013] Figure 11 is a flow diagram illustrating a method for reducing power in an integrated circuit, in accordance with some embodiments.

[0014] Figure 12is a flow chart illustrating another method for reducing power in an integrated circuit according to some embodiments.

[0015] Figure 13 is a block diagram of one embodiment of a power transmission system.

[0016] Figure 14 is a block diagram illustrating one embodiment including a computer system, a computer readable medium, and a fabrication system.

[0017] Figure 15 is a block diagram of one embodiment of an example system.

[0018] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments described. However, one skilled in the art will recognize that aspects of the disclosed embodiments can be practiced without these specific details. In some cases, well-known circuits, structures, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the disclosed embodiments. DETAILED DESCRIPTION

[0019] Figure 1 1 is a block diagram of one embodiment of a system including a system on a chip (SOC) 110 coupled to a memory 120 and a power management unit (PMU) 140. The PMU 140 may be configured to provide power to the SOC 110 and other components that may be included in the system, such as the memory 120. For example, the PMU 140 may be configured to generate one or more supply voltages to power the SOC 110 and may be further configured to generate power for other components of the system ( Figure 1 140). In addition, the PMU 140 (or accompanying circuitry coupled to the PMU 140) may be configured to monitor the supply voltage and detect transient undervoltage conditions, overcurrent conditions, power limit conditions, temperature conditions, or other conditions that may cause erroneous operation in the SOC 110. When such a condition occurs (e.g., the electrical load of the SOC 110 exceeds the capacity of the PMU 140), the PMU 140 may assert a trigger output signal to the SOC 110. As an example, for a power limit condition, power may be averaged over different time constants, where the power limits for the different time constants are different (e.g., a short averaging time constant may have a higher limit than a longer averaging time constant), and a trigger may be asserted based on exceeding any of the power limits for the different time constants. In some embodiments, the current squared (I 2 )RMS constraint to apply power limits.

[0020] In various embodiments, the trigger output signal can be communicated to the SOC 110 via a wired transmission (e.g., a hardwired interface between two components) or a serial communication interface (e.g., a bidirectional communication interface). The wired trigger signal transmission can be provided to a global power control circuit 130 included in the SOC 110, which can receive the trigger input, while the serial trigger signal transmission can be provided directly to a processor engine (e.g., a processor cluster 150, a GPU 160, or a peripheral device 180) via a serial controller 124 and / or a communication fabric 170. The serial controller 124 can be a system power management interface (SPMI) that provides bidirectional communication between the processor engine and the PMU 140. While the serial controller 124 is shown in communication with the processor engine through the communication fabric 170 in Figure 1 , in various embodiments, the serial controller 124 can be in direct communication with one or more of the processor engines. Wired and serial trigger signal transmissions are discussed in more detail below with respect to the embodiment of the PMU 140 depicted in Figure 2 . While SOC embodiments are used as examples herein, in other embodiments, a system including multiple integrated circuits coupled to a communication fabric can be used.

[0021] As the name implies, the components of the SOC 110 can be integrated onto a single semiconductor substrate as an integrated circuit “chip.” In the illustrated embodiment, the components of the SOC 110 include at least one processor cluster 150, at least one graphics processing unit (GPU) 160, one or more peripheral components (e.g., peripheral component 180 (more briefly, “peripheral device”)), at least one memory controller 122, a global power control circuit 130, and a communication fabric 170. The components 150, 160, 180, 122, and 130 can all be coupled to the communication fabric 170. The memory controller 122 can be coupled to a memory 120 during use. In some embodiments, there can be more than one memory controller coupled to a corresponding memory. In such embodiments, the memory address space can be mapped across the memory controllers in any desired manner. In the illustrated embodiment, the processor cluster 150 can include a plurality of processors (P) 152. The processors 152 can form a central processing unit (CPU) of the SOC 110. The processor cluster 150 can further include one or more co-processors (e.g., co-processor 154 in Figure 1 ). The co-processors can be optimized for a subset of the processor instruction set and can be used by the processors 152 to execute instructions in the subset. For example, the co-processor 154 can be a matrix engine optimized to perform vector and matrix operations.

[0022] As described above, the cluster of processors 150 can include one or more processors 152 that can serve as CPUs of the SOC 110. The CPUs of a system include one or more processors that execute the primary control software of the system, such as an operating system. Generally, the software executed by the CPUs in use can control other components of the system to implement the desired functionality of the system. The processors can also execute other software, such as application programs. Application programs can provide user functionality and can rely on the operating system for lower-level device control, scheduling, memory management, etc. Thus, the processors can also be referred to as application processors.

[0023] Generally, a processor can include any circuitry and / or microcode configured to perform instructions defined in an instruction set architecture implemented by the processor. The processor can encompass a processor core implemented on an integrated circuit with other components as a system on a chip (SOC 110) or other level of integration. The processor can also include a discrete microprocessor, processor core, and / or microprocessor integrated into a multi-chip module implementation, a processor implemented as multiple integrated circuits, etc.

[0024] The memory controller 122 can generally include circuitry to receive memory operations from other components of the SOC 110 and to access the memory 120 to complete the memory operations. The memory controller 122 can be configured to access any type of memory 120. For example, the memory 120 can be static random access memory (SRAM), dynamic RAM (DRAM) such as synchronous DRAM (SDRAM) including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low power / mobile versions of DDR DRAM can be supported (e.g., LPDDR, mDDR, etc.). The memory controller 122 can include a queue of memory operations for ordering (and potentially reordering) and presenting the operations to the memory 120. The memory controller 122 can also include data buffers for storing write data waiting to be written to the memory and read data waiting to be returned to the source of the memory operation. In some embodiments, the memory controller 122 can include a memory cache for storing recently accessed memory data. For example, in a SOC implementation, a memory cache can reduce power consumption in the SOC by avoiding re-accessing data from the memory 120 in situations where it is expected to be accessed again soon. In some cases, a memory cache can also be referred to as a system cache, which is distinct from a private cache such as an L2 cache or cache in a processor that only serves certain components. In addition, in some embodiments, a system cache need not be located within the memory controller 122.

[0025] The peripherals 180 can be any collection of additional hardware functionality included in the SOC 110. For example, the peripherals 180 can include video peripherals such as image signal processors configured to process image capture data from a camera or other image sensor, video encoders / decoders, extenders, rotators, mixers, display controllers, etc. The peripherals can include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. The peripherals can include interface controllers for various interfaces external to the SOC 110, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) including PCI Express (PCIe), serial and parallel ports, etc. The interconnections to external devices are shown by dashed arrows extending outside of the SOC 110. The peripherals can include networking peripherals such as a Media Access Controller (MAC). Any set of hardware can be included. Figure 1 The communication fabric 170 can be any communication interconnect and protocol used for communication between the components of the SOC 110. The communication fabric 170 can be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses with bridges. The communication fabric 170 can also be packet-based, and can be hierarchical with bridges, crossbar, point-to-point, or other interconnects.

[0026] The communication fabric 170 can be any communication interconnect and protocol used for communication between the components of the SOC 110. The communication fabric 170 can be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses with bridges. The communication fabric 170 can also be packet-based, and can be hierarchical with bridges, crossbar, point-to-point, or other interconnects.

[0027] It is noted that the number of components of the SOC 110 (as well as the number of subcomponents of those components shown in Figure 1 such as the processors 152 in each processor cluster 150) can vary from implementation to implementation. In addition to this, when multiple processor clusters are included, the number of processors 152 in one processor cluster 150 can be different than the number of processors 152 in another processor cluster 150. The number of each component / subcomponent can be more or less than the number shown. Figure 1

[0028] As described herein, the PMU 140 can be configured to assert one or more trigger signals upon detection of various conditions that can lead to erroneous operation in the SOC 110. Figure 2 is a block diagram of one embodiment of the PMU 140. In the illustrated embodiment, the PMU 140 includes a voltage regulator 142 and a power delivery trigger circuit 144. In certain embodiments, the power delivery trigger circuit 144 is configured to monitor a supply voltage in the voltage regulator 142 and provide a trigger signal when a transient undervoltage condition is detected in the voltage regulator. For example, the power delivery trigger circuit 144 can provide a trigger signal when the supply voltage provided by the voltage regulator 142 drops below a threshold (e.g., an undervoltage threshold). ​

[0029] Figure 3 FIG. 1 is a block diagram of another embodiment of a PMU 140. In the embodiment shown, the PMU 140 includes a voltage regulator 142, a wired power transfer trigger circuit 144, and a serial power transfer trigger circuit 146. Figure 3 As shown, the PMU 140 may include a plurality of voltage regulators 142 (e.g., voltage regulators 142A, 142B, 142C) connected to a plurality of sets of power transfer trigger circuits (e.g., wired power transfer trigger circuits 144A, 144B, 144C and serial power transfer trigger circuits 146A, 146B, 146C). Any number of voltage regulators 142, wired power transfer trigger circuits 144, and serial power transfer trigger circuits 146 are contemplated in the PMU 140. The voltage regulators 142A, 142B, 142C may represent different voltage regulators that provide different supply voltages to different portions of the SOC 110. For example, the voltage regulator 142A may provide a supply voltage to the processor cluster 150, while the voltage regulator 142B provides a supply voltage to the GPU 160. In various embodiments, the voltage regulators 142A, 142B, 142C may be a hierarchical power delivery system (e.g., Figure 9 Part of the hierarchical power transmission system 900 described in.

[0030] As described above, the wired power transfer trigger circuit 144 can be wired directly to the SOC 110 (e.g., the global power control circuit 130 in the SOC 110), while the serial power transfer trigger circuit 146 can be coupled to the SOC 110 (e.g., the communication structure 170 in the SOC 110) via a serial communication interface (e.g., SPMI). In various embodiments, the serial power transfer trigger circuit 146 includes an SPMI for communicating with the SOC 110 (e.g., via the serial controller 124). Thus, the serial power transfer trigger circuit 146 is capable of bidirectional communication with the SOC 110, while the wired power transfer trigger circuit 144 provides unidirectional communication from the wired power transfer trigger circuit 144 to the SOC 110.

[0031] In certain embodiments, the wired power transfer trigger circuit 144 and the serial power transfer trigger circuit 146 are configured to monitor one or more conditions in the voltage regulator 142 (e.g., voltage, current, or temperature) and provide a trigger signal when the condition exceeds various thresholds determined by the power transfer trigger circuit. Various embodiments of fast (nanosecond level) and slow (microsecond or millisecond level) responses can be implemented in the wired power transfer trigger circuit 144 or the serial power transfer trigger circuit 146. In certain embodiments, fast responses are implemented in the wired power transfer trigger circuit 144 to take advantage of the high transfer speed of the wired connection. Conversely, slow responses can be implemented in the serial power transfer trigger circuit 146 because the serial connection provides a signal transfer speed at the level of slow responses.

[0032] In various embodiments, the serial connection between the serial power transfer trigger circuit 146 and the SOC 110 allows for the conditions to be queried by the SOC 110. For example, the SOC 110 can provide a request for condition information when an operation of the SOC 110 changes or another event has occurred. The SOC 110 can provide the request query to the serial power transfer trigger circuit 146 through the serial communication interface. The serial power transfer trigger circuit 146 can then provide the condition state (e.g., a condition value above or below a threshold) via a trigger signal output back to the SOC 110 through the serial communication interface.

[0033] In some embodiments, a trigger signal is provided when an electrical load experienced in the voltage regulator 142 exceeds a threshold (e.g., a voltage drops below an under-voltage threshold). For example, a voltage threshold comparison can be implemented using a voltage sensing element such as a voltage-based comparator circuit. The voltage-based comparator circuit can be a fast response circuit typically used in the wired power transfer trigger circuit 144. In some embodiments, a trigger signal is provided when a current experienced in the voltage regulator 142 exceeds a current threshold (e.g., when the current exceeds a predetermined current limit). The current threshold comparison can be implemented by an output current comparator circuit (e.g., a current sensing element), which can be a fast response circuit used in the wired power transfer trigger circuit 144. In some contemplated embodiments, a current sensing capability is implemented to monitor a current condition (e.g., to determine whether the current exceeds an over-current threshold). For example, the current sensing capability can include a filtered current sensing capability, which can be implemented in the slow response serial power transfer trigger circuit 146. In some embodiments, a trigger signal is provided when a temperature experienced in the voltage regulator 142 exceeds a predetermined temperature in order to prevent overheating in the PMU 140. Temperature sensing is typically a slow response of the serial power transfer trigger circuit 146, which can be implemented in a temperature sensing scheme.

[0034] The above description provides example implementations of various response schemes under different conditions described herein. However, it should be appreciated that the location and number of response schemes can vary between voltage regulator 142, wired power delivery trigger circuit 144, and serial power delivery trigger circuit 146 for desired operation of PMU 140 and SOC 110. For example, in various implementations, both wired power delivery trigger circuit 144 and serial power delivery trigger circuit 146 can be implemented to monitor similar operating conditions (e.g., voltage or current) in the same voltage regulator 142. In such implementations, wired power delivery trigger circuit 144 provides a fast response time, while serial power delivery trigger circuit 146 provides a slower response.

[0035] In certain implementations, wired power delivery trigger circuit 144 and serial power delivery trigger circuit 146 can provide different power management capabilities based on different response times and locations of sending trigger signals in SOC 110. As an example, as shown in FIGS. 1A and IB, wired power delivery trigger circuit 144 provides a wired trigger signal to global power control circuit 130, while serial power delivery trigger circuit 146 provides a serial trigger signal to communication fabric 170, which then provides the serial trigger signal to components such as processor cluster 150 or GPU 160. As described herein, global power control circuit 130 can provide fast response and fast clock rate control in order to prevent functional failure in SOC 110 or PMU 140. However, the serial trigger signal provided by serial power delivery trigger circuit 146 can be implemented by components in SOC 110 (e.g., processor cluster 150 or GPU 160) to determine more precise control of operation of SOC 110 (e.g., by using dynamic voltage and frequency control in components of SOC 110). Figure 1 Figure 3 As shown, wired power delivery trigger circuit 144 provides a wired trigger signal to global power control circuit 130, while serial power delivery trigger circuit 146 provides a serial trigger signal to communication fabric 170, which then provides the serial trigger signal to components such as processor cluster 150 or GPU 160. As described herein, global power control circuit 130 can provide fast response and fast clock rate control in order to prevent functional failure in SOC 110 or PMU 140. However, the serial trigger signal provided by serial power delivery trigger circuit 146 can be implemented by components in SOC 110 (e.g., processor cluster 150 or GPU 160) to determine more precise control of operation of SOC 110 (e.g., by using dynamic voltage and frequency control in components of SOC 110).

[0036] ​Accordingly, in certain embodiments, the threshold of the wired power delivery trigger circuit 144 is closer to the functional failure point of the SOC 110 or PMU 140 than the threshold of the serial power delivery trigger circuit 146. The threshold of the wired power delivery trigger circuit 144 can be closer to the functional failure point of the SOC 110 or PMU 140 in order to provide a fast response when operating conditions can lead to a functional failure of the SOC 110 or PMU 140. Conversely, a slower response can be more appropriate when the SOC 110 or PMU 140 is further from the functional failure point. As an example, the voltage threshold of the wired power delivery trigger circuit 144 can be closer to an under-voltage that leads to a functional failure in the SOC 110 or PMU 140 than the voltage threshold of the serial power delivery trigger circuit 146 (e.g., the wired voltage threshold is lower than the serial voltage threshold). Thus, if the voltage starts to drop slowly, the serial voltage threshold can be exceeded first before the wired voltage threshold is reached, and the SOC 110 can respond to the serial trigger signal from the serial power delivery trigger circuit 146. However, if the voltage drops quickly, the fast response provided by the wired power delivery trigger circuit 144 and global power control circuit 130 can occur before the SOC 110 has a chance to respond to the serial trigger signal, even if the wired voltage threshold is reached after the serial voltage threshold. The response to the wired signal can preserve functionality until the later serial trigger signal read is performed and the SOC 110 reacts to it. This tiered response scheme can provide improved performance of the SOC 110 and PMU 140 while preventing functional failure in the device.

[0037] In some embodiments, the response scheme is tiered based on a hierarchy in the power delivery system (e.g., a hierarchy between voltage regulators 142A, 142B, 142C). For example, voltage regulator 142A can have a higher hierarchy than voltage regulator 142B. Thus, a trigger signal from wired power delivery trigger circuit 144A or serial power delivery trigger circuit 146A can have a higher hierarchy (e.g., a higher priority) in determining a power reduction than wired power delivery trigger circuit 144B or serial power delivery trigger circuit 146B. In addition to this, in a tiered power delivery system, a power reduction response (e.g., a power reduction of a component or power supply) can be triggered in one component by a trigger signal for another component. For example, a trigger signal from wired power delivery trigger circuit 144B or serial power delivery trigger circuit 146B can trigger a power reduction in voltage regulator 142A.

[0038] In various embodiments, one or more of the voltage regulators 142 are coupled to a battery (or other power supply unit) to supply power to the SOC 110. In some embodiments, one or more of the wired power transfer trigger circuit 144 or the serial power transfer trigger circuit 146 are configured to monitor the voltage in the battery. Direct monitoring of the voltage in the battery can help prevent a power down in the SOC 110 due to a low battery charge state.

[0039] Returning to Figure 1 In various embodiments, the global power control circuit 130 receives one or more trigger signals from the PMU 140. When an event associated with the trigger signal is occurring, the global power control circuit 130 can respond by quickly reducing the clock frequency at which components operate to prevent a functional failure in the SOC 110 or the PMU 140. In accordance with the present disclosure, an integrated circuit (e.g., the SOC 110) can include a plurality of components (e.g., the processor cluster 150, the GPU 160, the peripherals 180) and a global power control circuit 130 coupled to the plurality of components (via the communication fabric 170).

[0040] Figure 4 is a block diagram of one embodiment of the global power control circuit 130. In the illustrated embodiment, the global power control circuit 130 includes a trigger logic circuit 132 and a rate control circuit 134. The global power control circuit 130 receives one or more trigger signals from the PMU 140. In certain embodiments, the trigger signal is an asynchronous trigger signal with respect to the clock cycle of the SOC 110. For example, the trigger signal can be received by the global power control circuit 130 at any time during the clock cycle of the SOC 110.

[0041] In various embodiments, the trigger logic circuit 132 receives the trigger signal from the PMU 140 and determines a power down signal based on the received trigger signal. For example, the power down signal can be a synchronous signal provided to one or more components in the SOC 110 at the clock rate of the SOC 110. The one or more components can then implement a power down or a metric based on the received power down signal. In various embodiments, the trigger logic circuit 132 includes a combination of enables, hysteresis, and synchronizers to convert the asynchronous trigger signal to a synchronous power down signal.

[0042] Examples of techniques implemented by the trigger logic circuit 132 to provide the power reduction signal include clock dithering, clock gating, selective pulse removal, clock division, etc. These techniques can be effective for continuously operating the SOC 110 without errors, as the reduction in clock frequency offsets the impact of slower evaluation of transistors at reduced voltages. For example, dividing the clock frequency by 2 (for relatively fast operations) reduces performance by about ½. In certain cases, to ensure error-free operation, the performance reduction can be even greater, e.g., 75% or greater. Thus, the global power control circuit 130 can be coupled to various components of the SOC 110 (e.g., the processor 152 or the GPU 160) or can be coupled to at least clock resources (e.g., phase-locked loops (PLLs), delay-locked loops (DLLs), clock dividers, clock gates, clock trees, etc.) of the various components, to implement a frequency reduction that can help ensure error-free operation (or correct operation) during brown-out operation.

[0043] While the trigger logic circuit 132 provides a relatively fast power reduction response to the trigger signal from the PMU 140, faster response times for reducing clock frequency can be needed in various implementations of the SOC 110. For example, in implementations where the SOC 110 is a multi-die SOC (e.g., the SOC 110 has multiple chips that operate as a single chip), faster response times that can reduce clock frequency can be needed to prevent functional failure, as a large number of parallel transactions can overwhelm the PMU 140.

[0044] In various implementations, the rate control circuit 134 in the global power control circuit 130 implements faster response times to trigger signals received by the global power control circuit. For example, the rate control circuit 134 can include structures or other logic to control clock rates in the SOC 110 based on received trigger signals. For example, the rate control circuit 134 can quickly reduce the frequency of clocks in the communication fabric 170 in response to receiving a trigger signal. As Figure 4 As shown, the rate control circuit 134 can receive selected trigger signals from the PMU 140. In certain implementations, the selected power transfer trigger circuit 144 (as Figure 2 and Figure 3144 and the rate control circuit 170. For example, the wiring for the rate control circuit 134 may branch off from the wiring between the selected power transfer trigger circuit 144 and the trigger logic circuit 132. Thus, the rate control circuit 134 may receive the selected trigger signal asynchronously from the selected power transfer circuit 144. In one contemplated embodiment, the selected trigger signal is received from one or more voltage regulators 142 in the PMU 140 that provide power to the communications fabric 170.

[0045] In certain embodiments, rate control circuitry 134 controls the clock rate of SOC 110 or one or more components of SOC 110 based on receiving a selected trigger signal. For example, rate control circuitry 134 can reduce the clock rate based on receiving the selected trigger signal. Because the selected trigger signal is received asynchronously (from the SOC 110 clock cycle), rate control circuitry 134 can reduce the clock rate asynchronously and does not wait for another clock cycle before reducing power in SOC 110. Reducing the clock rate can reduce power consumption in SOC 110, thereby preventing functional failures in PMU 140 or SOC 110. Rate control circuitry 134 provides a fast asynchronous response time to reduce the clock rate upon receiving a trigger signal (e.g., within a few nanoseconds). The response time provided by rate control circuitry 134 is several orders of magnitude faster than the response time of power control using dynamic voltage and frequency control in components of SOC 110 (e.g., the time window in which rate control circuitry 134 responds is several orders of magnitude smaller than the time window in which components of SOC 110 respond). This fast response time improves protection against functional faults in power management of multi-die SOC systems.

[0046] In some embodiments, as Figure 4 As shown, rate control circuitry 134 receives a power reduction signal from trigger logic 132. For example, in one contemplated embodiment, rate control circuitry 134 may receive a power reduction signal for a CPU (processor 152) in SOC 110. As described above, the power reduction signal is synchronized with the clock cycle of SOC 110. Accordingly, rate control circuitry 134 may implement a slower but synchronized clock rate reduction based on the power reduction signal. However, providing both the selected trigger signal and the power reduction signal to rate control circuitry 134 may provide a redundant power reduction response in SOC 110 to prevent functional failures in PMU 140 or SOC 110.

[0047] In some embodiments, as Figure 4As shown, the trigger logic 132 can receive a power reduction signal from another SOC 110' (e.g., another chip or die) managed by the PMU 140. The trigger logic 132 can implement the power reduction signal from the SOC 110' to provide the power reduction signal to components in the SOC 110. In some embodiments, the trigger logic 132 can provide the power reduction signal to another SOC 110" managed by the PMU 140. The other SOC 110" can then implement a power reduction scheme (e.g., using trigger logic circuitry in the SOC 110") to reduce power in accordance with the received power reduction signal. The specific implementation of providing / receiving power reduction signals from other SOCs allows the trigger logic 132 and the SOC 110 to be part of a multi-die (e.g., multi-chip) power reduction scheme.

[0048] Returning to Figure 1 In various embodiments, rate limiting can be provided in the SOC through the memory controller 122. For example, the memory controller 122 can implement monitoring of the rate of transactions in the pipeline associated with the memory controller and slow down transactions as needed. Slowing down transactions can prevent or reduce power supply droops in the PMU 140 caused by many transactions across many sources (e.g., multiple SOCs in a multi-die configuration).

[0049] Figure 5 is a block diagram of one embodiment of a memory controller pipeline 500. The depiction of the pipeline 500 is a simplified block diagram of one embodiment of a memory controller pipeline. It should be understood that the pipeline 500 and components of the memory controller pipeline can vary outside the scope of the depiction without departing from the scope of the specification and claims herein. For example, additional components or elements can be included in the memory controller pipeline and / or the location of components or elements can vary. Figure 5 The depiction is not intended to limit the scope of the specification and claims herein. For example, additional components or elements can be included in the memory controller pipeline and / or the location of components or elements can vary.

[0050] Memory controller pipeline 500 can include a variety of control logic and data structures to queue memory requests, arbitrate between requests, and transmit memory requests to memory cache and ultimately to memory 120 in the case of a memory cache miss. Communication interfaces 550A-550B can be part of communication fabric 170 and can provide memory requests from other components of SOC 110 to memory controller 122. Requests can be received into request buffers 540A and 540C, which can track requests as they flow through memory controller pipeline 500 and are completed by returning data on communication interfaces 550A-550B (for reads) or updating memory cache or memory 120 (for writes). Response buffers 540B and 540D can be buffers for read data to be transmitted back to the requesting component for read transactions as well as for other responses such as completion responses for certain write transactions and coherency requests for coherency transactions. There can be more request buffers and response buffers for other communication interfaces 550( Figure 5 not shown in FIG. 6). Request buffers 540A and 540C (and other request buffers) can provide input into memory arbiter 525, which can arbitrate requests into memory cache 530. Requests received by memory cache 530 can pass through tag and directory pipeline 520, which can include tag memory for memory cache (storing address tags identifying cache blocks cached in memory cache 530). In one embodiment, tag and directory pipeline 520 can include a coherency directory, which tracks which coherency components in SOC 110 are caching copies of cache blocks from memory. The coherency directory and related logic can generate coherency requests, which can be routed to components via response buffers 540B and 540D.

[0051] If the request is a hit in memory cache (e.g., the address matches one of the tags in tag memory), the tag and directory pipeline 520 request can be placed in data pipeline queue 560 to access cache data memory 595. Read arbiter 565A can arbitrate between read requests in data pipeline queue 560 to read cache data memory 595, while write arbiter 565B can arbitrate between write requests in data pipeline queue 560 to write to cache data memory 595. Read data from cache data memory 595 can be provided to memory output buffer 580. For those write requests that use write responses, write responses can also be placed in memory output buffer 580.

[0052] If the request misses in the memory cache (e.g., the address does not match the tag in the tag memory), the tag and directory pipeline 520 can place the request in a memory queue 570 for transmission to the memory 120. The memory queue 570 can be connected to a memory channel controller that accesses the memory 120. Data (for read requests) or optional write completion (for write requests) can be later returned by the memory channel controller to a memory output buffer 580.

[0053] If data is to be loaded into the memory cache 530, data / write responses from the memory output buffer 580 can be provided to the tag and directory pipeline 520 and can also be provided to the output arbiters 590B, 590D, which can arbitrate to output the data / write responses to the response buffers 540B, 540D, respectively. The data / write responses can be subsequently provided to the requesting components through the communication interfaces 550A-550B.

[0054] The memory cache 530 can include multiple sections or planes that handle different portions of the memory address space mapped to the memory controller 122. The planes can allow multiple memory requests to proceed in parallel. Figure 5 One plane of the memory cache 530 is shown, but other planes can be similarly configured. There can be a memory arbiter 525 for each plane.

[0055] In various embodiments, multiple rate limiters 510 are placed throughout the pipeline 500. For example, rate limiters 510 can be placed at various arbitration points within the pipeline 500. Figure 5 An example of the placement of rate limiters 510 is shown. In the illustrated embodiment, rate limiter 510A is placed at the connection between the read arbiter 565A or the write arbiter 565B and the data pipeline queue 560, rate limiter 510B is placed at the connection between the tag and directory pipeline 520 and the memory arbiter 525, rate limiter 510C is placed at the connection between the output arbiters 590B and 590D and the response buffers 540B and 540D, and rate limiter 510D is placed at the connection between the response buffers 540B and 540D and the communication interfaces 550A, 550B. The number and location (e.g., arbitration points) of rate limiters 510 in the pipeline 500 can vary depending on the control of transaction rates desired in the pipeline 500.

[0056] Rate limiters 510 can be implemented to actively limit peak power levels in pipeline 500 in cases of typical high activity. In various embodiments, rate limiters 510 reduce the command stream by inserting stall cycles at arbitration points. In certain embodiments, rate limiters 510 are disabled by default, but can be configured (e.g., tuned) by a system (e.g., SOC 110 or memory controller 122) to provide a desired upper limit on power consumption through pipeline 500. For example, each rate limiter 510 location can have a rate limiter subcomponent associated with it.

[0057] Figure 6 is a block diagram of one embodiment of a rate limiter subcomponent 600. Rate limiter subcomponent 600 can be implemented in any rate limiter 510 described herein. Rate limiter subcomponent 600 can provide control over the operation and generation of stall control signals for rate limiter 510. In the illustrated embodiment, rate limiter subcomponent 600 includes a rate limiter mode generation circuit 610, a local activity detection circuit 620, and a rate limiter control circuit 630.

[0058] Rate limiter mode generation circuit 610 can include a mode arbitrator 612, a mode register 614, and a pointer 616. Rate limiter mode generation circuit 610 can be programmed using a Vmin mode input, a Vnom mode input, or a Vmax mode input. A rate limiter mode output can be determined based on an operating point input (e.g., a memory operating point) provided to mode arbitrator 612. In various embodiments, rate limiter mode generation circuit 610 determines a rate limiter mode by cycling through mode register 614 according to input from mode arbitrator 612. For example, different modes can be generated for higher performance (higher power) operating points with more stall cycles than for lower performance (lower power) operating points.

[0059] In certain embodiments, local activity detection circuit 620 is implemented to track local memory activity. Local activity detection circuit 620 includes a shift register 622 that receives a history depth input and an activity indication input, an activity counter 624 that receives the activity indication input, and an activity threshold comparator 626 to compare the activity count to an activity threshold. For example, the activity indication can include local activity indications such as a verifier of an arbitrator, a valid pass (e.g., tag pipe valid pass), a read enable control, a write enable control, a completion buffer write arbitrator grant, a completion buffer bypass, and a downstream interface arbitrator grant.

[0060] The shift register 622 can be a configurable register for tracking an activity history. For example, a history depth can program the shift register to track a history for a set number of cycles (e.g., 32 cycles, 16 cycles, or 8 cycles) before comparison to an activity threshold. The activity counter 624 can count activity during the set number of cycles programmed into the shift register 622. At this time, the amount of activity is compared to an activity threshold in the activity threshold comparator 626 to generate a raw stall signal output when the activity is above a predetermined activity threshold.

[0061] The raw stall signal is provided to a rate limiter control circuit 630, which can selectively block or pass the raw stall signal according to a programmed rate limiter mode, among other things. An enable arbiter 632 can be programmed with the rate limiter mode and make determinations of the mode implemented by the rate limiter control circuit 630. One mode can be "static on," in which the raw stall signal is passed and a stall signal is output from the rate limiter subassembly 600, where the rate limiter mode is determined by the rate limiter mode generation circuit 610. Another mode can be "static off," in which the raw stall signal is blocked and no rate limiting occurs. For example, the off mode can be used if it is known that a given memory operation point is low enough in power so as not to cause a PMU voltage drop.

[0062] It is contemplated that additional embodiments have a power management circuit (PMGR) included in any of the systems described herein. Figure 7 is a block diagram of one embodiment of a system including a system on a chip (SOC) 110 coupled to a memory 120 and a power management unit (PMU) 140. The PMU 140 can be configured to power the SOC 110 and other components that can be included in the system, such as the memory 120. For example, the PMU 140 can be configured to generate one or more supply voltages to power the SOC 110, and can further be configured to generate supply voltages for other components of the system (not shown in FIG. 1). In addition to this, the PMU 140 (or accompanying circuitry coupled to the PMU 140) can be configured to monitor the supply voltages and detect transient undervoltage conditions or other overload conditions that can cause erroneous operation in the SOC 110. When such a condition occurs (typically due to an electrical load of the SOC 110 exceeding a capacity of the PMU 140), the PMU 140 can assert a trigger input to the SOC 110. In the embodiment shown, a global power control circuit 130 included in the SOC 110 can receive the trigger input. Although a SOC embodiment is used as an example herein, in other embodiments, a system including multiple integrated circuits coupled to a communication fabric can be used. Figure 7 is a block diagram of one embodiment of a system including a system on a chip (SOC) 110 coupled to a memory 120 and a power management unit (PMU) 140. The PMU 140 can be configured to power the SOC 110 and other components that can be included in the system, such as the memory 120. For example, the PMU 140 can be configured to generate one or more supply voltages to power the SOC 110, and can further be configured to generate supply voltages for other components of the system (not shown in FIG. 1). In addition to this, the PMU 140 (or accompanying circuitry coupled to the PMU 140) can be configured to monitor the supply voltages and detect transient undervoltage conditions or other overload conditions that can cause erroneous operation in the SOC 110. When such a condition occurs (typically due to an electrical load of the SOC 110 exceeding a capacity of the PMU 140), the PMU 140 can assert a trigger input to the SOC 110. In the embodiment shown, a global power control circuit 130 included in the SOC 110 can receive the trigger input. Although a SOC embodiment is used as an example herein, in other embodiments, a system including multiple integrated circuits coupled to a communication fabric can be used.

[0063] As the name implies, the components of SOC 110 can be integrated onto a single semiconductor substrate as an integrated circuit "chip." In the illustrated embodiment, the components of SOC 110 include at least one processor cluster 150, at least one graphics processing unit (GPU) 160, one or more peripheral components (e.g., peripheral component 180 (more briefly, "peripherals")), a memory controller 122, a power management circuit (PMGR) 700, a global power control circuit 130, and a communication fabric 170. Components 150, 160, 180, 122, and 700 can all be coupled to communication fabric 170. Memory controller 122 can be coupled to memory 120 during use. In some embodiments, there can be more than one memory controller coupled to a corresponding memory. In such embodiments, the memory address space can be mapped across the memory controllers in any desired manner. In the illustrated embodiment, processor cluster 150 can include a plurality of processors (P) 152. Processors 152 can form the central processing units (CPUs) of SOC 110. Processor cluster 150 can further include one or more co-processors (e.g., co-processor 154 in Figure 7

[0064] PMGR 700 can be configured to manage power consumption in SOC 110. As Figure 7 illustrated, PMGR 700 can include a telemetry table 702, a power management processor (PMP) 704, and power budget control code 710, which can be stored in a memory within PMGR 700 (e.g., a local static random access memory (SRAM) or read-only memory, etc., local memory) and / or in memory 120. For example, power budget control code 710 can be stored in read-only memory or other form of non-volatile memory and can be loaded into PMGR 700 / memory 120 during initialization of the system. Telemetry table 702 can be any type of memory (e.g., static random access memory (SRAM), registers, etc.). The various components of SOC 110 can report activity levels, performance information, power consumption data, etc., to PMGR 700 in a "push" model with some degree of regularity and, thus, be available for analysis in PMGR 700 without PMGR 700 having to poll the various components to collect the information. More specifically, in this embodiment, PMP 704, in addition to power budget control code 710, can be configured to execute code to analyze the data in the telemetry table.

[0065] ​As previously described, the PMU 140 can be configured to assert a trigger signal when an undervoltage event is detected. When such an event occurs, the SOC 110 (and more specifically, the global power control circuit 130) can respond by quickly reducing the clock frequency at which components operate using techniques such as clock dithering, clock gating, selective pulse removal, clock division, control within various components, etc. While these techniques can be effective for continuous operation without errors (as the reduction in clock frequency offsets the effect of slower evaluation of transistors at reduced voltage), the performance reduction can be significant. For example, dividing the clock frequency by 2 (a relatively fast operation) reduces performance by about 1 / 2. In certain cases, to ensure error-free operation, the performance reduction can be even greater, e.g., 75% or greater. Accordingly, the global power control circuit 130 can be coupled to various components of the SOC 110 (not explicitly depicted in Figure 7 ) or to at least the clock resources (e.g., phase-locked loops (PLLs), delay-locked loops (DLLs), clock dividers, clock gates, clock trees, etc.) of the various components to implement a frequency reduction that can help ensure error-free operation (or correct operation) during undervoltage operation. In one embodiment, the global power control circuit 130 can be configured to record the frequency at which a trigger input to the global power control circuit 130 is asserted (e.g., how often) in the telemetry table 702 (or the frequency at which the global power control circuit 130 participates, depending on the frequency at which the trigger input is asserted), as shown via the dashed arrow in Figure 7 .

[0066] In many cases, less severe performance degradation will be sufficient to reduce the load such that under-voltage events occur less frequently. For example, if an under-voltage event occurs due to the PMU 140 being slightly overloaded, the amount of load reduction to prevent the event from occurring is relatively small, and can be achieved by temporarily reducing the power consumption of one or more controllable components in the system with a slight decrease in performance, but still within the capacity of the PMU 140. The PMP 704 and power budget control code 710 can be used to attempt to reduce the frequency of under-voltage events, or more specifically, reduce the frequency at which the global power control circuit is invoked to provide under-voltage control. For example, in one embodiment, the power budget control code 710 can analyze the telemetry table data and can determine the frequency of under-voltage events or the amount of time that the global power control circuit 130 is engaged to reduce power consumption during a given time window. The power budget control code 710 can modify the power budget to one or more components in the next time window to attempt to reduce the occurrence of under-voltage events. For example, the power budget can be reduced, and thus the components can consume less power in the next time window, reducing the total load current on the PMU 140. While the performance that can be achieved by the components can be reduced in the next time window, the reduction in under-voltage events and the severe performance loss that occurs due to under-voltage events can be reduced, and the overall performance can be higher. For example, the power budget control code 710 can attempt to reduce under-voltage triggers to a specified percentage (e.g., 1% of a given time window). Additional details will be provided further below.

[0067] At least some of the components can be configured to control power consumption based on a power budget. For example, processor cluster 150, GPU 160, and one or more of the peripheral devices 180 can include power control circuitry (PwrCtl) 720A-720C that includes a respective power budget 722A-722C. The power control circuitry 720A-720C can monitor operation of the respective component and measure / estimate power consumption. The power control circuitry 720A-720C can compare the measured / estimated power consumption to the power budget. If the budget is depleted or reduced below a threshold, the power control circuitry 720A-720C can invoke various power consumption mitigation mechanisms. For example, power control circuitry 720A can employ mitigation mechanisms such as deactivating one or more of the processors 152 and / or deactivating one or more pipelines in the processors 152. The instruction issue rate can be reduced, bubbles can be inserted in the pipeline so that the corresponding circuitry is not actively evaluated every cycle. Any set of one or more mitigation mechanisms can be used. Similarly, GPU 160 can reduce the number of active pipelines, limit the instruction issue rate, and / or implement any other mitigation mechanisms. The mitigation mechanisms can be specific to the given component being controlled, and different components can employ different mechanisms or some similar mechanisms and some specific mechanisms as needed. The PMP 704 / power budget control code 710 can be agnostic to the specific mechanisms, the details of setting and adhering to the budgets 722A-722C are implemented by the power control circuitry 720A-720C.

[0068] If the power budget control code 710 reduces the power budgets 722A-722C in one or more of the power control circuitry 720A-720C and the frequency of brownout events is still higher than desired in the next time window, the power budget 710 can be a further reduction in the power budgets in the next time window. Any algorithm for reduction can be used. For example, each budget can be reduced by an amount to achieve the reduction, distributing the performance reduction relatively evenly across the components that can be controlled. In another algorithm, different budgets 722A-722C can be reduced in different time windows, rotating the reduction among different subsets of one or more components and then returning the reduced power budgets to the original values in subsequent time windows.

[0069] Note that while some example implementations are described as power budget control being implemented as code 710 that can be executed by the PMP 704, other implementations can implement all or a portion of the power budget control in hardware, e.g., as state machines and / or combinational logic.

[0070] The PMGR 700 can be configured to control the magnitude of the supply voltage requested by the external PMU 140. There can be multiple supply voltages generated by the PMU 140 for the SOC 110. For example, there can be a supply voltage for the processor cluster 150 and at least one supply voltage for the rest of the SOC 110 other than the processor cluster 150. In one embodiment, the same supply voltage can be used for components of the SOC 110 other than the processor cluster 150, and power gating can be used to control one or more independent power domains powered by the supply voltage. In some embodiments, there can also be multiple supply voltages for the rest of the SOC 110. In some embodiments, there can also be a memory supply voltage for the processor cluster 150 and / or individual memory arrays in the SOC 110. The memory supply voltage can be used in conjunction with a voltage supplied to logic circuits, which can have a lower voltage magnitude than that required to ensure robust memory operation. The PMGR 700 can be under direct software control (e.g., software can directly request power up and / or power down of components) and / or can be configured to monitor the SOC 110 and determine when to power up or power down individual components. Various power states within components (e.g., power states of the processors 152) can be controlled via the PMGR 700, as well as the sequencing of changes in power states, different requested voltages and frequencies, etc.

[0071] As noted above, the processor cluster 150 can include one or more processors 152 that can serve as CPUs of the SOC 110. The CPUs of a system include one or more processors that execute the primary control software of the system, such as an operating system. Generally, the software executed by the CPUs in use can control other components of the system to implement the desired functionality of the system. The processors can also execute other software, such as application programs. Application programs can provide user functionality and can rely on the operating system for lower-level device control, scheduling, memory management, etc. Thus, the processors can also be referred to as application processors.

[0072] Generally, a processor can include any circuitry and / or microcode configured to execute instructions defined in an instruction set architecture implemented by the processor. The processor can encompass a processor core implemented on an integrated circuit with other components as a system on a chip (SOC 110) or other level of integration. The processor can also include a discrete microprocessor, processor core, and / or microprocessor integrated into a multi-chip module implementation, a processor implemented as multiple integrated circuits, etc.

[0073] Memory controller 122 can generally include circuitry to receive memory operations from other components of SOC 110 and to access memory 120 to complete the memory operations. Memory controller 122 can be configured to access any type of memory 120. For example, memory 120 can be static random access memory (SRAM), dynamic RAM (DRAM) such as synchronous DRAM (SDRAM) including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low power / mobile versions of DDR DRAM can be supported (e.g., LPDDR, mDDR, etc.). Memory controller 122 can include a queue of memory operations for ordering (and potentially reordering) the operations and presenting them to memory 120. Memory controller 122 can also include data buffers for storing write data waiting to be written to memory and read data waiting to be returned to the source of the memory operation. In some embodiments, memory controller 122 can include a memory cache for storing recently accessed memory data. For example, in SOC implementations, a memory cache can reduce power consumption in the SOC by avoiding re-accessing data from memory 120 if it is expected to be accessed again soon. In some cases, a memory cache can also be referred to as a system cache, which is distinct from a private cache such as an L2 cache or a cache in a processor that only serves certain components. In addition, in some embodiments, a system cache need not be located within memory controller 122.

[0074] Peripheral devices 180 can be any collection of additional hardware functionality included in SOC 110. For example, peripheral devices 180 can include video peripherals such as image signal processors configured to process image capture data from a camera or other image sensor, video encoders / decoders, expanders, rotators, mixers, display controllers, etc. Peripheral devices can include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. Peripheral devices can include interface controllers for various interfaces external to SOC 110, including interfaces such as universal serial bus (USB), peripheral component interconnect (PCI) including PCI Express (PCIe), serial and parallel ports, etc. Interconnections to external devices are shown by dashed arrows extending outside of SOC 110. Peripheral devices can include networking peripherals such as a media access controller (MAC). Any set of hardware can be included. Figure 7

[0075] ​The communication fabric 170 can be any communication interconnect and protocol for communicating between components of the SOC 110. The communication fabric 170 can be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses with bridges. The communication fabric 170 can also be packet-based, and can be hierarchical, crossbar, point-to-point, or other interconnect with bridges.

[0076] Note that the number of components of the SOC 110 (and the number of subcomponents of those components shown in FIG. 1, such as the number of processors 152 in each processor cluster 150) can vary from implementation to implementation. In addition to this, when multiple processor clusters are included, the number of processors 152 in one processor cluster 150 can be different than the number of processors 152 in another processor cluster 150. The number of each component / subcomponent can be more or less than the number shown in FIG. 1. Figure 7 Figure 8

[0077] According to the present disclosure, an integrated circuit (e.g., the SOC 110) can include a plurality of components, a global power control circuit coupled to the plurality of components, and a power management circuit. A given component of the plurality of components is configured to manage power consumption based on an amount of budget allocated to the given component. The global power control circuit is configured to apply power control across the plurality of components in response to a trigger input to the integrated circuit. The power management circuit is configured to: detect whether the power control applied by the global power control circuit exceeds a threshold; and based on a detection that the power control applied by the global power control circuit exceeds the threshold, reduce the amount of budget allocated to at least one component of the plurality of components. For example, the threshold can include a percentage of time that the power control is applied by the global power control circuit.

[0078] The power management circuit can be configured to measure the percentage of time within a fixed time window. For example, the power management circuit can be configured to detect the percentage during a first instance of the fixed time window, and can be configured to reduce the amount of budget for a next instance of the fixed time window, where the next instance is consecutive to the first instance. For example, the power management circuit can be configured to reduce the amount of budget for a first component of the plurality of components in a given fixed time window, and to reduce the amount of budget for a second component of the plurality of components in another given fixed time window.

[0079] Figure 8 is a block diagram illustrating various power management mechanisms in one embodiment of the SOC 110. These mechanisms are described in more detail in Figure 9 ​​The mechanisms are ordered from left to right in response to the speed at which power demand is managed. On the left is a global power management mechanism (reference numeral 800) that operates based on trigger inputs to quickly reduce clock frequency. The primary focus of the global power management mechanism is to ensure correctness when an undervoltage event occurs. As noted above, because the extent of the undervoltage event is unknown, this mechanism can be fairly coarse-grained, and thus the control can be designed to ensure correctness for worst-case events.

[0080] The second fastest mechanism can be a PMP / power budget control mechanism (reference numeral 802). The PMP mechanism can be slower than the global mechanism, but can have more nuanced, fine-grained control. The PMP mechanism can attempt to limit the engagement of the global power management mechanism by taking actions to improve efficiency and performance. For example, as noted above, the PMP mechanism can include modifying the power budgets of various components that implement power management based on the budgets. In another embodiment, the PMP mechanism can include temporary modifications to the clock frequency and / or supply voltage to one or more components.

[0081] In addition to these, a third power management mechanism can be employed, which is a CPU-based power control (reference numeral 804). The CPU-based power control mechanism can employ software executed by the processor 152, and thus can share execution time with the operating system and various applications. The CPU-based power control mechanism can examine a number of metrics, including telemetry data in the telemetry table 702, but also various measures of performance in the system. The CPU-based power control mechanism can employ dynamic voltage and frequency control, reducing voltage and frequency settings (e.g., “power states”) in the PMGR 700 as a mechanism to relieve power control engagement of the global power control circuit 130 and the PMP power control mechanism, and return power states to their original settings as needed to enhance performance. The CPU-based power control mechanism can reduce power states, for example, if global and PMP-based relief will reduce to a certain extent, i.e., a lower power state will result in higher overall performance / efficiency, even if the system runs slower. In general, the CPU-based mechanism can employ system-wide analysis and power management.

[0082] The global mechanism can have a time scale of about tens to hundreds of nanoseconds; the PMP mechanism can have a time window of about hundreds of microseconds; and the CPU-based mechanism can have a time scale of hundreds of milliseconds. That is, the PMP mechanism can operate using a time window that is one or more orders of magnitude longer than the time scale of the global mechanism, and the CPU-based mechanism can have a time window that is one or more orders of magnitude longer than the PMP mechanism. In one embodiment, the time window of the CPU-based mechanism can be an integer multiple of the time window of the PMP mechanism.

[0083] Figure 9 An embodiment of a power control window implemented using PMP-based power budget control (reference numerals 900A-900N) and CPU power control window 902 is shown. In this example, the power budget control 710 is implemented as part of the PMP 704. Figure 10 In this example, time increases from right to left in arbitrary units. As previously described, the PMP-based mechanism can measure under-voltage events and / or global power control activity in a given PMP window (e.g., window 900A) and modify the power budget of one or more components in a next subsequent or adjacent window (e.g., window 900B).

[0084] Figure 10 is a flowchart showing the operation of one embodiment of PMP-based power budget control 710. However, for ease of understanding, the block diagram shows a particular order, other orders can also be used. Blocks can be executed in parallel in a combinational logic in a hardware-based implementation. Instructions executed by the PMP 704 for a software-based implementation can cause the PMP 704 to perform the specified operations. For example, Figure 9 The operations in can be performed at or near the end of a given PMP time window 900A-900N in Slowly

[0085] The power budget control can read global telemetry from the telemetry table 702 (block 1000). Based on this telemetry data, the power budget control 710 can determine whether the occurrence of under-voltage events / triggers in the previous time window 900A-900N is greater than a desired threshold. The threshold can be measured, for example, in terms of the number of events, the percentage of time that the global power control circuit 130 participates in mitigation mechanisms, and so on. The threshold can be fixed or programmable as desired.

[0086] If the occurrence of events is greater than the desired threshold (decision block 1002, “yes” branch), the power budget control 710 can reduce the power budget of one or more components in the current window (block 1004). If the occurrence of events is not greater than the desired threshold (decision block 1002, “no” branch), the power budget control 710 can increase the power budget in the current window (block 1006). The increase and / or decrease can be subject to a certain amount of hysteresis. For example, if the most recent change was an increase in the power budget, a decrease in the power budget can be delayed until indicated over two or more consecutive PMP time windows. Similarly, if the most recent change was a decrease in the power budget, an increase can be delayed until indicated over two or more consecutive PMP time windows.

[0087] ​It is noted that the decrease in power budget and the increase in power budget can be performed with different weights or magnitudes. For example, the decrease from window to window application can be greater than the increase from window to window application. Thus, if frequent undervoltage events are observed, the power budget will decrease more rapidly in an attempt to quickly reduce the more coarse-grained, correctness-based control to a lower rate. Once the lower rate is achieved, the decrease in power budget is slowed Less than Increasing the power budget can allow the system to enter some stable state.

[0088] Thus, in one embodiment, at least one component of the integrated circuit can include one or more central processing unit (CPU) processors. The CPU can be configured to execute a plurality of instructions to implement power control in the integrated circuit using dynamic voltage and frequency control. The plurality of instructions can implement the power control over a second fixed time window, the second fixed time window being greater than a fixed time window employed by the power management circuit. For example, the second fixed time window can be one or more orders of magnitude longer than the fixed time window. In one embodiment, the second fixed time window can be an integer multiple of the fixed time window. The power management circuit can be configured to: detect that the power control applied by the global power control circuit is less than a threshold; and increase an amount of budget allocated to at least one of the plurality of components based on the detection that the power control applied by the global power control circuit exceeds the threshold. The increase in the amount of budget can be limited to a maximum amount for at least one of the plurality of components. The power management circuit can be configured to apply hysteresis when varying between the increase in the amount of budget and the decrease in the amount of budget. As previously described, in one embodiment, the power management circuit can include a power management processor and a memory coupled to the power management processor, the memory storing a plurality of instructions that, when executed by the power management processor, cause the power management processor to perform operations including the operations described above with respect to the power management circuit. Example method

[0089] Figure 11

[0090] Figure 12 is a flow diagram illustrating a method for reducing power in an integrated circuit, in accordance with some embodiments. The method 1100 can be implemented using any of the embodiments of the SOC as disclosed herein in conjunction with any of the circuits or other mechanisms in the integrated circuit.

[0091] At 1102, in the illustrated embodiment, the integrated circuit receives a plurality of supply voltages from a plurality of voltage regulators, where the integrated circuit includes: a plurality of components that generate memory transactions to access a memory; a plurality of memory controller circuits that control the memory; and a communication fabric that includes a plurality of circuits that interconnect the plurality of components and the plurality of memory controller circuits.​

[0092] At 1104, in the illustrated embodiment, a plurality of power delivery trigger circuits coupled to the integrated circuit and the plurality of voltage regulators generate a plurality of trigger signals based on electrical loads experienced by the plurality of voltage regulators.

[0093] At 1106, in the illustrated embodiment, a trigger logic circuit coupled to the plurality of power delivery trigger circuits generates a power reduction signal based on the plurality of trigger signals received from the plurality of power delivery trigger circuits.

[0094] At 1108, in the illustrated embodiment, a rate control circuit coupled to at least one of the plurality of power delivery trigger circuits controls a clock rate of a plurality of circuits in the communication fabric, wherein the clock rate is reduced based on at least one of the plurality of trigger signals from the at least one of the plurality of power delivery trigger circuits.

[0095] At 1110, in the illustrated embodiment, a given one of a plurality of memory controller circuits controls a rate of memory transactions flowing through a plurality of locations in a pipeline within the given one of the plurality of memory controller circuits according to a plurality of rate limiter circuits at the plurality of locations.

[0096] Example power transmission system is a flowchart illustrating another method for power reduction in an integrated circuit, according to some embodiments. The method 1200 can be implemented using any of the embodiments of a SOC as disclosed herein in conjunction with any of the circuits or other mechanisms in the integrated circuit.

[0097] At 1202, in the illustrated embodiment, the integrated circuit receives a plurality of supply voltages from a plurality of voltage regulators, wherein a plurality of power delivery trigger circuits are coupled to the integrated circuit and the plurality of voltage regulators.

[0098] At 1204, in the illustrated embodiment, a first set of power delivery trigger circuits coupled to the integrated circuit by a wire generate a trigger signal when electrical loads experienced by the plurality of voltage regulators satisfy a first threshold.

[0099] At 1206, in the illustrated embodiment, a second set of power delivery trigger circuits coupled to the integrated circuit by a plurality of serial communication interfaces generate a trigger signal when electrical loads experienced by the plurality of voltage regulators satisfy a second threshold, wherein the first threshold is closer to a functional failure point of the integrated circuit than the second threshold.

[0100] Figure 13 :

[0101] Turning now to Computer readable medium and manufacturing systemFIG. 13 illustrates a block diagram of a system with a power delivery system and a computing element. In the illustrated embodiment, system 1300 includes a hierarchical power delivery system 1310 and a computing element 1320. Hierarchical power delivery system 1310 includes a first power converter level 1312 coupled to receive an input voltage V_in from an external source (e.g., a battery). First power converter level 1312 includes one or more power converters configured to produce one or more first-level regulated supply voltages. These first-level regulated supply voltages are received by one or more power converters of a second power converter level 1314. The power converters of power converter level 1314 use the one or more first-level regulated supply voltages to produce one or more second-level regulated supply voltages. These voltages are provided to various loads of computing element 1320.

[0102] In the illustrated embodiment, computing element 1320 includes one or more integrated circuits (ICs or SOCs) 1322, generally shown here as IC 1322-1 through IC 1322-N. Computing element 1320 is configurable and scalable, with the number of ICs varying from implementation to implementation. For example, in a first implementation, computing element 1320 can include a single IC die, while in a second implementation, computing element 1320 can include two or more IC dies. Implementations that enable only a portion of an IC die are also possible and contemplated.

[0103] While computing element 1320 is thus scalable, the number of ICs of a particular implementation is transparent to the software executing thereon. Thus, regardless of the number of particular ICs in a given implementation, the software executing thereon can view computing element 1320 as a single entity. Computing element 1320 in the illustrated embodiment can thus implement a computing architecture that can be scaled up or down as needed and is capable of executing software on a variety of implementations without regard to such scaling.

[0104] Each of the ICs 1322-1 through 1322-N in the illustrated implementation can include multiple different types of circuitry. For example, the ICs 1322-1 through 1322-N can include various types of processor cores, graphics processing units (GPUs), neural network processors, memory controllers, input / output (I / O) circuitry, network switches for implementing various networks thereon, and the like. When two or more instances of the ICs 1322-1 through 1322-N are implemented to form a compute element, the various functional circuitry thereon can form a composite that is larger than the functional circuitry of an implementation using a single IC or a portion thereof. For example, the IC 1322-1 and the IC 1322-N can each include a composite of processor cores, and thus in an implementation of a compute element 1320 having two or more ICs, a larger composite of processor cores is implemented across multiple ICs. The processor cores of one IC can communicate with the processor cores of another IC through one or more die-to-die interfaces between the individual ICs.

[0105] Given the different power requirements from the different types of circuitry implemented on the instances of the ICs 1322-1 through 1322-N, there can thus be multiple power converters to generate respective voltages to meet the efficiency requirements of these loads. For example, the processor cores can have different power requirements than the I / O circuitry. Thus, the power converter hierarchy 1314 can include one or more power converters suitable to provide a first second hierarchy supply voltage for the processor cores and one or more power converters to provide a different second hierarchy supply voltage for the I / O circuitry.

[0106] The hierarchical power delivery system 1310 in the illustrated embodiment is also scalable, reflecting the scalability of the compute element 1320. In various embodiments, the power converter hierarchy of the hierarchical power delivery system 1310 can include multiple power converters (e.g., switching voltage regulators, etc.) to meet the power requirements of the various loads discussed above. The number of power converters enabled for a particular implementation can thus correspond to the number of ICs 1322-1 through 1322-N in a particular implementation of the compute element 1320. More generally, the power converter hierarchy 1312 and the power converter hierarchy 1314 can be arranged to increase the power supply capability as more computing capability is implemented in the compute element 1320. In this way, the design of the hierarchical power delivery system 1310 can be reused for a variety of different implementations of the compute element 1320. Reusing the design of the hierarchical power delivery system 1310 across a range of scalability of the compute element 1320 can in turn eliminate the need to provide custom power delivery solutions for various different implementations. This can in turn significantly simplify the design of various systems based on different implementations of the compute element 1320, and reduce the amount of time to implement a working system for any particular implementation.

[0107] Figure 14 :

[0108] Example system is a block diagram of one embodiment of a manufacturing system 1400. The system includes a non-transitory computer readable medium 1420 having stored thereon instructions / descriptions 1450 of a power delivery system of any embodiment within the scope of the present disclosure. The computer readable medium 1420 can be one of a variety of different types of non-transitory media capable of providing persistent storage of information, including magnetic disk storage, solid state hard drives (e.g., using flash memory), optical storage (e.g., CD-ROM), various types of random access memory (RAM), etc.

[0109] The computer system 1440 is configured to read the circuit instructions / descriptions 1450 from the computer readable medium 1420. In addition, the computer system 1440 can execute various instructions and use the circuit descriptions to cause a manufacturing system 1445 to manufacture one or more instances of the circuit represented by the circuit instructions / descriptions 1450. The manufacturing system 1445 can be any type of automated system capable of manufacturing electronic circuits.

[0110] Figure 15 :

[0111] Turning next to Figure 15FIG. 15 illustrates a block diagram of one embodiment of a system 1500 that can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 1500 includes at least one instance of a system on a chip (SoC) 1506, which can include multiple types of processing units such as central processing units (CPUs), graphics processing units (GPUs), or other communication structures, as well as interfaces to memory and input / output devices. In some embodiments, one or more of the processors in the SoC 1506 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 1506 is coupled to an external memory 1502, peripheral devices 1504, and a power supply 1508.

[0112] A power supply 1508 is also provided, which supplies a supply voltage to the SoC 1506 and one or more supply voltages to the memory 1502 and / or the peripheral devices 1504. In various embodiments, the power supply 1508 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, or tablet, or other device). In some embodiments, more than one instance of the SoC 1506 is included (and also more than one external memory 1502).

[0113] The memory 1502 is any type of memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module such as a single inline memory module (SIMM), dual inline memory module (DIMM), etc. Alternatively, the devices can be installed with the SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0114] The peripheral devices 1504 include any desired circuitry, depending on the type of system 1500. For example, in one embodiment, the peripheral devices 1504 include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripheral devices 1504 also include additional memory, including RAM memory, solid state memory, or disk memory. The peripheral devices 1504 include user interface devices such as a display screen, including a touch display screen or multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0115] As shown, the illustrated system 1500 has applications in a wide range of fields. For example, the system 1500 can be used as part of a desktop computer 1510, a laptop computer 1520, a tablet 1530, a cellular or mobile phone 1540, or a television 1550 (or a set-top box coupled to a television). A smart watch and health monitoring device 1560 are also shown. In some embodiments, the smart watch 1560 can include various general-purpose computing-related functionality. For example, the smart watch can provide access to email, cell phone service, a user’s calendar, and the like. In various embodiments, the health monitoring device can be a dedicated medical device or otherwise include dedicated health-related functionality. For example, the health monitoring device can monitor the user’s vital signs, track the user’s proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, and the like. In various embodiments, the aforementioned smart watch can or can not include some or any of the health monitoring-related functionality. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, and the like.

[0116] The system 1500 can also be used as part of a cloud-based service 1570. For example, the previously-mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely-located hardware and / or software resources). Still further, the system 1500 can be used in one or more devices of a home in addition to the previously-mentioned devices. For example, home appliances can monitor and detect noteworthy conditions. For example, various devices in a home (e.g., a refrigerator, a cooling system, and the like) can monitor the state of the device and provide an alert to the homeowner (or, for example, a repair agency) in the event that a particular event is detected. Alternatively, a thermostat can monitor the temperature in a home and can automate adjustments to the heating / cooling system based on a history of reactions to various conditions by the homeowner. Figure 15 Applications of the system 1500 to various modes of transportation are also shown. For example, the system 1500 can be used in the control and / or entertainment systems of an airplane, a train, a bus, a taxicab, a private car, watercraft ranging from a private boat to a cruise ship, a scooter (for rent or private), and the like. In various cases, the system 1500 can be used to provide automated guidance (e.g., a self-driving vehicle), general system control, and the like. Any of these and many other embodiments are possible and contemplated. Note that, Figure 15 The illustrated devices and applications are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated.

[0117] The present disclosure also contemplates that devices and / or systems described herein can include or be included within other devices and / or systems. For example, a computing device can be integrated into a vehicle, a home appliance, a wearable device, and the like. Similarly, a computing device can be integrated into a cloud-based service, and the like. ​Some or all of the various devices shown in FIG. 15 use a common, scalable computing architecture. Thus, the computing elements can be scaled according to the needs of the particular system in which the computing elements are implemented. For example, a smart watch / health monitor device 1560 can use a first implementation of the computing elements of the scalable architecture, while a tablet 1530 uses a second implementation, and a desktop computer 1510 uses a third implementation. In this particular example, the implementation of the computing elements in the tablet 1530 can be scaled up relative to the smart watch / health monitor device 1560. Similarly, the implementation of the computing elements in the desktop computer 1510 can be scaled up relative to the implementation of the tablet 1530. Thus, each of these devices can utilize a common computing architecture that is scaled according to the needs of its respective system. In conjunction with the scalable architecture, a power delivery system according to the present disclosure can be provided in each of these applications and can be scaled accordingly with the computing elements. Thus, while each example discussed herein can utilize a power delivery system having a common design, the implementation of the desktop computer 1510 can have a greater power delivery capability than the implementation of the tablet 1530, which in turn has a greater power delivery capability than the implementation of the smart watch / health monitor device 1560. However, the common design of the power delivery system used between these different devices can significantly simplify its implementation, as the power delivery system can be configured for a particular application by enabling / disabling the appropriate power converters therein.

[0118] ***

[0119] The present disclosure includes reference to “an embodiment” or “embodiments” or a group of embodiments (e.g., “some embodiments” or “various embodiments”). An embodiment is a different implementation or example of the disclosed concepts. Reference to “an embodiment,” “one embodiment,” “a specific embodiment,” or the like, is not necessarily a reference to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed and those falling within the scope of the present disclosure.

[0120] The present disclosure can discuss potential advantages that can arise from the disclosed implementations. Not all of the implementations of such embodiments will necessarily achieve any or all of the potential advantages. Whether an advantage is achieved depends on many factors, some of which are outside the scope of the disclosure. Indeed, there can be many reasons why a particular implementation falling within the scope of the claims can not exhibit some or all of any disclosed advantages. For example, particular implementations can include other circuitry outside the scope of the disclosure that negates or reduces one or more of the disclosed advantages. Further, sub-optimal design performance of a particular implementation (e.g., implementation technology or tooling) can also negate or reduce the disclosed advantages. Even assuming a technically optimal implementation, achievement of an advantage can depend on other factors, such as the circumstances surrounding the implementation of the implementation. For example, inputs provided to a particular implementation can prevent one or more problems addressed in the disclosure from occurring in a particular context, and as a result the benefits of its solutions can not be realized. In view of the potential for factors outside the disclosure to affect the realization of any potential advantage, no potential advantage described herein should be understood to be a limitation on the scope of the claims unless so stated in the claims. Rather, the identification of one or more potential improvements that a designer of the disclosure can use is intended to show the type of improvement(s) that a designer of the disclosure can use. The perpetual description of such advantages (e.g., stating that a particular advantage “may occur”) is not intended to convey a doubt that such advantages actually can be realized, but rather a recognition that the realization of such advantages is typically dependent on additional factors that are a reality of technology.

[0121] Unless otherwise indicated, embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims based on the disclosure, even if a single example is described for a particular feature. The disclosed embodiments are intended to be illustrative rather than limiting, without any requirement that any contrary statement be made in the disclosure. The present application is therefore intended to cover claims that encompass the disclosed embodiments, as well as such alternatives, modifications, and equivalents, as would be apparent to one of ordinary skill in the art having the benefit of the present disclosure.

[0122] For example, features in the present application can be combined in any suitable manner. Accordingly, new claims can be formed during the prosecution of the present patent application (or any patent application claiming priority to this patent application) for any such combinations. In particular, with reference to the appended claims, features of dependent claims can be combined with features of the parent claims to form new claims that are admissible under 35 U.S.C. § 112(f), also known as 35 U.S.C. § 120. Similarly, features from any of the dependent claims can be added to the parent claims, to form new claims that are admissible under 35 U.S.C. § 112(f). For example, the features of the dependent claims can be combined with the features of the parent claims to form new claims that are admissible under 35 U.S.C. § 112(f), also known as 35 U.S.C. § 120. Similarly, features from any of the dependent claims can be added to the parent claims, to form new claims that are admissible under 35 U.S.C. § 112(f).

[0123] Accordingly, although the appended claims are drafted in the singular and plural, claims conjoined with the singular, it is contemplated that the appended claims can also be drafted in the alternative. Any combination of the dependent claims in accordance with the present disclosure is contemplated, and these combinations can be claimed in the present application or in another patent application. In short, combinations are not limited to those specifically recited in the claims appended hereto.

[0124] Where appropriate, claims drafted in one format or style (e.g., means plus function) are intended to encompass corresponding claims drafted in the alternative format or style (e.g., method).

[0125] ***

[0126] Because the present disclosure is a legal document, various terms and phrases used herein can be subject to interpretation and judicial discretion. It is hereby given notice that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted in accordance with the present disclosure are interpreted.

[0127] Unless the context clearly dictates otherwise, a reference to an item in the singular (i.e., a noun or noun phrase preceded by “a,” “an,” or “the”) is intended to mean “one or more.” Thus, a reference in the claims to an “item” does not exclude additional instances of the item. A plurality of items is identified using the term “plurality.”

[0128] The word “can” is used herein in the permissive sense (i.e., having the potential to), and not in the mandatory sense (i.e., must).

[0129] The terms “comprise” and “comprising,” and variations thereof, are open-ended, and mean “including but not limited to.”

[0130] When the term “or” is used in the present disclosure with respect to a list of options, it will be generally understood, unless the context dictates otherwise, to be used in an inclusive sense. Thus, the expression “x or y” is equivalent to “x or y, or both,” and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “one of x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0131] The expressions “w, x, y, or z, or any combination thereof’ or “at least one of... w, x, y, and z” are intended to cover all possibilities involving up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. The phrase “at least one of... w, x, y, and z” thus refers to at least one element in the set [w, x, y, z], covering all possible combinations in the list of elements. The phrase should not be interpreted to require the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0132] In this disclosure, various “labels” can precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. In addition to this, unless otherwise noted, the labels “first,” “second,” and “third” when applied to a feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0133] The phrase “based on” is used to describe one or more factors to which a determination is based. This term is not exclusive, meaning that additional factors can influence the determination. That is, the determination can be based on the specified factors alone or on the specified factors and other unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor in determining A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A can also be based on some other factor, such as C. This phrase is also intended to cover implementations in which A is determined based on B alone. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

[0134] The phrases “in response to” and “in response” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors can influence or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect can be in response to the factors alone or in response to the specified factors and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A or that triggers a particular outcome of A. This phrase does not exclude the possibility that A can also be performed in response to some other factor, such as C. This phrase also does not exclude the possibility that A can be performed in response to B and C in conjunction. This phrase is also intended to cover implementations in which A is performed in response to B alone. As used herein, the phrase “in response” is synonymous with the phrase “in response at least in part to.” Similarly, the phrase “in response to” is synonymous with the phrase “in response at least in part to.”

[0135] ***

[0136] Within the present disclosure, different entities (which can be variously referred to as“units,”“circuits,” other components, etc.) can be described or claimed as“configured” to perform one or more tasks or operations. This form of expression is used herein to connote structure (i.e., physical

[0137] In some cases, various units / circuits / components can be described herein as performing a set of tasks or operations. It should be understood that these entities“configured” to perform those tasks / operations are capable of so doing, even when not specifically stated.

[0138] The term“configured” is used herein to connote some manner of changing internal portions of an apparatus, e.g., hardware. “Configured” does not equate to“able to be configured” in this context. For example, an unprogrammed FPGA would not be considered to be“configured” to perform specific functionality merely because it has the capability to do so once programmed.

[0139] For purposes of United States patent applications claiming the benefit of the present disclosure, stating a structure in a claim “configured to” perform one or more tasks expressly

[0140] Different“circuits” can be described in the present disclosure. These circuits or“circuitry” constitute hardware that includes various types of circuit elements, such as combination logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. The circuitry can be custom-designed, or taken from a standard library. In various implementations, the circuitry can include digital components, analog components, or a combination of both, as appropriate. Certain types of circuitry can be commonly referred to as“units” (e.g., decode units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to circuitry or circuitry.

[0141] Thus, the disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements, such as those described in the preceding paragraph. In many cases, the internal arrangement of a hardware element within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decode unit” can be described as performing the function of “processing the operation code of an instruction and routing the instruction to one or more of a plurality of functional units,” which means that the decode unit is “configured to” perform that function. To the skilled artisan in the computer field, this functional specification is sufficient to imply a set of possible structures for the circuit.

[0142] In various embodiments, circuits, units, and other elements can be defined by the functions or operations that they are configured to implement, as described in the preceding paragraph. The arrangement of relative to one another and the manner in which such circuits / units / components interact, as well as the manner in which they are programmed to operate, form a microarchitecture definition of the hardware that is ultimately fabricated in integrated circuits or programmed into FPGAs to form a physical implementation of the microarchitecture definition. Thus, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, a skilled artisan applying the teachings of the present disclosure could, without undue experimentation, implement the structure by coding the description of the circuits / units / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a manner that can appear functional. But to the skilled artisan, the HDL description is a way to transform the structure of the circuits, units, or components into a next level of implementation details. Such HDL descriptions can take the form of behavioral code (which is often not synthesizable), register transfer language (RTL) code (which is often synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description can be sequentially synthesized against a cell library designed for a given integrated circuit fabrication technology, and can be modified for timing, power, and other reasons to arrive at a final design database that is exported to a fabrication facility to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof can also be custom designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements. Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuits, and / or can use discrete elements in some embodiments. Alternatively, the HDL design can be synthesized for a programmable logic array such as a field programmable gate array (FPGA), and can be implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent lower level implementation of those circuits often results in a situation in which the circuit or logic designer never specifies a particular set of structures for the lower level implementation beyond a description of what the circuit is configured to do, as that process is performed at a different stage of the circuit implementation process.

[0143] The fact that many different low-level combinations of circuit elements can be used to achieve the same specifications of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries available for a particular project, and so on. In many cases, the selection of these different implementations made by different design tools or methodologies can be arbitrary.

[0144] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Consequently, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0145] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. An integrated circuit, comprising: a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budget amount allocated to the given component; a global power control circuit coupled to the plurality of components and configured to apply power control across the plurality of components in response to a trigger input to the integrated circuit, wherein total power consumption in the integrated circuit is reduced based on the power control applied by the global power control circuit; and A power management circuit, the power management circuit being configured to: analyzing telemetry data for the global power control circuit to detect whether the power control applied by the global power control circuit exceeds a threshold associated with performance of the global power control circuit; as well as Based on detecting that the power control applied by the global power control circuit exceeds the threshold, reducing the budget amount allocated to at least one of the plurality of components, wherein the at least one of the plurality of components is configured to manage its power consumption based on the reduction in the allocated budget amount. 2 . The integrated circuit of claim 1 , wherein the threshold comprises a percentage of time that the power control is applied by the global power control circuit. 3 . The integrated circuit of claim 2 , wherein the power management circuit is configured to measure the percentage of time within a fixed time window.

4. The integrated circuit of claim 3 , wherein the power management circuit is configured to detect the percentage during a first instance of the fixed time window and is configured to reduce the budget amount for a next instance of the fixed time window, wherein the next instance is consecutive to the first instance.

5. The integrated circuit of claim 4 , wherein the power management circuit is configured to reduce the budget amount for a first component among the plurality of components in a given fixed time window, and to reduce the budget amount for a second component among the plurality of components in another given fixed time window.

6. The integrated circuit of claim 3 , wherein at least one of the components comprises one or more central processing unit (CPU) processors, and wherein the CPU processors are configured to execute a second plurality of instructions to implement power control in the integrated circuit using dynamic voltage and frequency control.

7. The integrated circuit of claim 6, wherein the second plurality of instructions implements power control over a second fixed time window that is greater than the fixed time window.

8. The integrated circuit of claim 7, wherein the second fixed time window is one or more decades longer than the fixed time window.

9. The integrated circuit of claim 7, wherein the second fixed time window is an integer multiple of the fixed time window.

10. The integrated circuit of claim 1 , wherein the power management circuit is configured to: detecting that the power control applied by the global power control circuit is less than the threshold; and Based on the detection that the power control applied by the global power control circuit is less than the threshold, the budget amount allocated to at least one component of the plurality of components is increased.

11. The integrated circuit of claim 10, wherein an increase in the budget amount is limited to a maximum amount for at least one component of the plurality of components. 12 . The integrated circuit of claim 10 , wherein the power management circuit is configured to apply hysteresis when changing between an increase in the budget amount and a decrease in the budget amount.

13. The integrated circuit of claim 1 , wherein the power management circuit comprises a power management processor and a memory coupled to the power management processor, the memory storing a plurality of instructions that, when executed by the power management processor, cause the power management processor to perform operations including the operations described above for the power management circuit.

14. A system comprising: An integrated circuit, the integrated circuit comprising: a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budget amount allocated to the given component; a global power control circuit coupled to the plurality of components and configured to apply power control across the plurality of components in response to a trigger input to the integrated circuit, wherein total power consumption in the integrated circuit is reduced based on the power control applied by the global power control circuit; and A power management circuit, the power management circuit being configured to: analyzing telemetry data for the global power control circuit to detect whether the power control applied by the global power control circuit exceeds a threshold associated with performance of the global power control circuit; and reducing the budget amount allocated to at least one of the plurality of components based on detection that the power control applied by the global power control circuit exceeds the threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the reduction in the allocated budget amount; and A power management unit is coupled to the integrated circuit, wherein the power management unit is configured to provide power to the integrated circuit and generate the trigger input.

15. The system of claim 14, wherein the power management circuit is configured to: detecting that the power control applied by the global power control circuit is less than the threshold; and Based on detecting that the power control applied by the global power control circuit exceeds the threshold, the budget amount allocated to at least one component of the plurality of components is increased.

16. The system of claim 15, wherein an increase in the budget amount is limited to a maximum amount for at least one of the plurality of components.

17. The system of claim 14, wherein the threshold comprises a percentage of time that the power control is applied by the global power control circuit.

18. The system of claim 17, wherein the power management circuit is configured to measure the percentage of time within a fixed time window.

19. The system of claim 18, wherein the power management circuit is configured to detect the percentage during a first instance of the fixed time window and is configured to reduce the budget amount for a next instance of the fixed time window, wherein the next instance is consecutive to the first instance.

20. A non-transitory computer-readable medium storing a plurality of instructions for a power management processor in power management circuitry of an integrated circuit, the integrated circuit further comprising a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budget amount allocated to the given component, and the integrated circuit further comprising a global power control circuit configured to apply power control across the plurality of components in response to a trigger input to the integrated circuit, wherein total power consumption in the integrated circuit is reduced based on the power control applied by the global power control circuit, and wherein the plurality of instructions, when executed by the power management processor, causes the power management processor to perform operations comprising: analyzing telemetry data for the global power control circuit to detect whether the power control applied by the global power control circuit exceeds a threshold associated with performance of the global power control circuit; as well as Based on detecting that the power control applied by the global power control circuit exceeds the threshold, reducing the budget amount allocated to at least one of the plurality of components, wherein the at least one of the plurality of components is configured to manage its power consumption based on the reduction in the allocated budget amount.

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