Integrated device comprising a column interconnect with a cavity

Abstract

An integrated device (e.g., flip chip) (100) includes a die portion (102) including a plurality of pads (107a, 107b) and a plurality of under bump metallization interconnects (109a, 109b) coupled to the plurality of pads (107a, 107b); and a plurality of pillar interconnects (104a, 104b) including a first pillar interconnect (104a) including a first cavity (209) and a second pillar interconnect (104b) including a second cavity (209). The cavity (209) can extend partially through a height of the pillar interconnect (104a, 104b). A planar cross-section of the cavity (209) extending through the pillar interconnect (104a, 104b) can include an O-shape. A plurality of solder interconnects (106a, 106b) can be coupled to the plurality of pillar interconnects (104a, 104b) and can include a solder interconnect (106a, 106b) located in the cavity (209) of the pillar interconnect (104a, 104b). The pillar interconnect (104a, 104b) can include a first pillar interconnect portion (204) including a first width and a second pillar interconnect portion (206) including a second width different from (e.g., smaller than) the first width, where the cavity (209) of the pillar interconnect (104a, 104b) can be located in the second pillar interconnect portion (206). The pillar interconnect (104a, 104b) can include a shape of a top hat. A method (700) for manufacturing an integrated device (100) can include providing a die portion (102) and forming a plurality of pillar interconnects (104). Forming the plurality of pillar interconnects (104) can include forming and patterning a first photoresist layer (600) over the die portion (102); forming a first pillar interconnect portion (602) (e.g., ring-shaped); removing the first photoresist layer (600); forming and patterning a second photoresist layer (610) (e.g., having a circular pattern with a diameter between an inner diameter and an outer diameter of the ring-shaped first interconnect portion (602)) over the die portion (102); and forming a second pillar interconnect portion over the first pillar interconnect portion (602) such that a first cavity (209) is formed in the second pillar interconnect portion. Forming the plurality of pillar interconnects (104) can also include forming a solder interconnect (106) over the cavity (209) of the pillar interconnect (104). The second photoresist layer (610) can be removed after forming the first solder interconnect (106). Portions of the under bump metallization layer (109) can then be removed, and the plurality of solder interconnects (106) can be reflowed. A package (400) includes a substrate (402) and an integrated device (100) coupled to the substrate (402) by a plurality of pillar interconnects (104a, 104b) and a plurality of solder interconnects (106a, 106b).The solder interconnects (106a, 106b) can include intermetallic compounds (IMCs) (406a, 406b) that can be formed when metals from the substrate interconnects (422a, 422b) and / or the post interconnects (104a, 104b) diffuse in the solder interconnects (106a, 106b) upon a solder reflow process used to couple the integrated device (100) to the substrate (402). The cavities (209) allow more surface area of the solder interconnects (106a, 106b) to couple, providing a more robust and reliable bond between the integrated device (100) and the substrate (402). The cavities (209) also allow more solder interconnects (106a, 106b) to be located between the post interconnects (104a, 104b) and the substrate (402) without causing shorts between adjacent interconnects (104a, 104b) of the substrate (402).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to non-provisional application sequence 17 / 409,334, filed August 23, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as if their full contents were set forth below and used for all applicable purposes. Technical Field

[0003] Various features are involved in integrated devices. Background Technology

[0004] Packages may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing a variety of electrical functions. The performance of a package and its components may depend on the quality of the bonding points between the various components of the package. There has always been a need for packages that include robust and reliable bonding points between the components. Summary of the Invention

[0005] Various features are involved in integrated devices.

[0006] One example provides an integrated device including a die portion. The die portion includes multiple pads and multiple under-bump metallized interconnects coupled to the multiple pads. The integrated device includes multiple pillar interconnects coupled to the multiple under-bump interconnects. The multiple pillar interconnects include a first pillar interconnect including a first cavity.

[0007] Another example provides a package including a substrate and an integrated device coupled to the substrate via a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity.

[0008] Another example provides a method for manufacturing an integrated device. The method provides a die portion. The die portion includes a plurality of pads and a plurality of under-bump interconnects coupled to the plurality of pads. The method forms a plurality of pillar interconnects over the plurality of under-bump interconnects. Forming the plurality of pillar interconnects includes forming a first pillar interconnect including a first cavity. Attached Figure Description

[0009] The various features, essences, and advantages will become apparent when the following detailed description is understood in conjunction with the accompanying drawings, in which similar reference numerals are used throughout to indicate them accordingly.

[0010] Figure 1 A cross-sectional view of an exemplary integrated device including cavity-type pillar interconnects is shown.

[0011] Figure 2 An exemplary post interconnect with a cavity is shown.

[0012] Figure 3 A cross-sectional plan view of an exemplary post interconnect with a cavity is shown.

[0013] Figure 4 A cross-sectional view of an exemplary package including an integrated device comprising cavity-type pillar interconnects is shown.

[0014] Figure 5 A close-up view of an exemplary package including an integrated device comprising cavity pillar interconnects, wherein the integrated device is coupled to a substrate.

[0015] Figures 6A to 6D An exemplary process for manufacturing an integrated device including cavity post interconnects is shown.

[0016] Figure 7 An exemplary flowchart of a method for manufacturing an integrated device including cavity pillar interconnects is shown.

[0017] Figure 8 An exemplary process for manufacturing a package including an integrated device comprising cavity-type pillar interconnects is shown.

[0018] Figure 9 An exemplary flowchart of a method for manufacturing a package including an integrated device comprising cavity-type pillar interconnects is shown.

[0019] Figure 10 Various electronic devices are shown that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Detailed Implementation

[0020] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring these aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these aspects of this disclosure.

[0021] This disclosure describes a package including a substrate and an integrated device coupled to the substrate via a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects includes a first solder interconnect located within the first cavity of the first pillar interconnect. A planar cross-section extending through the first cavity of the first pillar interconnect includes an O-shape. The first pillar interconnect includes a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width different from the first width. The first cavity allows for coupling of more surface area of ​​the first solder interconnect, thereby providing a more robust and reliable connection point between the integrated device and the substrate. The first cavity also allows for more solder interconnects located between the first pillar interconnect and the substrate without causing short circuits between adjacent interconnects on the substrate. The more robust and reliable connection point provides a more reliable electrical path for current and / or signal travel between the integrated device and the substrate, which can lead to improved performance of the integrated device and the package.

[0022] Exemplary integrated device including cavity-type pillar interconnects

[0023] Figure 1 A cross-sectional view of an integrated device 100 including cavity-type pillar interconnects is shown. The integrated device 100 includes a die portion 102, a plurality of pillar interconnects 104, and a plurality of solder interconnects 106. The plurality of pillar interconnects 104 are coupled to the die portion 102. The plurality of solder interconnects 106 are coupled to the plurality of pillar interconnects 104. As will be further described below, at least one of the pillar interconnects 104 may include a cavity extending at least partially along the height of the pillar interconnect. This cavity establishes an additional surface area for coupling of the solder interconnects. The cavity also creates more space to accommodate more solder interconnects while reducing the likelihood of short circuits with nearby interconnects. The additional surface area of ​​the pillar interconnects and / or the additional amount of solder interconnects contribute to providing a more robust and reliable bonding point for the integrated device, thereby providing a more robust and reliable electrical path for current entering and exiting the integrated device. The integrated device 100 may include a flip chip.

[0024] The die portion 102 includes a die substrate 120, interconnect portions 122, a passivation layer 105, multiple pads 107, and multiple under-bump metallization interconnects 109. The die substrate 120 may include silicon (Si). Multiple cells and / or transistors (not shown) may be formed in and / or on the die substrate 120. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, fin FETs, and gate-all-around FETs. In some implementations, front-end processing (FEOL) processes may be used to fabricate the multiple cells and / or transistors in and / or on the die substrate 120. The interconnect portions 122 are located on and coupled to the die substrate 120. The interconnect portions 122 may be coupled to the multiple cells and / or transistors located in and / or on the die substrate 120. The interconnect portions 122 may include at least one dielectric layer and multiple die interconnects (not shown), wherein the multiple die interconnects are coupled to the multiple cells and / or transistors. In some implementations, back-end process (BEOL) technology can be used to manufacture interconnect portion 122.

[0025] A passivation layer 105 is located on and coupled to an interconnect portion 122. Multiple pads 107 are located on the interconnect portion 122. The multiple pads 107 may be coupled to die interconnects of the interconnect portion 122. In some implementations, the passivation layer 105 and / or the multiple pads 107 may be considered part of the interconnect portion 122. In some implementations, the passivation layer 105 and the multiple pads 107 may be fabricated using a back-end process (BEOL). Multiple under-bump metallized interconnects 109 are coupled to the multiple pads 107. The multiple under-bump metallized interconnects 109 may be located on the multiple pads 107. In some implementations, additional interconnects may exist between the multiple pads 107 and the multiple under-bump metallized interconnects 109. For example, metallized interconnects may exist between the multiple pads 107 and the multiple under-bump metallized interconnects 109. Examples of metallized interconnects include redistributed interconnects. In some implementations, multiple under-bump metallized interconnects 109 can be coupled to multiple pads 107 via metallized interconnects (e.g., redistributed interconnects). Thus, the multiple under-bump metallized interconnects 109 coupled to the multiple pads 107 can be directly coupled to the multiple pads 107 and / or indirectly coupled to the multiple pads 107 via at least one metallized interconnect.

[0026] Multiple pillar interconnects 104 may be coupled to die portion 102. Multiple pillar interconnects 104 may be coupled to multiple under-bump metallized interconnects 109. Multiple pillar interconnects 104 may be coupled to die portion 102 via multiple under-bump metallized interconnects 109. Multiple pillar interconnects 104 may be components for pillar interconnects. Multiple under-bump metallized interconnects 109 may be components for under-bump metallized interconnects.

[0027] Multiple pads 107 include a first pad 107a and a second pad 107b. Multiple under-bump metallized interconnects 109 include a first under-bump metallized interconnect 109a and a second under-bump metallized interconnect 109b. Multiple pillar interconnects 104 include a first pillar interconnect 104a and a second pillar interconnect 104b. Multiple solder interconnects 106 include a first solder interconnect 106a and a second solder interconnect 106b.

[0028] A first under-bump metallized interconnect 109a is coupled to a first pad 107a. A first pillar interconnect 104a is coupled to the first under-bump metallized interconnect 109a. A first solder interconnect 106a is coupled to the first pillar interconnect 104a. The first pillar interconnect 104a includes a first cavity, and a portion of the first solder interconnect 106a may be located within the first cavity of the first pillar interconnect 104a. Note that in some implementations, the first pillar interconnect 104a is coupled to the first under-bump metallized interconnect 109a via at least one metallized interconnect. That is, at least one metallized interconnect (e.g., a redistributed interconnect) may be located between the first pillar interconnect 104a and the first under-bump metallized interconnect 109a.

[0029] The second under-bump metallized interconnect 109b is coupled to the second pad 107b. The second pillar interconnect 104b is coupled to the second under-bump metallized interconnect 109b. The second solder interconnect 106b is coupled to the second pillar interconnect 104b. The second pillar interconnect 104b includes a second cavity, and a portion of the second solder interconnect 106b may be located within the second cavity of the second pillar interconnect 104b. At least in the following description... Figure 2 The following describes an example of the cavity of the pillar interconnect. Note that in some implementations, the second pillar interconnect 104b is coupled to the second under-bump metallized interconnect 109b via at least one metallized interconnect. That is, at least one metallized interconnect (e.g., a redistributed interconnect) may be located between the second pillar interconnect 104b and the second under-bump metallized interconnect 109b.

[0030] Figure 2 An exemplary view of the column interconnect 104 is shown. Figure 2 The column interconnect 104 can represent Figure 1 Any one of the multiple pillar interconnects in the array. For example... Figure 2 As shown, the pillar interconnect 104 includes a cavity 209. The cavity 209 may extend at least partially along the height of the pillar interconnect 104. Figure 2In this embodiment, cavity 209 has a hemispherical shape (e.g., bowl-shaped). However, the shape and / or size of cavity 209 may vary depending on the implementation. Cavity 209 may be a groove. Post interconnect 104 has a general top hat shape, even though post interconnect 104 has cavity 209. The brim portion of the top hat-shaped post interconnect 104 may be coupled to a bump-under-metallized interconnect.

[0031] The pillar interconnect 104 includes a first pillar interconnect portion 204 and a second pillar interconnect portion 206. The first pillar interconnect portion 204 may represent a base of the pillar interconnect 104. The first pillar interconnect portion 204 may be considered as a brim portion of the pillar interconnect 104. The first pillar interconnect portion 204 may be coupled to under-bump metallized interconnects (e.g., 109a, 109b). The first pillar interconnect portion 204 includes a first width. The first width may include a first diameter. The second pillar interconnect portion 206 includes a second width. The second width may include a second diameter. The second width is different from the first width. For example, the second width may be smaller than the first width. A cavity 209 is located in the second pillar interconnect portion 206. The cavity 209 may extend at least partially along the height of the pillar interconnect 104 (e.g., along the height of the second pillar interconnect portion 206). Figure 2 The planar cross-sectional area of ​​the pillar interconnect 104 is shown to be circular. However, the pillar interconnect 104 may have a planar cross-section of any shape (e.g., elliptical, rectangular, square). Solder interconnects (e.g., 106a, 106b) may be coupled to the second pillar interconnect portion 206. A portion of the solder interconnect may be located within the cavity 209 of the pillar interconnect 104. Note that the first pillar interconnect portion 204 and the second pillar interconnect portion 206 may be considered as one portion or two or more separate portions. An interface may or may not exist between the first pillar interconnect portion 204 and the second pillar interconnect portion 206. It should also be noted that in some implementations, a portion of the pillar interconnect 104 may be considered as part of the metallization layer (e.g., redistribution layer) of the integrated device.

[0032] Figure 3 A cross-sectional plan view of the column interconnect 104 is shown. Figure 3As shown, the planar cross-section extending through the cavity 209 of the first post interconnect 104 includes an O-shape. For example, the planar cross-section extending through the cavity 209 of the second post interconnect portion 206 includes an O-shape. However, different implementations may have different shapes for the planar cross-section of the post interconnect 104. The post interconnect 104 may have different sizes. For example, the first post interconnect portion 204 may have a first width (e.g., a first diameter) in the range of about 50 micrometers to 70 micrometers. The second post interconnect portion 206 may have a second width (e.g., a second diameter) in the range of about 30 micrometers to 50 micrometers. The cavity 209 may have a cavity width (e.g., a cavity diameter) in the range of about 20 micrometers to 40 micrometers. The post interconnect 104 may have a height in the range of about 10 micrometers to 15 micrometers. Note that the values ​​and ranges mentioned above are exemplary and not intended to be limiting. In some implementations, the values ​​and / or ranges may include values ​​greater than or less than those mentioned above.

[0033] The integrated device 100 can be implemented in a package. Figure 4 A package 400 is shown, comprising a substrate 402, an integrated device 100, and an encapsulation layer 408. The substrate 402 includes at least one dielectric layer 420, a plurality of interconnects 422, and a solder mask layer 426. A plurality of solder interconnects 430 are coupled to the plurality of interconnects 422 of the substrate 402. The integrated device 100 is coupled to a first surface (e.g., a top surface) of the substrate 402 via a plurality of pillar interconnects 104 and a plurality of solder interconnects 106. The encapsulation layer 408 may be located on and / or surrounding the integrated device 100 and / or the substrate 402. The encapsulation layer 408 may at least partially encapsulate the integrated device 100. The encapsulation layer 408 may comprise a molding compound, resin, and / or epoxy resin. The encapsulation layer 408 may be an encapsulation member. The encapsulation layer 408 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0034] Figure 5 A close-up view shows how integrated devices can be coupled to a substrate. Figure 5 A portion of a package 400, including an integrated device 100 and a substrate 402, may be shown. The integrated device 100 is coupled to the substrate 402 via a plurality of pillar interconnects 104 and a plurality of solder interconnects 106.

[0035] like Figure 5As shown, a first pillar interconnect 104a is coupled to a first solder interconnect 106a. The first solder interconnect 106a is coupled to a first interconnect 422a of the substrate 402. The first solder interconnect 106a may include an intermetallic compound (IMC) 406a. The intermetallic compound 406a may be coupled to both the first pillar interconnect 104a and the first interconnect 422a. The intermetallic compound 406a may be formed as metal from the first interconnect 422a and / or the first pillar interconnect 104a diffuses within the solder interconnect 106a.

[0036] The second pillar interconnect 104b is coupled to the second solder interconnect 106b. The second solder interconnect 106b is coupled to the second interconnect 422b of the substrate 402. The second solder interconnect 106b may include an intermetallic compound (IMC) 406b. The intermetallic compound 406b may be coupled to the second pillar interconnect 104b and the second interconnect 422b. The intermetallic compound 406b may be formed when metal from the second interconnect 422b and / or the second pillar interconnect 104b diffuses in the solder interconnect 106b.

[0037] Figure 5 This illustrates a large gap between the intermetallic compound (e.g., 406a) in the solder interconnect (e.g., 106a). This helps provide a more robust and reliable bonding point. It also helps reduce stress during coupling of the integrated device to the substrate, which helps reduce the likelihood of package breakage. The additional space provided by the cavity in the pillar interconnect helps prevent solder breakage because the increased solder volume reduces the likelihood of solder separation.

[0038] The integrated device (e.g., 100) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors, and / or combinations thereof. The integrated device (e.g., 100) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may be an example of an electrical component and / or electrical device.

[0039] Integrated devices with cavity pillar interconnects have been described; methods for manufacturing integrated devices will now be described below.

[0040] Exemplary process for manufacturing an integrated device including cavity pillar interconnects.

[0041] In some implementations, manufacturing integrated devices involves several processes. Figures 6A to 6D Exemplary steps for providing or manufacturing an integrated device including cavity-type pillar interconnects are shown. In some implementations, Figures 6A to 6D The process can be used to provide or manufacture integrated device 100. However, Figures 6A to 6D The process can be used to manufacture any integrated device described in this disclosure.

[0042] It should be noted that Figures 6A to 6D The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this disclosure.

[0043] like Figure 6A As shown, stage 1 illustrates the state after die portion 102 has been provided. Die portion 102 may include die substrate 120, interconnect portion 122, passivation layer 105, multiple pads 107, and multiple under-bump metallization interconnects 109. Die portion 102 may include bare die (e.g., semiconductor bare die).

[0044] Phase 2 illustrates the state after the first photoresist layer 600 is formed on the die portion 102 and patterned to include a plurality of openings 601 in the first photoresist layer 600. A photolithography process can be used to form the first photoresist layer 600 and define the pattern of the first photoresist layer.

[0045] Phase 3 illustrates the state after pillar interconnect portions 602 are formed through multiple openings 601 in the first photoresist layer 600. Pillar interconnect portions 602 may be formed over multiple under-bump metallized interconnects 109 (or under-bump metallization layers). Plating processes may be used to form the pillar interconnect portions 602. Pillar interconnect portions 602 may include copper.

[0046] like Figure 6B As shown, stage 4 illustrates the state after the first photoresist layer 600 has been removed from the die portion 102. The first photoresist layer 600 can be removed by a developing process. The first photoresist layer 600 can be removed by a rinsing process.

[0047] Stage 5 illustrates the state after the second photoresist layer 610 is formed on the die portion 102 and patterned to include a plurality of openings 611 in the second photoresist layer 610. The second photoresist layer 610 may be formed on the pillar interconnect portion 602. A photolithography process may be used to form the second photoresist layer 610 and define the pattern of the second photoresist layer.

[0048] like Figure 6C As shown, stage 6 illustrates the state after a plurality of pillar interconnects 104 have been formed through a plurality of openings 611 in the second photoresist layer 610. The plurality of pillar interconnects 104 may be formed over a plurality of under-bump metallized interconnects 109 (or under-bump metallization layers). The plurality of pillar interconnects 104 may be formed over pillar interconnect portions 602. Pillar interconnect portions 602 may be considered as part of the plurality of pillar interconnects 104. A plating process may be used to form the plurality of pillar interconnects 104. The pillar interconnects 104 may include copper. One or more interfaces may or may not exist between the pillar interconnect portions 602 formed in stage 3 and the portions of the plurality of pillar interconnects 104 formed in stage 6. The plurality of pillar interconnects 104 are formed such that at least one pillar interconnect includes a cavity 209.

[0049] Stage 7 illustrates the state after a plurality of solder interconnects 106 have been formed over the plurality of pillar interconnects 104 through the plurality of openings 611 of the second photoresist layer 610. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently.

[0050] like Figure 6D As shown, stage 8 illustrates the state after the second photoresist layer 610 has been removed from the die portion 102. The second photoresist layer 610 can be removed by a developing process. The second photoresist layer 610 can be removed by a rinsing process.

[0051] Stage 9 illustrates the state after portions of the under-bump metallization layer are selectively etched to define under-bump metallized interconnects 109a and 109b. Stage 9 may also illustrate the state after the plurality of solder interconnects 106 have undergone a solder reflow process to couple the plurality of pillar interconnects 104. Stage 9 may illustrate an integrated device 100 including a die portion 102, the plurality of pillar interconnects 104, and the plurality of solder interconnects 106, wherein at least one of the pillar interconnects 104 includes a cavity (e.g., 209) extending at least partially through the height (e.g., thickness) of the pillar interconnect. The plurality of solder interconnects 106 may be located within the cavity of the pillar interconnect. The plurality of solder interconnects 106 includes a first solder interconnect 106a coupled to a first pillar interconnect 104a and a second solder interconnect 106b coupled to a second pillar interconnect 104b.

[0052] Exemplary flowchart of a method for manufacturing an integrated device including cavity pillar interconnects

[0053] In some implementations, manufacturing integrated devices involves several processes. Figure 7 An exemplary flowchart of a method 700 for providing or manufacturing an integrated device including cavity pillar interconnects is shown. In some implementations, Figure 7Method 700 can be used to provide or manufacture the products described in this disclosure. Figure 1 The integrated device 100. However, method 700 can be used to provide or manufacture any integrated device described in this disclosure.

[0054] It should be noted that Figure 7 The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some implementations, the order of the processes may be changed or modified.

[0055] The method (at 705) provides a die portion (e.g., 102). The die portion 102 may include a die substrate 120, interconnect portions 122, a passivation layer 105, a plurality of pads 107, and a plurality of under-bump metallization interconnects 109. The die portion 102 may include a bare die (e.g., a semiconductor bare die). Figure 6A Phase 1 shows and describes an example of providing the die portion.

[0056] The method (at 710) forms a first photoresist layer (e.g., 600) over a die portion (e.g., 102). The method may also (at 710) pattern the first photoresist layer (e.g., 600). A photolithography process may be used to form the first photoresist layer 600 and define the pattern of the first photoresist layer. Figure 6A Stage 2 shows and describes an example of forming and patterning the first photoresist layer.

[0057] This method (at 715) forms pillar interconnect portions (e.g., 602). Pillar interconnect portions 602 may be formed over a plurality of under-bump metallized interconnects 109 (or under-bump metallization layers). A plating process may be used to form pillar interconnect portions 602. Pillar interconnect portions 602 may be formed through a plurality of openings 601 in the first photoresist layer 600. Figure 6A Stage 3 shows and describes an example of forming the column interconnection section.

[0058] The method (at 720) removes a first photoresist layer (e.g., 600). The first photoresist layer 600 can be removed by a developing process. The first photoresist layer 600 can be removed by a rinsing process. Figure 6B Stage 4 shows and describes an example of removing the first photoresist layer.

[0059] The method (at 725) forms a second photoresist layer (e.g., 610) over a die portion (e.g., 102). The method may also (at 725) pattern the second photoresist layer (e.g., 610). A photolithography process may be used to form the second photoresist layer 610 and define the pattern of the second photoresist layer. Figure 6B Stage 5 shows and describes an example of forming and patterning the second photoresist layer.

[0060] The method (at 730) forms another pillar interconnect portion to form a plurality of pillar interconnects 104, wherein at least one pillar interconnect includes a cavity (e.g., 209). The plurality of pillar interconnects 104 may be formed over a plurality of under-bump metallized interconnects 109 (or under-bump metallization layers). The plurality of pillar interconnects 104 may be formed over pillar interconnect portion 602. Pillar interconnect portion 602 may be considered part of the plurality of pillar interconnects 104. A plating process may be used to form the plurality of pillar interconnects 104. One or more interfaces may or may not exist between the pillar interconnect portion 602 formed (at 715) and the portions of the plurality of pillar interconnects 104 formed (at 730). The plurality of pillar interconnects 104 are formed such that at least one pillar interconnect includes a cavity 209. Figure 6C Phase 6 shows and describes an example of forming column interconnect portions to form column interconnects.

[0061] The method (at 735) provides a plurality of solder interconnects (e.g., 106) over cavities (e.g., 209) of a plurality of pillar interconnects (e.g., 104). The plurality of solder interconnects 106 may be formed over the plurality of pillar interconnects 104 through a plurality of openings 611 of a second photoresist layer 610. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently. Figure 6C Phase 7 shows and describes examples of providing and / or forming multiple solder interconnects.

[0062] The method (at 740) removes a second photoresist layer (e.g., 610). The second photoresist layer 610 can be removed by a developing process. The second photoresist layer 610 can be removed by a rinsing process. Figure 6D Stage 8 shows and describes an example of removing the second photoresist layer.

[0063] The method (at 745) removes portions of the under-bump metallization layer. The method may selectively etch portions of the under-bump metallization layer to define under-bump interconnects 109a and 109b. The method (at 745) may perform a solder reflow process to couple a plurality of solder interconnects 106 to a plurality of pillar interconnects 104. The plurality of solder interconnects 106 may be located within cavities (e.g., 209) of the plurality of pillar interconnects 104. Figure 6D Stage 9 shows and describes examples of removing portions of the metallization layer under the bumps and the solder reflow process for multiple solder interconnects.

[0064] The integrated device (e.g., 100) described in this disclosure may be manufactured one at a time, or may be manufactured together as part of one or more wafers and subsequently diced into individual integrated devices.

[0065] Exemplary process for manufacturing a package including an integrated device comprising cavity-containing pillar interconnects.

[0066] In some implementations, manufacturing the package involves several processes. Figure 8 Exemplary steps for providing or manufacturing a package comprising an integrated device including pillar interconnects with cavities are shown. In some implementations, Figure 8 The process can be used to provide or manufacture Figure 4 The packaging component is 400. However, Figure 8 The process can be used to manufacture any package described in this disclosure.

[0067] It should be noted that Figure 8 The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this disclosure.

[0068] like Figure 8 As shown, stage 1 illustrates the state after substrate 402 has been provided. Substrate 402 includes at least one dielectric layer 420, a plurality of interconnects 422, and a solder mask layer 426. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS).

[0069] Phase 2 illustrates the state after the integrated device 100 is coupled to the substrate 402 via multiple pillar interconnects 104 and multiple solder interconnects 106. The integrated device 100 is coupled to multiple interconnects 422 of the substrate 402 via multiple pillar interconnects 104 and multiple solder interconnects 106. A solder reflow process can be used to couple the integrated device 100 to the substrate 402. Figure 5 An example of how the integrated device 100 can be coupled to the substrate 402 is shown. Different implementations may couple different components and / or devices to the substrate 402.

[0070] Phase 3 illustrates the state after an encapsulation layer 408 has been provided (e.g., formed) on substrate 402. Encapsulation layer 408 may encapsulate integrated device 100. Encapsulation layer 408 may include molding materials, resins, and / or epoxy resins. Compression molding, transfer molding, or liquid molding processes may be used to form encapsulation layer 408. Encapsulation layer 408 may be photoetchable. Encapsulation layer 408 may be an encapsulation component.

[0071] Phase 4 illustrates the state after multiple solder interconnects 430 have been coupled to the substrate 402. A solder reflow process can be used to couple the multiple solder interconnects 430 to the substrate 402.

[0072] An exemplary flowchart of a method for manufacturing a package of an integrated device including cavity pillar interconnects.

[0073] In some implementations, manufacturing the package involves several processes. Figure 9 An exemplary flowchart of a method 900 for providing or manufacturing a package including an integrated device comprising cavity-containing pillar interconnects is shown. In some implementations, Figure 9 Method 900 can be used to provide or manufacture the products described in this disclosure. Figure 4 Package 400. However, method 900 can be used to provide or manufacture any package (e.g., 400) described in this disclosure.

[0074] It should be noted that Figure 9 The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some implementations, the order of the processes may be changed or modified.

[0075] The method (at 905) provides a substrate (e.g., 402). The substrate 402 may be supplied by a supplier or manufactured. Different implementations may use different processes to manufacture the substrate 402. Examples of processes that can be used to manufacture the substrate 402 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 402 includes at least one dielectric layer 420, a plurality of interconnects 422, and a solder mask layer 426. The substrate 402 may include an embedded trace substrate (ETS). In some implementations, the substrate may be a core substrate. In some implementations, at least one dielectric layer 420 may include a prepreg layer and / or polyimide. Figure 8 Phase 1 shows and describes an example of providing a substrate.

[0076] This method (at 910) couples an integrated device (e.g., 100) to a first surface of a substrate 402. For example, integrated device 100 may be coupled to a first surface (e.g., the top surface) of substrate 402. Integrated device 100 is coupled to substrate 402 via a plurality of pillar interconnects 104 and a plurality of solder interconnects 106. At least one pillar interconnect includes a cavity. A portion of the solder interconnect may be located within the cavity of the pillar interconnect. A solder reflow process may be used to couple integrated device 100 to substrate 402. Figure 5 An example of how the integrated device 100 can be coupled to the substrate 402 is shown. Figure 8 Phase 2 shows and describes an example of coupling an integrated device to a substrate.

[0077] The method (at 915) forms an encapsulation layer (e.g., 408) on the substrate (e.g., 402). The encapsulation layer 408 may be provided and formed on and / or around the substrate 402 and the integrated device 100. The encapsulation layer 408 may include molding materials, resins, and / or epoxy resins. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 408. The encapsulation layer 408 may be photoetchable. The encapsulation layer 408 may be an encapsulation member. Figure 8 Stage 3 shows and describes an example of forming an encapsulation layer.

[0078] This method (at 920) couples multiple solder interconnects (e.g., 430) to substrate 402. A solder reflow process can be used to couple the multiple solder interconnects 430 to substrate 402. Figure 8 Phase 4 shows and describes an example of coupling solder interconnects to a substrate.

[0079] The packages described in this disclosure (e.g., 400) may be manufactured one at a time, or may be manufactured together (as part of one or more wafers) and subsequently diced into individual packages.

[0080] Exemplary electronic devices

[0081] Figure 10 Various electronic devices are illustrated that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, PoPs, System-in-Packages (SiPs), or System-on-Chip (SoCs). For example, mobile phone device 1002, laptop computer device 1004, fixed-location terminal device 1006, wearable device 1008, or motor vehicle 1010 may include the device 1000 as described herein. Device 1000 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Figure 10The devices 1002, 1004, 1006, and 1008 shown, as well as vehicle 1010, are merely exemplary. Other electronic devices may also feature device 1000, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0082] Figures 1 to 5 , Figures 6A to 6D and / or Figures 7 to 10 One or more of the components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 5 , Figures 6A to 6D and / or Figures 7 to 10 The corresponding descriptions herein are not limited to dies and / or ICs. In some implementations, Figures 1 to 5 , Figures 6A to 6D and / or Figures 7 to 10 The descriptions and their corresponding information can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0083] Note that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0084] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component situated “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be situated above (e.g., above) a first surface of a second component, while a third component can be situated above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. Further note that the term “above,” as used in this application in the context of one component being above another component, can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component over second component" can mean: (1) the first component is over the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10 percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0085] In some implementations, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces (e.g., trace interconnects), vias (e.g., via interconnects), pads (e.g., pad interconnects), pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form the interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the interconnect.

[0086] It should also be noted that the various disclosures contained herein can be described as processes depicted as flowcharts, flow diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations within an operation can be performed in parallel or simultaneously. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0087] Further examples are described below to facilitate understanding of the invention.

[0088] Aspect 1: An integrated device comprising: a die portion. The die portion includes a plurality of pads and a plurality of under-bump metallized interconnects coupled to the plurality of pads. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under-bump metallized interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity.

[0089] Aspect 2: The integrated device according to aspect 1 further includes a plurality of solder interconnects coupled to the plurality of pillar interconnects.

[0090] Aspect 3: The integrated device according to aspect 2, wherein the plurality of solder interconnects includes a first solder interconnect located in the first cavity of the first pillar interconnect.

[0091] Aspect 4: The integrated device according to aspects 1 to 3, wherein the planar cross-section extending through the first cavity of the first pillar interconnect includes an O-shape.

[0092] Aspect 5: The integrated device according to aspects 1 to 4, wherein the first pillar interconnect includes: a first pillar interconnect portion including a first width; and a second pillar interconnect portion including a second width different from the first width.

[0093] Aspect 6: The integrated device according to aspect 5, wherein the first cavity of the first post interconnect is located in the second post interconnect portion.

[0094] Aspect 7: The integrated device according to aspects 1 to 6, wherein the first cavity extends partially through the height of the first post interconnect.

[0095] Aspect 8: The integrated device according to aspects 1 to 7, wherein the first pillar interconnect includes a top hat shape.

[0096] Aspect 9: The integrated device according to aspects 1 to 8, wherein the integrated device includes a flip chip.

[0097] Aspect 10: The integrated device according to aspects 1 to 9, wherein the die portion includes a die substrate; and a plurality of transistors formed in and / or on the die substrate.

[0098] Aspect 11: A package comprising: a substrate and an integrated device coupled to the substrate via a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity.

[0099] Aspect 12: The package according to aspect 11, wherein the plurality of solder interconnects includes a first solder interconnect located in the first cavity of the first pillar interconnect.

[0100] Aspect 13: The package according to aspect 12, wherein the first solder interconnect comprises an intermetallic compound (IMC).

[0101] Aspect 14: The package according to aspects 11 to 13, wherein the planar cross-section extending through the first cavity of the first post interconnect includes an O-shape.

[0102] Aspect 15: The package according to aspects 11 to 14, wherein the first post interconnect includes: a first post interconnect portion including a first width; and a second post interconnect portion including a second width different from the first width.

[0103] Aspect 16: The package according to aspect 15, wherein the first cavity of the first post interconnect is located in the second post interconnect portion.

[0104] Aspect 17: The package according to aspects 11 to 16, wherein the plurality of pillar interconnects are part of the integrated device.

[0105] Aspect 18: The package according to aspects 11 to 17, wherein the first post interconnect includes a top hat shape.

[0106] Aspect 19: The package according to aspects 11 to 18, wherein the package is a part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0107] Aspect 20: A method for manufacturing an integrated device. The method provides a die portion including a plurality of pads and a plurality of under-bump interconnects coupled to the plurality of pads. The method forms a plurality of pillar interconnects over the plurality of under-bump interconnects. Forming the plurality of pillar interconnects includes forming a first pillar interconnect including a first cavity.

[0108] Aspect 21: The method according to aspect 20, wherein forming the plurality of pillar interconnects includes forming and patterning a first photoresist layer on the die portion; forming a first pillar interconnect portion; removing the first photoresist layer; forming and patterning a second photoresist layer on the die portion; and forming a second pillar interconnect portion on the first pillar interconnect portion such that the first cavity is formed in the second pillar interconnect portion.

[0109] Aspect 22: According to the method of aspect 21, forming the plurality of pillar interconnects further includes forming a first solder interconnect over the first cavity of the first pillar interconnect.

[0110] Aspect 23: According to the method of aspect 22, wherein the first solder interconnect is at least partially located in the first cavity of the first post interconnect.

[0111] Aspect 24: The method according to aspects 20 to 23, wherein the first cavity extends partially through the height of the first post interconnect.

[0112] Aspect 25: The method according to aspects 20 to 24, wherein the planar cross-section extending through the first cavity of the first post interconnect includes an O-shape.

[0113] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be exemplary and not to limit the scope of the appended claims. Therefore, the teachings of this disclosure can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated device, the integrated device comprising: a die portion, the die portion comprising: a plurality of pads; and a plurality of under bump metallization interconnects coupled to the plurality of pads; and a plurality of stud interconnects coupled to the plurality of under bump metallization interconnects, wherein the plurality of stud interconnects comprises a first stud interconnect, the first stud interconnect comprising: a first cavity; a first stud interconnect portion comprising a first width of the first stud interconnect portion that is closest to a bottommost portion of the die portion; and a second stud interconnect portion comprising a second width that is less than the first width, the first cavity being located in the second stud interconnect portion; wherein the first width of the first stud interconnect portion is greater than a third width of a first pad of the plurality of pads.

2. The integrated device of claim 1, further comprising a plurality of solder interconnects coupled to the plurality of stud interconnects.

3. The integrated device of claim 2, wherein the plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first stud interconnect.

4. The integrated device of claim 1, wherein a planar cross-section extending through the first cavity of the first stud interconnect comprises an O-shape.

5. The integrated device of claim 1, wherein the first stud interconnect comprises a shape of a top hat.

6. The integrated device of claim 1, wherein the integrated device comprises a flip chip.

7. The integrated device of claim 1, wherein the die portion comprises: a die substrate; and a plurality of transistors formed in and / or on the die substrate.

8. The integrated device of claim 1, further comprising: wherein the first stud interconnect portion is directly coupled to a first under bump metallization interconnect of the plurality of under bump metallization interconnects; and wherein the first under bump metallization interconnect of the plurality of under bump metallization interconnects is coupled to a first pad of the plurality of pads.

9. The integrated device of claim 1, further comprising: wherein the first width of the first stud interconnect portion is greater than a third width of a first pad of the plurality of pads.

10. The integrated device of claim 1, wherein the first cavity extends partially through a height of the first stud interconnect.

11. A package, the package comprising: a substrate; and an integrated device coupled to the substrate by a plurality of stud interconnects and a plurality of solder interconnects, wherein the plurality of stud interconnects comprises a first stud interconnect, the first stud interconnect comprising: a first cavity; a first stud interconnect portion comprising a first width of the first stud interconnect portion that is closest to a bottommost portion of the integrated device; and a second stud interconnect portion comprising a second width that is less than the first width, the first cavity being located in the second stud interconnect portion; a plurality of pads, wherein the first width of the first stud interconnect portion is greater than a third width of a first pad of the plurality of pads.

12. The package of claim 11, wherein the plurality of solder interconnects includes a first solder interconnect located in the first cavity of the first stud interconnect.

13. The package of claim 12, wherein the first solder interconnect includes an intermetallic compound (IMC).

14. The package of claim 11, wherein a planar cross-section extending through the first cavity of the first stud interconnect includes an O-shape.

15. The package of claim 11, wherein the plurality of stud interconnects are part of the integrated device.

16. The package of claim 11, wherein the first stud interconnect includes a shape of a top hat.

17. The package of claim 11, wherein the package is part of a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

18. The package of claim 11, wherein the package is part of a device selected from the group consisting of: a communication device, and a computer.

19. The package of claim 11, further comprising: a plurality of under bump metallization interconnects, wherein the first stud interconnect portion is directly coupled to a first under bump metallization interconnect of the plurality of under bump metallization interconnects; and wherein the first under bump metallization interconnect of the plurality of under bump metallization interconnects is coupled to the first pad of the plurality of pads.

20. A method for manufacturing an integrated device, the method comprising: providing a die portion, the die portion comprising: a plurality of pads; and a plurality of under bump metallization interconnects coupled to the plurality of pads; and forming a plurality of stud interconnects over the plurality of under bump metallization interconnects, wherein forming the plurality of stud interconnects includes forming a first stud interconnect, the first stud interconnect comprising; a first cavity, a first stud interconnect portion including a first width of the first stud interconnect portion closest to a bottom-most portion of the die portion; and a second stud interconnect portion including a second width that is less than the first width, the first cavity located in the second stud interconnect portion; wherein the first width of the first stud interconnect portion is greater than a third width of a first pad of the plurality of pads.

21. The method of claim 20, wherein forming the plurality of stud interconnects includes: forming and patterning a first photoresist layer over the die portion; forming the first stud interconnect portion; removing the first photoresist layer; forming and patterning a second photoresist layer over the die portion; and forming the second solder interconnect portion over the first solder post interconnect portion.

22. The method of claim 21, wherein forming the plurality of stud interconnects further comprises: forming a first solder interconnect over the first cavity of the first solder post interconnect.

23. The method of claim 22, wherein the first solder interconnect is at least partially located in the first cavity of the first solder post interconnect.

24. The method of claim 20, wherein the first cavity extends partially through a height of the first solder post interconnect.

25. The method of claim 20, wherein a planar cross-section extending through the first cavity of the first solder post interconnect comprises an O-shape.

26. The method of claim 20, further comprising: wherein the first solder post interconnect portion is directly coupled to a first under bump metallization interconnect of the plurality of under bump metallization interconnects; and wherein the first under bump metallization interconnect of the plurality of under bump metallization interconnects is coupled to a first pad of the plurality of pads.

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