Method and device for quickly searching for GNSS signals

Abstract

A method and apparatus for performing a fast search for GNSS signals on a GNSS receiver includes the steps of receiving a signal having a known pseudo-random noise code. When the pseudo-random noise code is generated, state information of the code generator is stored. Multiple assumed Dopplers in the GNSS signal are searched simultaneously using multiple NCOs including a Doppler NCO. A search window associated with the received signal is first checked to identify the source of the received signal. After determining whether the source of the received signal can be identified, the state information is loaded into the code generator before a second check of the search window, and so on. The search window is shifted by a full-length PRN code. The loading of the state information allows the search window to be checked sequentially without re-adjusting the fast search module, which speeds up the process of analyzing the received signal.

Description

Technical Field

[0001] The present disclosure relates to a navigation receiver and a method for processing signals, and in particular, to quickly searching for global navigation satellite signals (GNSS) of different systems (e.g., Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), GALILEO satellite system, etc.) and further processing the signals. Background Art

[0002] The Global Navigation Satellite System (GNSS) uses satellites to broadcast radio signals, which are acquired by a receiver. The receiver uses the acquired signal to determine the location of the receiver. Code delay and Doppler shift are often used to search for GNSS signals. The search window S is defined as the number of delays considered while being viewed by the search unit. The simplest method for searching multiple channels uses a component including a code generator, multiple numerically controlled oscillators (NCOs) (including code NCOs (CRNCOs) and intermediate frequency NCOs (IFNCOs)) and correlators. The channels are configured to search for the Doppler shift of a signal, and different code delays need to be set for different channels when the channels are initialized. In order to search for a specific Doppler shift, the channel should be restarted / reset. This method requires a large number of channels, each of which is associated with its own correlator, code generator, CRNCO and IFNCO. Summary of the invention

[0003] The present disclosure generally relates to global navigation satellite systems (GNSS), and more particularly, to receivers for GNSS systems. In one embodiment, a device for rapidly searching for radio navigation signals with known pseudo-random noise (PRN) codes includes an antenna for receiving signals with known PRN codes. A radio frequency path is configured to receive radio signals from the antenna and shift these signals to intermediate frequency signals. A digitally controlled oscillator is configured to output pulses with a period of a PRN element, and an analog-to-digital converter (ADC) is configured to sample the intermediate frequency signal. A digital mixer is configured to receive a signal from the ADC and output a sampled signal at zero frequency. A decimator is configured to receive a sampled signal at zero frequency from the digital mixer. A correlator is configured to calculate the convolution of a shifted array of inputs received from the decimator via a pair of quantization units with a non-shifted array of PRN code elements, and a memory unit is configured to store the result of the value output from the correlator. A code generator is configured to calculate new elements based on pulses output from the digitally controlled oscillator. The intermediate frequency numerically controlled oscillator is configured to output an intermediate frequency for an intermediate frequency signal. The fast search numerically controlled oscillator (FSNCO) outputs a pulse of a preset period. In response to the output pulse of the FSNCO: the extractor is also configured to generate a new output sample, the correlator is also configured to shift the shift array of input samples to include the new output sample, and the correlator is also configured to shift the shift array of PRN code elements to include the current state of the output of the PRN code generator. The correlator is also configured to copy the shifted array of PRN code elements to the non-shifted array of PRN code elements once during S pulses of the numerically controlled oscillator, the correlator is also configured to calculate a new convolution value and a metric of the new convolution value, the corrector is configured to: compare the metric of the new convolution value with the stored result, and, if the new convolution value is greater than the stored result, store the new convolution value instead of the stored result, and the fast search module is configured to: for each S*k pulses once, for at least one value of the stored results, determine the availability of a signal with a known PRN code and parameters of the signal in the received radio signal.

[0004] In one embodiment, the Doppler numerically controlled oscillator (DopNCO) is configured to output the Doppler phase in S pulses of the FSNCO at a time. In this embodiment, at least D-1 digital phase shifters (where D-1 is an even number) rotate the new convolution value to a phase proportional to the phase at the DopNCO output. The memory unit is also configured to store D*S values. In this embodiment, for each pulse of FSNCO, the following operations are performed: in each of the D-1 phase shifters, the value output from the correlator is rotated to a phase proportional to the phase of the DopNCO output to generate D-1 rotated phase convolution results, the obtained D-1 rotated convolution results are added to the previous value in the memory cell configured to store D*S values ​​and the unrotated convolution result is added to the previous value in the memory cell configured to store D*S values, and the obtained D addition results are stored at the same address in the memory, and a metric of the new convolution value is calculated based on the result of adding the rotated convolution result / unrotated convolution result to the previous value in the memory cell configured to store D*S values.

[0005] In one embodiment of the device, at the Kth period of the S pulses, D-1 metrics obtained based on the obtained D-1 rotated convolution results are input to a memory unit configured to store D*S values. Also at the Kth period of the S pulses, the metrics obtained based on the unrotated results are input to a memory unit configured to store D*S values ​​to store the results, and for each S*k pulse at a time, the availability of a signal with a known PRN code and parameters of the signal in the received radio signal is determined.

[0006] In one embodiment of the device, the reload generator stores the state of the code generator in S+1 pulses, and at S*k+1 pulses at the end of the incoherent period, the reload generator loads the stored state of the code generator into the code generator.

[0007] In one embodiment, the apparatus further comprises a coherent counter and a non-coherent counter, wherein the coherent counter sums every S convolution values ​​and, if necessary, the non-coherent counter is used for S and the obtained value is stored in a memory unit configured to store D*S values.

[0008] In one embodiment, the apparatus further includes a control accumulator including N circular shift registers, the N circular shift registers moving forward at a rate of FSNCO, and an input of the control accumulator is set to 0 based on the configuration.

[0009] In one embodiment of the device, the sum estimated during the data sorting includes the results of the Doppler measure during the period S*k, and the Doppler measure for each shift is sorted separately.

[0010] In one embodiment, a method for rapidly searching for radio navigation signals comprises the following steps: receiving a radio signal at an antenna, the radio signal having a known PRN code. Transmitting the radio signal from the antenna to a radio frequency path, which then transmits the signal using an intermediate frequency. Sampling the intermediate frequency signal at an ADC. A digital mixer generates a sampled signal at zero frequency based on the signal received from the ADC. In response to a decimator receiving the sampled signal at zero frequency, a shift array of inputs is transmitted from the decimator. The convolution of the shift array of inputs received from the decimator via a pair of quantization units and a non-shift array of PRN code elements is calculated. The result of the value output from the correlator is stored in a first memory unit. A code generator calculates a new element based on a pulse output from a digitally controlled oscillator. A pulse of a preset period is output from a fast search digitally controlled oscillator. The decimator generates a new output sample based on the pulse of the preset period. The correlator shifts the shift array of input samples to include the new output sample. The correlator also shifts the shift array of PRN code elements to include the current state of the output of the PRN code generator. The correlator also copies the shifted array of PRN code elements to the non-shifted array of PRN code elements once during S pulses of the numerically controlled oscillator. The correlator also calculates a new convolution value and a metric of the new convolution value. The corrector compares the metric of the new convolution value with the stored result, and if the new convolution value is greater than the stored result, the new convolution value is stored instead of the stored result. The fast search module determines the availability of a signal with a known PRN code and parameters of the signal in the received radio signal for at least one value of the stored result for each S*k pulses once.

[0011] In one embodiment, a method for quickly searching for GNSS signals performed on a GNSS receiver includes the following steps: receiving a signal having a known pseudo-random noise code. When generating the pseudo-random noise, state information of the code generator is stored. The pseudo-random noise is associated with the pseudo-random noise code. A search window associated with the received signal is first checked to identify the source of the received signal. After determining whether the source of the received signal can be identified, the state information is loaded into the code generator before a second check of the search window. The loading of the state information allows the search windows to be viewed sequentially without re-adjusting the fast search module, which speeds up the process of analyzing the received signal. In one embodiment, the search window is shifted by the full length PRN code.

[0012] In one embodiment, the received signal is processed by a control accumulator using multiple multiplexed signals in a fast search numerically controlled oscillator frequency. One of the multiple multiplexed signals can be set to zero. This zeroing causes the zeroed signal to be ignored in the analysis of the multiple signals. In one embodiment, the received signal is multiplied by the intermediate frequency before determining whether the source of the signal can be identified. In one embodiment, the rotation angle is added to the received signal. The rotation angle can be based on a Doppler numerically controlled oscillator. The results generated when the search window is checked can be stored in a coherent mode or an incoherent mode. The incoherent mode allows searching for signals with superimposed data.

[0013] In one embodiment, at the end of the incoherent period and when the coherent counter counts K periods of S pulses, all incoherent metrics are added and the result is read by the CPU.

[0014] In one embodiment, at the end of the incoherent period and when the coherent counter counts K periods of S pulses, the availability of a signal with a known PRN code and the signal parameters in the received radio signal is determined in D*S incoherent measurements and the result is read by the CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A block diagram of a navigation receiver is shown;

[0016] Figure 2 Shows Figure 1 Detailed diagram of the quick search module shown in;

[0017] Figure 3 Shows Figure 2 Detailed diagram of the digital mixer and decimator shown in ;

[0018] Figure 4A Shows Figure 2 Detailed diagram of the control counter shown in ;

[0019] Figure 4B Shows the Figure 4A and Figure 2 An example of adjustment of the control counter is shown in;

[0020] Figure 4C Shows the Figure 4A and Figure 2 Additional examples of adjustment of the control counter shown in;

[0021] Figure 4D Shows the Figure 4A and Figure 2 Additional examples of adjustment of the control counter shown in;

[0022] Figure 5 Shows Figure 2 Detailed diagram of the partially parallel correlator shown in ;

[0023] Figure 6 Shows Figure 2 Detailed diagram of the searcher shown in ;

[0024] Fig. 7A Shows Figure 2 Detailed diagram of the control summing unit shown in ;

[0025] Figure 7B Shows Fig. 7A The standard operation of the control summing unit shown in ;

[0026] Figure 7C Shows Fig. 7A The non-accumulating mode of operation of the control accumulation unit shown in FIG.

[0027] Figure 8 Shows Figure 2 Detailed diagram of the corrector shown in ;

[0028] Fig. 9 Shows Figure 6 Detailed diagram of MAX shown in;

[0029] Fig.10 Shows Fig. 9 A flowchart of the operation of the sorting unit shown in;

[0030] Fig.11 Shows Figure 2 Detailed diagram of the packer shown in ;

[0031] Fig.12 Shown by Figure 2 The Doppler NCO generated signal shown in ; and

[0032] Fig.13 It is shown for Figure 1 A flow chart of a method of operation of a navigation receiver is shown in FIG. DETAILED DESCRIPTION

[0033] A method and apparatus for quickly searching for satellite signals includes a receiver that receives a signal transmitted from a global navigation satellite system satellite and processes the signal.

[0034] Figure 1A receiver 110 is shown for receiving and processing satellite signals. In one embodiment, a satellite signal including pseudo-random noise ("PRN") is received by an antenna 100. The received signal passes through an RF path 101(1) to an analog-to-digital converter (ADC) 102(1). The converted signal is transmitted from the ADC 102(1) to a satellite channel 103(1) and a fast search module (FSM) 104(1). The satellite channel 103(1) and the FSM 104(1) receive the digitized signal that is trsnafered to an intermediate frequency. The FSM 104(1) performs a signal search based on the intermediate frequency and a reference code delay. The satellite channel 103(1) processes the digitized signal from the ADC 102(1). It should be noted that multiple groups of RF paths 101(1) to 101(R), ADCs 102(1) to 102(R), satellite channels 103(1) to 103(C), and FSMs 104(1) to 104(F) may be utilized. It should be noted that where multiple similar paths are shown in the figure, only one channel may be described, and the other similar paths should be understood to be configured and operated similarly to the described paths.

[0035] The timing module 105 synchronizes the control of the FSM 104(1) and the satellite channel 103. The timing module 105 counts a preset number of clock pulses and generates an interrupt in a central processing unit (CPU) 106. The CPU 106 controls the timing module 105, the FSM 104 and the satellite channel 103. The CPU 106 processes the information from the FSM 104 and the channel 103 and transmits the data to the user 108 via the communication module 107.

[0036] Figure 2 Shows Figure 1Detailed diagram of FSM 104(1) is shown in FIG. Although only the configuration and operation of FSM 104(1) is described herein, additional fast search modules used in receiver 110 are similarly configured and operated. In one embodiment, FSM 104(1) includes the following components that interact with various signals. FSM 104(1) includes a code rate numerically controlled oscillator (NCO) 201 (referred to as CRNCO), a code generator 202, an intermediate frequency NCO (IFNCO) 204, a reference code (reference pseudo-random noise (PRN) sequence) S203, an extractor 205, a fast search NCO (FSNCO) 206, a divided fast search frequency S207, a quantization unit 208, a quantization unit 209, a partially parallel correlator 210, the number of "units 1" of component I S211, the number of "units 1" of component Q S212, a rotation unit 213, a Doppler NCO (DopNCO) 214, a rotation signal (D ... 2) S215, a searcher 216, and a control counter from signal S217, signal S218 for ending the operation of the delay counter (equal to S403), control counter 219, packer 220, memory unit 221, commutator 222, control accumulator 223, reload generator 224, divider 225, corrector 226, component I related signal S227, component Q related signal S228, signal S229 for ending the operation of the delay counter via the initial unit (equal to S417), signal S230 for ending the operation of the incoherent counter, digital mixer 231, control searcher 232, signal S233 read from the memory unit, signal S234 written to the memory unit, and intermediate frequency signal S235.

[0037] In one embodiment, the CPU 106 controls the following units within the FSM 104: code rate NCO (CRNCO) 201, code generator 202, fast search NCO (FSNCO) 206, quantization unit 208, quantization unit 209, partially parallel correlator 210, Doppler NCO (DopNCO) 214, searcher 216, control counter 219, packer 220, commutator 222, control accumulator 223, reload generator 224, divider 225 and corrector 226.

[0038] In one embodiment, the FSM 104 needs to be initialized before searching for a signal selected by the CPU 106. In one embodiment, the following operations are performed during initialization. The commutator 222 is electrically connected to one of the ADCs 102(1) to 102(R) based on the desired signal to be analyzed. The control accumulator 223 is adjusted as needed. The frequency of the pseudo-random noise generator (PRN) in the CRNCO 201 is set and the divider 225 is adjusted if necessary. The generator code 202 and the reload generator 224 are adjusted if necessary. The intermediate frequency S235 in the oscillator / generator IFNCO 204 is set. The fast search frequency in the oscillator FSNCO 206 is set. The Doppler frequency in the oscillator DopNCO 214 is set. The values ​​of the units 402, 405, and 408 are adjusted in the control counter 219. The settings in the quantizers 208 and 209 are adjusted. And the corrector 226, the packer 220 and the partially parallel correlator 210 are adjusted.

[0039] According to an embodiment, after initialization, the FSM 104 operates as follows. The IFNCO 204, the CRNCO 201, and the FSNCO 206 operate based on the signal from the timing module 105. The IFNCO 204 generates an intermediate frequency signal S235, which is fed to the digital mixer 231. The fast search frequency from the FSNCO 206 is input to the control accumulator 223 and the frequency divider 225. Then, the signal from the selected ADC 102 is fed from the commutator 222 to the control accumulator 223. If necessary, in the control accumulator 223, the input signal is set to 0. The signal from the output of the control accumulator 223 is input to the digital mixer 231. If necessary, the fast search frequency is divided by the frequency divider 225. The frequency divider 225 then outputs the divided fast search frequency signal S207, and the divided fast search frequency signal S207 is input to the extractor 205, the partial parallel correlator 210 and the control counter 219.

[0040] In the digital mixer 231, the signals from the control accumulator 223 and the IFNCO 204 are multiplied and input to the extractor 205. The extractor 205 receives the signals from the digital mixer 231 and accumulates and stores them with the divided fast search frequency S207. The stored signals are input to quantizers 208 and 209. The quantizers 208 and 209 output quantized signals, which are input to the partially parallel correlator 210.

[0041] The oscillator CRNCO 201 generates a code frequency, which is input to the reload generator 224 and the code generator 202. The code generator 202 generates a reference code S203, which is a PRN code. The reload generator 224 is used to reinitialize the code generator 202 when necessary. The reference code signal S203 is input to the partial parallel correlator 210. In one embodiment, the code generator 202 can generate different code types, including multiplexed codes, BOC codes, MBOC codes, memory codes, etc. In one embodiment, the unit 202 includes a frequency code divider and a meander generator for generating codes.

[0042] The divided fast search frequency signal S207 is fed to the input of the control counter 219. The control counter 219 generates control signals S217, S218, S229 and S230. The signal S217 is fed to the control searcher 232, the searcher 216 and the packer 220. The signal S218 is input to the DopNCO 214, the signal S229 is input to the partially parallel correlator 210, and the signal S230 is input to the CPU 106.

[0043] The signal S217 from the control counter includes the following information: delay number S401, coherent counter threshold trigger signal S406, signal S412 to find MAX, signal S413 to end the operation of the non-coherent counter, frequency S420 for the searcher, and signal S421 to start the accumulation process.

[0044] In the partially parallel correlator 210, the signal from the output 208, the signal from the output 209, and the signal S203 are used for correlation with the divided fast search frequency S207. From the partially parallel correlator 210, signals S211 and S212 correlated in time are output.

[0045] The signals S211 and S212 are input to the corrector 226. In the corrector 226, a mathematical operation depending on the correlation time in the partially parallel correlator 210 is generated. From the corrector 226, signals S227 and S228 are output.

[0046] The signal S218 is input to the DopNCO 214. Based on the signal S218, the DopNCO 214 generates a new rotation signal S215 (D...2). The signals S227, S228 and S215 are input to the rotation unit 213. In the rotation unit 213, the signal S215 is used to rotate the signals S227, S228.

[0047] The signals input to the searchers 216 (D) and 216 (2) include signals S217, S233, S234, S227, S228 (eg, S227, S228 output from the rotation units 213 (D) and 213 (2)).

[0048] The control searcher 232 generates a signal S233 when reading from the memory unit 221, and controls the searcher 232 to generate a signal S234 when writing to the memory unit 221. The control searcher 232 transmits information from the memory unit 221 to the searchers 216(1), 216(2), ... 216(D), and communicates with the memory unit 221 via the packetizer 220. The control searcher 232 generates the signals S233 and S234 based on the frequency S420 transmitted by the searcher, and controls the searcher 232 to read the memory unit 221 via the packetizer 220 and write to the memory unit 221 via the packetizer 220.

[0049] The searcher 216 performs coherent and incoherent actions for each delay number S401 using signals S227 and S228 (signals S227 and S228 output from the rotation unit 213), and stores the results in the memory unit 221. The temporary results of the calculation are read from the memory unit 221 via the packer 220, and written to the memory unit 221 via the packer 220. Among all the results of the most recent intervals of the coherent storage and the incoherent storage, the largest result is also selected and saved. The selected result is a metric. The CPU 106 reads the obtained metric from the searcher 216.

[0050] Fig. 7A Shows Figure 2 A detailed diagram of the control accumulation unit 223 is shown in FIG. Fig. 7A The control accumulation unit 223 shown in FIG. 7 includes registers 700(1), 700(2), 700(3) to 700(N) and a switch 701. In one embodiment, the register 700 is a circular shift register.

[0051] In the given example, N=2M. Prior to operation, the CPU 106 writes a value into register 700. The output signal from FSNCO 206 is fed to unit 223. Using a fast search frequency, the value from 700(1) is written to 700(2), the value from 700(2) is written to 700(3), the value from 700(N-1) is additionally written to 700(N), and the value from 700(N) is written to 700(1). The output of register 700(N) is connected to the input of 700(1) and to the control input of switch 701. The output of commutator 222 is fed to the input of switch 701. The output of switch 701 is connected to the input of digital mixer 231. When 0 is available at the output of 700(N), the signal from the output of unit 222 is fed to the output of 701. When 1 is available at the output of 700 (N), the value "0" is fed to the output 701.

[0052] Figure 7B The standard operating mode is shown. The processor 106 writes 0 to all registers 700. The signal from the commutator 222 is input to the control accumulator unit 223. In the standard operating mode, the signal from the input to the output is transmitted without any change. In this mode, the frequency divider 225 passes the frequency FSNCO 206 without dividing the frequency FSNCO 206.

[0053] Figure 7C The process of operating in a non-accumulation mode is shown. In this embodiment, the number of registers 700 is equal to 4, identified as registers 700 (1), 700 (2), 700 (3) and 700 (4). The processor (CPU) 106 writes the following values ​​to registers 700: 700 (1) = 0, 700 (2) = 1, 700 (3) = 0, 700 (4) = 1. As an example, an operation mode is described in which one chip of FSNCO 206 is not present. The signal from the commutator 222 is input to the control accumulation unit 223. The chip using FSNCO 206 sets the input signal to zero. One chip of FSNCO 206 equals 0 at the output, the next chip signal at the output equals the input signal, and so on. In this mode, the divider 225 divides the frequency FSNCO 206 into 2.

[0054] Figure 3 Detailed diagrams of digital mixer 231 and decimator 205 are shown. Digital mixer 231 includes cosine unit 300, sine unit 301, multiplier 302, and multiplier 303. Decimator 205 includes summing unit 304, summing unit 305, register 306, register 307, buffer 308, buffer 309, switch 310, and switch 311.

[0055] The digital mixer 231 shifts the digitized signal through 233 to zero frequency. The frequency IFNCO 204 is input to the digital mixer 231. The frequency IFNCO 204 is input to the cosine unit 300 and the sine unit 301 of the digital mixer 231. The output of the cosine unit 300 is input to the multiplier 302, in which the output of the cosine unit 300 is multiplied by the output of the control accumulation unit 223. The output of the sine unit 301 is input to the multiplier 303, in which the output of the sine unit 301 is multiplied by the output of the control accumulation unit 223. The outputs of the units 302 and 303 are input to the decimator 205.

[0056] The output of unit 302 is input to summing unit 304, where the output of unit 302 is added to the output signal of register 306 through switch 310. The output of unit 303 is input to summing unit 305, where the output of unit 303 is added to the output signal of register 307 through switch 311. The output of unit 304 is input to register 306. The output of unit 305 is input to register 307.

[0057] Over time, the sum of the results from units 304 and 305 is stored in registers 306 and 307. According to signal S207, the values ​​from registers 306 and 307 are written to buffers 308 and 309. According to signal S207, the zero from the output of switch 310 is input to summing unit 304. And according to signal S207, the zero from the output of switch 311 is input to summing unit 305. The output of buffer 308 is fed to the input of quantization unit 208. The output of buffer 309 is fed to the input of quantization unit 209. If necessary, the output of control accumulation unit 223 can be set to zero, so that the outputs of multipliers 302 and 303 are also zero.

[0058] Back to Figure 7B According to the signal S217 , the values ​​of the registers 306 and 307 are equal to 0. The input signal controlling the accumulating unit 223 is transmitted to the output of the extractor 205 , and the value is stored in the registers 306 and 307 .

[0059] Back to Figure 7C , according to signal S217, the values ​​of registers 306 and 307 are equal to 0. Then, the control accumulating unit 223 sets the values ​​of registers 306 and 307 to zero. Therefore, in registers 306 and 307, there are zero values ​​for a certain time. When the setting of the zero value is completed, the value is stored again in registers 306 and 307. Then the process starts again.

[0060] Figure 4A Shows Figure 2 Detailed diagram of control counter 219 shown in . In one embodiment, control counter 219 includes the following components, which interact with various signals, including delay counter 400, delay number S401, threshold delay counter 402, coherent counter 404, threshold coherent delay unit 405, coherent counter threshold trigger signal S406, incoherent counter 407, threshold incoherent delay 408, incoherent counter threshold trigger signal S409, AND gate 410, AND gate 411, search MAX / find MAX signal S412, signal S413 identifying the end of operation of incoherent counter, signal S414 identifying the end of operation of coherent counter, AND gate 415, signal S417 identifying the end of operation of delay counter, start of operation 418, AND gate 419, frequency signal S420 from searcher, and start of accumulation S421.

[0061] During initialization of FSM 104 , CPU 106 starts control counter 219 and allocates threshold delay counter 402 , threshold coherent delay unit 405 , and threshold incoherent delay unit 408 .

[0062] After initialization, the delay counter 400 is set to 0, the coherent counter 404 is set to 0, and the incoherent counter 407 is set to 0. The divided fast search frequency signal S207 is input to the control counter 219. The signal 207 is also input to the delay counter 400, the AND gate 415, and the AND gate 419.

[0063] If S207 is input to the delay counter 400, the current value is incremented by 1. The output signal of the unit 400 is input to the threshold delay counter 402. The output of the unit 402 is connected to the input of the AND gate 415. If the value at the input of the threshold delay counter 402 is equal to the threshold value set by the CPU 106, then: In the case where S207 is input to the unit 415, a signal S417 is generated to end the operation of the delay counter. According to the signal S417, the delay counter 400 takes the value 0.

[0064] The signal S417 ending the operation of the delay counter is input to the delay counter 400, the initial unit 416, the start unit 418 and the partially parallel correlator 210. The delay number signal S401 is the output of the unit 400. The delay number signal S401 is input to the searcher 216. The signal S417 ending the operation of the delay counter is the same as S229.

[0065] Initialization unit 416 blocks the first pulse of signal S417 that ends the operation of the delay counter to maintain zero in units 404 and 407. Such blocking corresponds to the initialization time (see Figure 4B / Figure 4C / Figure 4D ). The signal S417 that ends the operation of the delay counter passes through the initial 416 and then passes through the initial delay counter end signal S403.

[0066] Signal S403 is input to coherent counter 404, AND gate 416 and DopNCO unit 214. The delay counter end signal S403 through the initial module is the same as S218.

[0067] If S403 is input to the coherence counter 404, the current value is incremented by 1. The output of unit 404 is input to the threshold coherence delay 405. The output of unit 405 is connected to the input of AND gate 416. If the value at the input of threshold coherence delay 405 is equal to the threshold value set by CPU 106, then: In case S403 is available at the input of unit 416, a signal S414 is generated to end the coherence counter operation. According to signal S414, coherence counter 404 takes the value 0.

[0068] The signal S414 is input to the coherent counter 404, the incoherent counter 407, and the AND gate 411. The coherent counter threshold trigger signal S406 is output from the unit 405. The signal S406 is input to the searcher 216 and the operation and operation unit 410.

[0069] If S414 is input to the non-coherent counter 407, the current value is incremented by 1. The output signal of unit 407 is input to the threshold non-coherent delay unit 408. The output of unit 408 is connected to the AND gate 411. If the value at the input of the threshold non-coherent delay unit 408 is equal to the threshold value set by the CPU 106: Then, in the case where S414 is input to the unit 411, a signal S413 is generated to end the operation of the non-coherent counter. According to S413, unit 407 takes the value of 0.

[0070] Signal S413 is input to the non-coherent counter 407, the searcher 216, and the CPU 106. Note that signal S413 is the same as S230 fed to the CPU 106. Signal S409 is output from unit 408. Signal S409 is input to AND gates 410 and 411. Signals S406 and S409 are input to AND gate 410. If S406 and S409 are input to unit 410, a signal S412 for searching for MAX is generated.

[0071] Signal S417 is input to start unit 418. The output of unit 418 is input to AND gate 419. The output signal of unit 418 is input to AND gate 419, and AND gate 419 does not allow S207 to pass through AND gate 419 until the first pulse of S417 occurs. That is, the signal output from AND gate 419 occurs after delay counter 400 has counted to the threshold specified in unit 402 and then reset (occurs throughout the cycle of delay counter 400).

[0072] Signal S420 is the output signal of unit 419. Signal S421 is fed to the output of start unit 418. After initialization, S421=1. When the first pulse of signal S417 is input to start unit 418, the value of signal S421 is 1. When the second pulse of signal S417 arrives at unit 418, the value of signal S421 is 0. Both signals S421 and S420 are input to searcher 216.

[0073] The delay counter 400 counts from 0 to S−1, where S−1 is the maximum number programmed in the threshold delay counter 402 .

[0074] The signal S217 from the control counter includes a delay number signal S401, a coherent counter threshold trigger signal S406, a signal S412 for searching for MAX, a signal S413 indicating the end of operation of the non-coherent counter, a signal S420 for identifying the frequency used for the searcher, and a signal S421 indicating the start of accumulation.

[0075] Figure 4B , Figure 4C and Figure 4D The operation diagram of the control counter 219 for three configuration versions is as follows:

[0076] Figure 4B Example 1 is shown, in which: threshold delay counter 402 = 3; threshold coherent delay 405 = 1; and threshold incoherent delay 408 = 1;

[0077] Figure 4C Example 2 is shown, in which: threshold delay counter 402 = 3; threshold coherent delay 405 = 0; and threshold incoherent delay 408 = 2;

[0078] Figure 4D Example 3 is shown in which: threshold delay counter 402=3; threshold coherent delay 405=2; and threshold incoherent delay 408=0.

[0079] Figure 5 Shows Figure 2Detailed diagram of the partially parallel correlator 210 shown in FIG. , the partially parallel correlator 210 includes code shift registers (in scheme C) 500(1), 500(2), 500(3), 500(S), component I shift registers (in scheme I) 501(1), 501(2), 501(3), 501(S), reference code shift registers (in scheme RC) 502(1), 502(2), 502(3), 502(S), component Q shift registers (in scheme Q) 503(1), 503(2), 503(3), 503(S), multiplications 504(1), 504(2), 504(3), 504(S), multiplications 505(1), 505(2), 505(3), 505(S), summing unit 506, summing unit 507, key 508(S), key 509(S).

[0080] In one embodiment, initialization of the partially parallel correlator 210 is initiated by keys 508 and 509 .

[0081] In one embodiment, the partially parallel correlator 210 operates as follows. The reference code signal S203 is a bit number with a value that can be 1 or 0. The quantizers 208 and 209 output the sign of the value fed to the input. The bit number with values ​​0 and 1 is output at the output of the units 208 and 209.

[0082] Signal S207 is input to the partial parallel correlator 210. If signal S207 is available, code shift registers 500(1), 500(2), 500(3) and 500(S) repair the data. Reference code signal S203 is input to code shift register 500(1). Then, the output signal from 500(1) is input to shift register 500(2). The output signal from shift register 500(2) is input to shift register 500(3). The output signal from shift register 500(3) is input to shift register 500(S).

[0083] If S207 exists, the component I shift registers 501(1), 501(2), 501(3) and 501(S) and the component Q shift registers 503(1), 503(2), 503(3) and 503(S) repair the data. The signal output from unit 208 is input to shift register 501(1). Then, the output signal of shift register 501(1) is fed to the input of shift register 501(2). The output signal from the output of shift register 501(2) is fed to the input of shift register 501(3). The output of shift register 501(3) is input to shift register 501(S). The output signal of unit 209 is input to component Q shift register 503(1). Then, the output signal of shift register 503(1) is fed to the input of shift register 503(2). The output signal from the output of shift register 503(2) is fed to the input of shift register 503(3). The output of shift register 503(3) is input to shift register 503(S).

[0084] If S229 (S417) is present, the reference code shift register 502 repairs the data. The output signal of 500 (1) is fed to the input of 502 (1). The output signal of 500 (2) is fed to the input of 502 (2). The output signal of 500 (3) is fed to the input of 502 (3). The output signal of 500 (S) is fed to the input of 502 (S). The value in cell 502 does not change until the next S229 (S417) signal is available.

[0085] In units 500, 501 and 503, the value is shifted according to signal S207. The output signals from 501(1) and 502(1) are input to multiplier 504(1). The output signals from 501(2) and 502(2) are input to multiplier 504(2). Similarly, the output signals from 501(3) and 502(3) are input to multiplier 504(3). The output signals from 501(S) and 502(S) are input to multiplier 504(S). It is worth noting that the output signal of unit 504 is a bit. The values ​​of units 501 and 502 are multiplied in unit 504. The output signal from unit 504 is input to unit 506.

[0086] Some of the high bits of unit 504 are passed through key 508. If necessary, some of the output of unit 504 is not input to unit 506. In one embodiment, whether the output of unit 504 is not input to unit 506 depends on the threshold value written into threshold counter delay 402 by CPU 106.

[0087] The output signals from 503(1) and 502(1) are input to multiplier 505(1). The output signals from 503(2) and 502(2) are input to multiplier 505(2). The output signals from 503(3) and 502(3) are input to multiplier 505(3). The output signals from 503(S) and 502(S) are input to multiplier 505(S). The output signals from each of 505(1), 505(2), 505(3) and 505(S) are each bits. The values ​​of units 503 and 502 are multiplied in unit 505. The output signal from unit 505 is fed to unit 507.

[0088] Some of the high bits of unit 505 are passed through key 509. If necessary, some of the output of unit 505 is not input to unit 507. In one embodiment, whether the output of unit 505 is input to unit 507 depends on the threshold value written into threshold counter delay 402 by CPU 106.

[0089] The number of cells 1 fed from the output of cell 504 is output at the output of cell 506. The number of cells 1 fed from the output of cell 505 is output at the output of cell 507. The sum from the output of cell 506 is connected to the number of "cells 1" for component I S211. And the sum from the output of cell 507 is connected to the number of "cells 1" for component Q S212.

[0090] It should be noted that, in one embodiment, code shift register 500 is a shift array of elements of a PRN code. Component I shift register 501 and component Q shift register Q are shift arrays of input samples. Reference code shift register 502 is a non-shift array of elements of a PRN code. In partial parallel correlator 210, the convolution of shift array 501 and non-shift array 502 is calculated using units 504 and 506, and the result of the convolution is signal S211.

[0091] In the partially parallel correlator 210, the convolution of the shifted array 503 and the non-shifted array 502 is calculated using units 505 and 507, and the result of the convolution is signal S212.

[0092] Figure 8 Shows Figure 2 Detailed diagram of the corrector 226 shown in FIG. Corrector 226 includes X2 multiplier 800, X2 multiplier 801, summing unit 802, summing unit 803, and constant 804. In one embodiment, initialization of corrector 226 occurs as follows. Prior to operation, CPU 106 sets a value in unit 804, and the maximum value of the constant in unit 804 is equal to S.

[0093] In one embodiment, the operation of the corrector 226 occurs as follows. Signal S211 (output of unit 506) is input to the X2 multiplier 800. In the X2 multiplier 800, the input number is multiplied by 2. The output signal from the X2 multiplier 800 is input to the summing unit 802. In the summing unit 802, the constant from the output of unit 804 is subtracted from the value from the output of the X2 multiplier 800. The output of the summing unit 802 is input to the searcher 216 (1) and the rotation unit 213. The output of the summing unit 802 is signal S227.

[0094] Signal S212 (output of unit 507) is input to X2 multiplier 801. In X2 multiplier 801, the input value is multiplied by 2. The output of X2 multiplier 801 is input to constant 803. In constant 803, the constant output from unit 804 is subtracted from the output value of unit 801. The output of unit 803 is input to searcher 216 (1) and rotation unit 213. The output of unit 803 is S228.

[0095] The signal (S211) representing the digital "1" at output 506 is the result of the convolution of 501 and 502, and the mathematically corrected convolved numbers 501 and 502 are sent from the corrector 226 to the output S227.

[0096] The signal (S212) representing the digital "1" at output 507 is the result of convolution 503 and 502, and the mathematically corrected convolved numbers 503 and 502 arrive from the corrector 226 at output S228.

[0097] The following values ​​are used with the identified components when initializing FSM 104. Threshold counter delay 402 is equal to S-1 or less, key 508 and key 509 are on or off, and constant 804 is equal to S or less.

[0098] The expression for the output of corrector 226 is as follows:

[0099] S227 = summation unit (506) * 2 - constant (804); and

[0100] S228 = summing unit (507)*2-constant (804).

[0101] The following two examples show the connections between S227, S228, 402, 508, 509 and 804, and the table shows the values ​​of the outputs and constants and contains descriptions of the different scenarios.

[0102] Example 1.

[0103] Assume S=1023.

[0104] The number of delays processed is S=1023.

[0105] Threshold counter delay 402 = S-1 = 1023-1 = 1022. Counter delay 400 counts from 0 to 1022.

[0106] Constant 804=S=1023.

[0107] 508(S) and 509(S) are turned on.

[0108]

[0109] Example 2.

[0110] Assume S=1023-2=1021.

[0111] The number of delays processed is reduced by 2.

[0112] Threshold counter delay 402 = (S-1)-2 = (1023-1)-2 = 1020. Counter delay 400 counts from 0 to 1020.

[0113] Constant 804=S=1021.

[0114] 508(S)509(S)508(S-1)509(S-1) is disabled. Value 504(S)504(S-1) is not connected to input 508. Value 505(S)505(S-1) is not connected to input 509.

[0115]

[0116] Figure 6 It shows that Figure 2 Detailed diagram of searchers 216(1), 216(2) and 216(D) shown in FIG. In one embodiment, searcher 216 includes components for receiving and outputting various signals, including input correlation signal S601 of component I, input correlation signal S602 of component Q, summing unit 603 of component I, summing unit 604 of component Q; reading component I signal S605, reading component Q signal S606, reading estimated signal S607, switch 608, switch 609, switch 610, estimation calculation unit 611, summing unit for estimation 612, writing component I signal S613, writing component Q signal S614, writing estimated signal S615, switch 616, switch 617, switch 618, output signal S619 of component I, output signal S620 of component Q, estimated output signal S621, MAX 622 and switch 623. Signals S619 and S620 are coherence metrics. Signal S621 is an incoherent metric.

[0117] In one embodiment, the operation of the searcher 216 is as follows. When the searcher 216 interacts with the memory 221, the reading / writing of data is realized via the packetizer 220. In the searcher 216, all operations are performed serially for the signal S401, which is the address of the memory unit 221: S605, S606, S607 are read from the memory 221; units 603 and 604 add the input and read data of components I and Q; 611 estimates the sum of the obtained components I and Q; 612 adds the input and read estimated data; S613, S614, S615 of components I, Q and estimates are written to the memory 221; and 622 selects the maximum estimated value.

[0118] All operations in the searcher 216 are performed according to the signal S420. The control searcher 232 implements control of data processing in the searcher 216. The control searcher 232 generates control for writing / reading data from the memory 221. According to the signal S233 read from the memory, data is read from the memory 221. According to the signal S234 written to the memory, data is written to the memory 221.

[0119] After the above operations, the reset signal S421 is set equal to 1. The reset signal maintains a value of 1 during the first and second cycles of the delay counter 400 .

[0120] During the first cycle of the operation delay counter 400, there is no signal S420. During this time period, the cells 500, 501 and 503 are filled according to the signal S207, and this time period is the initial time (see Figure 4B , Figure 4C and Figure 4D ). According to signal S417, the value from component 500 is rewritten to component 502. In addition, according to signal S207, components 500, 501 and 503 are filled, and the value in component 502 does not change until signal S417 appears. The result of the convolution of units 501, 502, 503 passes through corrector 226 and is input to searcher 216 as signals S227 and S228. Signal S601 is the same as S227, and signal S602 is the same as S228.

[0121] Each value of the signals S601 and S602 corresponds to their delay number S401. In addition, the delay counter 400 operates in a cyclic manner, generating signals S601 and S602 according to the cyclically repeated delay number S401. The input values ​​of the signals S601 and S602 can be processed sequentially for each delay.

[0122] During the second cycle of operating delay counter 400, signal S421 is 1. According to signal S420, signals S601 and S602 are processed sequentially. Component I S605, component Q S606 and estimate S607 for the current delay S401 are read from memory. Signal S605 is fed to unit 608, signal S606 is fed to unit 609, and signal S607 is fed to 610. Since signal S421 is valid, zero is fed to the outputs of units 608, 609, 610.

[0123] The output signal from unit 608 is input to component 603. The output signal from unit 609 is input to component 604. The output signal from unit 610 is input to component 612.

[0124] For the current value S401, signal S601 is input to component 603. For the current value S401, signal S602 is input to component 604. The value of signal S601 and the output of 608 are added in unit 603. The value of signal S602 and the output of unit 609 are added in unit 604. Signal S619 is the output of unit 603. Signal S620 is the output of unit 604.

[0125] At S421=1, the data read from the memory is set to zero, and a new coherent convolution accumulation is started for cells 501, 502, and 503, or a non-coherent convolution accumulation is started if necessary.

[0126] Signals S619 and S620 are input to component 611. The following mathematical operation is performed by component 601:

[0127] Output 611 =√(S619*S619+S620*S620).

[0128] The output value from unit 611 is input to component 623. If S406=0, the output of component 623 is also equal to 0. If S406=1, the output signal from component 611 is input to component 623. The output signal from component 623 is input to component 612. Output 610 and output 623 are added in unit 612. Signal S621 is the output of component 612.

[0129] When S406=1, the incoherent accumulation of the convolution results of components 500, 501 and 503 occurs. Signal S619 enters the input of component 616. Signal S620 enters the input of component 617. If S406 is equal to "1", outputs 616 and 617 are set to "0". If S406 is equal to 0, signal S619 is fed to the output of component 616, and S620 is fed to the output of component 617. Signal S613 is the output of component 616. Signal S614 is the output of component 617. Signals S613 and S614 are written to memory 221 via packer 220. If S406=1, the coherent accumulation is set to zero for convolutions 501, 502, and (if S406=1, the coherent accumulation is set to zero for convolutions 501 502 503). At the next cycle of the delay counter 400, both signals S605 and S606 are equal to 0, ie the components I and Q are equal to 0, and the coherent accumulation of the convolution results in the units 501, 502 and 503 is restarted.

[0130] Signal S621 is input to element 618. If S412=1, the output value of element 618 is equal to 0. If S412=0, S621 is fed to the output of element 618. Signal S615 is the output of element 618. Signal S615 is written to memory 221 via packetizer 220.

[0131] If S412=1, then for convolutions 501, 502, and 503, the incoherent accumulation is set to zero (if S412=1, then for convolutions 501, 502, 503, the incoherent accumulation is set to zero). In the next cycle of delay counter 400, signal S607=0, that is, the evaluation unit is equal to 0, and the incoherent accumulation of the convolution results in units 501, 502, and 503 is restarted.

[0132] For the current value of the delay number S401 , signals S613 , S614 , and S615 are written to the memory 221 .

[0133] For each delay number S401, the signal S601 is added with the value S605 from the memory and stored in the memory as signal S613. During the entire operation cycle of the coherent counter 404, the signal S601 is stored.

[0134] For each delay number S401, the signal S602 is added with the value S606 from the memory and stored in the memory as signal S614. During the entire operation cycle of the coherent counter 404, the signal S602 is stored.

[0135] The values ​​of signals S619 and S620 are calculated for each delay number S401 at the output of unit 611. For each cycle of coherent counter 404, the output value from unit 611 is summed with the value from memory 610, which is stored during the operation cycle of incoherent counter 407.

[0136] For each delay number S401 at the end of the operation of the coherent counter 404 , the signals S613 and S614 written to the memory 221 are set to 0 according to S406 .

[0137] For each delay number S401 at the end of the operation of the non-coherent counter 407 , the signal S615 written to the memory 221 is set to 0 according to S412 .

[0138] For each delay number S401 , if S412 is available at the end of the operation of the incoherent counter 407 , the signals S619 , S620 , S621 , the results of the coherent and incoherent convolutions 501 , 502 and 503 are fed to a unit MAX 622 .

[0139] Fig. 9 Shows Figure 6 A detailed diagram of the MAX 622 is shown in FIG. The following signals are received by the MAX 622: output of component I S619, output of component Q S620, estimated output S621, delay number S401, find MAX S412, signal to end operation of the non-coherent counter S413, searcher frequency S420.

[0140] MAX 622 includes components for transmitting and receiving various signals, including: controlling MAX 900, data 901(1)...901(M), buffers 902(1)...902(M) for sorted data, summing unit 903, register 904, signal S905 indicating that search MAX / find MAX is in progress, signal S906 indicating that search MAX has ended, buffer 907, signal indicating search result for a single delay, signals S909(1), S909(2), S909(3),...S909(M) for sorting data, AND gate 910, and sorting signal S911.

[0141] In one embodiment, MAX 622 operates as follows: MAX 622 is a sorting device that sorts input data during operation of component 407, and the sorted data is stored and read by CPU 106 after the operation cycle of component 407 is completed. At initialization, 901, 902, 904 and 907 are all set equal to zero.

[0142] In one embodiment, the following signals are input to MAX 622: output S619 of component I, output S620 of component Q, output S621 of the estimation unit, delay number S401, signal S412 indicating search for MAX, signal S413 indicating the end of operation of the non-coherent counter, signal S420 identifying the searcher frequency.

[0143] Signals S412 and S420 are input to component 910. If S412 and S420 are equal to 1 (signal is available), the output of unit 910 is equal to 1 (signal is available). The output of unit 910 is the same as signal S911. Signal S911 is input to control MAX 900.

[0144] Signals S619, S620 and S621 are generated with each delay number S401 in MAX 622, and are derived within the operation of non-coherent counter 407. Search result S908 for a single delay includes signals: S401, S619, S620 and S621.

[0145] The following signals are input to the control MAX 900: output S619 of component I, output S620 of component Q, output S621 of the estimated signal, delay number S401, ordered signal 911, and signal S413 indicating the end of operation of the non-coherent counter.

[0146] When input S911 is input to control MAX 900, signal S908 is sorted for each signal S401. Sorting S908 is implemented using signal S621. Sorting lasts for the entire cycle of operating non-coherent counter 407. Signal S909 is the sorted value S908. Signal S909 from unit 900 is input to unit 901 (1), 901 (2), 901 (3), ..., 901 (M) and stored in unit 901 (1), 901 (2), 901 (3), ..., 901 (M). The number of sorted values ​​is M. When sorting S908 ends, if necessary, the value in unit 901 is updated.

[0147] When the signal S413 confirming the end of the operation on the non-coherent counter 407 is detected, the control MAX 900 waits for the sorting end signal S908 for the last value of S401. When the sorting is completed, the signal S906 is output. The sorted value S909 is written to the data 901 (1), 901 (2), 901 (3), ... 901 (M).

[0148] Signal S906 from control MAX 900 is input to the following components: buffers 902(1), 902(2), 902(3), ..., 902(M), register 904, and buffer 907 for sorted data. After the sorting is completed, the value from cell 901 is written to buffers 902(1), 902(2), 902(3), ..., 902(M) according to signal S906. According to signal S906, the value in cell 901 is set to 0.

[0149] The sequencing continues for the next operation cycle of the non-coherent counter 407. The data 902 is stored until the next signal S906 is received. The CPU 106 reads the values ​​from 902(1), 902(2), 902(3), ... 902(M).

[0150] The signal S905 at the output of the unit 900 is identical to the signal S911 .

[0151] The signal S621 is input to the adder 903. The output of the register 904 is input to the summing unit 903 and the buffer 907. The signal S621 and the output signal of the unit 904 are added in the unit 903. The output of the unit 903 is fed to the input of the unit 904. If S905 (S911) is available, the sum of the S621 values ​​for each delay number S401 is stored in the unit 904 during the operation of the non-coherent counter 407.

[0152] According to signal S906, the stored sum S621 from register 904 is written to unit 907 and the value in register 904 is set to 0. When the next operation cycle of the non-coherent counter 407 starts and the first signal S911 appears, the input value of unit 904 is set to 0. If signal S420 is available, the sum of the non-coherent values ​​for each signal S401 is stored in register 904 during the operation of signal S412=1. The value from buffer 907 is read by CPU 106.

[0153] Fig.10 A flow chart of a method for sorting search results for controlling a single delay in a MAX 900 is shown, wherein the method begins at a start operation 1001. A sort signal is generated at a generate signal sort 1002, and conditions 1003(1), 1003(2), 1003(3), ... 1003(M) are checked and operations 1004(1), 1004(2), 1004(3), ... 1004(M) are performed based on the conditions.

[0154] In one embodiment, the operation of sequencing the units in the control MAX 900 is based on Fig.10The method is carried out as follows.

[0155] If signal S911 is detected, data sorting in MAX 900 is started. Data sorting is performed based on output signal S621 of the estimation unit. Signal S621 is the input estimation. Search result S908 for a single delay includes signals: S401, S619, S620, and S621. Estimation 1 is signal S621 from data 901(1). Estimation 2 is S621 from data 901(2), and estimation 3 is S621 from data 901(3). Therefore, estimation M is signal S621 from data 901(M).

[0156] During initialization, cell 901 is set to 0. Once FSM 104 has been initialized, a signal is input to start at start 1001. The flowchart proceeds from step 1001 to step 1002. At step 1002, the method analyzes signal S911. If S911=0, the flowchart loops to step 1001 and then returns to cell 1002. If S911=1, the flowchart proceeds to 1003(1).

[0157] At step 1003(1), the condition "input estimate is greater than estimate 1" is analyzed. If the condition is not met, the method proceeds to step 1003(2). If the condition in step 1003(1) is met, the following operations are performed: write data 901(M-1) to data 901(M); write data 901(2) to data 901(3); write data 901(1) to data 901(2); write S908 to data 901(1); and then the method returns to the start 1001.

[0158] At step 1003(2), the condition "input estimate is greater than estimate 2" is analyzed. If condition 1003(2) is not satisfied, the method proceeds to step 1003(3). If 1003(2) is satisfied, the following operations are performed: data 901(M-1) is written to data 901(M); data 901(2) is written to data 901(3); S908 is written to data 901(2); data 901(1) remains unchanged; and the method then returns to the start 1001.

[0159] At step 1003(3), the condition "input estimate is greater than estimate 3" is analyzed. If condition 1003(3) is not met, the method proceeds to step 1003(4). If condition 1003(3) is met, the following operations are performed: data 901(M-1) is written to data 901(M); S908 is written to data 901(3); data 901(2) remains unchanged; data 901(1) remains unchanged; and the method then returns to start 1001.

[0160] At step 1003(M), the condition "input estimate is greater than estimate M" is analyzed. If condition 1003(M) is not met, the method proceeds to start 1001. If condition 1003(M) is met, the following operations are performed: S908 is written to data 901(M); data 901(3) is unchanged; data 901(2) is unchanged; data 901(1) is unchanged; and then the method returns to start 1001.

[0161] Fig.11 Shows Figure 2 Detailed diagram of packetizer 220 shown in . In one embodiment, packetizer 220 includes components that send and receive various signals, including data unpack 1100, address S1101, read data S1102, read S1103, write S1104, write data S1105 and pack data 1106.

[0162] In one embodiment, the packager 220 combines Fig.11 and Figure 2 The operation is performed as described. In the process of performing a signal search in combination with DopNCO 214, rotation unit 213 (2) ... 213 (D) and searcher 216 (1), 216 (2), ... 216 (D), the obtained result is written into memory 221 via packer 220 and read from memory 221 via packer 220. Using signal S401 as address S1101, signals S613, S614 and S615 pass through data packer 1106 and are written into memory 221 as one word. Write data S1105 includes data written into memory unit 221 in a similar manner.

[0163] Using signal S401 as address S1101, data is read as one word from memory 221 (or similarly read signal read data S1102). Signal S1102 through data unpacking 1100 is unpacked to generate signals S605, S606, and S607, which are then transmitted to searcher 216.

[0164] The result of the operation of the searcher 216 is signals S613, S614, and S615, which are written to the memory 221 at address S1101. The number of bits in the signals S613, S614, and S615 may exceed the number of bits in the word write data S1105. As a result, the signals S613, S614, and S615 may be packaged in different ways.

[0165] For example, there are integers at the input of the packer 220, but in the packer 220 the integers are converted to a floating point format, where a floating point number is a mantissa and an exponent, with all numbers having a common exponent. The mantissa for each number is reserved / different, but the exponent is common. The exponent is selected so that all high-order digits are within the mantissa.

[0166] The signals S615(1), S615(2), ... S615(D) from the outputs of the searchers 216(1), 216(2), ... 216(D) are combined by a common index. The signals S613 and S614 from the outputs of the searchers 216(1), 216(2), ... 216(D) are also combined by a common index. The mantissas and exponents of the signals S615, S613 and S614 obtained during data packing are fed to the output of the data packer 1106. In the data packer 1100, the data read from the memory is unpacked in consideration of the mantissas, exponents and operation mode of the packer 220.

[0167] In one embodiment, the packager 220 is initialized when the CPU 106 initiates operation of the packager 220. In one embodiment, the packager 220 operates as follows.

[0168] S401 is input to the packetizer 220. Signal S1101 is the same as signal S401. Signal S1101 is input to the memory unit 221 as an address. Signal S1102 is input to the data depacketization 1100 of the data read from the memory 221. In the memory unit 221, S1105 is input as write data from the unit 1106.

[0169] Signal S233(1) is input to packetizer 220. Signal S1103 read is identical to signal S233. S1103 is input to memory cell 221 as a read. If signal S233 is detected, data is read from memory cell 221 at the address identified by signal S1101, and signal S1102 is entered into the input of cell 1100 where the data is unpacked. These signals are input from data unpacking 1100 to: searcher 216(1), searcher 216(1) receives signals S605(1), S606(1) and S607(1); searcher 216(2), searcher 216(2) receives signals S605(2), S606(2) and S607(2); and searcher 216(D), searcher 216(D) receives signals S605(D), S606(D) and S607(D).

[0170] The signal S234 (1) is input to the packetizer 220. The signal S1104 to be written is the same as the signal S234. The signal S1104 is input to the memory 221 as written.

[0171] In data packet 1106, the input signals are packaged as follows: signals S613(1), S614(1) and S615(1) are output from searcher 216(1); signals S613(2), S614(2) and S615(2) are output from searcher 216(2); and signals S613(D), S614(D) and S615(D) are output from searcher 216(D).

[0172] If the signal S234 is available, the data write data S1105 packed in 1106 is written (write data S1105) to the memory 221 at the address S1101.

[0173] Depending on the searcher 216 mode and the number of Doppler NCOs, there are different packing and unpacking for storing the temporary data in unit 221 .

[0174] Here are some examples:

[0175] 1) Condition: Unit 405=0, unit 408=0.

[0176] Result: In this case, the data from signals S613, S614, S615 do not need to be saved in the memory 221.

[0177] 2) Condition: Unit 405 is greater than 0, unit 408 = 0.

[0178] Result: In this case, the data from signal S615 does not need to be saved in memory 221. Only the data from signals S613 and S614 are saved in memory 221.

[0179] 3) Condition: The capacity of signal S613 and signal S614 has a higher priority than the capacity of signal S615.

[0180] Result: To pack the data from signal S613 and signal S614, the low exponent and high mantissa are used. For signal S615, the high exponent and low mantissa are saved.

[0181] 4) Condition: The capacity of signal S615 has a higher priority than the capacities of signal S613 and signal S614.

[0182] Result: To pack the data from signal S615, the low exponent and high mantissa are used. For signal S613 and signal S614, the high exponent and low mantissa are saved.

[0183] 5) Condition: In memory 221, there is enough space for the values ​​of signals S615, S613 and S614.

[0184] Result: Signals S615 , S613 , and S614 are written to the memory 221 .

[0185] Fig.12 Shows Figure 2 Detailed diagram of Doppler NCO 214 is shown in FIG. Doppler NCO 214 generates rotation signals S215(D), ... S215(3), S235, S215(2) ... S215(D-1). Each rotation signal S215 is used to generate a left Doppler frequency or a right Doppler frequency.

[0186] The intermediate frequency S235 is used as the center Doppler frequency. The right Doppler frequency 1 generates S215(2), and the left Doppler frequency 1 is generated in a mirrored manner using signal S215(3). The right Doppler frequency D / 2 generates signal S215(D-1), and the left Doppler frequency D / 2 is generated in a mirrored manner using S215(D-1).

[0187] In FSM 104, Doppler frequencies are generated in steps of Fdop, and include: center Doppler; left Doppler 1; right Doppler 1; left Doppler D / 2; and right Doppler D / 2.

[0188] Considering the S length of the shift registers 500, 501, 502, 503 and the 402 unit set by the CPU 106, the left Doppler frequency (D / 2...1) and right Doppler frequency (D / 2...1) phase changes can be obtained by S218 (equal to S403). The calculation expression of Fdop is as follows.

[0189] Fdop=(F IF / S)*d[N-1:0] / 2 N .

[0190] Among them: F IF is the intermediate frequency S235; S is the length of the shift registers 500, 501, 502, 503 (the delay counter 400 counts from 0 to S-1); and N is the number of bits of the Doppler NCO phase; d[N-1:0] is the number written to the Doppler NCO 214.

[0191] The signal S215 from the output of the Doppler NCO 214 is input to the rotation unit 213. The signal S227 of the component I and the signal S228 of the component Q are input to the rotation unit 213. In each rotation unit 213, the signals S227 and S228 are rotated in phase at an angle set by S215. Its own rotation signal S215 (D ... 2) is generated for the left Doppler (D / 2) ... (1) and the right Doppler (D / 2) ... (1), and S227 and S228 are rotated in phase in different ways.

[0192] In unit 213 (D), signals S227 and S228 are rotated in phase at frequency left Doppler D / 2 (using S215 (D)) and fed to the input of searcher 216 (D).

[0193] In unit 213 (D-1), signals S227 and S228 are rotated in phase at frequency right Doppler D / 2 (using S215 (D-1)) and fed to the input of searcher 216 (D-1).

[0194] In unit 213 ( 3 ) signals S227 and S228 are rotated in phase at frequency left Doppler 1 (using S215 ( 3 )) and fed to the input of searcher 216 ( 3 ).

[0195] In unit 213 ( 2 ) , signals S227 and S228 are rotated in phase at frequency right Doppler 1 (using S215 ( 2 ) ) and fed to the input of searcher 216 ( 2 ) .

[0196] Signals S227 and S228 are fed to the input of searcher 216(1) at intermediate frequency S235.

[0197] The operation of the shift registers 500, 501, 502 and 503 and the reload generator 224 will now be explained using an example including a plurality of tables showing values ​​at different points in time. Assuming S=4, code length=12, the generated frequency CRNCO 201 is equal to the frequency of FSNCO 206. The state of the code generator 202 is stored as the 5th chip of FSNCO 206 and uploaded to the 13th chip of FSNCO 206. Table rows 500, 501 / 503 and 502 show the chip numbers of the code chips generated by the code generator 202 during initialization and during the step of performing detection of the signal.

[0198] Initialization of 500, 501, and 503

[0199]

[0200] Step 1: Search the code for the chip number with reference code 1 2 3 4

[0201]

[0202] Step 2: Store the reference code 1 2 3 4 + 5 6 7 8

[0203]

[0204] Step 3: Store the reference code 1 2 3 4+5 6 7 8+9 10 11 12

[0205]

[0206] Step 4: Search for the chip number with reference code 5 6 7 8

[0207]

[0208] Step 5: Store the reference code 5 6 7 8+9 10 11 12

[0209]

[0210] Step 6: Store the reference code 5 6 7 8+9 10 11 12+1 2 3 4

[0211]

[0212] Step 7: Search the chip number code for reference code 9 10 11 12

[0213]

[0214] Step 8: Store the reference code 9 10 11 12+1 2 3 4

[0215]

[0216] Step 9: Store the reference code 9 10 11 12+1 2 3 4+4 5 6 7

[0217]

[0218] The table for step 9 shows that the signal is detected (steps 4 to 6) for the sum of the convolution results of registers 501, 502, 503 for the generated chips FSNCO 206 and CRNCO 201 numbered 18 22 26. The reference code for the 5th code chip generated by the code generator 202 is matched.

[0219] Figure 2The capabilities of the FSM 104 shown in include the following. In operation using the FSM 104, a sliding window / search window S is available that determines the number of code delays that are viewed simultaneously.

[0220] In order to increase the sensitivity of the search or in case of a code length greater than S, it is necessary to increase the search time by a factor of k. The search time may increase due to coherent accumulation. An increase in the accumulation time is also possible when information symbols are available which are enhanced / overlapped on the code by non-coherent accumulation.

[0221] If the code length is greater than S, the reload generator 234 may also be used and after operation of the start FSM 104, the sliding window / search window S is moved along the entire code length and metrics for all delays may be obtained.

[0222] Different delay numbers can be set for one CODE chip using the fast search NCO 206. For example, one GPSCA chip uses two half chips, and the frequency fast search NCO 206 is twice that of the CRNCO 201.

[0223] The multiplexed code is used as at least two chip-by-chip codes. Using the fast search NCO 206, the control accumulation unit 223 and the frequency divider 225, one code can be sent to the search mechanism and the other code is set to zero in the input signal. The Doppler NCO 214 and the rotation unit 213 allow results for multiple Doppler frequencies to be obtained within the search window S.

[0224] Different operation modes of the packer 220 allow to select a preferred value: component I or component Q, or an estimate during data packing / unpacking. At the end of the search period S*k, when the metrics are sorted, all the estimates of S are added.

[0225] Using FSM 104, a CSK modulated signal can be received. For example, in the process of receiving GPS CA signals using half-chip CODE, the unit quickly searches the frequency of NCO 206 twice the frequency of CRNCO 201, the data is coherently accumulated within 2 milliseconds, and S=1023, the threshold incoherence 408 is set to 0. In this case, during the 4 cycles of the operation delay counter 400 for each S, the convolution results of all registers 501, 502 and 503 are coherently stored, and at the 4th cycle unit, the MAX 622 sorts the metrics.

[0226] It should be noted that the reload generator 224 remembers the state of the code generator 202 at the 1023+1 chip of the fast search NCO 206 and records the stored state of the unit 202 so that the code generator can immediately start from this state to enter / reach the 1023*4+1 chip of the fast search NCO 206. The setting data allows viewing of 2046 GPS CA half chip CODEs without re-adjusting the FSM 104.

[0227] Fig.13 A flow chart of a method 1300 for rapidly searching for global navigation satellite system signals according to an embodiment is depicted. In one embodiment, using Figure 1 1300 is performed by the navigation receiver 110 shown in . At step 1302, a signal is received at a receiver. The signal has a known pseudo-random noise code. At step 1304, when pseudo-random noise is generated by a code generator, the state information of the code generator is stored. In one embodiment, the state information is information related to the code generator, and it is necessary to input the information into the code generator to generate the same pseudo-random noise as previously generated. In one embodiment, the pseudo-random noise generated by the code generator is associated with the pseudo-random noise code of the signal. At step 1306, the search window associated with the received signal is checked for the first time. In one embodiment, the search window includes a string of data obtained from the received signal. As described above, the check is to try to identify the source of the received signal (that is, the satellite that transmits the received signal). At step 1308, it is determined whether the source of the received signal can be identified. After the source is identified, the information can be used to determine the position of the receiver. At step 1310, before checking the search window a second time in response to the determination, the state information previously stored in step 1304 is loaded into the code generator. Loading the state information into the code generator allows the search window to be checked sequentially without re-adjusting the FSM 104. In one embodiment, the received signal is processed by a control accumulator using multiple multiplexed signals at the frequency of the fast search numerically controlled oscillator. One of the multiple multiplexed signals can be set to zero. Setting one of the signals to zero causes the zeroed signal to be ignored in the analysis of the multiple signals. In one embodiment, the received signal is multiplied by the intermediate frequency before the determination in step 1308. In one embodiment, a rotation angle is added to the received signal. The rotation angle can be based on a Doppler numerically controlled oscillator. The results generated when checking the search window can be stored in a coherent mode or an incoherent mode. The incoherent mode allows searching for signals with superimposed data.

[0228] The foregoing detailed description is to be understood as being illustrative and exemplary in all respects, rather than restrictive, and the scope of the inventive concept disclosed herein is not to be determined from the detailed description, but is to be determined from the claims as interpreted, to the full extent permitted by patent law. It should be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concept, and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept. Various other feature combinations may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept.

Claims

1. A device for rapidly searching for a radio navigation signal having a known pseudo-random noise code, the device comprising: an antenna configured to receive a radio signal having a known pseudo-random noise code; a radio frequency path configured to receive a radio signal from the antenna and shift the radio signal to an intermediate frequency signal; a numerically controlled oscillator configured to output pulses having a period of a pseudo-random noise element; an analog-to-digital converter, the analog-to-digital converter being configured to sample the intermediate frequency signal; a digital mixer configured to receive a signal from the analog-to-digital converter and output a sampled signal at zero frequency; a decimator configured to receive a sampled signal at the zero frequency from the digital mixer; a correlator configured to compute a convolution of a shifted array of inputs received from the decimator via a pair of quantization units and a non-shifted array of pseudo-random noise code elements; a memory unit configured to store a result of a value output from the correlator; a code generator configured to calculate a new element based on the pulses output from the numerically controlled oscillator; an intermediate frequency digitally controlled oscillator, the intermediate frequency digitally controlled oscillator being configured to output an intermediate frequency for the intermediate frequency signal; as well as A fast search digitally controlled oscillator is provided, wherein the fast search digitally controlled oscillator outputs a pulse of a preset period, wherein in response to the pulse outputted by the fast search digitally controlled oscillator: The decimator is further configured to generate new output samples; The correlator is further configured to shift the shifted array of input samples to include the new output samples; The correlator is further configured to shift the shift array of pseudorandom noise code elements to include a current state of an output of the pseudorandom noise code generator; The correlator is further configured to copy the shifted array of pseudorandom noise code elements once to a non-shifted array of pseudorandom noise code elements during S pulses of the fast search numerically controlled oscillator; The correlator is further configured to calculate a new convolution value and a coherence measure of the new convolution value; The corrector is configured to compare the coherence measure of the new convolution value with the stored result and, if the new convolution value is greater than the stored result, store the new convolution value in place of the stored result; and The fast search module is configured to determine the availability of a signal having a known pseudo-random noise code and parameters of the signal in the received radio signal for at least one value of the stored results for every S*k pulses of the fast search numerically controlled oscillator, wherein S*k is a search period, S in the search period is a search window, and k in the search period is a multiplier.

2. The device according to claim 1, further comprising: a Doppler numerically controlled oscillator configured to output the Doppler phases of S pulses of the fast search numerically controlled oscillator at a time; at least D-1 digital phase shifters, wherein D-1 is an even number, the at least D-1 digital phase shifters rotate the new convolution value to a phase proportional to the phase at the output of the Doppler numerically controlled oscillator; The memory unit is further configured to store D*S values; Wherein, for each pulse of the fast search numerically controlled oscillator, the following operations are performed: In each of D-1 phase shifters, rotating the value output from the correlator into a phase proportional to the phase output by the Doppler numerically controlled oscillator to generate D-1 rotated phase convolution results; Adding the obtained D-1 rotated convolution results to the previous value in the memory unit configured to store D*S values ​​and adding the unrotated convolution result to the previous value in the memory unit configured to store D*S values, and storing the obtained D added results at the same address in the memory; and Coherence metrics of new D convolution values ​​are calculated according to the result of adding the rotated convolution result / the unrotated convolution result and the previous value in the memory unit configured to store D*S values.

3. The device according to claim 2, wherein: At the Kth period of the S pulses, the availability of a signal with a known pseudo-random noise code and parameters of the signal in the received radio signal in the D*S coherence metrics is determined.

4. The device according to claim 1, further comprising: A reload generator stores the state of the code generator and loads the stored state of the code generator into the code generator at S*k+1 pulses at the end of the incoherent period.

5. The device according to claim 1, further comprising: Coherence counter; as well as Non-coherent counter, wherein the coherent counter counts K periods of S pulses, and the incoherent counter is capable of counting periods of the coherent counter, wherein at the last S pulses before the incoherent counter is incremented, each D coherent measurement is converted into a value to be added to the D incoherent measurements, and the updated incoherent measurements and the obtained values ​​are stored in the memory unit.

6. The device according to claim 1, further comprising: A control accumulator includes N circular shift registers that move forward at the rate of the fast search numerically controlled oscillator, and an input of the control accumulator is set to zero based on a configuration.

7. The device according to claim 1, wherein: The sum estimated during data sorting includes the results of the Doppler measures during the period S*k, and the Doppler measures for each offset are sorted separately.

8. The device according to claim 5, wherein: When the incoherent period ends and when the coherent counter counts K periods of S pulses, the fast search module individually detects / sorts multiple maximum values ​​among the S*D incoherent metrics for each Doppler frequency, and saves the multiple maximum values, which are read by the CPU. The saved values ​​include incoherent metrics, coherent metrics and delay numbers.

9. The device according to claim 5, wherein: At the end of the incoherent period and when the coherent counter counts K periods of S pulses, all incoherent metrics are added and the result obtained by adding all incoherent metrics is read by the CPU.

10. A method for rapidly searching for a radio navigation signal having a known pseudo-random noise code, the method comprising: receiving a radio signal at an antenna, the radio signal having a known pseudo-random noise code; transmitting the radio signal from the antenna to a radio frequency path; transmitting the signal from the radio frequency path using an intermediate frequency signal; Sampling the intermediate frequency signal at an analog-to-digital converter, the sampling being performed at a period of a pseudo-random noise element of a pulse output from a digitally controlled oscillator; generating, by a digital mixer, a sampled signal at zero frequency based on a signal received from the analog-to-digital converter; in response to the decimator receiving the sampled signal at the zero frequency, transmitting an output from the decimator to the shift array of inputs; computing, at a correlator, a convolution of a shifted array of the input received from the decimator via a pair of quantization units and a non-shifted array of pseudo-random noise code elements; storing a result of the value output from the correlator in a first memory unit; At the code generator, new elements are calculated based on the pulses output from the digitally controlled oscillator; Outputting pulses of a preset period from a fast search digitally controlled oscillator; The extractor generates new output samples based on the pulses of the preset period; shifting, by the correlator, a shifted array of input samples to include the new output samples; shifting, by the correlator, a shifted array of pseudorandom noise code elements to include a current state of an output of a pseudorandom noise code generator; The correlator copies the shifted array of pseudo-random noise code elements to the non-shifted array of pseudo-random noise code elements once during S pulses of the numerically controlled oscillator; The correlator calculates a new convolution value and a coherent metric / incoherent metric of the new convolution value; comparing, by a corrector, a metric based on the calculated incoherent metric value with the stored result and storing, in place of the stored result, the new convolution value if the new metric value is greater than the stored result; as well as The fast search module determines the availability of a signal having a known pseudo-random noise code and parameters of the signal in the received radio signal for every S*k pulses of a fast search of the NCO for at least one value of the stored results, wherein S*k is a search period, S in the search period is a search window, and k in the search period is a multiplier.

11. The method according to claim 10, further comprising: Outputting the Doppler phases of S pulses of the fast search digitally controlled oscillator at one time from the Doppler digitally controlled oscillator; Rotating the new convolution value to a phase proportional to the phase at the output of the Doppler numerically controlled oscillator by at least D-1 digital phase shifters; Storing D*S values ​​in the memory cells; For each pulse of the fast search numerically controlled oscillator, in each of D-1 phase shifters, rotating the value output from the correlator to a phase proportional to the phase output by the Doppler NCO to generate D-1 rotated phase convolution results; For each pulse of the fast search numerically controlled oscillator, in the memory unit, the obtained D-1 rotated convolution results are added to the previous value in the memory unit and the unrotated convolution result is added to the previous value in the memory unit, and the obtained D addition results are stored at the same address in the memory unit; as well as For each pulse of the fast search numerically controlled oscillator, the coherence measure of a new result is calculated.

12. The method according to claim 11, wherein: Inputting D-1 metrics obtained based on the obtained D-1 rotated convolution results into the memory unit, wherein the memory unit is configured to store D*S values; Inputting a metric obtained based on the unrotated result / rotated result into the memory unit configured to store D*S values ​​to store the result; as well as The availability of a signal with a known pseudo-random noise code and parameters of said signal in the received radio signal is determined once for every S*k pulses.

13. The method according to claim 10, further comprising: At the reload generator, the state of the code generator is stored; as well as At S*k+1 pulses at the end of the incoherent period, the stored state of the code generator is loaded from the reload generator into the code generator.

14. The method according to claim 10, further comprising: Counting K periods of the S pulses, wherein the K periods are associated as coherent integration periods; counting a number of coherent integration periods, the number of coherent integration periods being associated as incoherent integration periods; The D coherent metrics are converted into values ​​to be added to the D incoherent metrics, each conversion being performed on each of the S most recent pulses from before the end of each coherent integration period, and the updated incoherent metrics are stored in the memory unit, which is configured to store D*S values.

15. The method according to claim 10, further comprising: N circular shift registers are shifted forward at the rate of the fast search numerically controlled oscillator, wherein the input of the control accumulator is set to zero based on the configuration.

16. The method according to claim 10, wherein: The sum estimated during data sorting includes the results of the Doppler measures during the period S*k, and the Doppler measures for each offset are sorted separately.

17. The method according to claim 14, wherein: At the end of the non-coherent integration period, multiple maximum values ​​among the S*D non-coherent metrics are selected individually for each Doppler frequency, and the selected values ​​are read by the CPU. The stored values ​​include the non-coherent metrics, the coherent metrics and the delay number.

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