A monolithic integrated high-speed modulation silicon-based optical chip and its preparation method

Abstract

The present invention relates to a monolithic integrated high-speed modulation silicon-based optical chip and a preparation method thereof, which comprises, from bottom to top, a silicon-based optoelectronic layer (I), an intermediate layer (II), a lithium niobate layer or a lithium tantalate layer (III); the silicon-based optoelectronic layer (I) comprises, from bottom to top, a substrate (1), an insulating layer (2), a silicon waveguide (3), an InP laser (4), a silicon germanium photodetector (5), and a thermo-optical phase shifter (6). Based on the excellent electro-optical modulation performance of lithium niobate (or lithium tantalate), the present invention focuses on a special bonding method and a CMOS-compatible silicon photonic flow-through process, obtains a lithium niobate (or lithium tantalate)-silicon multilayer structure, and further realizes a fully integrated transceiver optical chip with a laser, a photodetector, and an electro-optical modulator, which can meet the current requirements of on-chip optical systems for high compactness and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of information functional materials and devices, and in particular relates to a monolithic integrated high-speed modulation silicon-based optical chip and a preparation method thereof. Background Art

[0002] With the advancement of generative AI and cloud computing, developing universal models for multimodal, large-scale training sets has become a mainstream trend in this field, further driving the explosive growth of "east-west" traffic between data centers during parallel training. As core connectors in fiber-optic communications, optical modules enable high-speed electrical-to-optical conversion, enabling data transmission within fiber-optic networks to meet the low-power, high-bandwidth requirements of core computing infrastructure. Optical chips are key components of optical modules, and the performance of their transceivers and modulators determines the quality of their signal transmission. Beyond optical modules, optical chips that use photons as carriers can achieve high-speed optical computing with low energy consumption and high computing power through large-scale on-chip photonic devices. This feasibility further demonstrates the enormous potential competitiveness of optical chips in the era of expanding computing power.

[0003] Currently, the majority of commercial optical chips are still based on CMOS-compatible silicon-based platforms. However, silicon-based optoelectronic chips that utilize carrier dispersion effects for electro-optical modulation exhibit limited modulation bandwidth, low modulation rate, and low intrinsic linearity, making them unsuitable for applications in optical modules operating at 800G and above. Although optical chips based on the Pockels effect of lithium niobate (LNbO) can effectively address these low linearity issues, they are limited by the material system's incompatibility with traditional photodetectors and the large footprint of the modulation components. Therefore, the concept of co-packaged optical modules (CPO) and linear direct-drive pluggable optical modules (LPO) on LNbO platforms remains elusive. Similarly to LNbO, LTA has attracted significant research attention due to its excellent electro-optical properties and weak anisotropy. However, the development of on-chip LTA optoelectronic platforms and compatible planar fabrication processes remains a significant gap. Therefore, a platform with high compatibility and modulation linearity is crucial for the realization of integrated optoelectronic chips. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a monolithic integrated high-speed modulation silicon-based optical chip and a preparation method. The chip effectively solves the current problems in the industry of low integration, slow modulation rate and low modulation linearity of the transceiver end of silicon-based optical chips.

[0005] The present invention provides a monolithic integrated high-speed modulation silicon-based optical chip, which comprises, from bottom to top, a silicon-based optoelectronic layer, an intermediate layer, a lithium niobate layer or a lithium tantalate layer; the silicon-based optoelectronic layer comprises, from bottom to top, a substrate, an insulating layer, a silicon waveguide, an InP laser, a silicon germanium photodetector and a thermo-optical phase shifter; the intermediate layer comprises a silicon oxide protective layer, a silicon nitride waveguide and a silicon nitride microring.

[0006] Furthermore, the substrate includes but is not limited to a silicon oxide-silicon substrate.

[0007] Furthermore, the silicon waveguide includes a ridge waveguide, a stripe waveguide, a grating waveguide, a silicon region of a photodetector and a tapered coupling waveguide.

[0008] Preferably, the ridge waveguide is used to form the thermo-optical phase shifter and optical signal transmission, and the etching depth is 60nm-300nm.

[0009] Preferably, the strip waveguide is used to connect the ridge waveguide, and the etching depth is 200nm-600nm.

[0010] Preferably, the grating waveguide guides the laser light generated by the InP laser into an optical waveguide, which includes a shallowly etched waveguide structure with an etching depth of 60nm-300nm and a deeply etched periodic grating structure with an etching depth of 200nm-600nm.

[0011] Furthermore, the silicon region of the photodetector includes a P+ region and a P++ region from bottom to top.

[0012] Furthermore, the InP laser includes, from top to bottom, a P-type InGaAs layer, a P-type InP layer, a multi-quantum well structure MQW layer, and an N-type InP layer; the P-type InGaAs layer, the P-type InP layer, and the multi-quantum well structure MQW layer have the same length, and the length of the N-type InP layer is greater than that of the multi-quantum well structure MQW layer to form an uncovered area.

[0013] Furthermore, a first metal is deposited on the P-type InGaAs layer to form a P-type metal semiconductor contact; and a second metal is deposited on the uncovered area of ​​the N-type InP layer to form an N-type metal semiconductor contact.

[0014] Furthermore, the silicon germanium photodetector is obtained by depositing germanium Ge on the silicon region of the photodetector and performing selective ion implantation to form an N+ region and an N++ region.

[0015] Furthermore, Ti / Pt is deposited in the thermo-optical phase shifter.

[0016] Furthermore, windows are opened at the InP laser, silicon germanium photodetector and thermo-optical phase shifter, and lead metal and pad metal structures are provided.

[0017] Furthermore, the lithium niobate layer or the lithium tantalate layer is provided with an electro-optical waveguide, a tapered coupling waveguide, a wavelength division multiplexing device, and a coplanar waveguide electrode structure deposited on the electro-optical waveguide.

[0018] Preferably, the vertical distance between the silicon nitride waveguide and the silicon waveguide, the waveguide in the lithium niobate layer or the lithium tantalate layer is 2um-5um. The silicon nitride microring does not participate in the vertical coupling between layers and is used for self-injection locking and on-chip soliton generation of the InP laser, and its Q value is greater than 10 6 .

[0019] Furthermore, the thickness of the lithium niobate layer or the lithium tantalate layer is 600 nm; the mask used for etching the lithium niobate layer or the lithium tantalate layer includes silicon dioxide, HSQ photoresist, diamond-like carbon film (DLC), and chromium metal, the waveguide etching depth is 300 nm-600 nm, and the waveguide side wall inclination is 60°-80°; the lithium niobate (lithium tantalate) electro-optic modulator includes an electro-optic waveguide and a coplanar waveguide electrode structure (CPW); the electro-optic waveguide includes but is not limited to a Mach-Zehnder interferometer (MZI) structure and a microring structure, the CPW electrode structure includes but is not limited to a T-type structure and a straight waveguide structure, and the thickness is 300 nm-1000 nm; the wavelength division multiplexing device includes but is not limited to an arrayed waveguide grating and a cascaded filter microring cavity.

[0020] Furthermore, the above-mentioned metals include but are not limited to gold, copper, germanium, titanium and other metals.

[0021] The present invention also provides a method for preparing a monolithically integrated high-speed modulation silicon-based optical chip, comprising the following steps:

[0022] S1. A silicon-on-insulator (SOI) wafer is used to form a substrate and an insulating layer, and a silicon waveguide is etched on the SOI wafer using a standard silicon-based process.

[0023] S2. Prepare a cleaved InP chip with a multi-quantum well structure MQW, use plasma to activate the etched surface of the SOI wafer and the N-type InP surface of the cleaved InP chip, and bond the two together; then perform heat treatment and mechanical grinding to remove the InP substrate; etch the bonded cleaved InP chip using selective dry etching and wet etching, and then deposit metal to form a metal-semiconductor contact to obtain an InP laser;

[0024] S3, vapor-depositing a silicon dioxide protective layer, first dry-etching the silicon dioxide to open a window in the expected silicon germanium photodetector area, epitaxially depositing Ge, and performing selective ion implantation to obtain a silicon germanium photodetector;

[0025] S4, opening a window above the InGaAs layer in the InP laser to perform proton implantation;

[0026] S5, depositing Ti / Pt in the expected thermo-optical phase shifter region to obtain a thermo-optical phase shifter;

[0027] S6, depositing lead metal and pad metal structures at the InP laser, silicon germanium photodetector and thermo-optical phase shifter to form an interlayer lead electrode structure;

[0028] S7, opening a window to deposit silicon nitride waveguides and silicon nitride microrings in the expected middle layer area;

[0029] S8, vapor-depositing silicon dioxide again and performing surface chemical mechanical polishing;

[0030] S9, using plasma to activate the surface of the lithium niobate or lithium tantalate and the surface of the silicon dioxide protective layer in step S8, wafer bonding the two, and performing deep silicon etching on the silicon-silicon oxide substrate on the bonding structure side until the substrate is completely removed;

[0031] S10, transferring the pattern to a mask by ion beam lithography, and processing the electro-optical waveguide, tapered coupled waveguide, and wavelength division multiplexing device by ion beam etching;

[0032] S11, performing metal deposition on the electro-optical waveguide using a double-layer lift-off process to obtain a coplanar waveguide electrode structure;

[0033] S12. Etch the thin film again until the silicon dioxide protective layer, dry-etch the silicon dioxide to form a through hole, deposit a metal electrode, and obtain a monolithic integrated high-speed modulation silicon-based optical chip.

[0034] Preferably, the silicon layer thickness of the SOI wafer in S1 is 200 nm-600 nm.

[0035] Preferably, the size of the cleaved InP chip in S2 does not exceed 5 cm×5 cm.

[0036] Preferably, the cleaved InP chips in S2 are, from top to bottom, a P-type InGaAs layer, a P-type InP layer, an MQW layer, and an N-type InP layer, with an overall height in the range of 2um-3um; etching includes dry etching of the InGaAs layer and the InP layer and wet etching of the MQW structure.

[0037] Preferably, the gases used for plasma activation of the wafer and chip surfaces include but are not limited to argon, oxygen, and nitrogen. After activation, an argon-rich layer, an oxygen-rich layer, a nitrogen-rich layer, etc. can be formed on the film surface, with an energy range of 400eV to 2000eV; bonding can be carried out in a vacuum environment, at room temperature and pressure, and surface polishing is required before bonding to ensure that the surface roughness of the film is less than 0.3nm; the heat treatment after bonding is an annealing process. If the bonding structure is wafer-to-wafer bonding and the LNOI (LTOI) is bonded to the silicon-based optoelectronic wafer, the temperature is 500-1400°C; if the bonding structure is the LTOI (LTOI) is bonded to the silicon-based optoelectronic wafer, the annealing temperature is 300-500°C. The reason for avoiding excessively high annealing temperature is that high temperature will destroy the lattice quality of the LT film.

[0038] The above-mentioned window opening process utilizes an alignment process and conventional photolithography and etching technology to remove the protective layer at a specific location to expose the functional dielectric material underneath, so as to facilitate subsequent various planar process operations.

[0039] The working principle of the present invention is that the light generated by the on-chip InP laser is coupled into the high-Q silicon nitride microring through the coupled tapered waveguide to form laser self-injection locking; then it is coupled into the upper lithium niobate (lithium tantalate) tapered waveguide, and the wavelength division multiplexing device is used to separate different wavelengths into different electro-optical modulators. The electrodes apply external high-frequency digital electrical signals for high-speed electro-optical modulation; finally, the modulated signal is coupled back to the silicon-based optoelectronic layer through the lithium niobate (lithium tantalate) tapered waveguide and the silicon nitride tapered waveguide, and is received by the silicon germanium photodetector for optical-to-electrical conversion. The monolithic integrated high-speed modulation optical chip can realize chip-level electro-optical modulation function with integrated optical and electrical transmission and reception. Applications include but are not limited to optoelectronic integrated optical computing chips, optical chips in co-packaged optical modules, and on-chip lidar.

[0040] This invention proposes a monolithically integrated high-speed modulation optical chip based on a novel lithium niobate (or lithium tantalate) and silicon-based optoelectronic chip platform, and its fabrication method. The monolithically integrated high-speed modulation optical chip comprises a silicon-based optoelectronic layer, an intermediate layer, and a lithium niobate layer (or lithium tantalate layer). The silicon-based optoelectronic layer, located at the bottom of the optical chip, includes a substrate, an InP laser, a silicon waveguide, a silicon germanium photodetector, and a thermo-optical phase shifter. The silicon nitride waveguide in the intermediate layer enables interlayer coupling, and the silicon nitride microring enables self-injection locking of the laser. The lithium niobate layer (or lithium tantalate layer), located at the top of the optical chip, includes a high-speed electro-optical modulator, a wavelength division multiplexing device, and a waveguide. The preparation process includes: etching an optical waveguide structure on an SOI wafer using a standard silicon-based process; using plasma activation to achieve wafer-to-wafer bonding between the cleaved InP wafer and the SOI wafer, and integrating the optical transceiver of the on-chip InP laser and silicon-germanium photodetector through a variety of etching and deposition processes; bonding lithium niobate (or lithium tantalate) on a wafer-level insulator to a silicon-based optoelectronic wafer, and processing thereon a tapered waveguide that can be coupled between layers and an electro-optical modulator that can input high-frequency electrical signals; finally, using deep etching and electron beam deposition of metal to achieve electrical interconnection between layers, obtaining a complete monolithic integrated high-speed modulated optical chip.

[0041] Beneficial effects

[0042] Based on the excellent electro-optical modulation performance of lithium niobate (or lithium tantalate), this invention focuses on a special bonding method and CMOS-compatible silicon photonics flow-through process to obtain a lithium niobate (or lithium tantalate)-silicon multilayer structure. Furthermore, it realizes a fully integrated transceiver optical chip with lasers, photodetectors, and electro-optical modulators, which can meet the current requirements of on-chip optical systems for high compactness and low power consumption. This design can effectively solve the current problems of low integration, slow modulation rate, and low modulation linearity of the transceiver end of silicon-based optical chips in the industry, thereby promoting the commercialization of future 800G and above high-bandwidth co-packaged optical modules and integrated optical computing chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 and Figure 2 Schematic diagram of the structure of the chip of the present invention.

[0044] Figure 3 The figure is a flow chart of the preparation process of the chip of the present invention. DETAILED DESCRIPTION

[0045] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0046] Example 1

[0047] This embodiment provides a monolithic integrated high-speed modulation silicon-based optical chip, which includes, from bottom to top, a silicon-based optoelectronic layer (I), an intermediate layer II, and a lithium niobate layer or a lithium tantalate layer III; the silicon-based optoelectronic layer I includes, from bottom to top, a substrate 1, a silicon oxide insulating layer 2, a silicon waveguide 3, an InP laser 4, a silicon germanium photodetector 5, and a thermo-optical phase shifter 6; the intermediate layer II includes a silicon oxide protective layer 81, a silicon nitride waveguide 82, and a silicon nitride microring 83.

[0048] The silicon waveguide 3 includes a ridge waveguide 31 , a stripe waveguide 32 , a grating waveguide 33 , a silicon region 34 of a photodetector, and a tapered coupling waveguide 35 .

[0049] The silicon region 34 of the photodetector includes, from bottom to top, a P+ region 341 and a P++ region 342 .

[0050] The InP laser 4 includes, from top to bottom, a P-type InGaAs layer 41, a P-type InP layer 42, a multi-quantum well structure MQW layer 43 and an N-type InP layer 44; the P-type InGaAs layer 41, the P-type InP layer 42 and the multi-quantum well structure MQW layer 43 have the same length, and the length of the N-type InP layer 44 is greater than that of the multi-quantum well structure MQW layer 43, forming an uncovered area.

[0051] A first metal 45 is deposited on the P-type InGaAs layer 41 to form a P-type metal semiconductor contact; and a second metal 46 is deposited on the uncovered area of ​​the N-type InP layer 44 to form an N-type metal semiconductor contact.

[0052] The silicon germanium photodetector 5 is obtained by depositing germanium Ge on the silicon region 34 of the photodetector and performing selective ion implantation to form an N+ region 71 and an N++ region 72 .

[0053] Ti / Pt 9 is deposited in the thermo-optical phase shifter 6 .

[0054] Windows are opened at the InP laser 4 , the silicon germanium photodetector 5 and the thermo-optical phase shifter 6 , and lead metal 10 and pad metal structure 11 are provided.

[0055] The lithium niobate layer or lithium tantalate layer III is provided with an electro-optical waveguide 121 , a tapered coupling waveguide 122 , a wavelength division multiplexing device, and a coplanar waveguide electrode structure 123 deposited on the electro-optical waveguide 121 .

[0056] This embodiment provides a method for preparing a monolithically integrated high-speed modulation silicon-based optical chip, comprising the following steps:

[0057] (1) A SOI wafer with specifications of 220nm Si / 2um SiO2 / 4mm Si is provided. Based on a standard silicon-based process, a hard mask and dry etching of 70nm are used to define a shallow etched area. Then, a photoresist and dry etching of 150nm are used to define a deep etched area. The ridge waveguide 31, strip waveguide 32, grating waveguide 33, silicon region 34 of the photodetector, and tapered coupled waveguide 35 are fabricated. The hard mask is removed, and the silicon region 34 of the photodetector is lightly doped to form a P+ region 341 and heavily doped to form a P++ region 342. (2) A multi-layer cleaved InP wafer containing a multi-quantum well structure (MQW) is provided. The wafer comprises, from top to bottom, a P-type InGaAs layer 41, a P-type InP layer 42, a multi-quantum well structure (MQW) layer 43, and an N-type InP layer 44. The surface of the N-type InP layer 44 of the multi-layer cleaved InP wafer and the Si surface of the SOI wafer are activated by plasma to achieve wafer-to-wafer bonding at room temperature. The total thickness of the multi-layer cleaved InP wafer is 2.2 μm. After bonding, annealing is performed to enhance the bonding strength at a temperature of 700°C. Ion beam evaporation is used to deposit a first metal 45 (gold) on the surface of the P-type InGaAs layer 41 to form a P-type gold semi-contact to improve the laser carrier injection efficiency and output power; dry etching of the P-type InP 42, P-type InGaAs 41, and N-type InP 44 and wet etching of the MQW 43 are performed. This etching step requires alignment using a mark; a second metal 45 (gold) is deposited on the surface of the exposed N-type InP 44 to form a gold semi-contact, and silicon dioxide is deposited to form a protective layer, completing the preparation of the InP laser 4.

[0058] (3) Dry-etching the silicon dioxide protective layer in the silicon germanium detector area, epitaxially depositing Ge material, and re-doping it to form N+ region 71 and N++ region 72, thereby completing the preparation of the silicon germanium photodetector 5;

[0059] (4) Dry etching silicon dioxide to open windows on the surface of the P-type InGaAs 41 again for proton implantation to form a proton implantation layer to reduce current leakage;

[0060] (5) Dry etching the silicon dioxide protective layer in the thermo-optical phase shifter region to open a window, and depositing Ti / Pt metal 9 to obtain the thermo-optical phase shifter 6;

[0061] (6) A window is opened at the N-type and P-type gold semiconductor contacts to deposit the lead metal 10 and the pad metal structure 11; a window is opened above the tapered coupling waveguide 35 to deposit the silicon nitride waveguide 82 for interlayer coupling between the LN layer and the Si layer, and a window is opened in the area away from the active area to deposit the silicon nitride microring 83 for self-injection locking of the laser; a silicon oxide protective layer 81 is deposited to cross the pad metal structure 11, and the surface is polished to make the surface roughness less than 0.3 nm, completing the preparation of the silicon-based optoelectronic layer I and the intermediate layer II, and obtaining a silicon-based optoelectronic chip.

[0062] (7) A LNOI wafer with specifications of 600nm LN / 4.7um SiO2 / 4mmSi was prepared. The LN surface of the LNOI wafer and the upper silicon oxide surface of the silicon-based optoelectronic chip were activated by plasma to achieve bonding at room temperature, and then annealed at 300°C. The waveguide pattern was transferred from the LN film by electron beam lithography and ion beam etching to etch out the electro-optical waveguide 121, the tapered coupling waveguide 122 and the MZI waveguide structure.

[0063] (8) A double-layer lift-off process is used to deposit gold electrodes to obtain a coplanar waveguide electrode structure 123. Then, an electron beam is used to deeply etch the LN film and the silicon oxide protective layer until the pad metal electrode of the intermediate layer III is exposed. Finally, an ion beam is used to deposit gold electrodes 13 and pad electrodes to complete the preparation of the overall monolithic integrated high-speed modulation optical chip.

Claims

1. A monolithically integrated high-speed modulation silicon-based optical chip, characterized by: The invention comprises, from bottom to top, a silicon-based optoelectronic layer (I), an intermediate layer (II), a lithium niobate layer or a lithium tantalate layer (III); the silicon-based optoelectronic layer (I) comprises, from bottom to top, a substrate (1), (2), a silicon waveguide (3), an InP laser (4), a silicon germanium photodetector (5), and a thermo-optical phase shifter (6); the intermediate layer (II) comprises a silicon oxide protective layer (81), a silicon nitride waveguide (82), and a silicon nitride microring (83); The preparation method comprises the following steps: S1, using a silicon-on-insulator (SOI) wafer to form a substrate (1) and an insulating layer (2), and etching a silicon waveguide (3) on the SOI wafer using a standard silicon-based process; S2, preparing a cleaved InP chip with a multi-quantum well structure MQW, using plasma to activate the etched surface of the SOI wafer and the N-type InP surface of the cleaved InP chip, and bonding the two together; then performing heat treatment and mechanical grinding to remove the InP substrate; etching the bonded cleaved InP chip using selective dry etching and wet etching, and then depositing metal to form a metal-semiconductor contact to obtain an InP laser (4); S3, vapor-depositing a silicon dioxide protective layer, first dry-etching the silicon dioxide to open a window in the expected silicon germanium photodetector area, epitaxially depositing Ge, and performing selective ion implantation to obtain a silicon germanium photodetector (5); S4, opening a window above the InGaAs layer in the InP laser (4) to perform proton implantation; S5, depositing Ti / Pt (10) in the expected thermo-optical phase shifter region to obtain a thermo-optical phase shifter (6); S6, opening windows at the InP laser (4), the silicon germanium photodetector (5), and the thermo-optical phase shifter (6) to deposit lead metal (10) and a pad metal structure (11) to form an interlayer lead electrode structure; S7, opening a window to deposit a silicon nitride waveguide (82) and a silicon nitride microring (83) in the expected intermediate layer region (III); S8, vapor-depositing silicon dioxide again and performing surface chemical mechanical polishing; S9, using plasma to activate the surface of the lithium niobate or lithium tantalate and the surface of the silicon dioxide protective layer in step S8, wafer bonding the two, and performing deep silicon etching on the silicon-silicon oxide substrate on the bonding structure side until the substrate is completely removed; S10, transferring the pattern to a mask by ion beam lithography, and ion beam etching to form an electro-optical waveguide (121), a tapered coupled waveguide (122), and a wavelength division multiplexing device; S11, performing metal deposition on the electro-optical waveguide (121) using a double-layer lift-off process to obtain a coplanar waveguide electrode structure (123); S12, etching the thin film again until the silicon dioxide protective layer is reached, dry-etching the silicon dioxide to form a through hole, and depositing a metal electrode (13) to obtain a monolithic integrated high-speed modulation silicon-based optical chip.

2. The chip according to claim 1, wherein: The silicon waveguide (3) comprises a ridge waveguide (31), a strip waveguide (32), a grating waveguide (33), a silicon region (34) of a photodetector, and a tapered coupling waveguide (35).

3. The chip according to claim 2, wherein: The silicon region (34) of the photodetector includes a P+ region (341) and a P++ region (342) from bottom to top.

4. The chip according to claim 1, wherein: The InP laser (4) comprises, from top to bottom, a P-type InGaAs layer (41), a P-type InP layer (42), a multi-quantum well structure MQW layer (43), and an N-type InP layer (44); the P-type InGaAs layer (41), the P-type InP layer (42), and the multi-quantum well structure MQW layer (43) have the same length, and the N-type InP layer (44) is longer than the multi-quantum well structure MQW layer (43), forming an uncovered area.

5. The chip according to claim 4, characterized in that: A first metal (45) is deposited on the P-type InGaAs layer (41) to form a P-type metal semiconductor contact; and a second metal (46) is deposited on the uncovered area of ​​the N-type InP layer (44) to form an N-type metal semiconductor contact.

6. The chip according to claim 2, wherein: The silicon germanium photodetector (5) is obtained by depositing germanium (Ge) above the silicon region (34) of the photodetector and performing selective ion implantation to form an N+ region (71) and an N++ region (72).

7. The chip according to claim 1, wherein: Ti / Pt (9) is deposited in the thermo-optical phase shifter (6).

8. The chip according to claim 1, wherein: Windows are opened at the InP laser (4), the silicon germanium photodetector (5) and the thermo-optical phase shifter (6), and are provided with lead metal (10) and a pad metal structure (11).

9. The chip according to claim 1, wherein: The lithium niobate layer or lithium tantalate layer (III) is provided with an electro-optical waveguide (121), a tapered coupling waveguide (122), a wavelength division multiplexing device, and a coplanar waveguide electrode structure (123) deposited on the electro-optical waveguide (121).

10. A method for preparing a monolithically integrated high-speed modulation silicon-based optical chip, comprising the following steps: S1, using a silicon-on-insulator (SOI) wafer to form a substrate (1) and an insulating layer (2), and etching a silicon waveguide (3) on the SOI wafer using a standard silicon-based process; S2, preparing a cleaved InP chip with a multi-quantum well structure MQW, using plasma to activate the etched surface of the SOI wafer and the N-type InP surface of the cleaved InP chip, and bonding the two together; then performing heat treatment and mechanical grinding to remove the InP substrate; etching the bonded cleaved InP chip using selective dry etching and wet etching, and then depositing metal to form a metal-semiconductor contact to obtain an InP laser (4); S3, vapor-depositing a silicon dioxide protective layer, first dry-etching the silicon dioxide to open a window in the expected silicon germanium photodetector area, epitaxially depositing Ge, and performing selective ion implantation to obtain a silicon germanium photodetector (5); S4, opening a window above the InGaAs layer in the InP laser (4) to perform proton implantation; S5, depositing Ti / Pt (10) in the expected thermo-optical phase shifter region to obtain a thermo-optical phase shifter (6); S6, opening windows at the InP laser (4), the silicon germanium photodetector (5), and the thermo-optical phase shifter (6) to deposit lead metal (10) and a pad metal structure (11) to form an interlayer lead electrode structure; S7, opening a window to deposit a silicon nitride waveguide (82) and a silicon nitride microring (83) in the expected intermediate layer region (III); S8, vapor-depositing silicon dioxide again and performing surface chemical mechanical polishing; S9, using plasma to activate the surface of the lithium niobate or lithium tantalate and the surface of the silicon dioxide protective layer in step S8, wafer bonding the two, and performing deep silicon etching on the silicon-silicon oxide substrate on the bonding structure side until the substrate is completely removed; S10, transferring the pattern to a mask by ion beam lithography, and ion beam etching to form an electro-optical waveguide (121), a tapered coupled waveguide (122), and a wavelength division multiplexing device; S11, performing metal deposition on the electro-optical waveguide (121) using a double-layer lift-off process to obtain a coplanar waveguide electrode structure (123); S12, etching the thin film again until the silicon dioxide protective layer is reached, dry-etching the silicon dioxide to form a through hole, and depositing a metal electrode (13) to obtain a monolithic integrated high-speed modulation silicon-based optical chip.

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