Driving method of asymmetric gamma liquid crystal display panel

Abstract

The application relates to the technical field of liquid crystal display panels, and discloses a driving method of an asymmetric gamma liquid crystal display panel, wherein for a certain source chip, the gray scale data transmitted to the adjacent two rows of pixel units by a certain source line of the source chip are D1 and D2 respectively; if D1 is not equal to D2, the source line CH1 is called a gray scale change source line; an external charge sharing judgment condition is that the gray scale change source lines of the source chip CH account for more than one third of all the source lines of the source chip CH; if the external charge sharing judgment condition is met, the following charge sharing action is performed: charge sharing is performed between all the source lines of the source chip CH, and charge sharing is performed with the source lines of other source chips; and the asymmetric gamma liquid crystal display panel can achieve better charge sharing effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of liquid crystal display panel, and particularly relates to a driving method of asymmetric gamma liquid crystal display panel. BACKGROUND

[0002] Liquid crystal panel display has developed for decades. Due to the characteristics of liquid crystal, the driving voltage of liquid crystal molecules must be changed in polarity. Charge sharing technology is widely used in liquid crystal display to reduce power consumption and shorten charging time.

[0003] Figure 1 The commonly used display driving circuit is roughly divided into positive polarity voltage driving amplifier (AMPH) and negative polarity driving amplifier (AMPL). When the polarity is switched, the positive and negative polarity panel loads are short-circuited to share charge (Charge sharing) to accelerate the charging speed of the next line and reduce unnecessary power consumption.

[0004] Figure 2 The commonly used charging waveform is shown in the following figure: Figure 3 The schematic diagram of the display panel and the source chip is shown in the following figure. In the prior art, charge sharing is generally performed between two output terminals of a single source chip, as shown in the following figure: Figure 4 Or charge sharing is performed between all output terminals of a single source chip, as shown in the following figure: Figure 5

[0005] That is, the current charge sharing method is to share charge between any two output pins of the same chip, or to share charge between all pins of a single chip. However, the above charge sharing scheme can achieve good results only when the positive and negative polarities of the liquid crystal display panel Gamma are symmetrical.

[0006] However, in practice, the positive and negative polarities of Gamma are generally not completely symmetrical. Therefore, the final effect of applying the above charge sharing scheme for charge sharing, such as power saving effect and charging effect, is poor. SUMMARY

[0007] To solve the above technical problems, the present application provides a driving method of asymmetric gamma liquid crystal display panel, which combines the control of timing controller (Timing Controller) and the wiring across chips, and completes charge sharing between all source chips through dummy output pads and switches of the source chip to achieve better charge sharing effect.

[0008] To solve the above technical problems, the present application adopts the following technical scheme:

[0009] ​The application discloses a driving method of an asymmetric gamma liquid crystal display panel, and belongs to the technical field of liquid crystal display panel driving.

[0010] For a source chip CH, the gray scale data transmitted by a source line CH1 of the source chip CH to adjacent two rows of pixel units are D1 and D2 respectively; if D1≠D2, the source line CH1 is called a gray scale change source line.

[0011] The external charge sharing judgment condition is that the gray scale change source lines of the source chip CH account for more than one third of all the source lines of the source chip CH; if the external charge sharing judgment condition is met, the following charge sharing action is performed: charge sharing is performed between the source lines of the source chip CH, and charge sharing is performed with the source lines of other source chips.

[0012] Further, the external charge sharing judgment condition is replaced by that the most significant bit of the gray scale data transmitted by the source chip A to adjacent two rows of pixel units is changed.

[0013] Further, the external charge sharing judgment condition is replaced by that any one of the most significant bit to the least significant bit of the gray scale data transmitted by the source chip A to adjacent two rows of pixel units is changed.

[0014] Compared with the prior art, the application has the beneficial technical effects that:

[0015] The application judges whether the gray scale data transmitted by a source line to adjacent two rows of pixel units is changed, judges whether the source line belongs to a gray scale change source line, if the number of the gray scale change source lines of a source chip accounts for more than one third of all the source lines of the source chip, external charge sharing is performed on the source chip, that is, at least one source line of the source chip is connected with at least one source line of other source chips, so that external charge sharing is realized. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a schematic diagram of a common display driving circuit;

[0017] Figure 2 It is a schematic diagram of a common charging waveform;

[0018] Figure 3 It is a schematic diagram of a display panel and a source chip;

[0019] Figure 4 It is a schematic diagram of two-by-two charge sharing of output ends of a single source chip in the prior art;

[0020] Figure 5 A schematic diagram illustrating charge sharing across all output terminals of a single source chip in existing technology;

[0021] Figure 6 A symmetrical gamma curve of a liquid crystal display panel;

[0022] Figure 7 This is an asymmetric gamma curve of a liquid crystal display panel.

[0023] Figure 8 A schematic diagram illustrating the display of a specific pattern on a liquid crystal display panel;

[0024] Figure 9 Gamma curve of a specific pattern displayed on an LCD panel;

[0025] Figure 10 A schematic diagram of a liquid crystal display panel that displays a specific pattern by changing the polarity through dot flipping;

[0026] Figure 11 for Figure 10 The waveform diagram of charge sharing and charging of source chip C and source chip E at point X in the liquid crystal display panel;

[0027] Figure 12 for Figure 10 Waveform diagram of charge sharing and charging of the source chip D in the liquid crystal display panel at point X;

[0028] Figure 13 A schematic diagram illustrating the display of a specific pattern on a liquid crystal display panel;

[0029] Figure 14 This is a schematic diagram of the charge sharing circuit in Embodiment 1 of the present invention;

[0030] Figure 15 This is a schematic diagram of the charge sharing circuit in Embodiment 1 of the present invention;

[0031] Figure 16 This is a schematic diagram of the charge sharing circuit in Embodiment 2 of the present invention;

[0032] Figure 17 This is a schematic diagram of the charge sharing circuit in Embodiment 2 of the present invention;

[0033] Figure 18 This is a schematic diagram of the charge sharing circuit in Embodiment 3 of the present invention;

[0034] Figure 19 This is a schematic diagram of the charge sharing circuit in Embodiment 3 of the present invention;

[0035] Figure 20This is a schematic diagram of the level conversion unit used in various embodiments of the present invention. Detailed Implementation

[0036] A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0037] In the accompanying drawings of this invention, DVDD represents digital voltage, VSSD represents digital ground, VSSA represents analog operating negative voltage, HAVDD represents half-value analog voltage, VDDA is analog voltage, R represents resistance, C represents capacitance; OP (Output) represents analog voltage output to the display panel; COF represents flip-chip film; Y1, Y2, ..., Y n This represents the first to nth source lines output by the source chip (S-IC). GS (Gray Scale) represents grayscale; GS255+ represents a positive 255 grayscale voltage; GS255- represents a negative 255 grayscale voltage; GS0+ represents a positive 0 grayscale voltage; GS0- represents a negative 0 grayscale voltage; △V255+ represents the absolute value of the difference between the positive 255 grayscale voltage and VCOM (display panel common voltage); △V255- represents the absolute value of the difference between the negative 255 grayscale voltage and VCOM (display panel common voltage); △V0+ represents the absolute value of the difference between the positive 0 grayscale voltage and VCOM (display panel common voltage); △V0- represents the absolute value of the difference between the negative 0 grayscale voltage and VCOM (display panel common voltage); CS level (charge sharing level) represents the voltage after charge sharing; CS level① represents the voltage after the first charge sharing; CS level② represents the voltage after the second charge sharing; S-IC C represents the source chip C; S-IC D represents the source chip D; S-ICE represents the source chip E. TP1 is the control signal for controlling the display panel to share and charge, and TCON represents the timing controller.

[0038] Example 1

[0039] like Figure 6 and Figure 7 As shown, taking an 8-bit signal as an example, when the LCD panel has a symmetrical gamma curve, ΔV255+ equals ΔV255-, and ΔV0- equals ΔV0+; when the LCD panel has an asymmetrical gamma curve, ΔV255+ is greater than ΔV255-, and ΔV0- is greater than ΔV0+. An 8-bit signal, also known as 8-bit data, represents the amount of data per pixel, which is 2 to the power of 8. This can form 256 grayscale signals, corresponding to the previous 0-255 grayscale levels.

[0040] like Figure 8 and Figure 9As shown, when the liquid crystal display panel has a gray scale difference between the two regions in the vertical direction, due to the asymmetric gamma curve of the liquid crystal display panel, after polarity inversion, CS level ① is positive, and CS level ② is negative. The following analysis is made:

[0041] As shown in Figure 10 , Figure 11 , Figure 12 As shown, for a liquid crystal display panel that performs polarity conversion in the form of point inversion, at the X position of the liquid crystal display panel, after charge sharing between the two source lines output by the source chip C, the voltage is positive compared to the display panel common voltage (VCOM), and the next line has half of the output charging to positive G0 and the other half of the output charging to negative G0, which causes the difference in the required charging voltage to be different for positive and negative polarities, resulting in different charging completion times and poor charge reuse effect. The above analysis is also applicable to the source chip E. For the source chip D, after charge sharing, the voltage is negative compared to VCOM, and the next line has half of the output charging to positive G255 and the other half of the output charging to negative G255. Similarly, this will cause the difference in the required charging voltage to be different for positive and negative polarities, resulting in different charging completion times and poor charge reuse effect. The CS levels generated by the two chips due to the asymmetric gamma curve are also averaged, making the CS level closer to VCOM and the charge sharing more efficient.

[0042] As shown in Figure 13 , Figure 13 The gray scale of the two pixel units adjacent in the vertical direction in the dashed box does not change, and even if the Gamma is asymmetric, the generated CS level is not close to VCOM, but is in the middle, which is more suitable for internal charge sharing in a single chip.

[0043] In summary, in general, the gamma curve of a liquid crystal display panel is asymmetric, and as long as there is a polarity conversion in the vertical direction and a gray scale change, if the traditional scheme is still used, which only performs single-chip output charge sharing, the charge sharing effect will be poor. Even if the output charging capacity is sufficient to be unnoticed in most cases, the charge reuse effect is poor, power consumption is increased, and the chip temperature is also increased.

[0044] As shown in Figure 14 , in this embodiment, a judgment circuit is added in the TCON to generate a pattern judgment control signal (TP2). When external charge sharing is not needed, the pattern judgment control signal controls the external charge sharing switch SW to be disconnected through a level conversion unit, and at this time, charge sharing is only performed between the source lines output by each source chip.

[0045] When the external charge sharing judgment condition is met, the pattern judgment control signal controls the external charge sharing switch SW to be closed through the level shifting unit, at this time, the source chip not only shares the charge among the source lines, but also shares the charge with other chips, the wiring mode of sharing the charge among the source chips includes the panel wiring and the thin film wiring. As shown in Figure 15 Specifically, the source chip is connected with other source chips through the external charge sharing switch SW and the dummy pad, and the panel wiring or the thin film wiring.

[0046] As shown in Figure 20 The level shifting unit includes a level shifting module one and a level shifting module two. The level shifting module one is a double number stage inverter circuit, which is used to convert the pattern judgment control signal TP2 into the supply voltage VINB.

[0047] The level shifting module two includes MOS tubes N3, N4, N5, N6, P3, P4, P5, P6, wherein the MOS tubes N3, N4, N5, N6 are NMOS, and the MOS tubes P3, P4, P5, P6 are PMOS.

[0048] The gate of the MOS tube N3 is connected with the supply voltage VIN, the drain of the MOS tube N3 is connected with the voltage VOUT1B, the source of the MOS tube P3, and the gate of the MOS tube P4, the source of the MOS tube N3 is connected with the source of the MOS tube N4; the drain of the MOS tube P3 is connected with the drain of the MOS tube P4, the gate of the MOS tube P3 is connected with the drain of the MOS tube N4; the source of the MOS tube P4 is connected with the voltage VOUT1 and the drain of the MOS tube N4; the gate of the MOS tube N4 outputs the voltage VINB.

[0049] The drain of the MOS tube N5 is connected with the source of the MOS tube P5 and the gate of the MOS tube N6, the gate of the MOS tube N5 is connected with the source of the MOS tube P6, the voltage VCTRL, and the drain of the MOS tube N6, the source of the MOS tube N5 is connected with the source of the MOS tube N6; the gate of the MOS tube P5 is connected with the voltage VOUT1, the drain of the MOS tube P5 is connected with the drain of the MOS tube P6; the gate of the MOS tube P6 is connected with the voltage VOUT1B.

[0050] The external charge sharing switch SW is a MOS tube, and the voltage VCTRL as the output of the level shifting unit is connected with the gate of the MOS tube SW.

[0051] Embodiment two

[0052] As shown in Figure 16 and Figure 17As shown in FIG. 2, the difference between the embodiment two and the embodiment one is that two source chips in the embodiment two are on a film, and the two source chips are connected by the film wiring and share the external charge.

[0053] Embodiment three

[0054] As shown in FIG. 3, the difference between the embodiment three and the embodiment one is that one source line in one source chip is connected with one source line in another source chip through an external charge sharing switch SW, and the two source lines share the external charge. Figure 18 Figure 19 It is apparent to those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and that the present application can be carried out in other concrete forms without departing from the spirit or essential characteristics of the present application. Accordingly, no matter from which point of view, the embodiments should be considered as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and range of equivalency of the claims are intended to be embraced therein, and any drawing reference in the claims should not be considered as limiting the claims involved.

[0055] Furthermore, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the present specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.

[0056] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the present specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.​

Claims

1. A driving method of an asymmetric gamma liquid crystal display panel, the liquid crystal display panel comprising a pixel array area, a plurality of source chips, and a timing controller; the pixel array area comprising pixel units arranged in rows and columns, each row of pixel units being connected by a gate line, and each column of pixel units being connected by a source line, the source line being connected to a source chip; characterized in that: an external charge sharing judgment condition is that a gray scale variation of a source chip CH is more than one third of all source lines of the source chip CH; if the external charge sharing judgment condition is met, a charge sharing action is performed as follows: charge sharing is performed between the source lines of the source chip CH, and charge sharing is performed with the source lines of other source chips; For a source chip CH, a root source line of the source chip CH The gray scale data transmitted to the adjacent two rows of pixel units are respectively And If , the source line is called a gray scale change source line; the source chip is connected to other source chips through an external charge sharing switch and a dummy pad, and a panel wiring or a thin film wiring; the external charge sharing switch being controlled by a pattern judgment control signal generated by the timing controller. the external charge sharing judgment condition is replaced by: a most significant bit of gray scale data transmitted by the source chip A to two adjacent rows of pixel units is changed.

2. The driving method of the asymmetric gamma liquid crystal display panel according to claim 1, wherein the external charge sharing judgment condition is replaced by: any one of a most significant bit to a least significant bit of gray scale data transmitted by the source chip A to two adjacent rows of pixel units is changed.

3. The driving method of the asymmetric gamma liquid crystal display panel according to claim 2, wherein ​

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