Arithmetic logic unit and imaging system

Abstract

The present disclosure relates to image signal and phase detection autofocus signal extraction and storage in an arithmetic logic unit. An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. A first input of an adder stage is coupled to receive an output of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive the output of the GC to binary stage. An adder input multiplexer stage includes an output coupled to a second input of the adder stage and first and second inputs coupled to outputs of the first and second adder input latches, respectively.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to an arithmetic logic unit for use in image sensors. Background Technology

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, mobile phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range) through both device architecture design and image acquisition and processing.

[0003] A typical image sensor operates in response to image light from an external scene incident on it. The image sensor comprises an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge after absorption. The image charge generated by the pixel light can be measured as an analog output image signal on the bit lines, which varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the bit lines and converted into a digital value to provide information representing the external scene. Summary of the Invention

[0004] Embodiments of this disclosure provide an arithmetic logic unit (ALU) comprising: a front-end latch stage coupled to a Gray code (GC) generator to latch the GC output of the GC generator in response to a comparator output; a signal latch stage coupled to latch the output of the front-end latch stage in response to a signal latch enable signal; a GC-to-binary stage coupled to generate a binary representation of the GC output latched in the signal latch stage; an adder stage including a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC-to-binary stage, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; and an adder input latch stage coupled to latch the GC output. The C-to-binary output, wherein the adder input latch stage includes: a first adder input latch configured to latch the C-to-binary output in response to a first adder input latch enable signal; and a second adder input latch configured to latch the C-to-binary output in response to a second adder input latch enable signal; and an adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the output of the first adder input latch, wherein a second input of the adder input multiplexer stage is coupled to receive the output of the second adder input latch, and wherein the second input of the adder stage is coupled to receive the output of the adder input multiplexer stage.

[0005] Another embodiment of this disclosure provides an imaging system comprising: a pixel array including a plurality of pixel circuits arranged in rows and columns, each of the plurality of pixel circuits being coupled to generate an analog image data signal in response to incident light; a control circuit system coupled to the pixel array to control the operation of the pixel array; and a readout circuit coupled to the pixel array via a plurality of column lines, wherein the readout circuit includes: a plurality of comparators, each of the plurality of comparators being coupled to receive a ramp signal, wherein each of the plurality of comparators is further coupled to a corresponding one of the plurality of column lines to receive a corresponding analog image data signal, wherein... Each of a plurality of comparators is coupled to generate a corresponding comparator output in response to a comparison of the corresponding analog image data signal with the ramp signal; a Gray code (GC) generator is coupled to generate a GC output; and a plurality of arithmetic logic units (ALUs), each of which is coupled to receive the GC output, wherein each of the plurality of ALUs is further coupled to a corresponding of the plurality of comparators to receive the corresponding comparator output, wherein each of the plurality of ALUs includes: a front-end latch stage coupled to the GC generator to latch the GC output of the GC generator in response to the corresponding comparator output; and a signal. A latch stage coupled to latch the output of the front-end latch stage in response to a signal latch enable signal; a GC-to-binary stage coupled to generate a binary representation of the GC output latched in the signal latch stage; an adder stage including a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC-to-binary stage, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; an adder input latch stage coupled to latch the output of the GC-to-binary stage, wherein the adder input latch stage includes: a first adder input latch, wherein The system comprises: a first adder input latch configured to latch the output of the GC to a binary level in response to a first adder input latch enable signal; a second adder input latch configured to latch the output of the GC to a binary level in response to a second adder input latch enable signal; and an adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the output of the first adder input latch, wherein a second input of the adder input multiplexer stage is coupled to receive the output of the second adder input latch, and wherein the second input of the adder stage is coupled to receive the output of the adder input multiplexer stage. Attached Figure Description

[0006] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the accompanying drawings, wherein the same element symbols refer to the same parts in all various views unless otherwise specified.

[0007] Figure 1 This invention illustrates an example of an imaging system according to the teachings of this disclosure, comprising a pixel array having image sensing and phase detection autofocus pixels and a readout circuit comprising column arithmetic logic units for extracting and storing various signals.

[0008] Figure 2 This describes an example of a readout circuit comprising a column analog-to-digital converter having a Gray code generator and parallel column arithmetic logic units for extracting and storing various signals, according to the teachings of this disclosure.

[0009] Figure 3A This is a schematic diagram illustrating a portion of one of a plurality of arithmetic logic units according to the teachings of this disclosure.

[0010] Figure 3B This illustrates an example of the timing of analog-to-digital conversion and storage of various extracted signals in an arithmetic logic unit according to the teachings of this disclosure.

[0011] Figure 4A This is a schematic diagram illustrating another instance of a portion of one of the plurality of arithmetic logic units according to the teachings of this disclosure.

[0012] Figure 4B This illustrates another example of the timing of analog-to-digital conversion and storage of various extracted signals in an arithmetic logic unit, according to another example of the teachings of this disclosure.

[0013] Figure 5A This is a schematic diagram illustrating yet another example of a portion of one of the plurality of arithmetic logic units according to the teachings of this disclosure.

[0014] Figure 5B This is yet another example illustrating the timing of analog-to-digital conversion and storage of various extracted signals in an arithmetic logic unit, according to the teachings of this disclosure.

[0015] Corresponding reference characters indicate corresponding components in all of the various views in the figures. Those skilled in the art will understand that the elements in the figures are for illustrative purposes and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to facilitate understanding of the various embodiments of this disclosure. Additionally, common but well-known elements that are generally not depicted in commercially viable embodiments are not shown to facilitate unobstructed viewing of these various embodiments of this disclosure. Detailed Implementation

[0016] This document describes various examples involving the extraction and storage of image signals and phase-detection autofocus signals in the arithmetic logic unit (ALU) of an analog-to-digital converter contained in an imaging system. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details or by using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0017] In this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one instance of this disclosure. Therefore, the phrases "in an example" or "in an embodiment" appearing in various places in this specification do not necessarily all refer to the same example. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0018] For ease of description, spatial relative terms (e.g., “below,” “under,” “down,” “below,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like) are used herein to describe the relationship of one element or feature relative to another element(s), as illustrated in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, then an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the exemplary terms “below” or “below” can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise) and the spatial relative descriptive terms used herein may be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as “between two layers,” it may be the only layer between the two layers or there may be one or more intermediate layers.

[0019] Several technical terms are used in this specification. These terms take their common meaning in the art, unless specifically defined herein or the context in which they are used will explicitly suggest otherwise. It should be noted that element names and symbols are used interchangeably in this document (e.g., Si for silicon); however, they have the same meaning.

[0020] As will be discussed, various examples of the disclosed image sensor readout circuitry are provided, wherein analog image signals from the pixel array and phase-detection autofocus signals are extracted via the column bit lines of the image sensor and stored in the column arithmetic logic unit (ALU). In these various examples, it should be understood that digital power consumption is reduced via the column ALU according to the teachings of this disclosure by extracting the phase-detection autofocus signals and then storing them locally in a latch contained within the column ALU, rather than in an image signal processor (ISP) outside the column ALU.

[0021] Additionally, in various instances, the image sensing and phase detection autofocus signals can be read from the image sensor via a correlated double-sample (CDS) output and via dual conversion gains (e.g., high conversion gain and low conversion gain). In various instances, each column bit line of the pixel array is coupled to one of the inputs of a corresponding comparator. The other input of each comparator is coupled to receive a global ramp signal. The output of each comparator is coupled to a corresponding column ALU, which is configured to extract, store, and output a digital or binary representation of the image signal and the phase detection autofocus signal from the pixel array. In various instances, the normalized output (e.g., CDS output) generated by the column ALU can be based on the difference between one or more image signal or phase detection autofocus samples (e.g., a black signal and a reset value signal) from the pixel array. According to the teachings of this disclosure, in various instances, a shared Gray code (GC) generator is used to generate a GC output, which is coupled to be received by each of the column ALUs to perform parallel analog-to-digital conversion (ADC) of the signal read from the column bit lines.

[0022] To illustrate, Figure 1 An example of an imaging system 100, according to the teachings of this disclosure, is shown, comprising a pixel array 102 with image sensing and phase detection autofocus (PDAF) pixels and a readout circuit 106 comprising a column arithmetic logic unit (ALU) for extracting and storing various signals. In one example, according to an embodiment of the present disclosure, analog image signals and phase detection autofocus (PDAF) signals are read out in parallel to the readout circuit 106 via column bit lines 112. As will be discussed in more detail below, according to the teachings of the present disclosure, in various instances, the readout circuit 106 comprises a circuitry for performing analog-to-digital conversion (ADC) of image and PDAF data from the pixel array 102, having a parallel column ALU and a shared Gray code (GC) generator for correlated double sampling (CDS) and / or double conversion gain (DCG) processing.

[0023] Specifically, Figure 1The examples depicted illustrate an imaging system 100 comprising a pixel array 102, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array comprising a plurality of pixel circuits 104, each containing photodiodes (e.g., P1, P2, ..., Pn). In various examples, the photodiodes P1, P2, ..., Pn include photodiodes configured to provide image data and photodiodes configured to provide PDAF data. In various examples, the photodiodes configured to provide PDAF data may be distributed among the photodiodes configured to provide image data. As illustrated in the depicted examples, the pixel circuits 104 are arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data and / or PDAF data of people, locations, objects, etc., which can then be used to reproduce images of people, locations, objects, etc.

[0024] In one example, each pixel circuit 104 is configured to photogenerate an image and / or PDAF charge in response to incident light. After each pixel circuit 104 acquires its image and / or PDAF charge, the corresponding analog image and / or PDAF charge data is read out by the readout circuit 106 via column lines 112. In various examples, the image and / or PDAF charge data from each row of pixel circuits 104 are read out in parallel by the readout circuit 106 via column lines 112. According to the teachings of this disclosure, in various examples, the analog image charge signal and / or PDAF charge signal are converted into digital values, which are then transmitted to functional logic 108.

[0025] In various embodiments, analog-to-digital conversion is performed using a parallel ALU and a shared Gray code generator included in the readout circuit 106. In various embodiments, the parallel ALU readout included in the readout circuit 106 can be configured to extract the image signal and the PDAF signal and perform correlated double sampling (CDS) processing by calculating the difference between one or more signal level samples and one or more black level samples from each of the plurality of pixel circuits 104 of the pixel array 102. In various embodiments, the extracted image signal and the extracted PDAF signal can be locally stored in the column ALU in the readout circuit 106 and then output to image signal processing. In various embodiments, functional logic 108 can store image data and phase detection autofocus data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others).

[0026] Figure 2 This illustration describes an example of a readout circuit comprising a Gray code generator for extracting and storing various signals and a parallel column ALU, as taught in this disclosure. It should be understood that... Figure 2 The readout circuit 206 can be Figure 1 An example of the readout circuit 106 of the image sensor 100 shown in the figure is illustrated, and similarly named and numbered elements are similarly coupled and operated below.

[0027] like Figure 2 As shown in the example depicted, a portion of the readout circuit 206 includes multiple comparators 216. Each of the multiple comparators 216 is coupled to receive a ramp signal 214, which in one example is a global ramp signal. Each of the multiple comparators 216 is further coupled to a corresponding one of the multiple column bit lines 212 from the image sensor to receive a corresponding analog image or PDAF data signal from a column of the image sensor. As shown in the example, the outputs of the multiple comparators 216 are coupled in parallel to the corresponding column ALU 218. Each of the multiple ALUs 218 is also coupled to receive a Gray code (GC) output 222 generated by a shared Gray code (GC) generator 220, as shown. In one example, the GC output 222 generated by the GC generator 220 is a phase-aligned 13-bit Gray code signal.

[0028] In operation, each of the plurality of comparators 216 is coupled to generate a corresponding comparator output in response to a comparison of a corresponding analog image or PDAF data signal received from a corresponding bit line 212 with a ramp signal 214. In one example, a falling edge occurs at the output of the corresponding comparator 216 when the voltage of the ramp signal 214 slopes down to a value equal to or less than the voltage of the analog image or PDAF data signal carried by the corresponding column bit line 212. In another example, each corresponding column ALU 218 is coupled to sample and hold or latch the 13-bit Gray code signal 222 received from the GC generator 220 when a falling edge occurs at the output of the corresponding comparator 216 coupled to the corresponding column ALU 218. In various examples, each column ALU 218 is then configured to perform Gray code to binary code conversion on the latched GC code signal 222.

[0029] In various instances, column ALU 218 is configured to extract the image signal and the PDAF signal and store the signals locally within the column ALU. By extracting the PDAF signal and storing it locally within the column ALU 218 rather than in an image signal processor outside the column ALU 218, it should be understood that, according to the teachings of this disclosure, digital power consumption is reduced. According to the teachings of this disclosure, in various instances, column ALU 218 can also be coupled to perform correlated double sampling (CDS) operations in parallel by determining the difference between one or more Sample and Hold Reset (SHR) values ​​(which may also be referred to as black level samples in this disclosure) from the corresponding column bit line 212 and one or more Sample and Hold Signal (SHS) samples (which may also be referred to as signal level samples in this disclosure) to generate normalized digital image signals or PDAF data from the image sensor. In one instance, the digital image or PDAF signal data extracted and stored within column ALU 218 can then be output to the corresponding global readout bit line of readout circuit 206.

[0030] In one instance, Figure 2 The portion of the readout circuit 206 shown can be one of multiple portions of the readout circuit 206 that are repeated or "stitched together" across columns of the image sensor array. Figure 2 In the example shown, the image signal output from column ALU 218 can therefore be relayed from "right" to "left" through each part of the readout circuit 206 of column ALU 218, and wherein shift register readout 224 is coupled to the first and last columns and scattered between every N columns of the image sensor array to read out image or PDAF data from the image sensor array. For example, in an example of a 48-megapixel sensor array, there are 8,000 columns. In this example, a single GC generator 220 can be shared between every N=500 columns of the sensor array, such that... Figure 2 The readout circuit 206 shown comprises a total of 16x portions, including shift register readouts 224 coupled to the first and last columns and distributed among every 500 columns to read out image signal outputs from the sensor array. In other words, the shift readout register 224 is coupled to a corresponding ALU 218, which is coupled to the first and last columns of the image sensor. Furthermore, the shift register 224 is coupled to and distributed among multiple ALUs 218 in each of the multiple readout circuits 206 to read out corresponding digital image data signals from the multiple ALUs 218.

[0031] Figure 3A This is a schematic diagram illustrating one example of a portion of the teachings of ALU 318 according to this disclosure. It should be understood that... Figure 3A The portion of ALU 318 depicted in the image can be... Figure 2This is an example of one of the multiple column ALU 218 shown, and similarly named and numbered elements are similarly coupled and operate below. It should also be understood that... Figure 3A The section depicting the ALU 318 illustrates the circuitry for processing one of the bits of the ALU 318. For example, in various instances, it should be noted that each of the plurality of ALUs 318 is coupled to sample and hold or latch the corresponding bit of the received 12-bit Gray code q_gc<11:0> 322 in response to the falling edge of the comparator output cmpout 350 to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 322 into a binary value.

[0032] To illustrate, Figure 3A The example ALU 318 shown includes a front-end latch stage 326 coupled to receive and latch the corresponding bits of the Gray code q_gc<11:0> 322 signal in response to the comparator output cmpout 350. In the illustrated example, each latch of the front-end latch stage 326 has a data input “D” coupled to receive the corresponding bits of the Gray code q_gc<11:0>.

[0033] In one example, ALU 318 also includes a pulse generator 344 coupled to receive comparator output cmpout 350 from a corresponding comparator (e.g., comparator 216) in the column. In one example, pulse generator 344 is coupled to generate a front-end latch enable signal 352 in response to a falling edge arriving at comparator output cmpout 350. In one example, the pulse of front-end latch enable signal 352 is coupled to the enable input of each latch in front-end latch stage 326.

[0034] In the depicted example, ALU 318 also includes a signal latch stage 328 coupled to the output of front-end latch stage 326. In operation, signal latch stage 328 is coupled to latch the output of front-end latch stage 326 in response to signal latch enable signal wen_sig 354. As shown in the depicted example, each latch of signal latch stage 328 includes a data input "D" coupled to the "Q" output of the corresponding latch in front-end latch stage 326.

[0035] Figure 3AThe example shown in the diagram illustrates that the ALU 318 also includes a GC to binary level (e.g., G2B) 330, which is coupled to generate Gray code q_gc latched in the front-end latch level 326. <0> The binary representation of the 322 signal value. In one instance, the GC to binary stage 330 contains multiple XOR gates (not shown), each having a first input coupled to produce a corresponding binary bit output and coupled to receive the corresponding "Q" output of the corresponding latch of the signal latch stage 328.

[0036] like Figure 3A As shown in the illustrated example, the ALU 318 also includes an adder stage 336 comprising a plurality of full adders, each of which has a first input coupled to the output of the GC-to-binary stage 330 and a second input coupled to the output of the adder input multiplexer stage 334, as will be described in more detail below. In operation, the output of the adder stage 336 is generated in response to the first input from the GC-to-binary stage 330 and the second input from the adder input multiplexer stage 334. In one example, the output of the adder stage 336 is configured to determine the difference between the value received at the first input of the adder stage 336 and the value received at the second input.

[0037] continue Figure 3A In the example depicted, ALU 318 further includes an adder input latch stage 332 coupled to latch the GC to the output of binary stage 330. In one example, adder input latch stage 332 includes a first adder input latch 332A configured to latch the GC to the output of binary stage 330 in response to a first adder input latch enable signal wen_1st 356A. In another example, adder input stage 332 includes a second adder input latch 332B configured to latch the GC to the output of binary stage 330 in response to a second adder input latch enable signal wen_2nd 356B. In the depicted example, a first input of adder input multiplexer stage 334 is coupled to receive the output of first adder input latch 332A, and a second input of adder input multiplexer stage 334 is coupled to receive the output of second adder input latch 332B. In operation, the second input of adder stage 336 is coupled to receive the output of either the first adder input latch 332A or the second adder input latch 332B via the output of adder input multiplexer stage 334.

[0038] Figure 3AThe example shown in the illustration indicates that the ALU 318 also includes a data latch stage 340 coupled to latch the output of the adder stage 336. As shown in the illustrated example, the data latch stage 340 includes a first data latch 340A, a second data latch 340B, and a third data latch 340C. As will be discussed in the described example, a first data latch 340A is configured to latch a first phase detection signal (e.g., cdssigL) from the output of adder stage 336 in response to a first data latch enable signal wwl_PDL 364A, a second data latch 340B is configured to latch a second phase detection signal (e.g., cdssigR) from the output of adder stage 336 in response to a second data latch enable signal wwl_PDR 364B, and a third data latch 340C is configured to latch a first summation data signal (e.g., cdssigLR) from the output of adder stage 336 in response to a third data latch enable signal wwl_sum 364C.

[0039] In various instances, it should be understood that the data latch stage 340 includes a PDAF data storage latch 345 coupled to latch PDAF data and an image storage latch 346 coupled to latch image signal data. In an example, the PDAF data storage latch 345 includes a first data latch 340A and a second data latch 340B, and the image storage latch 346 includes a third data latch 340C.

[0040] As previously discussed, in various instances, it should be understood that the pixel array (e.g., pixel array 102) contains pixels (e.g., pixel 104) that include PDAF pixels scattered among the image sensing pixels. Therefore, there are more image sensing pixels than PDAF pixels. Consequently, the image storage latch 346 contains more third data latches 340C than the first data latches 340A and second data latches 340B in the PDAF data storage latch 345. In one instance, the data latch stage 340 contains three first data latches 340A and three second data latches 340B for every twelve third data latches 340C.

[0041] To illustrate, Figure 3AThe example depicted shows a first data latch 340A ("3 bits"), a second data latch 340B ("3 bits"), and a third data latch 340C ("3 bits x 4") in a data latch stage 340. In this example, the data itself is 12 bits and divided into 4 x 3 bits, depicting the storage distribution. In a four-column example of a 4x8 pixel area with a pixel array (e.g., pixel array 102), for the four analog-to-digital converters at the top, the storage provided by the data latches 340 includes 4 x 3 bits provided by the third data latch 340C for image signal data, plus 3 bits provided by the first data latch 340A for PDAF "left" data, plus 3 bits provided by the second data latch 340B for PDAF "right" data. In other words, it should be understood that the PDAF data storage latch 345 can be shared among multiple columns of the pixel array (e.g., pixel array 102).

[0042] Figure 3B Explanation based on the teachings of this disclosure Figure 3A This is an example of the timing of various analog-to-digital conversion (ADC) operations and storage of extracted signals in the example arithmetic logic unit 318. Specifically, Figure 3B This demonstrates a sequence of three ADC operations: a first ADC operation 349A, a second ADC operation 349B, and a third ADC operation 349C. In this example, the second ADC operation 349B occurs after the first ADC operation 349A, and the third ADC operation 349C occurs after the second ADC operation 349B.

[0043] In this example, the ADC operation of the black signal (e.g., blk) occurs during the first ADC operation 349A. Therefore, after the first ADC operation 349A completes and before the second ADC operation 349B begins, the Gray code representation q_gc<11:0> 322 of the black signal (e.g., blk) is latched in the signal latch stage 328, and the binary representation of the black signal (e.g., blk) is latched in the first adder input latch 332A of the adder input latch stage 332 in response to the first adder input latch enable signal wen_1st 356A.

[0044] During the second ADC operation 349B, the ADC operation of the left signal (e.g., sigL) occurs. Therefore, after the second ADC operation 349B completes and before the third ADC operation 349C begins, the Gray code representation q_gc<11:0> 322 of the left signal (e.g., sigL) is latched in the signal latch stage 328, and the binary representation of the left signal (e.g., sigL) is latched in the second adder input latch 332B of the adder input latch stage 332 in response to the second adder input latch enable signal wen_2nd 356B. Additionally, the binary representation of the left signal (e.g., sigL) is also received by the first input of the adder stage 336. In this example, the adder input multiplexer stage 334 is configured such that the black signal (e.g., blk) latched in the first adder input latch 332A is coupled to be received by the second input of the adder stage 336 through the first input of the adder input multiplexer stage 334. Thus, when the left signal (e.g., sigL) is at the first input of the adder stage 336 and when the black signal (e.g., blk) is at the second input of the adder stage 336, the correlated double-sampled (CDS) left signal (e.g., cdssigL) is coupled to be latched in the first data latch 340A of the data latch stage 340 through the output of the adder stage 336 in response to the first data latch enable signal wwl_PDL 364A. In this example, the CDS left signal (e.g., cdssigL) is equal to the difference between the first and second inputs of the adder stage 336 (e.g., sigL - blk).

[0045] During the third ADC operation 349C, ADC operation of the left-right signal (e.g., sigLR) occurs. Therefore, during ADC operation 349C, the left-right signal is coupled to be latched in signal latch stage 328 and received by the first input of adder stage 336. Specifically, the Gray code representation q_gc<11:0> 322 of the left-right signal (e.g., sigLR) is latched in signal latch stage 328, and the binary representation of the left-right signal (e.g., sigLR) is coupled to be received by the first input of adder stage 336. In an example, adder input multiplexer stage 334 is configured such that the left signal (e.g., sigL) latched in the second adder input latch 332B is coupled to be received by the second input of adder stage 336 via the second input of adder input multiplexer stage 334. Therefore, when the left-right signal (e.g., sigLR) is at the first input of adder stage 336 and when the left signal (e.g., sigL) is at the second input of adder stage 336, the CDS right signal (e.g., cdssigR) is coupled to be latched in the second data latch 340B of data latch stage 340 via the output of adder stage 336 in response to the second data latch enable signal wwl_PDR 364B. In an example, the CDS right signal (e.g., cdssigR) is equal to the difference between the first and second inputs of adder stage 336 (e.g., sigLR - sigL).

[0046] Continuing with the third ADC operation 349C, after the CDS right signal (e.g., cdssigR) is latched in the second data latch 340B, the adder input multiplexer stage 334 is configured such that the black signal (e.g., blk) latched in the first adder input latch 332A is coupled to be received by the second input of adder stage 336 through the first input of adder input multiplexer stage 334. Therefore, when the left-right signal (e.g., sigLR) is at the first input of adder stage 336 and when the black signal (e.g., blk) is at the second input of adder stage 336, the CDS left-right signal (e.g., cdssigLR) is coupled to be latched in the third data latch 340C of data latch stage 340 through the output of adder stage 336 in response to the third data latch enable signal wwl_sum 364C. In this example, the CDS left-right signal (e.g., cdssigLR) is equal to the difference between the first and second inputs of adder stage 336 (e.g., sigLR-blk).

[0047] In various examples, it should be understood that the CDS left signal (e.g., cdssigL) latched in the first data latch 340A, the CDS right signal (e.g., cdssigR) latched in the second data latch 340B, and the CDS left-right signal (e.g., cdssigLR) latched in the third data latch 340C can be output from ALU 318 as output bit rbl<11:0> 347 via output switches rwl_pdl 343A, rwl_pdr 343B, and rwl_cdssig 343C, respectively, as shown.

[0048] Figure 4A This is a schematic diagram illustrating another example of a portion of one of the various ALU 418s taught according to this disclosure. It should be understood that... Figure 4A The portion of ALU 418 depicted in the image can be... Figure 2 This is another instance of one of the multiple column ALU 218 shown, and the similarly named and numbered elements described above are similarly coupled and operate below. It should also be understood that... Figure 4A The part depicted in the image of ALU 418 is similar to... Figure 3A The ALU 318 described in the text shares many similarities. For example, in various instances, it should be noted that each of the multiple ALUs 418 is coupled to sample and hold or latch the corresponding bits of the received 12-bit Gray code q_gc<11:0> 422 in response to the falling edge reaching the comparator output cmpout 450 to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 422 into a binary value.

[0049] As shown in the illustrated example, the ALU 418 includes a front-end latch stage 426 coupled to receive and latch the corresponding bits of the Gray code q_gc<11:0> 422 signal in response to the comparator output cmpout 450. In the illustrated example, each latch of the front-end latch stage 426 has a data input “D” coupled to receive the corresponding bits of the Gray code q_gc<11:0>.

[0050] In one example, ALU 418 also includes a pulse generator 444 coupled to receive comparator output cmpout 450 from a corresponding comparator (e.g., comparator 216) in the column. In one example, pulse generator 444 is coupled to generate a front-end latch enable signal 452 in response to a falling edge arriving at comparator output cmpout 450. In one example, the pulse of front-end latch enable signal 452 is coupled to the enable input of each latch in front-end latch stage 426.

[0051] In the depicted example, ALU 418 also includes a signal latch stage 428 coupled to the output of front-end latch stage 426. In operation, signal latch stage 428 is coupled to latch the output of front-end latch stage 426 in response to signal latch enable signal wen_sig 454. As shown in the depicted example, each latch of signal latch stage 428 includes a data input "D" coupled to the "Q" output of the corresponding latch in front-end latch stage 426.

[0052] Figure 4A The example shown in the diagram illustrates that the ALU 418 also includes a GC to binary level (e.g., G2B) 430, which is coupled to produce Gray code q_gc latched in the front-end latch level 426. <0> The binary representation of the 422 signal value. In one instance, the GC to binary stage 430 contains multiple XOR gates (not shown), each having a first input coupled to produce a corresponding binary bit output and coupled to receive the corresponding "Q" output of the corresponding latch of the signal latch stage 428.

[0053] like Figure 4A As shown in the illustrated example, the ALU 418 also includes an adder stage 436 comprising a plurality of full adders, each of which has a first input coupled to the output of the GC-to-binary stage 430 and a second input coupled to the output of the adder input multiplexer stage 434, as will be described in more detail below. In operation, the output of the adder stage 436 is generated in response to the first input from the GC-to-binary stage 430 and the second input from the adder input multiplexer stage 434. In one example, the output of the adder stage 436 is configured to determine the difference between the value received at the first input of the adder stage 436 and the value received at the second input.

[0054] Figure 4A ALU 418 and Figure 3A One difference between ALU 318 is Figure 4A The ALU 418 also includes a feedback multiplexer stage 451. For example... Figure 4A As shown in the example depicted, the feedback multiplexer stage 451 includes a first feedback multiplexer 451A having a first input coupled to the output of the GC to the binary stage 430 and a second input coupled to the output of the adder stage 436. As shown, the feedback multiplexer stage 451 also includes a second feedback multiplexer 451B having a first input coupled to the output of the GC to the binary stage 430 and a second input coupled to the output of the adder stage 436.

[0055] continue Figure 4AIn the example depicted, ALU 418 further includes an adder input latch stage 432 coupled to latch the GC to the output of binary stage 430 or adder stage 436 via feedback multiplexer stage 451. In one example, adder input latch stage 432 includes a first adder input latch 422A configured to latch the GC to the output of binary stage 430 or adder stage 436 in response to a first adder input latch enable signal wen_1st 456A. ​​In another example, adder input stage 432 also includes a second adder input latch 432B configured to latch the GC to the output of binary stage 430 or adder stage 436 in response to a second adder input latch enable signal wen_2nd 456B. In the depicted example, the first input of adder input multiplexer stage 434 is coupled to receive the output of first adder input latch 432A, and the second input of adder input multiplexer stage 434 is coupled to receive the output of second adder input latch 432B. In operation, the second input of adder stage 436 is coupled to receive the output of either first adder input latch 432A or second adder input latch 432B via the output of adder input multiplexer stage 434.

[0056] Figure 4A The example shown in the diagram illustrates that the ALU 418 also includes a data latch stage 440 coupled to latch the output of the adder stage 436. It should be understood that... Figure 4A Data latch stage 440 and Figure 3A The data latch stage 340 shares many similarities. For example, as Figure 4A As illustrated in the example, data latch stage 440 includes a first data latch 440A, a second data latch 440B, and a third data latch 440C. In this example, the first data latch 440A is configured to latch a first phase detection signal (e.g., cdssigL) from the output of adder stage 436 in response to a first data latch enable signal wwl_PDL 464A; the second data latch 440B is configured to latch a second phase detection signal (e.g., cdssigR) from the output of adder stage 436 in response to a second data latch enable signal wwl_PDR 464B; and the third data latch 440C is configured to latch a first summed data signal (e.g., cdssigL + cdssigR) from the output of adder stage 436 in response to a third data latch enable signal wwl_sum 464C.

[0057] In various instances, it should be understood that the data latch stage 440 includes a PDAF data storage latch 445 coupled to latch PDAF data and an image storage latch 446 coupled to latch image signal data. In an example, the PDAF data storage latch 445 includes a first data latch 440A and a second data latch 440B, and the image storage latch 446 includes a third data latch 440C.

[0058] In the depicted example, it should be understood that the image storage latch 446 contains more third data latches 440C than the first data latches 440A and second data latches 440B in the PDAF data storage latch 445. In one example, the data latch stage 440 comprises three first data latches 440A and three second data latches 440B for every twelve third data latches 440C.

[0059] Similar to Figure 3A The examples described in Figure 4A The example depicted shows a first data latch 440A ("3 bits"), a second data latch 440B ("3 bits"), and a third data latch 440C ("3 bits x 4") in a data latch stage 440. In this example, the data itself is 12 bits and divided into 4 x 3 bits, depicting the storage distribution. In a four-column example of a 4x8 pixel area with a pixel array (e.g., pixel array 102), for the four analog-to-digital converters at the top, the storage provided by the data latch 440 includes 4 x 3 bits provided by the third data latch 440C for image signal data, plus 3 bits provided by the first data latch 440A for PDAF "left" data, plus 3 bits provided by the second data latch 440B for PDAF "right" data. In other words, it should be understood that the PDAF data storage latch 445 can be shared among multiple columns of the pixel array (e.g., pixel array 102).

[0060] Figure 4B Explanation based on the teachings of this disclosure Figure 4A This is another example of the timing of various analog-to-digital conversion (ADC) operations and storage of extracted signals in the example arithmetic logic unit 418. Specifically, Figure 4B This demonstrates a sequence of four ADC operations: a first ADC operation 449A, a second ADC operation 449B, a third ADC operation 449C, and a fourth ADC operation 449D. In this example, the second ADC operation 449B occurs after the first ADC operation 449A, the third ADC operation 449C occurs after the second ADC operation 449B, and the fourth ADC operation 449D occurs after the third ADC operation 449C.

[0061] In this example, the ADC operation of the left black signal (e.g., blkL) occurs during the first ADC operation 449A. Therefore, after the first ADC operation 449A completes and before the second ADC operation 449B begins, the Gray code representation q_gc<11:0> 422 of the left black signal (e.g., blkL) is latched in the signal latch stage 428, and the binary representation of the black signal (e.g., blkL) is latched through the first input of the first feedback multiplexer 451A and in response to the first adder input latch enable signal wen_1st 456A in the first adder input latch stage 432.

[0062] During the second ADC operation 449B, the ADC operation of the left signal (e.g., sigL) occurs. Therefore, after the second ADC operation 449B completes and before the third ADC operation 449C begins, the Gray code representation q_gc<11:0> 422 of the left signal (e.g., sigL) is latched in the signal latch stage 428, and the binary representation of the left signal (e.g., sigL) is coupled to be received at the first input of the adder stage 436. In this example, the adder input multiplexer stage 434 is configured such that the left black signal (e.g., blkL) latched in the first adder input latch 432A is coupled to be received by the second input of the adder stage 436 through the first input of the adder input multiplexer stage 434. Therefore, when the left signal (e.g., sigL) is at the first input of adder stage 436 and when the left black signal (e.g., blkL) is at the second input of adder stage 436, the correlated double-sampled (CDS) left signal (e.g., cdssigL) is coupled to be latched in the first data latch 440A of data latch stage 440 via the output of adder stage 436 in response to the first data latch enable signal wwl_PDL 464A. In this example, the CDS left signal (e.g., cdssigL) is equal to the difference between the first and second inputs of adder stage 436 (e.g., sigL - blkL). Additionally, the CDS left signal (e.g., cdssigL) is also latched in the second adder input latch 432B of adder input latch stage 432 via the second input of the second feedback multiplexer 451B and in response to the second adder input latch enable signal wen_2nd 456B.

[0063] During the third ADC operation 449C, the ADC operation of the right black signal (e.g., blkR) occurs. Therefore, during ADC operation 449C, the right black signal is coupled and latched in signal latch stage 428 and received by the first input of adder stage 436. Specifically, the Gray code representation q_gc<11:0> 422 of the right black signal (e.g., blkR) is latched in signal latch stage 428, and the binary representation of the right black signal (e.g., blkR) is coupled and received by the first input of adder stage 436. In an example, adder input multiplexer stage 434 is configured such that the CDS left signal (e.g., cdssigL) latched in the second adder input latch 432B is coupled and received by the second input of adder stage 436 via the second input of adder input multiplexer stage 434. Therefore, when the right black signal (e.g., blkR) is at the first input of adder stage 436 and when the CDS left signal (e.g., cdssigL) is at the second input of adder stage 436, the difference between the right black signal and the CDS left signal (e.g., blkR-cdssigL) is coupled to the first data latch 440A of data latch stage 440 in response to the second data latch enable signal wwl_PDR 464B, through the output of adder stage 436 and through the second input of the first feedback multiplexer 451A.

[0064] Continuing with the third ADC operation 449C, after the difference between the right black signal and the CDS left signal (e.g., blkR-cdssigL) is latched in the first adder input latch 432A, the right black signal (e.g., blkR) is latched in the second adder input latch 432B through the first input of the second feedback multiplexer 451B.

[0065] During the fourth ADC operation 449D, the ADC operation of the right signal occurs. Therefore, during ADC operation 449D, the right signal (e.g., sigR) is coupled to be latched in signal latch stage 428 and received by the first input of adder stage 436. Specifically, the Gray code representation q_gc<11:0> 422 of the right signal (e.g., sigR) is latched in signal latch stage 428, and the binary representation of the right signal (e.g., sigR) is coupled to be received by the first input of adder stage 436. In an example, adder input multiplexer stage 434 is configured such that the difference (e.g., blkR - cdssigL) between the right black signal latched in the first adder input latch 432A and the CDS left signal is coupled to be received by the second input of adder stage 436 through the first input of adder input multiplexer stage 434. Therefore, when the right signal (e.g., sigR) is at the first input of adder stage 436 and when the difference between the right black signal and the CDS left signal (e.g., blkR - cdssigL) is at the second input of adder stage 436, the difference between the right signal (e.g., sigR) and the difference between the right black signal and the CDS left signal (e.g., blkR - cdssigL) (which is equal to sigR - (blkR - cdssigL), which is equal to the CDS left - right signal (e.g., cdssigL + cdssigR)) is coupled to be latched in the third data latch 440C of data latch stage 440 through the output of adder stage 436.

[0066] Continuing with the fourth ADC operation 449D, after the CDS left-right signals (e.g., cdssigL + cdssigR) are latched in the third data latch 440C, the right black signal (e.g., blkR) latched in the second adder input latch 432B is coupled to be received at the second input of adder stage 436 via the second input of adder input multiplexer stage 434. Therefore, when the right signal (e.g., sigR) is at the first input of adder stage 436 and when the right black signal (e.g., blkR) is at the second input of adder stage 436, the difference between the right signal and the right black signal (e.g., sigR - blkR) (which is equal to the CDS right signal (e.g., cdssigR)) is coupled to be latched in the second data latch 440B of data latch stage 440 via the output of adder stage 436.

[0067] In various examples, it should be understood that the CDS left signal (e.g., cdssigL) latched in the first data latch 440A, the CDS right signal (e.g., cdssigR) latched in the second data latch 440B, and the CDS left-right signal (e.g., cdssigL+cdssigR) latched in the third data latch 440C can be output from ALU 418 as output bit rbl<11:0> 447 via output switches rwl_pdl 443A, rwl_pdr 443B, and rwl_cdssig 443C, respectively, as shown.

[0068] Figure 5A This is a schematic diagram illustrating yet another example of a portion of one of the various ALU 518s taught according to this disclosure. It should be understood that... Figure 5A The portion of ALU 518 depicted in the image can be... Figure 2 This is yet another example of one of the multiple column ALU 218 shown, and the similarly named and numbered elements described above are similarly coupled and operate below. It should also be understood that... Figure 5A The part depicted in the image of ALU 518 is similar to... Figure 4A The portion of ALU 418 depicted and / or related to Figure 3A The ALU 318s depicted share many similarities. For example, in various instances, it should be noted that each of the multiple ALUs 518s is coupled to sample and hold or latch the corresponding bits of the received 12-bit Gray code q_gc<11:0> 522 in response to the falling edge reaching the comparator output cmpout 550 to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 522 into a binary value.

[0069] As shown in the illustrated example, the ALU 518 includes a front-end latch stage 526 coupled to receive and latch the corresponding bits of the Gray code q_gc<11:0> 522 signal in response to the comparator output cmpout 550. In the illustrated example, each latch in the front-end latch stage 526 has a data input “D” coupled to receive the corresponding bits of the Gray code q_gc<11:0>.

[0070] In one example, ALU 518 also includes a pulse generator 544 coupled to receive comparator output cmpout 550 from a corresponding comparator (e.g., comparator 216) in the column. In one example, pulse generator 544 is coupled to generate a front-end latch enable signal 552 in response to a falling edge arriving at comparator output cmpout 550. In one example, the pulse of front-end latch enable signal 552 is coupled to the enable input of each latch in front-end latch stage 526.

[0071] In the depicted example, ALU 518 also includes a signal latch stage 528 coupled to the output of front-end latch stage 526. In operation, signal latch stage 528 is coupled to latch the output of front-end latch stage 526 in response to signal latch enable signal wen_sig 554. As shown in the depicted example, each latch of signal latch stage 528 includes a data input "D" of the corresponding "Q" output of the latches in front-end latch stage 526.

[0072] Figure 5A The example shown in the diagram illustrates that the ALU 518 also includes a GC to binary level (e.g., G2B) 530, which is coupled to generate Gray code q_gc latched in the front-end latch level 526. <0> The binary representation of the 522 signal value. In one instance, the GC to binary level 530 contains multiple XOR gates (not shown), each of which has an output coupled to produce the corresponding binary bit and an input coupled to receive the corresponding "Q" output of the corresponding latch of the signal latch level 528.

[0073] like Figure 5A As shown in the illustrated example, the ALU 518 also includes an adder stage 536 comprising a plurality of full adders, each of which has a first input coupled to the output of the GC-to-binary stage 530 and a second input coupled to the output of the adder input multiplexer stage 534, as will be described in more detail below. In operation, the output of the adder stage 536 is generated in response to the first input from the GC-to-binary stage 530 and the second input from the adder input multiplexer stage 534. In one example, the output of the adder stage 536 is configured to determine the difference between the value received at the first input of the adder stage 536 and the value received at the second input.

[0074] continue Figure 5A As depicted in the example, the ALU 518 further includes an adder input latch stage 532 coupled to latch the output of the GC to the binary stage 530. Figure 5A ALU 518 and Figure 3A One difference between ALU 318 is Figure 5A The adder input latch stage 532 contains three adder input latches. For example, as... Figure 5AAs shown in the example depicted, the adder input latch stage 532 includes: a first adder input latch 532A configured to latch GC to the output of binary stage 530 in response to a first adder input latch enable signal wen_1st 556A; a second adder input latch 532B configured to latch GC to the output of binary stage 530 in response to a second adder input latch enable signal wen_2nd 556B; and a third adder input latch 532C configured to latch GC to the output of binary stage 530 in response to a third adder input latch enable signal wen_3rd 556C. In the depicted example, the first input of adder input multiplexer stage 534 is coupled to receive the output of first adder input latch 532A, the second input of adder input multiplexer stage 534 is coupled to receive the output of second adder input latch 532B, and the third input of adder input multiplexer stage 534 is coupled to receive the output of third adder input latch 532C. In operation, the second input of adder stage 536 is coupled to receive the output of one of the first adder input latch 532A, the second adder input latch 532B, or the third adder input latch 532C via the output of adder input multiplexer stage 534.

[0075] Figure 5A The example shown in the diagram illustrates that the ALU 518 also includes a data latch stage 540 coupled to latch the output of the adder stage 536. It should be understood that... Figure 5A The data latch stage 540 also has Figure 4A Data latch stage 440 and / or Figure 3A The data latch stage 340 shares many similarities. For example, as Figure 5A As shown in the example depicted, the data latch stage 540 includes a first data latch 540A, a second data latch 540B, and a third data latch 540C. Figure 5A Data latch stage 540 and Figure 4A Data latch level 440 or Figure 3A One difference between the data latch stages 340 is Figure 5A The data latch stage 540 further includes a fourth data latch 540D.

[0076] In this example, a first data latch 540A is configured to latch the high conversion gain (HCG) CDS left signal (e.g., HCGcdssigL) from the output of adder stage 536 in response to a first data latch enable signal wwl_PDL 564A; a second data latch 540B is configured to latch the HCG CDS right signal (e.g., HCGcdssigR) from the output of adder stage 536 in response to a second data latch enable signal wwl_PDR 564B; a third data latch 540C is configured to latch the HCG CDS left-right signal (e.g., HCGcdsLR) from the output of adder stage 536 in response to a third data latch enable signal wwl_hcg 564C; and a fourth data latch 540D is configured to latch the LCG from the output of adder stage 536 in response to a fourth data latch enable signal wwl_lcg 564D. CDS left-right signals (e.g., LCGcdsLR).

[0077] In various instances, it should be understood that the data latch stage 540 includes a PDAF data storage latch 545 coupled to latch PDAF data and an image storage latch 546 coupled to latch image signal data. In an example, the PDAF data storage latch 545 includes a first data latch 540A and a second data latch 540B, and the image storage latch 546 includes a third data latch 540C and a fourth data latch 540D.

[0078] In the depicted examples, it should be understood that the image storage latch 546 contains more third data latches 540C and fourth data latches 540D than the first data latches 540A and second data latches 540B in the PDAF data storage latch 545. For example, in one example, the data latch stage 540 comprises three first data latches 540A or three second data latches 540B for every twelve third data latches 540C or every twelve fourth data latches 540D. In another example, the data latch stage 540 comprises three first data latches 540A and three second data latches 540B for every twelve third data latches 540C and every twelve fourth data latches 540D.

[0079] Similar to Figure 3A and 4A The examples described in Figure 5AThe example depicted shows a data latch stage 540 containing a first data latch 540A (3 bits), a second data latch 540B (3 bits), a third data latch 540C (3 bits x 4), and a fourth data latch 540D (3 bits x 4). In this example, the data itself is 12 bits and divided into 4 x 3 bits, depicting the storage distribution. In an 8-column example with a pixel array (e.g., pixel array 102) of 4 x 8 pixel areas, for 4 up-to-down analog-to-digital converters and 4 down-to-up-to-digital converters, the storage provided by the data latch 540 includes 4 x 3 bits provided by the third data latch 540C or the fourth data latch 540D, plus 1 x 3 bits provided by the first data latch 540A for HCG CDS left PDAF data or by the second data latch 540B for HCG CDS right PDAF data. Therefore, it should be understood that the PDAF data storage latch 545 can be shared among multiple columns of a pixel array (e.g., pixel array 102).

[0080] Figure 5B Explanation based on the teachings of this disclosure Figure 5A This is yet another example of the timing of analog-to-digital conversion and storage of various extracted signals in the example arithmetic logic unit 518. Specifically, Figure 5B This demonstrates a sequence of five ADC operations: a first ADC operation 549A, a second ADC operation 549B, a third ADC operation 549C, a fourth ADC operation 549D, and a fifth ADC operation 549E. In this example, the second ADC operation 549B occurs after the first ADC operation 549A, the third ADC operation 549C occurs after the second ADC operation 549B, the fourth ADC operation 549D occurs after the third ADC operation 549C, and the fifth ADC operation 549E occurs after the fourth ADC operation 549D.

[0081] In this example, the ADC operation of the low conversion gain (LCG) black signal (e.g., LCGblk) occurs during the first ADC operation 549A. Therefore, after the first ADC operation 549A completes and before the second ADC operation 549B begins, the Gray code representation q_gc<11:0> 522 of the LCG black signal (e.g., LCGblk) is latched in the signal latch stage 528, and the binary representation of the LCG black signal (e.g., LCGblk) is latched in the first adder input latch 532A of the adder input latch stage 532 in response to the first adder input latch enable signal wen_1st 556A.

[0082] During the second ADC operation 549B, the ADC operation of the high conversion gain (HCG) black signal (e.g., HCGblk) occurs. Therefore, after the second ADC operation 549B completes and before the third ADC operation 549C begins, the Gray code representation q_gc<11:0> 522 of the HCG black signal (e.g., HCGblk) is latched in the signal latch stage 528, and the binary representation of the HCG black signal (e.g., HCGblk) is latched in the second adder input latch 532B of the adder input latch stage 532 in response to the second adder input latch enable signal wen_2nd 556B.

[0083] During the third ADC operation 549C, the ADC operation of the HCG left signal (e.g., HCGsigL) occurs. Therefore, after the third ADC operation 549C completes and before the fourth ADC operation 549D begins, the Gray code representation q_gc<11:0> 522 of the HCG left signal (e.g., HCGsigL) is latched in the signal latch stage 528, and the binary representation of the HCG left signal (e.g., HCGsigL) is latched in the third adder input latch 532C of the adder input latch stage 532 in response to the third adder input latch enable signal wen_3rd 556C and coupled to be received at the first input of the adder stage 536. In this example, the adder input multiplexer stage 534 is configured such that the HCG black signal (e.g., HCGblk) latched in the second adder input latch 532B is coupled to be received by the second input of the adder stage 536 through the second input of the adder input multiplexer stage 534. Thus, when the HCG left signal (e.g., HCGsigL) is at the first input of the adder stage 536 and when the HCG black signal (e.g., HCGblk) is at the second input of the adder stage 536, the HCG correlated double sample (CDS) left signal (e.g., HCGcdsL) is coupled to be latched in the first data latch 540A of the data latch stage 540 through the output of the adder stage 536 in response to the first data latch enable signal wwl_PDL 564A. In this example, the left signal of HCG CDS (e.g., HCGcdsL) is equal to the difference between the first and second inputs of adder stage 536 (e.g., HCGsigL-HCGblk).

[0084] During the fourth ADC operation 549D, the ADC operation of the HCG left-right signal (e.g., HCGsigLR) occurs. Therefore, during the fourth ADC operation 549D, the HCG left-right signal (e.g., HCGsigLR) is coupled and latched in signal latch stage 528 and received by the first input of adder stage 536. Specifically, the Gray code representation q_gc<11:0> 522 of the HCG left-right signal (e.g., HCGsigLR) is latched in signal latch stage 528, and the binary representation of the HCG left-right signal (e.g., HCGsigLR) is coupled and received at the first input of adder stage 536. In this example, the adder input multiplexer stage 534 is configured such that the HCG left signal (e.g., HCGsigL) latched in the third adder input latch 532C of the adder input latch stage 532 is coupled to be received by the second input of the adder stage 536 through the third input of the adder input multiplexer stage 534. Thus, when the HCG left-right signal (e.g., HCGsigLR) is at the first input of the adder stage 536 and when the HCG left signal (e.g., HCGsigL) is at the second input of the adder stage 536, the HCG correlated double sample (CDS) right signal (e.g., HCGcdsR) is coupled to be latched in the second data latch 540B of the data latch stage 540 through the output of the adder stage 536 in response to the second data latch enable signal wwl_PDR 564B. In this example, the right signal of HCG CDS (e.g., HCGcdsR) is equal to the difference between the first and second inputs of adder stage 536 (e.g., HCGsigLR - HCGsigL).

[0085] Continuing with the fourth ADC operation 549D, after the HCG CDS right signal (e.g., HCGcdsR) is latched in the second data latch 540B, the adder input multiplexer stage 534 is configured such that the HCG black signal (e.g., HCGblk) latched in the second adder input latch 532B is coupled to be received by the second input of the adder stage 536 through the second input of the adder input multiplexer stage 534. Therefore, when the HCG left-right signal (e.g., HCGsigLR) is at the first input of adder stage 536 and when the HCG black signal (e.g., HCGblk) is at the second input of adder stage 536, the HCG correlated double sample (CDS) left-right signal (e.g., HCGcdsLR) is coupled to the third data latch 540C of data latch stage 540 via the output of adder stage 536 in response to the third data latch enable signal wwl_hcg 564C. In this example, the HCG CDS left-right signal (e.g., HCGcdsLR) is equal to the difference between the first and second inputs of adder stage 536 (HCGsigLR - HCGblk).

[0086] During the fifth ADC operation 549E, ADC operation of the low conversion gain (LCG) left-right signal (e.g., LCGsigLR) occurs. Therefore, after the fifth ADC operation 549E completes, the Gray code representation q_gc<11:0> 522 of the LCG left-right signal (e.g., LCGsigLR) is latched in the signal latch stage 528, and the binary representation of the LCG left-right signal (e.g., LCGsigLR) is coupled to be received at the first input of the adder stage 536. In this example, the adder input multiplexer stage 534 is configured such that the LCG black signal (e.g., LCGblk) latched in the first adder input latch 532A is coupled to be received by the second input of the adder stage 536 through the first input of the adder input multiplexer stage 534. Therefore, when the LCG left-right signal (e.g., LCGsigLR) is at the first input of adder stage 536 and when the LCG black signal (e.g., LCGblk) is at the second input of adder stage 536, the LCG correlated double sample (CDS) left-right signal (e.g., LCGcdsLR) is coupled to be latched in the fourth data latch 540D of data latch stage 540 via the output of adder stage 536 in response to the fourth data latch enable signal wwl_lcg 564D. In this example, the LCG CDS left-right signal (e.g., LCGcdsLR) is equal to the difference between the first and second inputs of adder stage 536 (e.g., LCGsigLR - LCGblk).

[0087] In various examples, it should be understood that the HCG CDS left signal (e.g., HCGcdsL) latched in the first data latch 540A, the HCG CDS right signal (e.g., HCGcdsR) latched in the second data latch 540B, the HCG CDS left-right signal (e.g., HCGcdsLR) latched in the third data latch 540C, and the LCG CDS left-right signal (e.g., LCGcdsLR) latched in the fourth data latch 540D can be output from ALU 518 as output bit rbl<11:0> 547 via output switches rwl_pdl 543A, rwl_pdr 543B, rwl_cdssig_hcg 543C, and rwl_cdssig_lcg 543D, respectively, as shown.

[0088] The foregoing description of the examples illustrated in the embodiments (including those described in the specification summary) is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific examples of the embodiments have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the embodiments.

[0089] These modifications can be made to the embodiments in light of the detailed description above. The terminology used in the appended claims should not be construed as limiting the embodiments to the specific instances disclosed in the specification. Rather, the scope of the embodiments will be fully defined by the appended claims, which should be interpreted according to the established principles of claim interpretation.

Claims

1. An arithmetic logic unit (ALU), comprising: A front-end latch stage, coupled to a Gray code GC generator, latches the GC output of the GC generator in response to the comparator output; A signal latch stage, which is coupled to latch the output of the front-end latch stage in response to a signal latch enable signal; The GC is converted to a binary level, which is coupled to produce a binary representation of the GC output latched in the signal latch stage; An adder stage comprising a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC to the binary stage, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; An adder input latch stage, coupled to latch the output of the GC to the binary stage, wherein the adder input latch stage includes: A first adder input latch, configured to latch the GC to the binary-level output in response to a first adder input latch enable signal; and A second adder input latch, configured to latch the GC to the binary output in response to a second adder input latch enable signal; and An adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the output of a first adder input latch, wherein a second input of the adder input multiplexer stage is coupled to receive the output of a second adder input latch, and wherein the second input of the adder stage is coupled to receive the output of the adder input multiplexer stage.

2. The ALU of claim 1, further comprising a pulse generator coupled to the comparator output to generate a front-end latch enable signal in response to an analog-to-digital ADC operation on a signal from the pixel array, wherein the front-end latch stage is coupled to latch the GC output of the GC generator in response to the front-end latch enable signal.

3. The ALU of claim 2, further comprising a data latch stage coupled to latch the output of the adder stage, wherein the data latch stage comprises: A first data latch is configured to latch a first phase detection signal from the output of the adder stage in response to a first data latch enable signal; A second data latch is configured to latch a second phase detection signal from the output of the adder stage in response to a second data latch enable signal; and A third data latch is configured to latch a first summed data signal from the output of the adder stage in response to a third data latch enable signal.

4. The ALU according to claim 3, wherein the number of latches included in the data latch stage is as follows: for every 12 third data latches, there are 3 first data latches and 3 second data latches.

5. The ALU of claim 3, wherein the data latch stage further includes a fourth data latch configured to latch a second summing data signal from the output of the adder stage in response to a fourth data latch enable signal.

6. The ALU according to claim 5, wherein the number of latches included in the data latch stage is such that for every 12 third data latches or every 12 fourth data latches, there are 3 first data latches or 3 second data latches.

7. The ALU according to claim 5, wherein the number of latches included in the data latch stage is as follows: for every 12 third data latches and every 12 fourth data latches, there are 3 first data latches and 3 second data latches.

8. The ALU of claim 3, wherein the ADC operation is one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, the black signal is coupled to be latched in the signal latch stage and latched in the first adder input latch of the adder input latch stage.

9. The ALU of claim 8, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: The left signal is coupled and latched in the signal latch stage, latched in the second adder input latch of the adder input latch stage, and received by the first input of the adder stage. The black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The relevant double-sampled CDS left signal is coupled to be latched in the first data latch of the data latch stage via the output of the adder stage.

10. The ALU of claim 9, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: The left-plus-right signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The left signal is coupled to be received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The CDS right signal is coupled to be latched in the second data latch of the data latch stage via the output of the adder stage.

11. The ALU of claim 10, wherein after the CDS right signal is latched in the second data latch of the data latch stage: The left-plus-right signal is coupled to be received by the first input of the adder stage. The black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The CDS left and right signals are coupled to be latched in the third data latch of the data latch stage via the output of the adder stage.

12. The ALU of claim 3, wherein the ALU further comprises a feedback multiplexer stage, wherein the feedback multiplexer stage comprises: A first feedback multiplexer has a first input coupled to the output of the GC-to-binary stage and a second input coupled to the output of the adder stage, wherein the first adder input latch is further configured to latch the output of the GC-to-binary stage or the output of the adder stage. and A second feedback multiplexer has a first input coupled to the output of the GC-to-binary stage and a second input coupled to the output of the adder stage, wherein the second adder input latch is further configured to latch the output of the GC-to-binary stage or the output of the adder stage.

13. The ALU of claim 12, wherein the ADC operation is one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, the left black signal is coupled to be latched in the signal latch stage and latched in the first adder input latch of the adder input latch stage via the first input of the first feedback multiplexer of the feedback multiplexer stage.

14. The ALU of claim 13, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: The left signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The left black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The relevant double-sampled CDS left signal is coupled to be latched in the first data latch of the data latch stage through the output of the adder stage and to be latched in the second adder input latch of the adder input latch stage through the second input of the second feedback multiplexer of the feedback multiplexer stage.

15. The ALU of claim 14, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: The right black signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The CDS left signal is coupled to be received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The difference signal between the right black signal and the CDS left signal is coupled to be latched in the first adder input latch of the adder input latch stage via the second input of the first feedback multiplexer of the feedback multiplexer stage and via the output of the adder stage.

16. The ALU of claim 15, wherein after the difference signal between the right black signal and the CDS left signal is coupled to be latched in the first adder input latch of the adder input latch stage, the right black signal is coupled to be latched in the second adder input latch of the adder input latch stage via the first input of the second feedback multiplexer of the feedback multiplexer stage.

17. The ALU of claim 16, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the right black signal is coupled to be latched in the second adder input latch of the adder input latch stage, wherein after the fourth ADC operation: The right signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The difference signal between the right black signal and the CDS left signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The CDS left and right signals are coupled to be latched in the third data latch of the data latch stage via the output of the adder stage.

18. The ALU of claim 17, wherein after the CDS left plus right signal is latched in the third data latch of the data latch stage: The right black signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The CDS right signal is coupled to be latched in the second data latch of the data latch stage via the output of the adder stage.

19. The ALU of claim 5, wherein the adder input latch stage further includes a third adder input latch configured to latch the output of the GC to the binary stage in response to a third adder input latch enable signal, wherein a third input of the adder input multiplexer stage is coupled to receive the output of the third adder input latch.

20. The ALU of claim 19, wherein the ADC operation is one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, the low conversion gain LCG black signal is coupled to be latched in the signal latch stage and latched in the first adder input latch of the adder input latch stage.

21. The ALU of claim 20, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation, the high conversion gain HCG black signal is coupled to be latched in the signal latch stage and latched in the second adder input latch of the adder input latch stage.

22. The ALU of claim 21, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: The HCG left signal is coupled and latched in the signal latch stage, latched in the third adder input latch of the adder input latch stage, and received by the first input of the adder stage. The HCG black signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The HCG CDS left signal is coupled to be latched in the first data latch of the data latch stage via the output of the adder stage.

23. The ALU of claim 22, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the third ADC operation, wherein after the fourth ADC operation: The HCG left-plus-right signals are coupled and latched in the signal latch stage and received by the first input of the adder stage. The HCG left signal is coupled to be received by the second input of the adder stage through the third input of the adder input multiplexer stage, and The HCG CDS right signal is coupled to be latched in the second data latch of the data latch stage via the output of the adder stage.

24. The ALU of claim 23, wherein after the HCG CDS right signal is latched in the second data latch of the data latch stage: The HCG black signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The HCG CDS left and right signals are coupled to be latched in the third data latch of the data latch stage via the output of the adder stage.

25. The ALU of claim 24, wherein after the HCG CDS left plus right signals are latched in the third data latch of the data latch stage: The LCG left-plus-right signals are coupled and latched in the signal latch stage and received by the first input of the adder stage. The LCG black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The LCG CDS left and right signals are coupled to be latched in the fourth data latch of the data latch stage via the output of the adder stage.

26. An imaging system comprising: A pixel array comprising a plurality of pixel circuits arranged in rows and columns, each of the plurality of pixel circuits being coupled to generate an analog image data signal in response to incident light; A control circuit system coupled to the pixel array to control the operation of the pixel array; and A readout circuit, coupled to the pixel array via a plurality of column bit lines, wherein the readout circuit includes: A plurality of comparators, wherein each of the plurality of comparators is coupled to receive a ramp signal, wherein each of the plurality of comparators is further coupled to a corresponding of a plurality of column lines to receive a corresponding analog image data signal, wherein each of the plurality of comparators is coupled to generate a corresponding comparator output in response to a comparison of the corresponding analog image data signal with the ramp signal. Gray code GC generator, which is coupled to produce GC output; and A plurality of arithmetic logic units (ALUs), each of which is coupled to receive the GC output, each of which is further coupled to a corresponding of a plurality of comparators to receive the corresponding comparator output, wherein each of the plurality of ALUs comprises: A front-end latch stage, coupled to the GC generator, latches the GC output of the GC generator in response to the corresponding comparator output; A signal latch stage, which is coupled to latch the output of the front-end latch stage in response to a signal latch enable signal; The GC is converted to a binary level, which is coupled to produce a binary representation of the GC output latched in the signal latch stage; An adder stage comprising a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC to the binary stage, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; An adder input latch stage, coupled to latch the output of the GC to the binary stage, wherein the adder input latch stage includes: A first adder input latch, configured to latch the GC to the binary-level output in response to a first adder input latch enable signal; and A second adder input latch, configured to latch the GC to the binary output in response to a second adder input latch enable signal; and An adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the output of a first adder input latch, wherein a second input of the adder input multiplexer stage is coupled to receive the output of a second adder input latch, and wherein the second input of the adder stage is coupled to receive the output of the adder input multiplexer stage.

27. The imaging system of claim 26, further comprising functional logic circuitry coupled to the readout circuitry to store the image data read from the pixel array.

28. The imaging system of claim 26, wherein each of the plurality of ALUs includes a pulse generator coupled to the respective comparator output to generate a front-end latch enable signal in response to an analog-to-digital ADC operation on a signal from the pixel array, wherein the front-end latch stage is coupled to latch the GC output of the GC generator in response to the front-end latch enable signal.

29. The imaging system of claim 28, wherein each of the plurality of ALUs includes a data latch stage coupled to latch the output of the adder stage, wherein the data latch stage includes: A first data latch is configured to latch a first phase detection signal from the output of the adder stage in response to a first data latch enable signal; A second data latch is configured to latch a second phase detection signal from the output of the adder stage in response to a second data latch enable signal; and A third data latch is configured to latch a first summed data signal from the output of the adder stage in response to a third data latch enable signal.

30. The imaging system according to claim 29, wherein the number of latches included in the data latch stage is such that for every 12 third data latches, there are 3 first data latches and 3 second data latches.

31. The imaging system of claim 29, wherein the data latch stage further includes a fourth data latch configured to latch a second summed data signal from the output of the adder stage in response to a fourth data latch enable signal.

32. The imaging system according to claim 31, wherein the number of latches included in the data latch stage is such that for every 12 third data latches or every 12 fourth data latches, there are 3 first data latches or 3 second data latches.

33. The imaging system according to claim 31, wherein the number of latches included in the data latch stage is such that for every 12 third data latches and every 12 fourth data latches, there are 3 first data latches and 3 second data latches.

34. The imaging system of claim 29, wherein the ADC operation is one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, the black signal is coupled to be latched in the signal latch stage and latched in the first adder input latch of the adder input latch stage.

35. The imaging system of claim 34, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: The left signal is coupled and latched in the signal latch stage, latched in the second adder input latch of the adder input latch stage, and received by the first input of the adder stage. The black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The relevant double-sampled CDS left signal is coupled to be latched in the first data latch of the data latch stage via the output of the adder stage.

36. The imaging system of claim 35, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: The left-plus-right signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The left signal is coupled to be received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The CDS right signal is coupled to be latched in the second data latch of the data latch stage via the output of the adder stage.

37. The imaging system of claim 36, wherein after the CDS right signal is latched in the second data latch of the data latch stage: The left-plus-right signal is coupled to be received by the first input of the adder stage. The black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The CDS left and right signals are coupled to be latched in the third data latch of the data latch stage via the output of the adder stage.

38. The imaging system of claim 29, wherein each of the plurality of ALUs further comprises a feedback multiplexer stage, wherein the feedback multiplexer stage comprises: A first feedback multiplexer has a first input coupled to the output of the GC-to-binary stage and a second input coupled to the output of the adder stage, wherein the first adder input latch is further configured to latch the output of the GC-to-binary stage or the output of the adder stage. and A second feedback multiplexer has a first input coupled to the output of the GC-to-binary stage and a second input coupled to the output of the adder stage, wherein the second adder input latch is further configured to latch the output of the GC-to-binary stage or the output of the adder stage.

39. The imaging system of claim 38, wherein the ADC operation is one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, the left black signal is coupled to be latched in the signal latch stage and latched in the first adder input latch stage via the first input of the first feedback multiplexer of the feedback multiplexer stage.

40. The imaging system of claim 39, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: The left signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The left black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The relevant double-sampled CDS left signal is coupled to be latched in the first data latch of the data latch stage through the output of the adder stage and to be latched in the second adder input latch of the adder input latch stage through the second input of the second feedback multiplexer of the feedback multiplexer stage.

41. The imaging system of claim 40, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: The right black signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The CDS left signal is coupled to be received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The difference signal between the right black signal and the CDS left signal is coupled to be latched in the first adder input latch of the adder input latch stage via the second input of the first feedback multiplexer of the feedback multiplexer stage and via the output of the adder stage.

42. The imaging system of claim 41, wherein after the difference signal between the right black signal and the CDS left signal is coupled to be latched in the first adder input latch of the adder input latch stage, the right black signal is coupled to be latched in the second adder input latch of the adder input latch stage via the first input of the second feedback multiplexer of the feedback multiplexer stage.

43. The imaging system of claim 42, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the right black signal is coupled to be latched in the second adder input latch of the adder input latch stage, wherein after the fourth ADC operation: The right signal is coupled and latched in the signal latch stage and received by the first input of the adder stage. The difference signal between the right black signal and the CDS left signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The CDS left and right signals are coupled to be latched in the third data latch of the data latch stage via the output of the adder stage.

44. The imaging system of claim 43, wherein after the CDS left plus right signals are latched in the third data latch of the data latch stage: The right black signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The CDS right signal is coupled to be latched in the second data latch of the data latch stage via the output of the adder stage.

45. The imaging system of claim 31, wherein the adder input latch stage further includes a third adder input latch configured to latch the output of the GC to the binary stage in response to a third adder input latch enable signal, wherein a third input of the adder input multiplexer stage is coupled to receive the output of the third adder input latch.

46. ​​The imaging system of claim 45, wherein the ADC operation is one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, the low conversion gain LCG black signal is coupled to be latched in the signal latch stage and latched in the first adder input latch of the adder input latch stage.

47. The imaging system of claim 46, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation, the high conversion gain HCG black signal is coupled to be latched in the signal latch stage and latched in the second adder input latch of the adder input latch stage.

48. The imaging system of claim 47, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: The HCG left signal is coupled and latched in the signal latch stage, latched in the third adder input latch of the adder input latch stage, and received by the first input of the adder stage. The HCG black signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The HCG CDS left signal is coupled to be latched in the first data latch of the data latch stage via the output of the adder stage.

49. The imaging system of claim 48, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the third ADC operation, wherein after the fourth ADC operation: The HCG left-plus-right signals are coupled and latched in the signal latch stage and received by the first input of the adder stage. The HCG left signal is coupled to be received by the second input of the adder stage through the third input of the adder input multiplexer stage, and The HCG CDS right signal is coupled to be latched in the second data latch of the data latch stage via the output of the adder stage.

50. The imaging system of claim 49, wherein after the HCG CDS right signal is latched in the second data latch of the data latch stage: The HCG black signal is coupled so that it is received by the second input of the adder stage through the second input of the adder input multiplexer stage, and The HCG CDS left and right signals are coupled to be latched in the third data latch of the data latch stage via the output of the adder stage.

51. The imaging system of claim 50, wherein after the HCG CDS left plus right signals are latched in the third data latch of the data latch stage: The LCG left-plus-right signals are coupled and latched in the signal latch stage and received by the first input of the adder stage. The LCG black signal is coupled so that it is received by the second input of the adder stage through the first input of the adder input multiplexer stage, and The LCG CDS left and right signals are coupled to be latched in the fourth data latch of the data latch stage via the output of the adder stage.

Images