DRAM with analog refresh loop

Abstract

A dynamic random access memory (DRAM) device (100, 200) includes a plurality of DRAM cells (202), control circuitry (104), and an analog arithmetic logic unit (aALU - 114, 232, 300, 400). The DRAM cells include respective storage capacitors (204) configured to be charged to respective voltages. The control circuitry is configured to read a voltage from a target DRAM cell and refresh the target DRAM cell using a refresh voltage derived from the read voltage. The aALU is configured to derive the refresh voltage from the read voltage by performing an analog operation such that the refresh voltage approximates a voltage previously written to the target DRAM cell.

Description

[0001] Cross-reference to related applications This application claims the benefit of U.S. Provisional Patent Application 63 / 547,690, filed November 8, 2023, the disclosure of which is incorporated herein by reference.

[0002] Invention Field This invention relates generally to dynamic random access memory (DRAM), and more particularly to refresh operations in DRAM. Background of the Invention Dynamic Random Access Memory (DRAM) is a high-efficiency memory technology that uses small-area capacitors as storage elements. Multilevel DRAM further improves storage efficiency by storing multiple bits per capacitor without significantly increasing cell size.

[0004] Background techniques for multilevel DRAM can be found, for example, in "Design and Characterization of a Multilevel DRAM" by Koob et al. (IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 19, No. 9, September 2011), where the authors describe a multilevel DRAM (MLDRAM) that uses reference cell signals and data cell signals generated in a cell array using charge sharing. A single-step sensing method uses multiple reference signals in parallel. The authors go on to describe an operable 19200-cell MLDRAM test chip in a 1.8V, 180nm mixed-signal CMOS, which allows operation of 1 bit, 1.5 bits, 2 bits, 2.25 bits, and 2.5 bits per cell using 2, 3, 4, 5, and 6 data signal levels, respectively.

[0005] In Liu et al.’s “A Multi-Level DRAM with Fast Read and Low Power Consumption” (2005 IEEE Workshop on Microelectronics and Electron Devices, 2005 - WMED '05), the authors proposed a multi-level DRAM design that can store three voltage levels (0, Vcc, and Vcc / 2) in a single memory cell without requiring a special reference voltage, thus simplifying the design of peripheral circuitry.

[0006] Finally, U.S. Patent 5,612,912 discloses a multilevel DRAM in which one of a plurality of voltage levels can be stored in each memory cell. In a four-level system, each of a pair of bit lines is divided into two sub-bit lines, which are connected to a corresponding sense amplifier. Dummy cells matching the memory cell are provided on each sub-bit line to balance the capacitance. The stored voltage is dumped onto the left and right sub-bit lines, which are then isolated, and one of the voltages is sensed to provide the sign bit. A second reference level is generated by dumping the charge associated with the sign bit onto the three sub-bit lines, and this reference level is used to sense the magnitude bit. The stored voltage is recovered by charge sharing between the sign bit charge on two bit lines and the magnitude bit charge on one bit line. Invention Overview Embodiments of the present invention described herein provide a dynamic random access memory (DRAM) device including a plurality of DRAM cells, control circuitry, and an analog arithmetic logic unit (aALU). The DRAM cells include corresponding storage capacitors configured to be charged to a corresponding voltage. The control circuitry is configured to read a voltage from a target DRAM cell and refresh the target DRAM cell using a refresh voltage derived from the read voltage. The aALU is configured to derive the refresh voltage from the read voltage by performing an analog operation such that the refresh voltage approximates the voltage previously written to the target DRAM cell.

[0008] In some embodiments, one or more DRAM cells are used as one or more reference DRAM cells, which are programmed to have one or more corresponding reference voltages, and the aALU is configured to derive the refresh voltage of the target DRAM cell based on (i) the voltage read from the target DRAM cell, (ii) one or more voltages read from the one or more reference DRAM cells, and (iii) the time elapsed since the voltage was previously written to the target DRAM cell.

[0009] In the disclosed embodiments, aALU includes: (i) one or more reference sampling capacitors configured to store one or more sampled reference DRAM cell voltages, and (ii) a data sampling capacitor configured to store sampled target DRAM data voltages.

[0010] In an example embodiment, the aALU includes a voltage ratio amplifier configured to generate a refresh voltage by multiplying one of one or more reference voltages by the ratio between the corrected target DRAM cell voltage and the corresponding corrected reference DRAM cell voltage among one or more corrected reference DRAM cell voltages, thereby mitigating the decay of the target DRAM cell.

[0011] In some embodiments, the aALU includes a differential amplifier configured to: (i) amplify the difference between the precharge voltage and the data read voltage by the inverse of the charge-shared attenuation factor to generate a corrected target DRAM cell voltage for the target DRAM cell; and (ii) amplify one or more differences between the precharge voltage and one or more reference read voltages by the inverse of the charge-shared attenuation factor to generate one or more corrected reference DRAM cell voltages for one or more reference DRAM cells.

[0012] In an embodiment, the aALU is configured to generate a refresh voltage by adding the product of the following to a first reference voltage among one or more reference voltages: (i) a DRAM cell degradation metric, and (ii) the difference between a corrected first reference voltage among one or more corrected reference voltages and a corresponding first reference voltage among one or more reference voltages, thereby compensating for additive noise induced on the storage capacitor.

[0013] In an example embodiment, aALU is configured to calculate a DRAM cell degradation metric by dividing the difference between a first reference voltage and a second reference voltage by the difference between a corrected first reference voltage and a corrected second reference voltage.

[0014] In some embodiments, the aALU includes a differential amplifier configured to amplify the difference between the precharge voltage and the voltage read from the target DRAM cell, and the aALU is configured to generate a corrected target DRAM cell voltage based on the analog output of the differential amplifier.

[0015] In an embodiment, when deriving the refresh voltage from the read voltage, the aALU is configured to compensate for one or more of the following: (i) process variations affecting the DRAM device, (ii) variations associated with the power supply voltage of the DRAM device, and (iii) variations associated with the temperature of the DRAM device.

[0016] According to an embodiment of the present invention, an analog dynamic random access memory (analog DRAM) device is further provided, which includes a plurality of storage capacitors configured to store charges representing a continuous range of continuously defined analog values.

[0017] According to embodiments of the present invention, a method is also provided, the method comprising operating a plurality of dynamic random access memory (DRAM) cells, each DRAM cell including a corresponding storage capacitor configured to be charged to a corresponding voltage. Using control circuitry, a voltage is read from a target DRAM cell, and a refresh voltage derived from the read voltage is used to refresh the target DRAM cell. Using an analog arithmetic logic unit (aALU), the refresh voltage is derived from the read voltage by performing an analog operation such that the refresh voltage approximates the voltage previously written to the target DRAM cell.

[0018] The invention will be more fully understood from the following detailed description of embodiments thereof, taken in conjunction with the accompanying drawings, in which: Brief description of the attached diagram Figure 1 This is a block diagram schematically illustrating a dynamic random access memory (DRAM) device including an analog refresh circuit according to an embodiment of the present invention; Figure 2 This is a block diagram illustrating, in more detail, the architecture of a DRAM device including an analog refresh circuit according to an embodiment of the present invention; Figure 3 This is a block diagram schematically illustrating an analog arithmetic logic unit (aALU) circuit according to an embodiment of the present invention; Figure 4 This is a block diagram schematically illustrating a dual-reference aALU circuit according to an embodiment of the present invention; Figure 5 This is a timing diagram illustrating the waveform of the write sequence according to an embodiment of the present invention; Figure 6 This is a refresh timing diagram schematically illustrating the waveform of the refresh sequence according to an embodiment of the present invention; Figure 7 The embodiments of the present invention are schematically shown in Figure 4 Functional stage block diagram of the operation of the voltage ratio amplifier used in the aALU; Figure 8A The embodiments of the present invention are schematically shown for implementation. Figure 7 Block diagram of a logarithmic amplifier for voltage ratio amplifiers; Figure 8B The embodiments of the present invention are schematically shown for implementation. Figure 7 Block diagram of the voltage ratio amplifier and the anti-sigma amplifier; Figure 9 This is a flowchart illustrating, schematically, a method for analog-only refresh of a multilevel DRAM according to an embodiment of the present invention; Figure 10 This is a block diagram schematically illustrating two packet arrays in a DRAM device including an analog refresh circuit, according to an embodiment of the present invention; and Figure 11 This is a block diagram schematically illustrating a 6-bank DRAM device including an analog refresh circuit according to an embodiment of the present invention. Detailed Implementation

[0019] Overview Dynamic random access memory (DRAM), in which data is stored on capacitors (“storage capacitors”), is essential for modern computing and is used as the primary type of memory in most devices due to its cost-effectiveness and high storage capacity. DRAM with storage capacities exceeding 10Gb is available today, and capacity is expected to increase further in the future.

[0020] An inherent drawback of DRAM technology is capacitor leakage (typically leaking into the substrate). This leakage causes the stored voltage to decay over time. To address this drawback, DRAM devices typically include a refresh mechanism that periodically reads and refreshes all stored capacitors. Refreshing can also be performed as part of a user-initiated read operation.

[0021] The embodiments of the invention disclosed herein provide apparatus and methods for simulating DRAM, wherein each storage capacitor is configured to store an analog value representing one or more encoded binary bits of data. In embodiments, the simulated DRAM includes an analog-only refresh circuit that reads analog data stored on a target storage capacitor, calculates the pre-fading voltage on the storage capacitor using an analog arithmetic logic unit (aALU), and then accurately refreshes the target storage capacitor to compensate for any fixed bias that may be included in the read analog data.

[0022] The high accuracy of analog refresh circuits is useful, for example, for storing multiple bits in each storage capacitor with high reliability. Therefore, the embodiments described below primarily relate to multilevel DRAM (theoretically, the number of levels and thus the number of bits stored is unlimited; in practice, this number is set by parameters such as capacitor size, voltage, and signal-to-noise ratio). However, the disclosed techniques are not limited to multilevel storage and can also be used for single-level DRAM storing one bit per capacitor.

[0023] The use of only analog refresh circuits provides significant power savings because analog-to-digital conversion and digital-to-analog conversion are only required when the DRAM device is read or written separately. Furthermore, the large serial output registers typically used in DRAM for fast I / O can be saved.

[0024] In one embodiment, to read the storage capacitor, the analog DRAM device couples a selected target storage capacitor to a common line connected to an aALU. The aALU includes a first stage for compensating for voltage attenuation caused by charge sharing between the storage capacitor and the common line.

[0025] To improve accuracy, in some embodiments disclosed below, each column of DRAM storage capacitors (or more precisely, each group of DRAM storage capacitors in each DRAM column) includes one or more reference storage capacitors storing a preset reference voltage. In one embodiment, a group of DRAM cells including one or more reference storage capacitors are read sequentially. One or more reference storage capacitors are read first, and their voltages are corrected by a first aALU level and stored in one or more correction reference voltage capacitors. Each of the subsequent data storage capacitors is read sequentially, and its voltage is corrected by the first aALU level and stored in a correction data voltage capacitor.

[0026] In one embodiment, the aALU includes a second stage that calculates the pre-degradation voltage of the data storage capacitor based on the voltage stored on the correction data voltage capacitor and the voltage stored on one or more correction reference voltage capacitors. In another embodiment, the aALU estimates the degradation based on the degradation of a reference memory cell; in some embodiments, the degradation of the difference between the two reference voltages is used to estimate the degradation of the target data storage capacitor.

[0027] In one embodiment, the second stage of the aALU includes a nonlinear voltage ratio amplifier. In some embodiments, the voltage ratio amplifier includes logarithmic and anti-logarithmic circuits; in other embodiments, the voltage ratio amplifier includes a voltage-controlled variable resistor. Other embodiments of the voltage ratio amplifier are disclosed in the system description below.

[0028] In some embodiments, as part of the process of deriving the refresh voltage from the read voltage, the aALU can also compensate for process-voltage-temperature (PVT) variations, i.e., process variations affecting the DRAM device, variations associated with the power supply voltage of the DRAM device, and / or variations associated with the temperature of the DRAM device. PVT compensation can be performed, for example, as part of the device's built-in self-test (BIST) process and / or during production.

[0029] System Description Multilevel dynamic random access memory (DRAM) has been proposed in the past, where each storage capacitor can store more than one bit of information. While potentially offering higher storage density, multilevel storage presents challenges; in particular, refreshing multilevel charges using analog-to-digital and then digital-to-analog processes can consume significant amounts of energy. The embodiments disclosed herein use a purely analog refresh cycle that does not involve analog-to-digital or digital-to-analog conversion and does not corrupt the stored data (e.g., it guarantees that worst-case refresh inaccuracies will not change the digital value of the stored data). No digital-to-analog (DAC) converters and analog-to-digital (ADC) converters are required in the subsystem analog domain level, and the DAC and ADC converters are only used to interface the analog domain to the system-level digital domain. The large digital output registers present in conventional DRAM are not required.

[0030] Nibble and word In an embodiment, a multi-level DRAM cell stores more than one bit of data; for example, if the noise level allows for the safe use of eight levels (e.g., the distance between the storage capacitor voltages for any two adjacent levels is safely below the maximum expected noise), then each DRAM cell can store three data bits.

[0031] A set of bits stored in a DRAM cell is referred to below as a nibble (not to be confused with the strict 4-bit nibble often used in the industry). In the example embodiment, the nibble size is 8 bits.

[0032] On the other hand, the typical width of a digital DRAM word can be 4 bits, 8 bits, or 16 bits (or more bits when error correction codes are added to each word). In other examples, the word size can be smaller than a nibble; in one example, an 8-bit nibble can store a pair of 4-bit I and Q values ​​in a communication system.

[0033] The difference in width can be addressed by a variety of techniques, which are beyond the scope of this disclosure. For example, in order to store a 16-bit word in a 4-bit nibble, the digital input can be divided into four nibbles, which are input to four identical 16-level DRAMs; then, the digital output is a cascade of nibbles output from the four 16-level DRAM cells.

[0034] In the following description, we will ignore the difference between word size and nibble size, and will only describe nibble-sized DRAM devices. However, the disclosed techniques are by no means limited to nibble-width data words in which the data word size is the same as the number of bits stored in each DRAM cell; any other suitable data word size may be used in embodiments.

[0035] Rows, columns and groups Similar to common DRAM technology and terminology, we assume below that DRAM comprises one or more DRAM memory banks; each DRAM memory bank comprises horizontal rows that are connected to the gates of the corresponding row of select transistors. Vertically, each DRAM memory bank comprises columns that are further divided into vertical groups; each group is connected to the source of the select transistor in that vertical group. These groups are connected to the corresponding columns via group select devices.

[0036] For ease of understanding, the vertical and horizontal orientations defined above can be changed in some of the following figures, which are not necessarily layout orientations (we will specify the orientations in the description).

[0037] Figure 1 This is a block diagram schematically illustrating a dynamic random access memory (DRAM) device 100 according to an embodiment of the present invention. DRAM 100 includes a memory array 102, which in turn includes a plurality of DRAM cells, each DRAM cell including a memory capacitor charged to a voltage level representing a digital word. In embodiments, at any given time, some DRAM cells (referred to as "data DRAM cells") may store DRAM data, while other DRAM cells (referred to as "reference DRAM cells") may store reference data. In some embodiments, the partitioning of data DRAM cells and reference DRAM cells is fixed; for example, in an embodiment, the memory array comprises a matrix of rows and columns (which are further divided into groups); the central DRAM cell of each group is a reference DRAM cell (however, in an embodiment, the reference DRAM cell is read before the data DRAM cell is read). In other embodiments, the partitioning of data DRAM cells and reference DRAM cells may change dynamically.

[0038] DRAM 100 also includes control circuitry 104, which controls write, read, and refresh operations of the DRAM cells. In an embodiment, the control circuitry controls switches (e.g., transistors, not shown) of the memory array 102; the switches are configured to selectively couple storage capacitors to data lines 108. In an embodiment, various coupling circuits may be used, including, for example, combinations of column and group selection.

[0039] For DRAM write operations, the control circuit activates buffer 110, and buffer 110 writes a voltage level V. 写入 (For example, the voltage generated by the digital-to-analog converter (DAC)) is transmitted to the data line 108; the control circuit also connects the selected data DRAM cell to the data line, so that the corresponding storage capacitor is charged according to the write voltage.

[0040] For DRAM refresh operations, the control circuit first reads the target DRAM cell (the read operation will be described below), and then activates the transmission refresh voltage level V. 刷新 The buffer 112 (described below) connects the selected data DRAM cell to the data line; thus, the selected target storage capacitor is charged according to the refresh voltage.

[0041] To read the charge stored on the storage capacitor, control circuit 104 selects the corresponding DRAM cell but does not activate either buffer 110 or 112. As a result, charge sharing occurs between the charge stored on the storage capacitor and the charge stored on the data line 108 (in this embodiment, the control circuit may pre-charge the data line to a preset pre-charge voltage before reading). Hereinafter, we will refer to the voltage on the data line after the read operation as V08. 读取 .

[0042] DRAM 100 also includes an analog arithmetic logic unit (aALU) 114, which is configured to receive V 读取 Voltage, and in response generate V 刷新 Voltage. In this embodiment, the refresh voltage V 刷新 This ensures that when written to the storage capacitor (by control circuit 104), the original charge on the storage capacitor prior to the read operation is nearly restored. In some embodiments, in order to generate V 刷新 The control circuit also reads one or more reference DRAM cells, and the aALU responds to the voltage V when a reference DRAM cell is read. 读取 Generate V 刷新 (This will be described in detail below).

[0043] In the embodiment, V is generated by aALU 114. 刷新 Only analog operations are included to achieve higher speed and better accuracy (good accuracy of read refresh cycles, such as those achieved through analog operations, is crucial because DRAM should maintain data integrity over long periods of time).

[0044] In an embodiment, for a DRAM read operation, the output of aALU 114 is coupled to an analog-to-digital converter (ADC), which converts multi-level voltages into digital words.

[0045] It was referenced through an example. Figure 1 The configuration of the DRAM device 100 shown and described above is illustrated. Other configurations may be used in alternative embodiments. For example, in one embodiment, multiple data lines are used and multiple V values ​​are configured to be generated concurrently. 刷新 The voltage-controlled aALU can simultaneously write to and read from multiple DRAM cells.

[0046] Figure 2 This is a block diagram schematically illustrating the architecture of a DRAM device 200 according to an embodiment of the present invention. Figure 2 In the illustrated example embodiment, DRAM device 200 includes a two-dimensional array of DRAM cells 202, each DRAM cell including a storage capacitor 204 and a selection transistor 206. The two-dimensional array includes a plurality of DRAM columns 201, each column 201 including a plurality of groups 214. It should be noted that... Figure 2 The orientation is mixed—vertical groups 214 are drawn horizontally, while vertical columns 201 are drawn vertically. In this embodiment, both groups and columns are vertical, using different metal layers.

[0047] Capacitor 204 can be a gate-source capacitor, metal-insulator-metal (MIM) capacitor, or intrinsic capacitor used in some modern capacitor-free technologies.

[0048] Control circuit (e.g., control circuit 104, Figure 1 The control circuit is configured to drive a set of column select lines 208 and a set of group select lines 210. To couple the Xth storage capacitor to data line 212 (where X represents the column number), the control circuit activates the Xth column select line (e.g., sets it to logic high) and deactivates all other column select lines (e.g., sets them to logic low). Simultaneously, the control circuit (based on the group of the Xth column) activates one of the group select lines 210 and deactivates all other group select lines.

[0049] Each column select line 208 is connected to the gate of a single select transistor 206 of DRAM column 201. When a column select line is activated, the selected memory capacitor is coupled to group line 214. Each group select line 210 is connected to the gate of group select transistor 216, which is configured to connect the selected group line 214 to data line (column) 212.

[0050] To write data to a selected DRAM cell 202, a digital-to-analog converter (DAC) 218 ​​first converts the data to be written (assuming a half-byte size, as described above) into an analog value. The analog value is forwarded via transistor 220 to a buffer (e.g., a unity-gain amplifier) ​​222 and a drive enable transistor 224, reaching the data line 212, and from the data line 212 to the selected storage capacitor 204 via a group select transistor 216 (selected according to the active group select line 210) and a select transistor 206 (selected according to the active column select line 208). Thus, the voltage on bit line 210 charges the selected storage capacitor.

[0051] To read data from a selected DRAM cell 202, the precharge transistor 226 charges (or discharges) the data line 212 via the refresh / read transistor 228, the buffer 222, and the drive enable transistor 224. The control circuitry activates one of the group select lines 210 but not any of the column select lines 208; therefore, the selected group line 214 is precharged via the corresponding group select transistor 216. In the subsequent clock phase, the control circuitry activates one of the column select lines 208, connecting the storage capacitor of the selected DRAM cell (via one of the select transistors 206) to the corresponding group line 214, and from there (via the activated group select transistor 216) to the data line 212.

[0052] In an embodiment, the source voltage of the precharge transistor 226 can be varied (e.g., set during device calibration), thereby allowing precharging or pre-discharging to any voltage.

[0053] The coupling of the selected storage capacitor with line 214 and data line 212 will result in charge sharing, thereby reducing the storage capacitor voltage (or more precisely, the difference between the pre-charge voltage and the storage capacitor voltage) according to the capacitance ratio: V 读出 = V pc + (V sc -V pc )*C sc / (C sc +C rl +C dl +C p ) in: V 读出 It is the voltage on the data line after charge sharing; V pc It is the pre-charge voltage; V sc It is the initial voltage on the storage capacitor before charge sharing; C sc It is the capacitance of the storage capacitor; C rl It is the capacitor of the selected group of lines 214; C dl It's the capacitor in data cable 212; and C p These are additional parasitic capacitances (e.g., the capacitance of transistors 206 and 216).

[0054] After charge sharing, the voltage on data line 212 is input to analog arithmetic logic unit (aALU) 232 via sensing transistor 230. aALU 232 is configured to compensate for charge sharing decay and to compensate for the decay of stored charge over time (see below). Figure 3 and Figure 4 Two example embodiments of aALU 232 are disclosed. The voltage generated by aALU 232 is input to analog-to-digital converter (ADC) 234, which is configured to convert the aALU output into a digital nibble representing the output of DRAM.

[0055] To refresh the target DRAM cell, the control circuit first performs a read cycle as described above, and then in the subsequent clock phase, routes the output of aALU 232 to data line 212 via refresh transistor 236, refresh / read transistor 228, buffer 222 and drive enable transistor 224, and there via a selected group select transistor 216 and a selected column select transistor 206 to the target storage capacitor of the DRAM cell being refreshed.

[0056] It should be noted that the control circuit 104 is configured to activate switching transistors 220, 228, 236, 224, 230, 206, and 216 and pre-charge transistor 226 according to the above-described functions and a timing scheme. This timing scheme ensures sample charging time while avoiding contention. The following will refer to... Figure 5 and Figure 6 Describe some timing examples.

[0057] In some embodiments, each DRAM group is written / read / refreshed sequentially. Each DRAM group includes one or more reference DRAM cells that are close in time to the data DRAM cells being read (but before the data DRAM cells are read) (e.g., if the DRAM group is accessed from left to right, the reference DRAM cell may be the leftmost DRAM cell in the group; in another example, the reference DRAM cell may be located in the center of the DRAM group or elsewhere in the group, but is accessed first).

[0058] This allows the aALU to accurately compensate for degradation of the storage capacitors (as will be referenced below). Figure 3 and Figure 4 (As explained).

[0059] It should be noted that the DRAM device 200 includes other circuitry not described above, such as column and group decoders, and sometimes includes error detection and correction circuitry.

[0060] It was referenced through an example. Figure 2The configuration of the DRAM device 200 shown and described above is illustrated. Other configurations may be used in alternative embodiments. For example, in some embodiments, buffer 222 is not required. In other embodiments, the DRAM device includes multiple memory banks; all memory banks are continuously refreshed, but for read and write operations, only selected memory banks are activated.

[0061] Example of simulated ALU configuration Figure 3 This is a block diagram schematically illustrating an aALU circuit 300 according to an embodiment of the present invention. This aALU can be used, for example, to implement aALU 114 (… Figure 1 ) or aALU 232 ( Figure 2 ).

[0062] Figure 3 The aALU includes linear amplifier 302, V s Sampling transistor 304, V ref Sampling transistor 306, V s Storage capacitor 308, V ref Storage capacitor 310 and voltage ratio amplifier 312.

[0063] As mentioned above, after charge sharing, the voltage across the storage capacitor (as read on the data line) decays: (1) in: V DL It is the voltage on the data line after charge sharing; V PC It is the pre-charge voltage; V S It is the voltage on the storage capacitor before charge sharing; C S It is the capacitance of the storage capacitor; and C DL It is a combination capacitor of data lines, row lines, group lines, and any parasitic capacitances of shared charges.

[0064] Linear amplifier 302 is configured to compensate for this attenuation, and through (C DL +C S ) / C S Amplification difference V S -V PC Then subtract V pc To obtain V S .

[0065] The purpose of the voltage ratio amplifier 312 is to compensate for charge decay over time. For this purpose, each DRAM bank includes a reference memory cell that is charged to a known voltage level V.REF We assume that the decay ratios of the data DRAM cells and the reference DRAM cells are the same. This assumption should be accurate if the structure and decay time of the reference DRAM cells and the data DRAM cells are closely matched; the first assumption is based on the same drawing layout and the geometric proximity of the cells; the latter assumption is reasonable because the entire row (including all its groups) is precharged and then read in an uninterrupted sequence.

[0066] When the voltage V on the data line DL It is V ref (V refers to the voltage after the DRAM cell is read) ref The sampling transistor 306 is turned on, and the Vref storage capacitor 310 stores the attenuated voltage V. ref-s When the voltage on the data line is V Si (Voltage after each data DRAM cell is read) s Sampling transistor 304 is turned on, and V ref (t) Storage capacitor 310 stores the attenuated compensated voltage V s (ti).

[0067] The voltages across both the data storage capacitor and the reference storage capacitor begin to decay after they are written to; therefore, we specify the voltages across capacitors 308 and 310 as V, respectively. s and V ref(t) (Capacitor 310 is configured to maintain a compensated reference voltage when the data DRAM cells in this group are read).

[0068] Assuming exponential decay with equal time constants, and assuming that both the reference DRAM cell and the data DRAM cell have the same decay time, we obtain: (2) Where V REF It is the initial voltage on the reference DRAM cell, and: (3) Where V SI(0) It is the initial voltage on the i-th data DRAM cell.

[0069] The voltage ratio amplifier 312 is configured to compensate for degradation and by increasing V REF The voltage V is generated by multiplying by the ratio of the voltages across capacitors 308 and 310. Si (0): (4) Figure 3The configuration of the aALU 300 shown and described above is relatively simple, requiring a single reference voltage V. REF (In the example embodiment, V) REF Set to the maximum value V S (half of the original). However, the noise immunity of the aALU 300 is worse than that of the dual-reference voltage embodiment disclosed below.

[0070] Figure 4 This is a block diagram schematically illustrating a dual-reference aALU circuit 400 according to an embodiment of the present invention. The dual-reference aALU circuit 400 can also be used, for example, to implement aALU 114 (…). Figure 1 ) or aALU 232 ( Figure 2 ).

[0071] The dual-reference aALU uses two reference voltages, which are stored in two reference DRAM cells within the same DRAM bank. In an embodiment, the first reference cell (denoted as a MINV-DRAM cell) is charged to V, which is equal to the minimum operating voltage of the DRAM cell. MIN The voltage level, the second first reference cell (denoted as MAXV-DRAM cell) is loaded to a voltage level V equal to the maximum operating voltage of the DRAM cell. MAX After the reference DRAM cell is charged, the reference voltage will decay over time; we denote the time values ​​of the voltage as V. min (t) and V max (t). Furthermore, we will consider V min (0) is represented as V MIN And V max (0) is represented as V MAX .

[0072] As in the aALU 300, the linear amplifier 402 amplifies the data line 212 via charge-shared attenuation of the inverse amplification. Figure 2 The difference between the read voltage level and the pre-charge voltage is used to compensate for attenuation. Switch 404 is connected to V. max The attenuation-compensated value of (t) is sampled and then stored in C. max On capacitor 410, switch 406 is connected to V. min The attenuation-compensated value of (t) is sampled and then stored in C. min On capacitor 412, and for each data DRAM cell, switch 408 pairs V Si The attenuation-compensated value of (t) (the i-th data DRAM cell in the DRAM group) is sampled. V Si The compensation value of (t) is stored in C. S 414 on the capacitor.

[0073] Assuming exponential decay with equal time constants, and assuming that the two reference DRAM cells and the data DRAM cells have the same decay time, we obtain: (5) (6) (7) in: V MAX It is the initial voltage on the MAXV-DRAM cell; V MIN It is the initial voltage on the MINV-DRAM cell; V Si (0) is the initial voltage on the i-th data DRAM cell; and: n(t) is the noise added to the three voltages (the noise is equal in the first approximation).

[0074] We now define the recession compensation factor SF: (8) and difference signal V diff : (9) In order to restore V Si (0), the ALU 400 also includes a voltage ratio amplifier 416, which is configured to compensate for degradation and generate a voltage V. Si (0): (10) Therefore, according to Figure 4 In the example embodiment shown, the aALU 400 can compensate for equal noise induced on the sampling capacitor to accurately reconstruct the initial voltage stored in the data DRAM cell.

[0075] Figure 4 The configuration of the dual reference amplifier 400 shown and described above, along with the use of two reference voltages that are close to each other and close to the target DRAM cell, provides high accuracy, thereby mitigating common noise and providing resilience against (i) process variations affecting the DRAM device, (ii) variations associated with the power supply voltage of the DRAM device, and (iii) variations associated with the temperature of the DRAM device.

[0076] Time series diagram Figure 5This is a write timing diagram 500 schematically illustrating the waveforms of a write sequence according to an embodiment of the present invention. Timing diagram 500 shows the write operation of an 8-column group in a DRAM with dual reference voltages aALU. Clock curve diagram 502 shows the waveform of a clock signal that pulses for each column; write curve diagram 504 shows the write signal, which is high for 8 clock cycles; V dl Graph 506 shows the voltage of the data lines; Graph 508 shows the group address (which remains unchanged); and Graph 510 shows the column selection index, which is counted from 0 to 7.

[0077] according to Figure 5 In the example embodiment shown, the first reference DRAM cell stored in the first column (column 0) is set to a relatively high voltage V. MAX The second reference DRAM cell stored in the second column (column 1) is set to a relatively low voltage V. MIN .

[0078] Therefore, in the first clock cycle (column address = 0), V dl It is set to a relatively high level to charge the first reference DRAM cell. In the second clock cycle (column address = 1), V... dl It is set to a relatively low level to charge the second reference DRAM cell. In a separate clock cycle, when a data DRAM cell is written, V is set according to the value of the multi-level nibble of the selected DRAM cell being written to. dl .

[0079] Figure 6 A refresh timing diagram 600 schematically illustrates the waveform of the refresh sequence according to an embodiment of the present invention. Timing diagram 600 shows the refresh of an 8-column group in a DRAM with dual reference voltage aALU. Clock curve diagram 602 shows the waveform of the clock signal. The clock pulses are three times per column. The first pulse (referred to as stage 0) is used to precharge the data lines; the second pulse (stage 1) is used to read the DRAM cell; and the third pulse (stage 2) is used to write the refreshed data back into the DRAM cell (the stage numbers are indicated above curve diagram 602).

[0080] Precharge curve 604 shows the precharge control signal, which pulses at stage 0 to prepare the data lines for read operations; V 感测 Graph 606 illustrates the sensing control signal, which pulses at stage 1 to read DRAM cells into the aALU via the data lines; V 刷新 Graph 608 shows the refresh control signal, which pulses at stage 2 and stores the refresh voltage back into the DRAM cell.

[0081] Vdl Graph 610 shows the voltage on the data line, which is pre-charged at stage 0 and then set at stage 1 according to the read voltage, or at stage 2 according to the refresh voltage. Note that in the first two columns, two reference DRAM cells are refreshed, and in the following columns (columns 2 to 7), six data DRAM cells storing various voltage levels are read and then refreshed.

[0082] Group address graph 612 shows the group address (which remains unchanged); and column address graph 614 shows the column selection index, which is counted from 0 to 7.

[0083] It was referenced through an example. Figure 5 , Figure 6 The write timing diagrams shown and described above, as well as the read and refresh timing diagrams, are illustrated. Other timing diagrams may be used in alternative embodiments. For example, in some embodiments, the number of columns in a set may be different (typically much higher than) 8. In some embodiments, the number of data reference units in a set may be different from 2.

[0084] Voltage ratio amplifier implementation Figure 7 This is a block diagram schematically illustrating a functional stage block diagram of a voltage ratio amplifier 700 according to an embodiment of the present invention. This configuration can be used, for example, in a voltage ratio amplifier 416 ( Figure 4 For example, in voltage ratio amplifier 312 ( Figure 3 A simplified version of the configuration used in ().

[0085] Voltage ratio amplifier 700 includes voltage ratio amplifier 416 with the same input. Figure 4 Example implementation of ).

[0086] As shown above, (12) We use logarithmic and antilogarithmic amplifier functions to implement multiplication and division; the logarithmic amplifier approximates the logarithmic function: output = Log 10 (Input), within a predefined range, and may have scaling. An anti-inverse amplifier implements the inverse function: output = 10 输入 (The base 10 used above is an example; other suitable bases may be used in alternative embodiments.)

[0087] Using the logarithmic function, we can rewrite equation (12) as: (13) The linear amplifier 702 is configured to output differential V MSB -VLSB The linear amplifier 704 is configured to output differential V. max -V min And the linear amplifier 706 is configured to output differential V S -V lsb .

[0088] Then, the logarithmic amplifier 708 generates Log(V) MAX -V MIN Logarithmic amplifier 710 generates Log(V) max -V min ) ， Furthermore, the logarithmic amplifier 712 generates Log(V) S -V min ).

[0089] Linear amplifier 714 subtracts the output of logarithmic amplifier 710 from the output of logarithmic amplifier 708 to generate Log(V MAX -V MIN )-Log(V max (t)-V min (t)), and the linear amplifier 716 adds the output of the logarithmic amplifier 712 to the output of the linear amplifier 714 to generate Log(V MAX -V MIN )-Log(V msb (t)-V min (t)).

[0090] Finally, the anti-sigma amplifier 710 outputs V Si (0).

[0091] As can be observed, if the logarithmic amplifier and the anti-logarithmic amplifier output negative values ​​(-Log and -Log), -1 If so, the voltage ratio amplifier 700 will also operate correctly.

[0092] Figure 8A This is a block diagram schematically illustrating a logarithmic amplifier 800 according to an embodiment of the present invention. The logarithmic amplifier 800 can be used, for example, to implement amplifiers 708, 710, and 712 (…). Figure 7 This implementation is based on the voltage-current relationship of a forward-biased diode: .

[0093] Where I S It is the saturation current, V T It is the positive threshold voltage, V DIt is the forward voltage, and I is the current through the diode. I = ISeVD / (nVT). Therefore, within a given range and with a given accuracy, the forward voltage across the diode is a logarithmic function of the voltage.

[0094] The logarithmic amplifier 800 includes a negative feedback operational amplifier 802; a virtual ground (negative input) is connected to the output of the operational amplifier via a diode 804 and to the input of the logarithmic amplifier circuit via a resistor 806 (note that the output of the logarithmic amplifier 800 is inverted).

[0095] Figure 8B This is a block diagram schematically illustrating an anti-reciprocal amplifier 850 according to an embodiment of the present invention. The anti-reciprocal amplifier 850 can be used, for example, to implement amplifier 718 (… Figure 7 The anti-sigma amplifier 850 includes a negative feedback operational amplifier 852; a virtual ground (negative input) is connected to the output of the operational amplifier via a resistor 854 and to the input of the anti-sigma amplifier circuit via a diode 856 (note that the output of the anti-sigma amplifier 850 is inverted).

[0096] Both the logarithmic amplifier 850 and the anti-logarithmic amplifier 852 should be designed such that the operating range of diodes 804 and 854 is within the logarithmic region of the diodes, where I is safely below I0. S .

[0097] The configuration of voltage ratio amplifier 700, including logarithmic amplifier 800 and anti-logarithmic amplifier 852, is illustrated by way of example. Other configurations may be used in alternative embodiments. For example, in one embodiment, a variable gain amplifier is used to perform signal multiplication. In another embodiment, a varistor (VDR) is used.

[0098] Refresh Method Description Figure 9 This is a flowchart 900 schematically illustrating a method for analog-only refresh of a multilevel DRAM according to an embodiment of the present invention. The flowchart consists of control circuitry 104 and an ALU 114 (…). Figure 1 )implement.

[0099] The flowchart begins with operation 902, which clears the column counter (CC) to zero to point to the first column (column 0) of the DRAM array. (It is assumed that the group counter has already been set to point to the selected group; this group counter remains unchanged during the operation of flowchart 900 and will be ignored below.) Next, at precharge operation 904, the control circuit will precharge the data lines and, through group selection transistor 216, precharge the selected group line 214. Figure 2Pre-charge. Now, at operation 906 of the coupled DRAM cell, the control circuit will activate the CC-th column select line 208 ( Figure 2 This couples the storage capacitor 204 of the CC-th DRAM cell to the group line and to the data line via the group select transistor.

[0100] The flowchart now proceeds to operation 908, which corrects charge-sharing attenuation. Here, the aALU amplifies the difference between the data line voltage and the pre-charge voltage by storing the reciprocal of the voltage decay on the capacitor. This voltage decay is due to charge sharing with the data lines and group lines (and any parasitic capacitances). The corrected voltage will be stored in another operation.

[0101] Next, in operation 910, which checks if CC is less than 2, the control circuit checks if the CC counter is below a value of 2 (i.e., CC points to one of the two reference DRAM cells). If so, the flowchart proceeds to operation 912, which stores the attenuated corrected voltage of the two reference DRAM cells in two storage capacitors, and then proceeds to operation 914, which refreshes the reference DRAM cells with a predefined reference voltage level. The attenuated corrected reference voltage stored on the capacitors (in operation 912) will be used in another operation to estimate the voltage of the other storage capacitor 204. Figure 2 The decay of ) and thus compensate for additive noise.

[0102] After operation 914, the flowchart increments the CC counter at operation 916, then re-enters operation 904 to precharge the data lines and group lines and read the next DRAM cell.

[0103] If CC has reached or exceeded the value 2 in operation 910, the flowchart proceeds to operation 918, which stores the corrected data voltage, whereby the control circuit stores the attenuated corrected voltage of the data DRAM cell at column CC in a storage capacitor. The flowchart then proceeds to attenuation correction operation 920, where the ALU generates a refresh voltage that corrects the attenuated data DRAM cell voltage, assuming that the attenuation time constants of the storage capacitors in the same DRAM group are closely matched. In an embodiment, the ALU multiplies the attenuated corrected data DRAM cell voltage (which is stored in the capacitor in operation 918) by the reciprocal of the attenuation of the difference between two reference voltages, which is the difference between the initial difference and the voltage stored on the reference storage capacitor in operation 912.

[0104] Next, at operation 922, which refreshes the data DRAM cell, the control circuit uses the refresh voltage generated in operation 920 to refresh the data DRAM cell.

[0105] After operation 922, the flowchart checks at operation 924 whether the last CC has been reached (in other words, the last DRAM cell in the group has been refreshed). If the last CC value has not been reached, the flowchart proceeds to operation 916, incrementing CC to point to the next column, and then re-enters operation 904 to refresh the next DRAM cell.

[0106] Therefore, according to Figure 9 The example flowchart shown can refresh a set of DRAM cells that store analog data along with two reference voltages using only analog operations.

[0107] The example references [the relevant text]. Figure 9 The configuration shown in the flowchart 900 described above is illustrated in the figure. Other configurations may be used in alternative embodiments. For example, in some embodiments, only one reference DRAM cell is used; in other embodiments, more than two reference DRAM cells may be used, for example, in one embodiment, every 16th DRAM cell stores a reference voltage.

[0108] Analog memory In some embodiments, the techniques described above are used to implement analog dynamic memory only (analog DRAM). Analog DRAM includes a plurality of storage capacitors 204 ( Figure 2 The storage capacitor is configured to store a continuous range of charge representing continuously defined analog values.

[0109] In some embodiments, the analog DRAM includes an analog input (e.g., a continuous voltage source); in other embodiments, the output of the analog DRAM is connected to analog circuitry. For example, in one embodiment, the analog DRAM stores multiple analog IQ samples of a communication channel input from a communication receiver, and the output of the analog DRAM is connected to a communication transmitter or analog oscilloscope for storing the communication channel.

[0110] Physical Design Examples We will now describe the physical design and layout architecture of two example embodiments.

[0111] Figure 10This is a block diagram schematically illustrating a two-dimensional array 1000 in a DRAM device including an analog refresh circuit, according to an embodiment of the present invention. The block diagram is layout-oriented (but rotated so that rows are drawn vertically and columns are drawn horizontally) and shows a practical preferred two-dimensional arrangement of DRAM cells including memory groups 1002 (each memory group comprising four groups formed by four corresponding columns).

[0112] Each memory bank includes an array of select transistors 1004, each select transistor being coupled to a corresponding storage capacitor 1006, and configured to couple the capacitor to a horizontally drawn bank line 1008.

[0113] For optimal layout, selection transistors 1004 and corresponding storage capacitors 1006 are arranged in a checkerboard pattern between the horizontal group lines and the vertical select lines (the latter denoted as RAi). Group select transistors 1010 couple the group lines to the corresponding data lines 1012. For the leftmost group, the group select vertical control signal is designated as LA0, and for the second group from the left, the group select vertical control signal is designated as LA1 (and so on for other groups if they exist).

[0114] To minimize leakage from the storage capacitor, the unselected group line is coupled to a preset voltage level V via transistor 1014, which is adjusted (e.g., calibrated) to minimize leakage.

[0115] It was referenced through an example. Figure 10 The configuration of the two-dimensional array 1000 shown and described above is illustrated. Other configurations may be used in alternative embodiments. For example, in some embodiments, the checkerboard structure is replaced by a sparser or denser structure. In one embodiment, transistor 1008 may include a PMOS transistor (with inverted control polarity), and in another embodiment, transistor 1014 is not implemented.

[0116] Figure 11 This is a block diagram schematically illustrating a 6-bank DRAM device 1100 including an analog refresh circuit according to an embodiment of the present invention. The DRAM device 1100 includes six memory arrays (“banks”). The memory arrays store analog values ​​representing nibbles in the digital domain. Each memory array 1102 is configured to concurrently process eight nibbles (in other words, the width of the memory array in the digital domain is eight nibbles).

[0117] The DRAM device 1100 also includes 24 aALUs 1104; each aALU is shared by the memory arrays 1102 in the top row and the memory arrays in the bottom row of the memory array. Therefore, the width of the DRAM device 1100 in the digital domain is 24 nibbles.

[0118] A pair of address decoders 1106 selects the corresponding group in the top and bottom rows of the memory array 1102 based on the group address input (in an embodiment, the group address input includes 4 bits; the most significant bit is selected between the top address decoder and the bottom address decoder 1106, while the least significant 3 bits are input to both address decoders).

[0119] Finally, column selector 1108 selects the output of three aALUs 1104 based on the column address input (selecting one aALU from each pair of memory arrays 1102).

[0120] It was referenced through an example. Figure 11 The configuration of the 6-bank DRAM device 1100 shown and described above is illustrated. Other configurations may be used in alternative embodiments. For example, in some embodiments, the number of banks may be different from 6; in other embodiments, the number of address lines may be higher or lower than 4; and in still other embodiments, the number of nibbles per memory array may be different from 8. In one embodiment, each aALU 1104 is shared by more than two memory arrays, and in another embodiment, the aALU is not shared.

[0121] The above references Figures 1 to 11 The described apparatus, waveforms, and methods; the configurations of DRAM devices 200, 1000, and 1100; the configurations of aALU 300 and aALU 400; the configurations of voltage ratio amplifier 700, logarithmic amplifier 800, and anti-logarithmic amplifier 850; the write waveform 500 and refresh waveform 600; and the methods of flowchart 900 (including all its cells and subcells) are illustrative configurations, waveforms, and methods shown purely for conceptual clarity. Any other suitable methods, waveforms, and configurations may be used in alternative embodiments.

[0122] The sequential analog memory device described above includes a physical layer for efficient data-intensive storage structures, thereby enabling precoding, calibration, and other functions to be performed using an additional link layer in the implementation of an adaptive software-defined memory solution.

[0123] It should be noted that although the term DRAM device may imply additional circuitry beyond the memory array, such as decoders, I / O buffers, etc., the term DRAM device used above applies to both the complete DRAM device and its components (such as the memory array).

[0124] In various embodiments, the DRAM device 100 (including its sub-cells) may be implemented using suitable hardware, such as one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), or a combination of ASICs and FPGAs.

[0125] Although the embodiments described herein are primarily for analog DRAM, the methods and systems described herein can also be used in other applications, such as in various ultra-low power analog-only circuits and in ICs that combine analog ALUs and analog memories.

[0126] Therefore, it should be understood that the above embodiments are cited by way of example, and the invention is not limited to what has been specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications of the invention that would be conceived by one of skill in the art upon reading the above description and that are not disclosed in the prior art. Documents incorporated herein by reference are considered part of this application, and the definitions in this specification should be considered only, unless any terms are defined in these incorporated documents in a manner that conflicts to some extent with the definitions expressly or implicitly made in this specification.

Claims

1. A dynamic random access memory (DRAM) device, comprising: Multiple DRAM cells, each including a corresponding storage capacitor configured to be charged to a corresponding voltage; A control circuit configured to read a voltage from a target DRAM cell and refresh the target DRAM cell using a refresh voltage derived from the read voltage; as well as An analog arithmetic logic unit (ALU) is configured to derive the refresh voltage from the read voltage by performing an analog operation, such that the refresh voltage approximates the voltage previously written to the target DRAM cell.

2. The DRAM device of claim 1, wherein, One or more of the DRAM cells are used as one or more reference DRAM cells, the one or more reference DRAM cells being programmed to have one or more corresponding reference voltages, and wherein the aALU is configured to derive the refresh voltage of the target DRAM cell based on (i) the voltage read from the target DRAM cell, (ii) one or more voltages read from the one or more reference DRAM cells, and (iii) the time elapsed since the voltage was previously written to the target DRAM cell.

3. The DRAM device of claim 1, wherein, The aALU includes: (i) one or more reference sampling capacitors configured to store one or more sampled reference DRAM cell voltages, and (ii) a data sampling capacitor configured to store sampled target DRAM data voltages.

4. The DRAM device according to any one of claims 1-3, wherein, The aALU includes a voltage ratio amplifier configured to generate the refresh voltage by multiplying one of the one or more reference voltages by the ratio between the corrected target DRAM cell voltage and the corresponding corrected reference DRAM cell voltage among the one or more corrected reference DRAM cell voltages, thereby mitigating degradation of the target DRAM cell.

5. The DRAM device according to claim 4, wherein, The aALU includes a differential amplifier, which is configured to: The difference between the precharge voltage and the data read voltage is amplified by the reciprocal of the charge-sharing decay factor, thereby generating the corrected target DRAM cell voltage of the target DRAM cell; as well as The difference between the precharge voltage and one or more reference read voltages is amplified by the reciprocal of the charge-sharing decay factor, thereby generating one or more corrected reference DRAM cell voltages for the one or more reference DRAM cells.

6. The DRAM device according to claim 4, wherein, The aALU is configured to generate the refresh voltage by adding the product of the following to a first reference voltage among the one or more reference voltages: (i) a DRAM cell degradation metric, and (ii) the difference between a corrected first reference voltage among the one or more corrected reference voltages and a corresponding first reference voltage among the one or more reference voltages, thereby compensating for additive noise induced on the storage capacitor.

7. The DRAM device according to claim 6, wherein, The aALU is configured to calculate the DRAM cell degradation metric by dividing the difference between the first reference voltage and the second reference voltage by the difference between the corrected first reference voltage and the corrected second reference voltage.

8. The DRAM device according to any one of claims 1-3, wherein, The aALU includes a differential amplifier configured to amplify the difference between a precharge voltage and a voltage read from the target DRAM cell, and wherein the aALU is configured to generate a corrected target DRAM cell voltage based on the analog output of the differential amplifier.

9. The DRAM device according to any one of claims 1-3, wherein, When deriving the refresh voltage from the read voltage, the aALU is configured to compensate for one or more of the following: (i) process variations affecting the DRAM device, (ii) variations associated with the power supply voltage of the DRAM device, and (iii) variations associated with the temperature of the DRAM device.

10. An analog dynamic random access memory (analog DRAM) device, comprising a plurality of storage capacitors configured to store charge representing a continuous range of continuously defined analog values.

11. A method comprising: Operate a plurality of dynamic random access memory (DRAM) cells, each DRAM cell including a corresponding storage capacitor configured to be charged to a corresponding voltage; Using control circuitry, a voltage is read from the target DRAM cell, and the target DRAM cell is refreshed using a refresh voltage derived from the read voltage; and Using an analog arithmetic logic unit (aALU), the refresh voltage is derived from the read voltage by performing an analog operation, such that the refresh voltage approximates the voltage previously written to the target DRAM cell.

12. The method according to claim 11, wherein, One or more of the DRAM cells are used as one or more reference DRAM cells, the one or more reference DRAM cells being programmed to have one or more corresponding reference voltages, and wherein the refresh voltage of the target DRAM cell is derived based on: (i) the voltage read from the target DRAM cell, (ii) one or more voltages read from the one or more reference DRAM cells, and (iii) the time elapsed since the voltage was previously written to the target DRAM cell.

13. The method according to claim 11, wherein, Deriving the refresh voltage includes: (i) storing one or more sampled reference DRAM cell voltages in one or more reference sampling capacitors of the aALU, and (ii) storing the sampled target DRAM data voltage in the data sampling capacitor of the aALU.

14. The method according to any one of claims 11-13, wherein, Deriving the refresh voltage includes: using a voltage ratio amplifier in the aALU to generate the refresh voltage by multiplying one of the one or more reference voltages by the ratio between the corrected target DRAM cell voltage and the corresponding corrected reference DRAM cell voltage among one or more corrected reference DRAM cell voltages, thereby mitigating the degradation of the target DRAM cell.

15. The method according to claim 14, wherein, Deriving the refresh voltage involves using the differential amplifier in the aALU: The difference between the precharge voltage and the data read voltage is amplified by the reciprocal of the charge-sharing decay factor, thereby generating the corrected target DRAM cell voltage of the target DRAM cell; as well as The difference between the precharge voltage and one or more reference read voltages is amplified by the reciprocal of the charge-sharing decay factor, thereby generating one or more corrected reference DRAM cell voltages for the one or more reference DRAM cells.

16. The method of claim 14, wherein, Derivation of the refresh voltage includes generating the refresh voltage by adding the product of the following to a first reference voltage among the one or more reference voltages: (i) a DRAM cell degradation metric, and (ii) the difference between a corrected first reference voltage among the one or more corrected reference voltages and a corresponding first reference voltage among the one or more reference voltages, thereby compensating for additive noise induced on the storage capacitor.

17. The method according to claim 16, wherein, Deriving the refresh voltage includes calculating the DRAM cell degradation metric by dividing the difference between the first reference voltage and the second reference voltage by the difference between the corrected first reference voltage and the corrected second reference voltage.

18. The method according to any one of claims 11-13, wherein, Deriving the refresh voltage includes: amplifying the difference between the precharge voltage and the voltage read from the target DRAM cell using a differential amplifier in the aALU, and generating a corrected target DRAM cell voltage for the target DRAM cell based on the analog output of the differential amplifier.

19. The method according to any one of claims 11-13, wherein, Deriving the refresh voltage includes compensating for one or more of the following: (i) process variations affecting the DRAM cell, (ii) variations associated with the power supply voltage of the DRAM cell, and (iii) variations associated with the temperature of the DRAM cell.

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