Software-based instruction scoreboard for arithmetic logic units

Abstract

A software-based instruction scoreboard (126) indicates dependencies between closely spaced instructions (302, 304, 306) issued to an arithmetic logic unit (ALU) pipeline (218). The software-based instruction scoreboard inserts one or more control words (308) into a command stream (300) between dependent instructions, which are then executed by the ALU pipeline. The control words identify the instruction(s) on which the dependent instruction depends (parent instructions), allowing the processor hardware (104) to ensure that the ALU pipeline does not stall while the dependent instruction waits for a result from the parent instruction.

Description

Background Art

[0001] Conventional processing systems include processing units such as a central processing unit (CPU) and a graphics processing unit (GPU) that implement audio applications, video applications, multimedia applications, and, in some cases, general-purpose computing. The physical resources of the GPU include a shader engine and fixed-function hardware units used to implement user-defined reconfigurable virtual pipelines. For example, a conventional graphics pipeline for processing three-dimensional (3D) graphics is formed by an arrangement of a series of fixed-function hardware blocks supported by programmable shaders. Processing in the GPU is typically initiated by an application programming interface (API) call (e.g., a draw call) processed by the CPU. A draw call is a command generated by the CPU, transmitted to the GPU, and used to instruct the GPU to render an object (or a part of an object) within a frame.

[0002] The graphics hardware within the GPU typically includes arithmetic logic units (ALUs) such as scalar ALUs or vector ALUs, which are implemented as corresponding pipelines and used to perform arithmetic operations such as addition, subtraction, multiplication, division, and movement, and to execute various transcendental functions. In some cases, one pipeline is used to implement most of the arithmetic functions, and another pipeline is used to implement more complex transcendental functions. Instructions for the ALU are held in an instruction buffer until an arbiter selects an instruction to execute in one of the pipelines. Some instructions in the instruction buffer are dependent on other instructions. For example, the source register of a first (dependent) instruction receives input from the destination register of a second instruction. Therefore, the second instruction needs to be completed before the first instruction is executed.

[0003] This disclosure will be better understood by referring to the accompanying drawings, and its many features and advantages may become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items. [Brief explanation of the drawing]

[0004] [Figure 1] This is a block diagram of a processing system using a software-based instruction scoreboard, according to several embodiments. [Figure 2] This is a block diagram of a software-based instruction scoreboard, in several embodiments, which inserts control words indicating the dependencies of certain instructions into the command stream. [Figure 3] This is a block diagram of control words showing the dependencies of an instruction inserted into a command stream, according to several embodiments. [Figure 4] This flowchart illustrates a method, in several embodiments, for inserting control words indicating the dependencies of certain instructions into a command stream and delaying the issuance of dependent instructions based on those control words. [Modes for carrying out the invention]

[0005] The ALU pipeline has a length corresponding to a predetermined number of cycles, such as a 4-cycle pipeline. Therefore, a dependent instruction may stall if it is sent to the pipeline before the instruction it depends on has completed. For example, if an add instruction depends on a move instruction and the ALU pipeline is 4 cycles long, the add instruction will stall for 3 cycles if it is sent to the pipeline 1 cycle after the move instruction. Conventional GPUs include a hardware instruction scoreboard that stores information (e.g., in one or more flops) used to delay sending dependent instructions to the ALU pipeline until the instruction the dependent instruction depends on has completed. For example, in some cases, the instruction scoreboard includes six registers (entries) for storing information indicating the processing status of six instructions that have been issued to the pipeline in advance. Each instruction compares its source register to the destination register of the instruction in the instruction scoreboard to determine if there is a dependency. If an instruction depends on one or more instructions in the instruction scoreboard, the corresponding entry in the instruction scoreboard is monitored to determine when to send the dependent instruction to the pipeline. This process requires circuitry to perform instruction decoding and numerous register comparisons. As a result, hardware instruction scoreboards incur high costs in terms of both power consumption and area on the chip.

[0006] Figures 1-4 show an instruction scoreboard for the ALU pipeline implemented in software to reduce the power consumption and area consumed by the hardware within the GPU. The software-based instruction scoreboard indicates the dependencies between instructions issued to the ALU pipeline, with intervals between instructions shorter than the pipeline execution time (referred to as "short-interval" instructions). The software-based instruction scoreboard selectively inserts one or more delayed instructions, referred to as "control words," into the command stream between dependent instructions in the program code, which is then executed by the GPU. The control words identify the instructions (one or more) that the dependent instructions depend on (referred to herein as "parent instructions"), thereby causing the GPU hardware to stall the ALU pipeline by not issuing the dependent instructions to the ALU pipeline because the parent instructions have not yet completed.

[0007] In some embodiments, a software-based instruction scoreboard inserts a control word into the command stream immediately before a dependent instruction, the control word indicating the preceding instruction to which the dependent instruction depends. For example, the control word indicates that the next instruction in the command stream depends on the Nth preceding vector ALU(VALU) instruction. In some embodiments, the software-based instruction scoreboard implements a control word compression technique to reduce instruction stream overhead by including two or more delay values ​​within a single control word that identify two or more dependencies of upcoming instructions. For example, a single control word further includes a “skip” indicator that identifies the parent instruction for the next instruction in the command stream and identifies an instruction issued following the next instruction as depending on another instruction in the command stream. This control word compression technique can be applied to any number of dependency specifiers per control word. In some embodiments, the control word indicates the dependency of a given instruction on two or more parent instructions executed in two or more ALU pipelines. For example, in some embodiments, a control word indicates a dependency between instructions executed in both the scalar ALU pipeline and the vector ALU pipeline, or between a special function unit (e.g., sine / cosine) ALU pipeline and instructions executed in both the scalar ALU pipeline and the vector ALU pipeline.

[0008] A software-based instruction scoreboard generates control words based on a dependency graph maintained by the compiler. This dependency graph identifies all dependencies in the program. However, not all dependent instructions require the delay caused by a control word. Depending on the depth of the ALU pipeline and the number of independent instructions issued between the parent and dependent instructions, it may not be necessary to insert extra idle cycles between the parent and dependent instructions. In some embodiments, the software-based instruction scoreboard only inserts control words as needed, based on the number of independent instructions between dependent instructions and the number of stages in the ALU pipeline. For example, if a dependent instruction is issued beyond a threshold number of cycles after its parent instruction, based on the length of the ALU pipeline, the parent instruction has completed before the dependent instruction is issued, and there is no need to provide additional idle cycles to avoid stalling the dependent instruction. Therefore, the software-based instruction scoreboard inserts a control word into the command stream only if the dependent instruction is issued within a threshold number of cycles after its parent instruction. In some embodiments, the threshold number of cycles is based on the number of stages in the ALU pipeline. The techniques described herein are used in various embodiments in any of the various parallel processors (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, and other multithreaded processing units).

[0009] Figure 1 shows a processing system 100 using a software-based instruction scoreboard in several embodiments. The processing system 100 includes a central processing unit (CPU) 102 and an accelerated processing device (APD) 104, which is an example of a parallel processor. In various embodiments, the CPU 102 includes one or more single-core CPUs or multi-core CPUs. In various embodiments, the APD 104 includes any cooperating collection of hardware and / or software that performs functions and calculations associated with accelerated graphics processing tasks, data parallel tasks, nested data parallel tasks, etc., in an accelerated manner in relation to resources such as conventional CPUs, conventional graphics processing units (GPUs), and combinations thereof. In the embodiment of Figure 1, the processing system 100 is formed on a single silicon die or package that combines the CPU 102 and the APD 104 to provide a unified programming and execution environment. This environment allows the APD 104 to be used as flexibly as the CPU 102 for several programming tasks. In other embodiments, the CPU 102 and the APD 104 are formed separately and mounted on the same or different substrates. It should be understood that the processing system 100 may include more or fewer components than those shown in Figure 1. For example, the processing system 100 may further include one or more input interfaces, non-volatile storage, one or more output interfaces, a network interface, and one or more displays or display interfaces.

[0010] As shown in Figure 1, the processing system 100 includes a system memory 106, an operating system 108, a communication infrastructure 110, and one or more applications 112. Access to the system memory 106 is managed by a memory controller (not shown) connected to the memory 106. For example, requests from the CPU 102 or other devices to read from or write to the system memory 106 are managed by the memory controller. In some embodiments, one or more applications 112 include various programs or commands for performing calculations that are also executed on the CPU 102. The CPU 102 sends selected commands for processing on the APD 104. The operating system 108 and the communication infrastructure 110 are described in more detail below. The processing system 100 further includes a device driver 114 and memory management units such as an input / output memory management unit (IOMMU) 116. The components of the processing system 100 may be implemented as hardware, firmware, software, or any combination thereof. In some embodiments, the processing system 100 includes one or more software components, hardware components, and firmware components in addition to or different from those shown in Figure 1.

[0011] Within the processing system 100, the system memory 106 includes non-persistent memory such as DRAM (not shown). In various embodiments, the system memory 106 stores processing logic instructions, constant values, variable values ​​during the execution of an application or other part of processing logic, or other desired information. For example, a part of the control logic for executing one or more operations on the CPU 102 may reside in the system memory 106 during the execution of each part of the operation by the CPU 102. During execution, each application such as application 112, operating system functions such as operating system 108, processing logic commands, and system software reside in the system memory 106. Control logic commands essential to the operating system 108 usually reside in the system memory 106 during execution. In some embodiments, other software commands (e.g., device drivers 114) reside in the system memory 106 during the execution of the processing system 100.

[0012] The IOMMU116 is a multi-context memory management unit. In the present invention, the context takes into account the environment in which the kernel runs and the domains in which synchronization and memory management are defined. The context includes a set of devices, the memory accessible to those devices, the corresponding memory properties, and one or more command queues used to schedule the execution of kernels or operations on memory objects. The IOMMU116 contains logic for performing virtual-to-physical address translation for memory page access for devices such as the APD104. In some embodiments, the IOMMU116 includes or has access to a translation lookaside buffer (TLB) (not shown). The TLB is implemented in Content Addressable Memory (CAM) to accelerate the translation of logical (i.e., virtual) memory addresses to physical memory addresses in response to requests made by the APD104 for data in system memory 106.

[0013] In various embodiments, the communication infrastructure 110 interconnects the components of the processing system 100. The communication infrastructure 110 includes one or more of the following: a Peripheral Component Interconnection (PCI) bus, an Expansion PCI (PCI-E) bus, an Advanced Microcontroller Bus Architecture (AMBA) bus, an Advanced Graphics Port (AGP), or other such communication infrastructure and interconnections (not shown). In some embodiments, the communication infrastructure 110 includes an Ethernet® network or any other suitable physical communication infrastructure that meets the data transfer rate requirements of the application. The communication infrastructure 110 also includes functions for interconnecting components, including the components of the processing system 100.

[0014] A driver, such as a device driver 114, communicates with a device (e.g., APD 104) via an interconnection or communication infrastructure 110. When a calling program invokes a routine within the device driver 114, the device driver 114 issues a command to the device. When the device returns data to the device driver 114, the device driver 114 invokes the routine of the original calling program. Generally, device drivers are hardware-dependent and operating system-specific in order to provide essential interrupt handling to any necessary asynchronously dependent hardware interfaces. In some embodiments, a compiler 120 is embedded within the device driver 114. The compiler 120 compiles the source code into program instructions necessary for execution by the processing system 100. During such compilation, the compiler 120 may apply translations to the program instructions at various stages of compilation. In other embodiments, the compiler 120 is a standalone application.

[0015] The CPU 102 includes one or more of the following: a control processor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a digital signal processor (DSP), although these entities are not shown in Figure 1 for clarity. The CPU 102 executes at least a portion of the control logic that controls the operation of the processing system 100. For example, in various embodiments, the CPU 102 executes the operating system 108, one or more applications 112, and a device driver 114. In some embodiments, the CPU 102 initiates and controls the execution of one or more applications 112 by distributing the processing associated with one or more applications 112 across the CPU 102 and other processing resources such as the APD 104.

[0016] The APD104 executes commands and programs for selected functions, such as graphics operations and other operations that are particularly well-suited for parallel processing. The APD104 is typically frequently used to perform graphics pipeline operations such as pixel manipulation, geometric calculations, and rendering images to a display. In some embodiments, the APD104 performs computational operations (such as video manipulation, physical simulations, computational fluid dynamics, etc., operations unrelated to graphics) based on commands or instructions received from the CPU102. For example, a command can be considered a special instruction not typically defined in the instruction set architecture (ISA) of the APD104. A command can be executed by a special processor such as a dispatch processor, command processor, or network controller.

[0017] In various embodiments, the APD104 includes one or more computing units, such as one or more processing cores 122, which include one or more SIMD units 124 that execute threads simultaneously with other threads in the Wavefront, for example, according to a Single Instruction Multiple Data (SIMD) execution model. The SIMD execution model is one in which multiple processing elements, such as arithmetic logic units (ALUs), share a single program control flow unit and program counter, and thus can execute the same program but with different data. Some embodiments of the APD104 are used to implement a GPU, in which case the processing cores 122 are referred to as shader cores or streaming multiprocessors (SMX). The number of processing cores 122 implemented in the APD104 can be freely selected in design.

[0018] Each of the one or more processing cores 122 processes input data by performing an instantiation of a specific work item, and the basic unit of execution in one or more processing cores 122 is a work item (e.g., a thread). Each work item represents a single instance creation of a collection of parallel executions of kernels invoked on the device by, for example, parallel-executing commands. A work item may be executed by one or more processing elements as part of a work group executed in the processing cores 122.

[0019] APD104 includes a GPU that issues and executes work items, which include a group of threads that run concurrently as a “Wavefront” on a single SIMD unit 124. Multiple Wavefronts are included in a “Workgroup,” which includes a collection of work items designated to run the same program. A workgroup is executed by executing each of the Wavefronts that make up the workgroup. In some embodiments, these Wavefronts run sequentially on a single SIMD unit 124, or partially or fully in parallel on different SIMD units. In other embodiments, all Wavefronts from a workgroup are processed by the same processing core 122. Wavefronts may also be interchangeably referred to as warps, vectors, or threads. In some embodiments, a Wavefront includes an instance of parallel execution of a shader program, but each Wavefront includes multiple work items that run concurrently on a single SIMD unit 124 according to a SIMD paradigm (e.g., one instruction control unit that executes multiple data and the same instruction streams). The scheduler 128 performs operations related to scheduling various wavefronts on different processing cores 122 and SIMD units 124, as well as other operations to coordinate various tasks on the APD 104.

[0020] The parallel processing provided by one or more processing cores 122 is suitable for graphics-related operations such as pixel value calculation, vertex transformation, tessellation, geometry shading operations, and other graphics operations. The graphics processing pipeline 130 receives graphics processing commands from the CPU 102 and thereby provides computation tasks to one or more processing cores 122 for parallel execution. Some graphics pipeline operations, such as pixel processing and other parallel computation operations, require the same command stream or computation kernel to be executed on a stream or collection of input data elements. Each instance of the same computation kernel is executed simultaneously on multiple SIMD 124 units in one or more processing cores 122 to process such data elements in parallel. As referred to herein, for example, a computation kernel is a function containing instructions declared in a program and executed on the APD processing core 122. This function is also referred to as a kernel, shader, shader program, or program.

[0021] The width of the wavefront is a hardware characteristic of the SIMD unit 124 of the APD104. In various embodiments, the APD104 includes a GPU architecture that emits a fixed-size wavefront, depending on the microarchitecture of the GPU hardware. Each processing core 122 includes one or more processing elements, such as scalar and / or vector floating-point units and arithmetic logic units (ALUs). In various embodiments, the processing core 122 further includes special-purpose processing units (not shown), such as inverse square root units and sine / cosine units.

[0022] Work items (e.g., threads) within a Wavefront are executed on SIMD hardware lanes (hereinafter referred to as "SIMD lanes") during their execution. In one embodiment, the processing elements of each SIMD unit 124 are arranged in an array containing 16 ALUs (referred to as lanes), each lane executing the same instruction simultaneously with other lanes in the SIMD unit 124, but using different data, and each work item is mapped to a lane during execution. In some embodiments, the Wavefront is a group of 64 threads referred to as Wave64 (thus each thread in the Wavefront is assigned to a lane ranging from 0 to 63), and these threads are issued in groups of 16 threads over 4 cycles via a 16-lane wide SIMD unit. However, those skilled in the art will understand, without departing from the scope of this disclosure, that the width of the Wavefront and the SIMD unit 124 may include any configuration or number of threads (e.g., 8, 16, 32, 64, etc.).

[0023] To facilitate dependency identification without incurring the power consumption and area costs of a hardware instruction scoreboard, the compiler 120 includes a software-based instruction scoreboard 126 that inserts control words, such as control word 118, into the command stream to indicate the dependency of one instruction on another. Based on the control word 118, the SIMD unit 124 delays the execution of a dependent instruction until the instruction it depends on (the parent instruction) has completed.

[0024] Figure 2 is a block diagram of a portion 200 of a processing system 100, showing a compiler 120 that inserts control words 206 indicating instruction dependencies into a command stream 204 of instructions for execution in a SIMD unit 124, according to several embodiments. Each SIMD unit 124 includes an instruction buffer 210, an issue stage 212, and a plurality of arithmetic logic units (ALUs) 214 (only one of which is illustrated). In some embodiments, one or more of the instruction buffer 210 and issue stages 212 are shared among the plurality of SIMD units 124, while in other embodiments, each SIMD unit 124 includes its own instruction buffer and issue stage. In the process of executing an operation, the compiler 120 generates a set of instructions to be executed in the ALUs 214. Examples of ALU instructions include addition instructions, multiplication instructions, matrix operation instructions, etc. The SIMD unit 124 stores the ALU instructions in the instruction buffer 210 for execution. The issue stage 212 controls one or more pointers that refer to entries in the instruction buffer 210. The issuing stage 212 manipulates pointers to read instructions from the instruction buffer and then provides the read instructions to the ALU 214. The act of reading instructions from the instruction buffer 210 and supplying them to the ALU 214 is referred to as "issuing" instructions to the ALU 214.

[0025] The ALU 214 executes the issued instructions to perform the arithmetic operations defined by the instructions. To facilitate the execution of instructions, the ALU 214 includes an ALU control module 216 and an ALU pipeline 218. The ALU pipeline 218 includes a plurality of pipeline stages (e.g., stage 220), and each stage executes one or more operations based on the instruction being executed and, in particular, on the data provided by the previous stage of the ALU pipeline 218. Thus, the issued instruction starts execution at the first stage of the ALU pipeline 218, and the first stage provides the result of the execution to the second stage that executes an operation based on the received data, then provides the result to the third stage, and so on until the instruction reaches the final stage of the ALU pipeline 218. The final stage stores the final result of the operation in a register file (not shown) or other storage location of the SIMD unit 124. Further, the ALU pipeline 218 executes instructions in a pipelined manner such that each stage of the ALU pipeline 218 executes different instructions simultaneously. That is, every predetermined cycle of the ALU pipeline 218, the first stage executes one instruction, the second stage executes another instruction, the third stage executes yet another instruction, and so on.

[0026] The ALU control module 216 monitors the states in the ALU pipeline 218 and controls, based on the monitored states, which stage executes the instructions of a given cycle. That is, in some embodiments, the ALU control module 216 controls the gating of the clock signal and other control signals to determine which stage of the ALU pipeline 218 executes an instruction in a given cycle. For example, under some conditions, the stages of the ALU pipeline 218 enter a stall state where the stage waits for data from the cache or waits for the preparation of a cache line for storing data, etc., waiting for an operation in another execution unit before the stage can proceed. The ALU control module 216 detects that the stage has entered the stall state and suspends the execution in other stages of the ALU pipeline 218 while the stall state persists, thereby preventing an instruction from proceeding in the stalled stage and causing an execution error.

[0027] The compiler 120 generates a dependency graph 202 that identifies all dependencies within the software programs executed in each of the SIMD units 124, and then generates a command stream 204 of instructions to be executed in the SIMD units 124. Based on the dependency graph 202, the software-based instruction scoreboard 126 identifies whether to schedule for issue without intervening instructions, or to schedule for issue within each other's threshold cycle counts, or the parent instructions and dependent instructions. The software-based instruction scoreboard 126 inserts a control word 206 into the command stream 204 to identify the dependent instructions and the parent instructions that the dependent instructions depend on.

[0028] In some embodiments, the software-based instruction scoreboard 126 simply inserts a control word 206 into the command stream if it determines that there are no (or insufficient) intervening instructions scheduled to be issued between a parent instruction and a dependent instruction. In some embodiments, the software-based instruction scoreboard 126 determines the sufficiency of the number of intervening instructions based on the number of stages in the ALU pipeline 218. For example, if the ALU pipeline 218 has four stages and there are fewer than four intervening instructions to be issued between a parent instruction and a dependent instruction, the software-based instruction scoreboard 126 determines that the interval between the parent instruction and the dependent instruction is short and inserts a control word 206 into the command stream 204 indicating the dependency of the dependent instruction to the parent instruction. However, if there are more than four intervening instructions to be issued between the parent instruction and the dependent instruction, the software-based instruction scoreboard 126 bypasses inserting the control word 206 into the command stream because the parent instruction completes before the dependent instruction is issued without requiring further delay.

[0029] Upon receiving the control word 206, the ALU control module 216 pauses the execution of dependent instructions until the parent instruction completes execution. The number of cycles required for the parent instruction to complete is the number of cycles from the time the issuance cycle elapses until the ALU 214 generates a result that can be consumed by subsequent instructions. In some embodiments, the number of cycles required for the parent instruction to complete execution depends on the width of the parent instruction's wavefront and the dependent instruction's wavefront. For example, in the case of a Wave 32 wavefront, the number of cycles required for the parent instruction to complete execution is the number of cycles required to issue the parent instruction plus the length of the ALU pipeline 218 (i.e., the number of ALU stages 220 in the ALU pipeline 218). In the case of a Wave 64 wavefront, the number of cycles required for the parent instruction to complete execution depends on whether the parent instruction is issued once or twice. In some embodiments, the Wavefront of Wave64 is issued in two passes, and the ALU control module 216 issues the dependent instruction after the first pass of the parent instruction is completed but before the second pass of the parent instruction is completed, so that the dependent instruction overlaps with the second pass of the parent instruction.

[0030] Figure 3 is a block diagram of a control word 308 showing the dependencies of certain instructions inserted into a command stream 300 in several embodiments. The command stream 300 includes instructions-1 302,-2 304,-3 306,-4 310,-5 312, and-6 314. In the illustrated example, instruction-4 310 depends on instruction-1 302, and instruction-6 314 depends on instruction-5 312.

[0031] To indicate dependencies and instruct the ALU control module 216 to delay the dependent instructions, instructions-4 310 and-6 314, until their respective parent instructions, instructions-1 302 and-5 312, are completed, the software-based instruction scoreboard 126 inserts a control word 308 into the command stream 300 before instruction-4 310. The control word 308 includes an identifier for the ALU 214 in which the parent instruction(s) are being executed, and an indication of the number of intervening instructions issued between the parent instruction and the dependent instruction. In the illustrated embodiment, the control word 308 identifies instruction-4 310 as dependent on an instruction issued three cycles prior to instruction-4 310, and identifies instruction-6 314 as dependent on an instruction issued one cycle prior to instruction-6 314. The control word 308 includes a “skip” code to identify the second dependent instruction (instruction-6 314) and its dependency on instruction-5 312. In one embodiment of the illustrated example, the control word 308 is: Data dependency: Instruction ID0=3, skip=2, instruction ID1=1. Here, instruction ID0=3 declares that the instruction word immediately following control word 308 (instruction-4 310) depends on an instruction issued three cycles prior to instruction-4 310 (instruction-1 302), skip=2 means that the next delay is not for the next instruction but for the instruction after the next instruction (instruction-6 314), and instruction ID1=1 declares that instruction-6 314 depends on an instruction issued one cycle prior to instruction-6 314 (instruction-5 312). In response to receiving control word 308, the ALU control module 216 adds a delay before issuing each of instructions-4 310 and instruction-6 314.

[0032] Figure 4 is a flowchart illustrating a method 400 for inserting control words indicating instruction dependencies into a command stream, according to several embodiments. The method 400 is described with respect to an exemplary implementation in the processing system 100 of Figure 1. In block 402, the compiler 120 identifies instruction dependencies. For example, in some embodiments, the compiler 120 generates a dependency graph 202 that identifies each dependency in the software program. In block 404, the compiler 120 issues instructions in the command stream 300. In block 406, a software-based instruction scoreboard 126 determines whether the instruction (parent instruction) that the dependent instruction depends on has been issued more than a threshold number of cycles before the dependent instruction. In some embodiments, the threshold number is based on the number of ALU stages 220 in the ALU pipeline 218. In block 406, if the software-based instruction scoreboard 126 determines that the parent instruction has been issued more than a threshold number of cycles before the dependent instruction, the method flow returns to block 404 and continues.

[0033] In block 406, if the software-based instruction scoreboard 126 determines that the parent instruction was not issued for more than a threshold number of cycles before the dependent instruction, the method flow proceeds to block 408. In block 408, the software-based instruction scoreboard 126 inserts a control word 308 into the command stream 300. The control word 308 identifies the ALU 214 from which the parent instruction was issued and the number of intervening instructions between the issuance of the parent instruction and the issuance of the dependent instruction. In some embodiments, the control word 308 indicates the dependency between two or more instructions, for example, by including a skip indicator. In block 410, the ALU control module 216 delays the execution of the dependent instruction until the parent instruction is completed.

[0034] In some embodiments, the above apparatus and techniques are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing systems described with reference to Figures 1 to 4. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used to design and manufacture these IC devices. These design tools are typically represented as one or more software programs. One or more software programs include computer-executable code for operating a computer system to operate with code representing the circuit of one or more IC devices in order to perform at least part of the process of designing or adapting a manufacturing system for manufacturing the circuit. This code may include instructions, data, or combinations of instructions and data. Software instructions representing the design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of designing or manufacturing an IC device is stored in and accessed from the same or different computer-readable storage medium.

[0035] Computer-readable storage media include any non-temporary storage media or combination of non-temporary storage media that are accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray® discs), magnetic media (e.g., floppy disks, magnetic tapes, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical system (MEMS) based storage media. Computer-readable storage media (e.g., system RAM or ROM) may be built into the computing system, computer-readable storage media (e.g., magnetic hard drives) may be permanently mounted to the computing system, computer-readable storage media (e.g., optical disks or Universal Serial Bus (USB) based flash memory) may be detachably mounted to the computing system, and computer-readable storage media (e.g., network-accessible storage (NAS)) may be connected to the computer system via a wired or wireless network.

[0036] In some embodiments, certain aspects of the technology described above are implemented by one or more processors of a processing system that executes the software. The software includes one or more sets of executable instructions, which are stored in a non-temporary computer-readable storage medium or otherwise clearly embodied. The software may also include instructions and specific data, which, when executed by one or more processors, operate the one or more processors to execute one or more aspects of the technology described above. Non-temporary computer-readable storage mediums may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, caches, random-access memory (RAM), or other non-volatile memory devices (one or more). Executable instructions stored in a non-temporary computer-readable storage medium can be implemented as source code, assembly language code, object code, or other instruction forms that can be interpreted or otherwise executed by one or more processors.

[0037] In addition to the foregoing, it should be noted that not all activities or elements described in the summary are required, and certain activities or parts of devices may not be required, and one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed does not necessarily indicate the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and variations can be made without departing from the scope of the invention as described in the claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all of these variations are intended to fall within the scope of the invention.

[0038] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and features that may give rise to or manifest any benefits, advantages, or solutions are not to be construed as essential, necessary, or indispensable features to any or all of the claims. Furthermore, the disclosed invention can be modified and implemented in different but similar ways, in ways that are obvious to those skilled in the art who are interested in the teachings of this specification; therefore, the specific embodiments described above are merely illustrative. There are no limitations to the details of the configuration or design shown herein beyond those described in the appended claims. Accordingly, the specific embodiments described above may be modified or altered, and it is clear that all such modifications are within the scope of the disclosed invention. Accordingly, the protection sought herein is described in the appended claims.

Claims

1. It is a method, The method involves inserting a control word into a command stream of a wavefront, wherein the command stream includes a first instruction executed in an arithmetic logic unit (ALU) pipeline of a single instruction multiple data (SIMD) unit, the SIMD unit is configured to execute the wavefront based on graphics commands received from a processor other than the SIMD unit, the control word indicates a first dependency of the first instruction to a second instruction to be executed in the ALU pipeline, and the ALU pipeline includes multiple stages. The insertion of the control word is performed after the issuance of the second instruction, in response to the issuance of the first instruction if the number of instructions is less than the threshold number. The aforementioned control word is received from the compiler of a device driver implemented in a circuit separate from the SIMD unit. method.

2. The ALU pipeline further includes delaying the execution of the first instruction based on the control word, The method according to claim 1.

3. The threshold number is based on the number of stages in the ALU pipeline. The method according to claim 1.

4. The aforementioned control word is, The identifier of the ALU in which the second instruction is being executed, Including an indication of the number of instructions issued between the issuance of the second instruction and the issuance of the first instruction, The method according to any one of claims 1 to 3.

5. The control word further includes indicating at least one second dependency of at least one third instruction to at least one fourth instruction for execution in the ALU pipeline. The method according to any one of claims 1 to 4.

6. It is a method, In a single instruction multiple data (SIMD) unit, a control word is received from a circuit separate from the SIMD unit, wherein the control word indicates that the first instruction depends on the second instruction when the first instruction issues fewer than a threshold number of instructions after the second instruction has been issued. The arithmetic logic unit (ALU) pipeline of the SIMD unit, comprising multiple stages, delays the execution of the first instruction by inserting the control word into the command stream of the wavefront, wherein the ALU pipeline is configured to execute a wavefront generated based on a graphics command received from a processor other than the SIMD unit. method.

7. The threshold number is based on the number of stages in the ALU pipeline. The method according to claim 6.

8. The aforementioned control word is, The identifier of the ALU in which the second instruction is being executed, Including an indication of the number of instructions issued between the issuance of the second instruction and the issuance of the first instruction, The method of claim 6 or 7.

9. The control word further includes indicating a second dependency of the third instruction on a fourth instruction to be executed in the ALU pipeline. The method according to any one of claims 6 to 8.

10. It is a device, A single instruction multiple data (SIMD) unit including an arithmetic logic unit (ALU) pipeline having multiple stages, the SIMD unit configured to execute a wavefront generated based on a graphics command received from a processor other than the SIMD unit, It comprises a circuit separate from the aforementioned SIMD unit, The aforementioned other circuit implements a device driver, The aforementioned device driver uses a compiler to: Inserting a control word into the command stream of a wavefront, wherein the command stream includes the first instruction that is executed in the ALU pipeline in response to the issuance of a second instruction and the issuance of fewer than a threshold number of instructions by the first instruction. The control word indicates a first dependency of the first instruction to the second instruction executed in the ALU pipeline. device.

11. The aforementioned ALU pipeline is The system is configured to delay the execution of the first instruction based on the control word. The device according to claim 10.

12. The threshold number is based on the number of stages in the ALU pipeline. The device according to claim 10.

13. The insertion of the control word is performed after the issuance of the second command to the ALU pipeline and while the wavefront is being executed in the ALU pipeline after the issuance of the first command to the ALU pipeline. The method according to claim 1.

14. The insertion of the control word is performed after the issuance of the second command to the ALU pipeline and while the wavefront is being executed in the ALU pipeline after the issuance of the first command to the ALU pipeline. The method according to claim 6.

15. The insertion of the control word is performed after the issuance of the second command to the ALU pipeline and while the wavefront is being executed in the ALU pipeline after the issuance of the first command to the ALU pipeline. The device according to claim 10.

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