Compilation optimization method, computer device and storage medium

Abstract

This application discloses a compilation optimization method, apparatus, computer device, and storage medium. The compilation optimization method includes obtaining source code, wherein the source code includes at least two code blocks of different processing types; determining data dependencies between instructions in the code blocks based on the processing types; automatically determining labels for the code blocks based on the data dependencies; and determining the execution order between the code blocks based on the labels to generate a pipeline. This compilation optimization method can improve code compilation efficiency in complex task flow scenarios.

Description

Technical Field

[0001] The present application relates to the field of code compilation, and in particular to a compilation optimization method, computer device, and storage medium. Background Art

[0002] Software pipelining is a method for accelerating code compilation. Currently, for simple task flow scenarios, software pipelining can be implemented using mechanisms such as double buffering. However, for complex task flow scenarios, software pipelining is currently difficult to implement effectively, resulting in low code compilation efficiency. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a compilation optimization method, a computer device, and a storage medium to solve the problem of low code compilation efficiency in complex task flow scenarios.

[0004] In a first aspect, an embodiment of the present application provides a compilation optimization method, comprising:

[0005] Obtaining source program code, wherein the source program code includes at least two code blocks of different processing types;

[0006] determining data dependencies between instructions in the code block based on the processing type;

[0007] Automatically determining a label of the code block according to the data dependency;

[0008] The execution order between the code blocks is determined according to the labels, and a pipeline is generated.

[0009] According to the above aspect and any possible implementation, further provided is an implementation, wherein the code blocks of the source program code include at least: a code block containing memory access instructions and a code block containing calculation instructions, and determining the data dependency between the instructions in the code blocks based on the processing type includes:

[0010] Determining data movement directions of the memory access instruction and the calculation instruction respectively, wherein the data movement direction of the memory access instruction includes from a first storage space to a second storage space, the data movement direction of the calculation instruction includes from the second storage space to a third storage space, and the data movement direction of the memory access instruction also includes from the third storage space to the first storage space;

[0011] The data dependency relationship between the memory access instruction and the calculation instruction is determined according to the data movement direction.

[0012] According to the above aspect and any possible implementation, an implementation is further provided, wherein the automatically determining the label of the code block according to the data dependency relationship includes:

[0013] If the instructions in at least one of the code blocks all read and write data to the same cache space, the label of the code block is automatically determined according to the data dependency relationship.

[0014] According to the above aspect and any possible implementation, further provided is an implementation, wherein determining the execution order between the code blocks according to the labels and generating a pipeline includes:

[0015] When the source program code includes n code blocks of the processing type, the execution order between the code blocks is determined according to the labels to generate at least two and at most n pipelines, where n≥2 and n is an integer.

[0016] According to the above aspects and any possible implementation, an implementation is further provided, wherein the source program code is code contained in a loop body.

[0017] According to the above aspects and any possible implementation manner, an implementation manner is further provided, wherein the method further includes:

[0018] Allocating pipeline memory according to the code block in the source program code;

[0019] The total pipeline memory is obtained by multiplying the pipeline memory by the number of types of the processing type.

[0020] According to the above aspects and any possible implementation manner, there is further provided an implementation manner, wherein the source program code includes a status identifier, and the method further includes:

[0021] When the status flag is true, the pipeline function is enabled and memory for the pipeline is allocated;

[0022] When the status flag is false, the pipeline function is disabled.

[0023] According to the above aspects and any possible implementation manner, an implementation manner is further provided, wherein the method further includes:

[0024] The source program code that determines the execution order is compiled into target code.

[0025] In a second aspect, an embodiment of the present application provides a compilation optimization device, comprising:

[0026] An acquisition module, configured to acquire source program code, wherein the source program code includes at least two code blocks of different processing types;

[0027] a first determining module, configured to determine data dependencies between instructions in the code block based on the processing type;

[0028] A second determining module, configured to automatically determine a label of the code block according to the data dependency;

[0029] The third determining module is configured to determine the execution order between the code blocks according to the labels and generate a pipeline.

[0030] Furthermore, the code block of the source program code includes at least: a code block containing a memory access instruction and a code block containing a calculation instruction, and the first determining module is specifically configured to:

[0031] determining a data movement direction of the memory access instruction and the calculation instruction, wherein the data movement direction of the memory access instruction includes from a first storage space to a second storage space, the data movement direction of the calculation instruction includes from the second storage space to a third storage space, and the data movement direction of the memory access instruction also includes from the third storage space to the first storage space;

[0032] The data dependency relationship between the memory access instruction and the calculation instruction is determined according to the data movement direction.

[0033] Furthermore, the second determining module is specifically configured to:

[0034] If the instructions in at least one of the code blocks all read and write data to the same cache space, the label of the code block is automatically determined according to the data dependency relationship.

[0035] Furthermore, the third determining module is specifically configured to:

[0036] When the source program code includes n code blocks of the processing type, the execution order between the code blocks is determined according to the labels to generate at least two and at most n pipelines, where n≥2 and n is an integer.

[0037] Furthermore, the source program code is code contained in a loop body.

[0038] Furthermore, the compilation optimization method further includes:

[0039] Allocating pipeline memory according to the code block in the source program code;

[0040] The total pipeline memory is obtained by multiplying the pipeline memory by the number of types of the processing type.

[0041] Furthermore, the source program code includes a status identifier, and the compilation optimization method further includes:

[0042] When the status flag is true, the pipeline function is enabled and memory for the pipeline is allocated;

[0043] When the status flag is false, the pipeline function is disabled.

[0044] Furthermore, the compilation optimization method further includes:

[0045] The source program code that determines the execution order is compiled into target code.

[0046] In a third aspect, an embodiment of the present application provides a computer device comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein the processor executes the steps of the compilation optimization method described in the first aspect when executing the computer-readable instructions.

[0047] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores computer-readable instructions. When the computer-readable instructions are executed by a processor, the steps of the compilation optimization method described in the first aspect are implemented.

[0048] In an embodiment of the present application, source program code including at least two code blocks of different processing types is first obtained, and the data dependency relationship between the instructions in the code block is determined based on the processing type of the code block, so as to analyze and confirm the data dependency relationship between the instructions in the code block based on the instruction itself, and then the label of the code block is automatically determined according to the data dependency relationship to automatically classify the code block, and finally the execution order between the code blocks is determined according to the label to generate a pipeline. The pipeline order between the code blocks in the pipeline can be determined according to the classified labels, and the efficiency of code compilation can be improved in complex task flow scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 This is a schematic diagram of a double buffering mechanism implementation in an embodiment of the present application;

[0051] Figure 2 This is a flowchart of a compilation optimization method in an embodiment of the present application;

[0052] Figure 3 This is a schematic diagram of a source code using software pipelining in an embodiment of the present application;

[0053] Figure 4 This is a principle block diagram of a device corresponding one-to-one to the compilation optimization method in an embodiment of the present application;

[0054] Figure 5 It is a schematic diagram of a computer device in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0056] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0057] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a," "an," and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0058] It should be understood that the term "and / or" as used herein is simply a term used to describe the existence of three possible relationships between related objects. For example, "A and / or B" can represent the existence of A alone, the existence of both A and B, and the existence of B alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0059] It should be understood that although the terms "first," "second," and "third" may be used in the embodiments of the present application to describe preset ranges, etc., these preset ranges should not be limited to these terms. These terms are merely used to distinguish one preset range from another. For example, without departing from the scope of the embodiments of the present application, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0060] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0061] Currently, for simple task flow scenarios, software pipelining can be implemented using a double buffer mechanism. Figure 1 This is a schematic diagram of a double buffer mechanism implementation in the embodiment of the present application. Figure 1 As shown, the double-buffer mechanism can specifically divide a cache space into cache space A and cache space B. The data input to cache space A and cache space B comes from the storage unit. In order to fully utilize the computing unit, the data in cache space A can be first transferred to the computing unit for computational processing. In the process of the computing unit computing the data in cache space A, the data in cache space B can be transferred to the computing unit in parallel, so that after the computing unit completes the computational processing of the data in cache space A, it continues to compute the data in cache space B without waiting, thereby achieving the purpose of parallel data processing. This approach is easier to implement in simple task flow scenarios, but for complex task flow scenarios, since the double-buffer mechanism targets the computational tasks of the computing units in a pipeline, it is necessary to find code content in the code that can implement the computational tasks to execute the computational tasks. When the number of tasks in the pipeline increases, the complexity of the software pipeline implementation will be significantly increased.

[0062] The present application provides a compilation optimization method. Figure 2 This is a flowchart of a compilation optimization method in an embodiment of the present application. The compilation optimization method can be applied in the scenario of code compilation and can be implemented in a computer device that supports code compilation. In this application, the code compilation efficiency will be optimized to make full use of computer resources. Figure 2 As shown, the compilation optimization method includes the following steps:

[0063] S10: Acquire source program code, wherein the source program code includes at least two code blocks of different processing types.

[0064] The codes in the source program code that perform different operations or realize different functions can be classified into different code blocks, and each code block can include at least one instruction.

[0065] Among them, the processing type of the code block is classified according to the type of hardware resources of the computer device required to execute the instructions in the code block. The hardware resources of the computer device include at least storage resources (such as cache space) and computing resources (such as computing units). For example, access (load) and storage (store) type operations (instructions), both of which access storage resources through a memory access interface (such as an I / O interface or DMA (Direct Memory Access, direct memory access), etc.), and the processing type of such code blocks can be marked as a memory access type. For data calculation type operations (instructions), such operations (instructions) require computing resources to implement the calculation process of specific operations, and the processing type of such code blocks can be marked as a computing type. Among them, such data calculation type instructions include but are not limited to addition instructions, multiplication instructions, convolution instructions and activation instructions, etc., which are only given as examples here.

[0066] It should be noted that, for example, if data processing operations such as load and store operations can be implemented through dedicated processing interfaces (i.e., two different memory access channels), the code blocks for load and store operations should be considered to be two different processing types. This processing type is related to the type of resources occupied by the data processing and has nothing to do with the operation type of the instructions in the code block itself.

[0067] In one embodiment, when optimizing code compilation, source code is first obtained. The source code includes at least two code blocks of different processing types. Software pipelines can be performed on the source code based on the at least two code blocks of different processing types, allowing the source code to fully utilize computer resources that would otherwise be idle during compilation.

[0068] S20: Determine data dependencies between instructions in the code block based on the processing type.

[0069] Data dependencies can refer to the relationship between the operands of instructions. If the source operand or destination operand of one instruction is the source operand of another instruction, the instructions can be considered to have a data dependency. The operands of an instruction can be represented as data addresses. For tensor data such as vectors or matrices, the data dependency between instructions can refer to the overlapping relationship between the storage addresses of the data processed by the instructions.

[0070] For example, before executing a calculation type instruction, the computing unit needs to first execute a memory access type instruction and transfer the input data required for the calculation type instruction to the computing unit. At this time, the execution of the calculation type instruction depends on the execution result of the memory access type instruction.

[0071] In one embodiment, the data dependency between instructions in the code block is analyzed and determined based on the processing type of the code block, so as to determine the order of execution of instructions in the code block in the underlying logic based on the data dependency. Specifically, the processing type of the code block can reflect the stage of the instruction when it is executed. For example, the instruction can be divided into different stages of data access, data calculation and data storage. These stages have their own logical order of execution. For example, when operating on data, it is first necessary to read (access) the data from the storage space, then process (calculate) the data, and finally write (store) the processing result to the storage space. In addition to reflecting the various stages of the instruction when it is executed, the processing type of the code block can also reflect the direction of the data in different storage spaces during compilation, thereby determining the data dependency between instructions in the code block. It can be understood that when operating on data, multiple different storage spaces are involved. The present application fully analyzes the data in different storage spaces during code compilation, thereby realizing software pipelining under the premise of determining the data dependency.

[0072] S30: Automatically determine the label of the code block based on data dependencies.

[0073] In one embodiment, each code block may be labeled accordingly, and the label is used to determine the stage of execution of the instructions contained in the code block. After determining the data dependencies of the instructions in the source code, in this application, the label of the code block will be automatically generated according to the data dependencies. For example, a source code includes three types of codes representing different processing types, specifically including the following memory access type codes: tcp.memcpy(X,global_inputx[i]); tcp.memcpy(global_outputX[i],X), and the following calculation type codes: tcp.sigmoid(X,X); tcp.relu(X,X). For these code blocks of different processing types, the code can be labeled according to the type of code, such as the code that performs the access operation tcp.memcpy(X,global_inputx[i]), its label can be expressed as stage = "load". Similarly, for the code tcp.memcpy(global_outputX[i],X) that performs a storage operation, its label can be expressed as stage = "store", and for the code tcp.sigmoid(X,X) and tcp.relu(X,X) that performs a computational operation, its label can be expressed as stage = "compute". In this way, by automatically determining the labels for the instructions, the source code can be classified into code blocks of different stages. When implementing software pipelining, the instructions can be correctly executed according to these labels. When targeting complex task flow scenarios, different tasks can be accurately distinguished, and the source code can be compiled correctly and quickly. Optionally, the above labels can be stored in a storage space to facilitate pipeline generation. Furthermore, the instructions in the code block can be stored in the storage space in a one-to-one correspondence with their corresponding labels.

[0074] S40: Determine the execution order between code blocks according to the labels and generate a pipeline.

[0075] In one embodiment, when a computer compiles source code, it first reads the tags in the code and then determines the code blocks in the source code based on the tags. During the compilation process, a pipeline is generated with the code blocks as the basic units and the execution order corresponding to the tags. Figure 3 This is a schematic diagram of a source code using software pipelining in an embodiment of the present application. Figure 3As shown in the figure, there are 3 pipelines, each of which represents the pipeline process in the form of a code block. Specifically, as in the first pipeline, when the computer compiles the source program code, it can read the label in the code. For example, when reading stage_scope="load", it can be determined that the code block is the code block for the access operation, and according to the execution order of the data before and after in the data dependency relationship, it can be known that the access operation is the first operation in the data processing. Similarly, the code block for the calculation operation and the code block for the storage operation can be determined according to the label in the code, and then the execution order between the code blocks can be determined according to the data dependency relationship, access-calculation-storage, thereby forming a sequence as shown below. Figure 3 The pipeline shown.

[0076] The compiler can automatically generate Figure 3 The pipeline shown enables code blocks to call different hardware resources to operate on data at the same time during pipeline operation, thereby improving the efficiency of code compilation.

[0077] In steps S10-S40, the source program code including at least two code blocks of different processing types is first obtained, and the data dependency relationship between the instructions in the code block is determined based on the processing type of the code block, so as to analyze and confirm the data dependency relationship between the code block instructions from the instruction itself, and then the label of the code block is automatically determined according to the data dependency relationship to automatically classify the code block, and finally the execution order between the code blocks is determined according to the label, and a pipeline is generated. The pipeline order between the code blocks in the pipeline can be determined according to the classified labels, which can improve the efficiency of code compilation in complex task flow scenarios.

[0078] Furthermore, the above-mentioned code blocks may include memory access type code blocks and calculation type code blocks, wherein the memory access type code blocks may include at least one memory access instruction, and the calculation type code blocks may include at least one calculation instruction.

[0079] Furthermore, the memory access instruction may specifically include a load instruction and a store instruction. Based on this, the memory access type code block may also be divided into an access type code block and a store type code block.

[0080] In this application, memory access instructions are divided into two processing types: access instructions and storage instructions. The solution is described using instructions of these three processing types and their corresponding code blocks. It is understood that when data memory access relies on different storage resources, access instructions and storage instructions should be considered two independent processing types.

[0081] Furthermore, in step S20, i.e., the step of determining the data dependency relationship between instructions based on the processing type, the following steps are specifically included:

[0082] S21: respectively determine the data movement direction of the memory access instructions in the memory access type code block and the data movement direction of the calculation instructions in the calculation type code block, wherein the data movement direction of the memory access instructions in the memory access type code block includes from the first storage space to the second storage space, the data movement direction of the calculation instructions in the calculation type code block includes from the second storage space to the third storage space, and the data movement direction of the memory access instructions in the memory access type code block also includes from the third storage space to the first storage space.

[0083] The data movement direction reflects the transformation of data in the storage space.

[0084] In one embodiment, the source code may be a code formed by a tensor computing primitive constructed based on the Python language, such as TCP (Tensor Computer Primitive). Specifically, the source code includes the following code for memory access instructions:

[0085] tcp.memcpy(X,global_inputx[i]);tcp.memcpy(global_outputX[i],X), and the following code with calculation instructions: tcp.sigmoid(X,X);tcp.relu(X,X). Among them, from the tcp.memcpy(X,global_inputx[i]) code, we can see that the code represents a data access operation, and its data movement direction is global_inputx[i]->X, where the storage space where global_inputx[i] is located is specifically the first storage space, and the storage space where X is located is specifically the second storage space. Similarly, the tcp.memcpy(global_outputX[i],X) code represents a data storage operation, and its data movement direction is X->global_outputX[i]. Among them, because the hardware resources involved in the access operation and the storage operation are the same, the storage space where global_outputX[i] is located is specifically the first storage space, and the storage space where X is located is specifically the second storage space. Furthermore, global_inputx[i] and global_outputX[i] can be off-chip storage on the hardware processor, such as DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and X can be on-chip storage space on the hardware processor. Analyzing the code of the calculation instructions, we can see that tcp.sigmoid(X,X) and tcp.relu(X,X) represent the calculation operations of performing sigmoid and relu operations on the data, respectively. Since the calculation process involves the same hardware resources (such as GPU) and the intermediate results of the activation operation do not need to be saved, the storage space in this application can use the same storage space X, that is, the second storage space and the third storage space point to the same storage space, which can improve data processing efficiency.

[0086] In other embodiments, the second storage space and the third storage space are different storage spaces. For example, the calculation instruction is tcp.relu(X1, X2). In this application, at this time, the data movement direction of the calculation instruction is from the second storage space X2 to the third storage space X1, that is, data is read from the storage space pointed to by X2 to perform relu activation operation, and the operation result is stored in the storage space pointed to by X1. X1 and X2 point to different address spaces respectively.

[0087] S22: Determine the data dependency between the memory access instruction and the calculation instruction according to the data movement direction.

[0088] In one embodiment, the relationship between data and storage space during instruction execution can be determined based on the data movement direction, thereby determining the data dependency between memory access instructions and calculation instructions. Those skilled in the art will appreciate that before a processor executes a calculation, the data required for the calculation instruction should first be read into the processor's on-chip storage space (i.e., the data load process). After completing the calculation instruction, the calculation result obtained by the calculation instruction can be transferred from the on-chip storage space back to the off-chip storage space (i.e., the data store process), thereby reducing the occupancy of the on-chip storage space. Based on this, combined with the above analysis to obtain the data movement direction, the data dependency of each instruction can be determined. For example, when performing a calculation operation (such as addition, multiplication, convolution, etc.) on a data object, it is first necessary to read the data object required for the calculation operation. This process is also the data access operation process. Afterwards, after reading the data object, the calculation operation can be performed, i.e., the calculation process of the data object. After completing the calculation operation, the calculation result is stored in the designated storage space, i.e., the storage process of the data object. In this way, under the premise of determining the direction of data movement, combined with the execution logic that the data processing process should have, the data dependency relationship between memory access instructions and calculation instructions can be determined.

[0089] In an embodiment of the present disclosure, when there are more than two instructions in a code block of a computing type, the data dependency between the at least two computing instructions can also be determined based on the data movement direction between the at least two computing instructions, so as to determine the execution order between the computing instructions based on the data dependency between the at least two computing instructions.

[0090] Furthermore, in order to implement the execution of the above-mentioned source program code, the present application may first allocate storage space for the source program code in the hardware processor before executing the above-mentioned source program code. The storage space may be cache space. The specific cache allocation method is described below. In the above-mentioned embodiment, the memory access instructions and calculation instructions can access the cache space to implement data movement and calculation processes. Specifically, the above-mentioned method further includes the following steps:

[0091] If at least one code block reads and writes data to the same cache space, the code block label is automatically determined based on the data dependency. Instructions in each code block of a pipeline can read and write to the same cache space, which may include the aforementioned second storage space. Therefore, if instructions read and write data to the same cache space, the code block label is automatically determined based on the dependency between the instructions to implement automatic software pipelining. Otherwise, if instructions read and write to different cache spaces, there is no need to automatically determine the instruction label based on the data dependency, and an error may be reported in this case.

[0092] For example, Figure 1The dual-buffer mechanism used divides the cache space into cache space A and cache space B. When instructions read and write cache space A or cache space B, corresponding labels can be automatically generated for each code block based on the above method to automatically generate the pipeline; if the load instruction operates on cache space A and the compute instruction operates on cache space B, there is no need to automatically determine the instruction label based on the data dependency, and an error may be reported at this time.

[0093] Similarly, when compiling source code, it is necessary to ensure that the data read and write of the compiled instructions will not be interfered with by the execution of other instructions. In one embodiment, to implement software pipelining, each pipeline must correspond to a cache space, and each instruction in the source code reads and writes data to the same cache space. If an instruction involves reading and writing data to multiple cache spaces, an error is reported and pipelining is not executed.

[0094] Specifically, the starting address of the instruction and the size of its data can be used to determine whether the instruction is reading and writing data in the same cache space, wherein the data size can be the data length or the address offset relative to the starting address. In an embodiment of the present application, the above-mentioned source code can be a code formed by a tensor calculation primitive built based on the Python language. At this time, the compiler can obtain the starting address and data size of the data involved in each instruction at compile time, and judge whether each instruction accesses the same cache space at compile time. Compared with the prior art, the method of obtaining the size of the data in the instruction during intelligent operation, the present application can more conveniently realize the dependency judgment between data, thereby automatically generating a software pipeline.

[0095] Optionally, the compiler may determine the address range accessed by each instruction based on the starting address and data size of each instruction. If the address ranges of each instruction are all within the address range of the cache space, the multiple instructions are determined to access the same cache space. Otherwise, if the address range of at least one of the multiple instructions is not within the address range of the cache space, the multiple instructions are determined to access different cache spaces.

[0096] Furthermore, in the step of determining the execution order between code blocks according to the labels and generating the pipeline, the following steps are specifically included:

[0097] When the source program code includes code blocks of n processing types, the execution order between the code blocks is determined according to the labels, and at least two and at most n pipelines are generated, where n≥2 and n is an integer.

[0098] In one embodiment, the processing types of code blocks in the source program code correspond to different hardware resources. If the source program code includes code blocks of n processing types, a maximum of n pipelines can be set.

[0099] For example, suppose the source code contains code blocks for different processing types, including load instructions, compute instructions, and store instructions. The load instructions can specifically call hardware resources such as I / O interfaces, the store instructions can specifically call storage interfaces such as DMA, and the compute instructions can call hardware computing resources such as GPUs. In this case, the compiler can automatically generate three pipelines.

[0100] like Figure 3 As shown, there are three pipelines in total, each of which includes a code block containing access instructions, a code block containing computation instructions, and a code block containing storage instructions. It can be seen that at the same time, different hardware resources can execute different instructions. For example, on the three pipelines, access instructions, computation instructions, and storage instructions are executed simultaneously in the vertical direction. Specifically, the three code blocks of the first pipeline can be divided into T1, T2, and T3 on the timeline. At T1, the Data_load of the first pipeline is executed; at T2, the Data_compute of the first pipeline and the Data_load of the second pipeline are executed; and at T3, the Data_store of the first pipeline, the Data_compute of the second pipeline, and the Data_load of the third pipeline are executed. At this time, the Data_load, Data_compute, and Data_store instructions are executed in different hardware resources, achieving the effect of parallel execution. It can be understood that this software pipeline can execute different code blocks of the source code on different pipelines, completing the data operations contained in different code blocks on different hardware resources, significantly improving compilation efficiency compared to traditional compilation.

[0101] For example, suppose the source code contains code blocks of different processing types, each containing load instructions, compute instructions, and store instructions. The load instructions and store instructions call the same interface, meaning they belong to the same processing type. The compute instructions may call hardware computing resources such as a GPU. In this case, the compiler can automatically generate two pipelines.

[0102] In one embodiment, the source program code may specifically be a code portion included in a loop body. The source program code in the loop body may execute software pipelining, decouple the original loop logic in the loop body, and perform parallel operations on data at the same time, thereby improving compilation efficiency.

[0103] Furthermore, the compilation optimization method further includes the following steps:

[0104] S511: Allocate pipeline memory according to code blocks in the source program code.

[0105] Among them, one pipeline corresponds to one cache space. Allocating memory for the pipeline is to determine the size of the cache space. The allocation of pipeline memory should be determined by the memory required when compiling the code blocks on the pipeline.

[0106] In one embodiment, when allocating memory for a pipeline, the memory size occupied by each code block in the source code can first be obtained. The code block with the largest memory usage is then used as the pipeline memory. It is understood that when the source code is compiled, multiple pipelines may be running at the same time, but the memory occupied by each pipeline at the current moment does not exceed the largest memory usage among the instructions in the source code. Therefore, when allocating pipeline memory, the minimum memory usage must be equal to the memory usage of the largest code block in the source code. This can improve the utilization of memory resources.

[0107] S512: Multiply the pipeline memory by the number of processing types to obtain the total pipeline memory.

[0108] In one embodiment, assuming that the memory allocated to a pipeline is m, and the number of types of processing types in the code block of the source program code is n, the total pipeline memory is m*n. In order to implement software pipelining, the memory can be allocated once for the compilation of the source program code, thereby completing the compilation quickly.

[0109] like Figure 3 As shown, when the number of source code processing types is 3, the total pipeline memory of the pipeline is 3*the maximum memory required for compiling the code block in a pipeline.

[0110] Furthermore, the source program code includes a status identifier.

[0111] Furthermore, the compilation optimization method further includes the following steps:

[0112] S521: When the status flag is true, the pipeline function is enabled and pipeline memory is allocated.

[0113] S522: When the status flag is false, the pipeline function is closed.

[0114] Among them, the status identifier can be represented by stage. When stage=1, it indicates that the pipeline function is turned on, and the compilation optimization method as in the above embodiment can be used to automatically generate software pipelines for the source program code. When stage=0, it indicates that the pipeline function is turned off. It can be understood that the user can control the opening and closing of the pipeline function. If the user does not need to turn on the pipeline function, the stage can be set to 0. If the user wants to turn on the pipeline function, the stage can be set to 1.

[0115] In one embodiment, the user can choose to enable the pipelining function based on actual circumstances. It is understood that enabling pipelining requires the computer to allocate a certain amount of memory for compilation, and the memory occupied by such compilation is greater than that of normal compilation mode. If the workload of compiling source code is low or if enabling pipelining consumes too much memory, the pipelining function can be disabled.

[0116] Furthermore, the compilation optimization method further includes the following steps:

[0117] Compile the source code that determines the execution order into object code.

[0118] In the embodiment of the present application, by pipeline compilation of the source program code as described above, the source program code that has completed pipeline optimization can be compiled to generate target code. For example, after the code formed by the tensor calculation primitive constructed based on the Python language is compiled and optimized using software pipelining, the code formed by the tensor calculation primitive constructed based on the Python language can be converted into a corresponding C-like language code, such as a BANGC language code, based on the code blocks in the software pipelining. It can be understood that in the embodiment of the present application, the code blocks in the pipelining can be first determined, and then the target code required by the user can be generated according to the execution order of the code blocks in the software pipelining, so that when the target code is executed again, the software pipelining method can be used to achieve compilation optimization in the compilation environment of the target code, thereby improving compilation efficiency.

[0119] Furthermore, the present application can also compile the target code into binary instructions that can be executed by the hardware platform.

[0120] In an embodiment of the present application, the data dependency between instructions in a code block is analyzed and confirmed based on the instructions themselves, and the labels of the code blocks are automatically determined to achieve automatic classification of the code blocks. The present application uses a pipeline generated based on data dependency to improve the efficiency of code compilation in complex task flow scenarios. Furthermore, the present application also analyzes the data movement direction of memory access instructions and calculation instructions, and obtains the true logical execution relationship of data in the source program code based on the relationship between data transformation in storage space when instructions are executed, and determines the data dependency between memory access instructions and calculation instructions.

[0121] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0122] Figure 4 This is a principle block diagram of a device corresponding to the compilation optimization method in the embodiment of the present application. Figure 4As shown, the compilation optimization device includes an acquisition module 10 , a first determination module 20 , a second determination module 30 and a third determination module 40 .

[0123] The acquisition module 10 is used to acquire source program code, wherein the source program code includes at least two code blocks of different processing types.

[0124] The first determining module 20 is configured to determine data dependencies between instructions in a code block based on a processing type.

[0125] The second determining module 30 is configured to automatically determine the label of the code block according to the data dependency relationship.

[0126] The third determining module 40 is configured to determine the execution order between code blocks according to the tags and generate a pipeline.

[0127] Furthermore, the code blocks of the source program code include at least: a code block containing a memory access instruction and a code block containing a calculation instruction, and the first determining module 20 is specifically configured to:

[0128] Determining data movement directions of memory access instructions and calculation instructions respectively, wherein the data movement direction of the memory access instructions includes from the first storage space to the second storage space, the data movement direction of the calculation instructions includes from the second storage space to the third storage space, and the data movement direction of the memory access instructions also includes from the third storage space to the first storage space;

[0129] The data dependency between memory access instructions and computation instructions is determined based on the data movement direction.

[0130] Furthermore, the second determining module 30 is specifically configured to:

[0131] If the instructions in at least one code block all read and write data to the same cache space, the label of the code block is automatically determined based on the data dependency.

[0132] Furthermore, the third determining module 40 is specifically configured to:

[0133] When the source program code includes code blocks of n processing types, the execution order between the code blocks is determined according to the labels, and at least two and at most n pipelines are generated, where n≥2 and n is an integer.

[0134] Furthermore, the source program code is the code contained in a loop body.

[0135] Furthermore, the compilation optimization method further includes:

[0136] Allocate pipeline memory according to code blocks in the source code;

[0137] Multiply the pipeline memory by the number of types being processed to get the total pipeline memory.

[0138] Furthermore, the source program code includes a status identifier, and the compilation optimization method further includes:

[0139] When the status flag is true, the pipeline function is turned on and the pipeline memory is allocated;

[0140] When the status flag is false, the pipeline function is disabled.

[0141] Furthermore, the compilation optimization method further includes:

[0142] Compile the source code that determines the execution order into object code.

[0143] In an embodiment of the present application, first, a source program code including at least two code blocks of different processing types is obtained, and the data dependency relationship between the code block instructions is determined based on the processing type of the code block, so as to analyze and confirm the data dependency relationship between the instructions in the code block from the instruction itself, and then the label of the code block is automatically determined based on the data dependency relationship to automatically classify the code block, and finally the execution order between the code blocks is determined based on the label to generate a pipeline, which can determine the pipeline order of each code block instruction on the pipeline based on the classified label, and can improve the efficiency of code compilation in complex task flow scenarios. Furthermore, the present application also obtains the true logical execution relationship of the data in the source program code based on the relationship between the data transformation in the storage space when the instruction is executed, and determines the data dependency relationship between the memory access instruction and the calculation instruction by analyzing the data movement direction of the memory access instruction and the calculation instruction.

[0144] The present application also provides a computer-readable storage medium, which stores computer-readable instructions. When the computer-readable instructions are executed by a processor, the compilation optimization method as described in the embodiment is implemented.

[0145] The present application also provides a computer device. Figure 5 Schematic diagram of a computer device in an embodiment of the present application. Figure 5 As shown, the computer device 110 includes a processor 111, a memory 112, and computer-readable instructions 113 stored in the memory 112 and executable on the processor 111. When the processor 111 executes the computer-readable instructions 113, each step of the compilation optimization method is implemented.

[0146] For example, the computer-readable instructions 113 may be divided into one or more modules / units, one or more of which are stored in the memory 112 and executed by the processor 111 to implement the present application. The one or more modules / units may be a series of computer-readable instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer-readable instructions 113 in the computer device 110.

[0147] The computer device 110 may be a desktop computer, a notebook computer, a PDA, a cloud server, or other computing device. The computer device may include, but is not limited to, a processor 111 and a memory 112. Those skilled in the art will appreciate that Figure 5 This is merely an example of the computer device 110 and does not constitute a limitation of the computer device 110 . The computer device 110 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the computer device may also include input and output devices, network access devices, buses, etc.

[0148] The processor 111 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0149] The memory 112 may be an internal storage unit of the computer device 110, such as a hard disk or memory of the computer device 110. The memory 112 may also be an external storage device of the computer device 110, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the computer device 110. Furthermore, the memory 112 may include both an internal storage unit of the computer device 110 and an external storage device. The memory 112 is used to store computer-readable instructions and other programs and data required by the computer device. The memory 112 may also be used to temporarily store data that has been output or is about to be output.

[0150] The embodiments of the present application can acquire and process relevant data based on artificial intelligence technology. Artificial Intelligence (AI) is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use knowledge to achieve optimal results.

[0151] Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interaction systems, and mechatronics. AI software technologies primarily encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0152] In an embodiment of the present application, the server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0153] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0154] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium, and the computer-readable instructions, when executed by the processor, can implement the steps of the above-mentioned various method embodiments. Wherein, the computer-readable instructions include computer-readable instruction codes, and the computer-readable instruction codes can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device that can carry the computer-readable instruction code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practices in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practices, computer-readable media does not include electrical carrier signals and telecommunication signals.

[0155] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0156] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A compilation optimization method, characterized in that: include: Obtaining source program code, wherein the source program code includes at least two code blocks of different processing types; determining data dependencies between instructions in the code block based on the processing type; Automatically determining a label of the code block according to the data dependency; Determine the execution order between the code blocks according to the labels and generate a pipeline; The code blocks of the source program code include at least: a code block including memory access instructions and a code block including calculation instructions, and determining the data dependency between the instructions in the code blocks based on the processing type includes: Determining data movement directions of the memory access instruction and the calculation instruction respectively, wherein the data movement direction of the memory access instruction includes from a first storage space to a second storage space, the data movement direction of the calculation instruction includes from the second storage space to a third storage space, and the data movement direction of the memory access instruction also includes from the third storage space to the first storage space; determining the data dependency relationship between the memory access instruction and the calculation instruction according to the data movement direction; The method further comprises: The source program code that determines the execution order is compiled into target code.

2. The method according to claim 1, characterized in that The automatically determining the label of the code block according to the data dependency relationship includes: If the instructions in at least one of the code blocks all read and write data to the same cache space, the label of the code block is automatically determined according to the data dependency relationship.

3. The method according to claim 1, characterized in that Determining the execution order between the code blocks according to the labels and generating a pipeline includes: When the source program code includes n code blocks of the processing type, the execution order between the code blocks is determined according to the labels to generate at least two and at most n pipelines, where n≥2 and n is an integer.

4. The method according to claim 1, wherein The source program code is the code contained in a loop body.

5. The method according to claim 1, wherein The method further comprises: Allocating pipeline memory according to the code block in the source program code; The total pipeline memory is obtained by multiplying the pipeline memory by the number of types of the processing type.

6. The method according to claim 1, characterized in that The source program code includes a status identifier, and the method further includes: When the status flag is true, the pipeline function is enabled and memory for the pipeline is allocated; When the status flag is false, the pipeline function is disabled.

7. A computer device comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein: When the processor executes the computer-readable instructions, the processor performs the steps of the compilation optimization method according to any one of claims 1 to 6.

8. A computer-readable storage medium storing computer-readable instructions, characterized in that: When the computer-readable instructions are executed by a processor, the steps of the compilation optimization method according to any one of claims 1 to 6 are implemented.

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