A Binding Method for Parallel Circuit Simulation Threads Based on the ARM Platform

Abstract

A binding method, an electronic device, and a storage medium for parallel circuit simulation threads based on an ARM platform. The method includes: determining the circuit scale to which the circuit belongs based on the specific structure of the circuit, where the circuit scale includes a first scale level and a second scale level; for circuits at the first scale level, binding the corresponding circuit simulation threads to the same NUMA Node according to the NUMA Node binding order and binding them to the processor cores according to the processor core binding order corresponding to the NUMA Node; for circuits at the second scale level, dispersedly binding the corresponding circuit simulation threads to multiple NUMA Nodes according to the NUMA Node binding order and binding them to the processor cores according to the processor core binding order corresponding to each NUMA Node. The binding method for parallel circuit simulation threads based on an ARM platform in this application improves the performance of multi-threaded parallel simulation of circuits.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method for binding parallel circuit simulation threads based on an ARM platform, an electronic device, and a storage medium. Background Art

[0002] In the process of circuit transient simulation, the Newton-Raphson iteration method is used to solve a large-scale non-linear equation system at each time point. Each step of the Newton-Raphson iteration method is a process of solving the linear equation system Ax = b. The solution of the sparse linear equation system Ax = b has high complexity and long time consumption, occupying the largest proportion of the total circuit simulation time, and becoming the performance bottleneck of circuit simulation.

[0003] With the increasing advancement of circuit design technology, the circuit scale is getting larger and larger, and the matrix dimension is also getting larger and larger. Using multi-threaded circuit simulation thread parallel simulation has become an important means.

[0004] In the prior art, circuit simulation does not perform thread affinity binding, and threads will be frequently assigned by the scheduler to different processor cores for execution, that is, the so-called threads migrate on different processor cores, which will bring performance overhead. Because when a thread migrates to a new processor core, the data in the cache may need to be refilled, and the branch predictor also needs to re-predict branches. These operations will all consume a certain amount of time, so the performance may decrease for a period of time after migration. In particular, the prior art rarely utilizes the hardware characteristics of NUMA in the NUMA architecture. At this time, when there is cross-NUMA migration of threads, the probability of memory page fault interrupts will increase greatly, and memory access latency will also be caused, further affecting the performance of circuit simulation. Summary of the Invention

[0005] In order to solve the deficiencies of the prior art, the purpose of the present application is to provide a method for binding parallel circuit simulation threads based on an ARM platform, an electronic device, and a storage medium, so as to improve the efficiency and performance of circuit simulation.

[0006] To achieve the above purpose, the present application provides a method for binding parallel circuit simulation threads based on an ARM platform, including:

[0007] Based on the available memory size of NUMA Nodes, perform a descending order sorting on each NUMA Node to form a NUMA Node binding order;

[0008] Based on the load size of the processor cores corresponding to the NUMA Nodes, perform an ascending order sorting on each processor core corresponding to the NUMA Nodes to form a processor core binding order corresponding to the NUMA Nodes;

[0009] In response to the simulation of a circuit, a circuit simulation thread is generated;

[0010] Based on the specific structure of the circuit, the circuit scale to which the circuit belongs is determined. The circuit scale includes a first scale level and a second scale level, and the circuit scale of the second scale level is larger than that of the first scale level;

[0011] Bind the circuit simulation thread to the NUMA Node using the thread binding method corresponding to the circuit scale; among them, for the circuit of the first scale level, bind its corresponding circuit simulation thread to the same NUMA Node according to the NUMA Node binding order and bind it to the processor core according to the processor core binding order corresponding to the NUMA Node; for the circuit of the second scale level, disperse and bind its corresponding circuit simulation thread to multiple NUMA Nodes according to the NUMA Node binding order and bind it to the processor core according to the processor core binding order corresponding to each NUMA Node.

[0012] Furthermore, the method further includes:

[0013] By reading the system cpuinfo and sysfs files, obtain and establish the correspondence between the processor core and the NUMA Node.

[0014] Furthermore, the method further includes:

[0015] When sorting each NUMA Node in descending order, exclude the NUMA Node with free memory less than 10KB.

[0016] Furthermore, the method further includes:

[0017] When sorting each processor core in ascending order, exclude the processor core with a load greater than 50%.

[0018] Furthermore, the method further includes:

[0019] In response to the number of bound circuit simulation threads being less than the number of generated circuit simulation threads, sort the NUMA Nodes including the excluded NUMA Node in descending order according to the memory size to form the NUMA Node heavy load binding order;

[0020] Sort each processor core corresponding to the NUMA Node including the excluded processor core in ascending order according to the load to form the processor core heavy load binding order corresponding to the NUMA Node;

[0021] Disperse and bind the unbound circuit simulation threads to multiple NUMA Nodes according to the heavy-load binding order of NUMA Nodes, and bind them to the processor cores according to the heavy-load binding order of the processor cores corresponding to the NUMA Nodes.

[0022] Further, the method further includes:

[0023] Divide the circuit into multiple circuit sub-blocks, and allocate the multiple circuit sub-blocks to each bound circuit simulation thread.

[0024] Further, the circuit scale of the first scale level is a circuit scale with the number of circuit devices less than 50,000 and the number of circuit nodes less than 70,000.

[0025] Further, the circuit scale of the second scale level is any circuit scale other than the first scale level.

[0026] To achieve the above object, the electronic device provided by the present application includes:

[0027] A processor;

[0028] A memory, on which one or more computer program instructions running on the processor are stored;

[0029] Wherein, when the processor runs the computer instructions, it executes the binding method of the parallel circuit simulation thread based on the ARM platform as described above.

[0030] To achieve the above object, the computer-readable storage medium provided by the present application stores computer instructions, and when the computer instructions are run by the processor, it executes the steps of the binding method of the parallel circuit simulation thread based on the ARM platform as described above.

[0031] The binding method of the parallel circuit simulation thread based on the ARM platform of the present application can automatically select appropriate NUMA Nodes and processor cores for binding according to the specific structure of the circuit, and realizes high-efficiency multi-thread parallel simulation.

[0032] The binding method of the parallel circuit simulation thread based on the ARM platform of the present application makes full use of the advantages of NUMA, balances the memory access efficiency and CPU computing efficiency of circuit simulation, maximizes the use of memory bandwidth, reduces the latency waiting of memory read and write, and avoids memory occupation and page fault interrupts, thereby improving the simulation performance of large-scale circuits.

[0033] Other features and advantages of the present application will be described in the subsequent specification, and part of them will become obvious from the specification or be understood by implementing the present application. Description of the Drawings

[0034] The accompanying drawings are used to provide a further understanding of the present application, and form a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation to the present application. In the accompanying drawings:

[0035] Figure 1 It is a schematic flowchart of a method for binding parallel circuit simulation threads based on an ARM platform in the present application;

[0036] Figure 2 It is a schematic diagram of a NUMA architecture;

[0037] Figure 3 It is a schematic diagram of binding circuit simulation threads of a circuit at the first scale level;

[0038] Figure 4 It is a schematic diagram of binding circuit simulation threads of a circuit at the second scale level;

[0039] Figure 5 It is a schematic diagram of comparing transient analysis performance of a circuit at the second scale level using different binding methods;

[0040] Figure 6 It is a schematic diagram of partitioning and binding a circuit at the second scale level;

[0041] Figure 7 It is a schematic flowchart of a method for binding circuit simulation threads under heavy load. Detailed implementation manners

[0042] Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the accompanying drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.

[0043] It should be understood that the various steps recited in the method embodiments of the present application can be executed in a different order and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this regard.

[0044] The term "including" and its variations used herein are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0045] It should be noted that the modifications of "one" and "multiple" mentioned in this application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.

[0046] Next, the embodiments of this application will be described in detail with reference to the accompanying drawings.

[0047] Embodiment 1

[0048] An embodiment of this application provides a method for binding parallel circuit simulation threads based on an ARM platform, which improves the efficiency and performance of circuit simulation.

[0049] Figure 1 is a schematic flow chart of the method for binding parallel circuit simulation threads based on an ARM platform of this application. Next, reference will be made to Figure 1 The method for binding parallel circuit simulation threads based on an ARM platform of this application will be described in detail, including:

[0050] Step S101: Based on the available memory size of NUMA Nodes, sort each NUMA Node in descending order to form a NUMA Node binding order.

[0051] It should be noted that in the NUMA (Non-Uniform Memory Access) architecture, each processor socket is connected to local memory through a memory controller and accesses the remote memory of other processor sockets through a high-speed bus. In the same NUMA, the performance of accessing local memory is usually significantly higher than that of accessing across NUMA, and this phenomenon is called the NUMA effect.

[0052] Exemplarily, Figure 2 is a schematic diagram of the NUMA architecture. Refer to Figure 2 , the local memory of NUMA Node0 is mem0, the remote memory across NUMA is mem1, the distance between the 8 CPU processors on Socket0 and mem0 is 10, and the distance between them and mem1 is 20. At this time, the access time of the CPU processors on Socket0 to mem1 will be twice that of accessing mem0.

[0053] In this embodiment, the ARM platform is a multi-core NUMA architecture, there are multiple NUMA Nodes, and each NUMA Node corresponds to multiple processor cores.

[0054] In this embodiment, when sorting each NUMA Node in descending order, NUMA Nodes with less than 10KB of free memory are excluded.

[0055] In some other embodiments, it is also possible not to exclude, or NUMA Nodes with a spatial memory less than a certain value can be adaptively excluded according to actual needs. For example, it may be to exclude NUMA Nodes with an idle memory less than 20KB.

[0056] Step S102: Based on the load size of the processor cores corresponding to the NUMA Node, sort the processor cores corresponding to the NUMA Node in ascending order to form the binding order of the processor cores corresponding to the NUMA Node.

[0057] In this embodiment, when sorting the processor cores in ascending order, the processor cores with a load greater than 50% will be excluded.

[0058] In some other embodiments, it is also possible not to exclude, or NUMA Nodes with a load greater than a certain value can be adaptively excluded according to actual needs. For example, it may be to exclude the processor cores with a load greater than 40%.

[0059] In this embodiment, the corresponding relationship between the processor cores and the NUMA Node is obtained and established by reading system files such as cpuinfo and sysfs.

[0060] Step S103: In response to the simulation of the circuit, generate circuit simulation threads.

[0061] When the circuit emulator simulates the circuit, a certain number of threads will be generated for circuit simulation, that is, multi-threaded circuit simulation threads will be generated.

[0062] Step S104: Based on the specific structure of the circuit, determine the circuit scale to which the circuit belongs. The circuit scale includes a first scale level and a second scale level, and the circuit scale of the second scale level is greater than that of the first scale level.

[0063] Since the memory overhead of circuit simulation is closely related to the specific structure of the circuit, in this embodiment, the circuit scale of the circuit is determined according to the specific structure of the circuit, so as to adopt different thread binding methods according to the level of the circuit scale.

[0064] In this embodiment, the circuit scale of the first scale level is a circuit scale with the number of circuit devices less than 50,000 and the number of circuit nodes less than 70,000. The circuit scale of the second scale level is any circuit scale other than the first scale level.

[0065] It should be noted that a NUMA Node with a single idle memory greater than 10KB should be able to meet the memory consumed by the circuit of the first scale level.

[0066] It should be noted that the free memory exclusion threshold of the NUMA Node is closely related to the specific parameters of the circuit scale level. Any NUMA Node in the NUMA Node binding order should be able to meet the memory consumed by the circuits of the first scale level.

[0067] Therefore, the free memory exclusion threshold and the specific parameters of the circuit scale level can be adaptively set as needed. For example, the larger the free memory exclusion threshold, the more device numbers and node numbers corresponding to the first circuit scale level can be.

[0068] Step S105: Bind the circuit simulation threads using the thread binding method corresponding to the circuit scale to the NUMA Node. Among them, for the circuits of the first scale level, bind the corresponding circuit simulation threads to the same NUMA Node according to the NUMA Node binding order, and bind them to the processor cores according to the processor core binding order corresponding to the NUMA Node; for the circuits of the second scale level, disperse and bind the corresponding circuit simulation threads to multiple NUMA Nodes according to the NUMA Node binding order, and bind them to the processor cores according to the processor core binding order corresponding to each NUMA Node.

[0069] Exemplarily, Figure 3 is a binding schematic diagram of the circuit simulation threads for the circuits of the first scale level. As Figure 3 shown, 2 threads are bound to two processor cores CPU0 and CPU1 of NUMA Node0.

[0070] Exemplarily, Figure 4 is a binding schematic diagram of the circuit simulation threads for the circuits of the second scale level. As Figure 4 shown, 2 threads are respectively bound to NUMA Node0 and NUMA Node1.

[0071] Refer to Figure 5 , Figure 5 is a schematic diagram for comparing the transient analysis performance of a second-scale circuit using different binding methods. As shown in the figure, this circuit is simulated using 32 threads. When using the binding method corresponding to the second scale level of the present application for binding, the transient analysis time is the shortest.

[0072] In this embodiment, when the circuit scale is a circuit of the second scale level, since some NUMA Nodes and processor cores with heavy loads and small free memory are excluded, there are not enough NUMA Nodes and processor cores, and some generated circuit simulation threads are not bound. Therefore, when this situation occurs, it is also necessary to reorder the NUMA Nodes and processor cores to bind the unbound circuit simulation threads.

[0073] Figure 7 Schematic diagram of the process of the binding method for circuit simulation threads under heavy load, refer to Figure 7 The binding method for parallel circuit simulation threads based on the ARM platform further includes:

[0074] Step S201: In response to the number of bound circuit simulation threads being less than the number of generated circuit simulation threads, sort the NUMA Nodes including the excluded NUMA Node in descending order according to memory size to form a NUMA Node heavy-load binding order;

[0075] Step S202: Sort each processor core corresponding to the NUMA Node including the excluded processor core in ascending order according to load to form a processor core heavy-load binding order corresponding to the NUMA Node;

[0076] Step S203: Bind the unbound circuit simulation threads to multiple NUMA Nodes in the NUMA Node heavy-load binding order and bind them to the processor cores in the processor core heavy-load binding order corresponding to the NUMA Node;

[0077] After all threads are bound, the circuit will be divided into multiple circuit sub-blocks, and the multiple circuit sub-blocks will be allocated to each bound circuit simulation thread to start the simulation.

[0078] It should be noted that circuit simulation is based on the connection relationship of each basic component in the circuit (such as resistors, capacitors, power supplies, diodes, MOS transistors), taking the node voltage as an unknown, using the node analysis method to establish a circuit equation, and then selecting the Newton iteration method to solve the unknowns to obtain the voltages of all nodes in the circuit. The Newton iteration method requires all devices in the circuit to construct an N-dimensional sparse matrix A and an N-dimensional residual vector b to form an N-order linear equation system Ax = b, and the node voltages are corrected by solving the linear equation system. Constructing A, b and solving Ax = b are the two most time-consuming modules in circuit simulation. The multi-core architecture of modern servers provides the possibility for parallel acceleration. The circuit simulation software divides the circuit in the BBD mode. The so-called BBD mode is to convert Ax = b into a linear equation system with the following structure

[0079]

[0080] In this way, each computing core is responsible for calculating the matrix A of a circuit sub-block i / B i / C i and the residual vector b i , according to the Schur method for solving matrix partitioning, the linear equation system A of each sub-block i x i =bi It can also be solved separately, so that the calculations and solutions of different sub-blocks can be carried out simultaneously, and thus multi-core parallel simulation can be achieved.

[0081] Exemplarily, refer to Figure 6 , Figure 6 As a schematic diagram of circuit partitioning and binding at the second scale level, as shown in the figure, the circuit is partitioned into 8 middle-level circuit sub-blocks, each middle-level circuit sub-block is divided into 4 bottom-level circuit sub-blocks, and every 4 bottom-level circuit sub-blocks and their corresponding middle-level circuit sub-blocks are divided into a group. A group of threads is allocated to be responsible for the device calculations and equation solutions of them. These threads are bound to the corresponding NUMA Node and processor cores. When the operating system calls this thread to process the same sub-block each time, it will allocate it to the specified processor core to ensure that it accesses the local memory and improve the simulation performance.

[0082] Embodiment 2

[0083] In this embodiment, an electronic device is further provided. The electronic device includes a processor and a memory. The memory is used to store non-temporary computer-readable instructions (such as one or more computer program modules). The processor is used to run the non-temporary computer-readable instructions. When the non-temporary computer-readable instructions are run by the processor, one or more steps of the above-mentioned method for binding parallel circuit simulation threads based on the ARM platform can be executed.

[0084] For example, the processor can be a central processing unit (CPU), a digital signal processor (DSP), or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA), etc.; for example, the central processing unit (CPU) can be of the X86 or ARM architecture, etc.

[0085] For example, the memory can include any combination of one or more computer program products. The computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage media. The processor can run one or more computer program modules to implement various functions of the electronic device. Various application programs and various data, as well as various data used and / or generated by the application programs, can also be stored in the computer-readable storage media.

[0086] It should be noted that in the embodiments of the present application, for the specific functions and technical effects of the electronic device, reference may be made to the description of the method for binding parallel circuit simulation threads based on the ARM platform in the foregoing text, and details are not elaborated herein.

[0087] Embodiment 3

[0088] In this embodiment, a computer-readable storage medium is further provided, and the storage medium is used to store non-transitory computer-readable instructions. For example, when the non-transitory computer-readable instructions are executed by a computer, one or more steps in the method for binding parallel circuit simulation threads based on the ARM platform in the foregoing text can be executed.

[0089] For example, the storage medium can be applied to the above-mentioned electronic device. For example, the storage medium can be the memory in the electronic device in Embodiment 2. For example, for the relevant description of the storage medium, reference can be made to the corresponding description of the memory in the electronic device in Embodiment 2, and details are not elaborated herein.

[0090] It should be noted that the above-mentioned storage medium (computer-readable medium) in the present application can be a computer-readable signal medium or a non-transitory computer-readable storage medium or any combination of the two. A non-transitory computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the non-transitory computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0091] In the present application, a non-transitory computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which computer-readable program code is carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a non-transitory computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0092] The above computer-readable medium may be included in the above electronic device; or may exist separately without being assembled into the electronic device.

[0093] Computer program code for performing the operations of the present application may be written in one or more programming languages or combinations thereof. The above programming languages include, but are not limited to, object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0095] The units described in the embodiments of the present application may be implemented in software or in hardware. Among them, the name of the unit does not constitute a limitation to the unit itself in some cases.

[0096] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: Field Programmable Gate Arrays (FPGA), Application Specific Integrated Circuits (ASIC), Application Specific Standard Products (ASSP), System on Chip (SOC), Complex Programmable Logic Devices (CPLD), etc.

[0097] The above description is only part of the embodiments of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

[0098] In addition, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present application. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0099] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. On the contrary, the specific features and acts described above are merely example forms for implementing the claims.

Claims

1. A binding method for parallel circuit simulation threads based on the ARM platform, characterized in that The method includes: Based on the available memory size of NUMA Nodes, descendingly sort each NUMA Node to form a NUMA Node binding order. Based on the load size of the processor cores corresponding to the NUMA Nodes, ascendingly sort each processor core corresponding to the NUMA Nodes to form a processor core binding order corresponding to the NUMA Nodes. In response to simulating the circuit, generate a circuit simulation thread. Based on the specific structure of the circuit, determine the circuit scale to which the circuit belongs. The circuit scale includes a first scale level and a second scale level, and the circuit scale of the second scale level is larger than that of the first scale level. Bind the circuit simulation thread using the thread binding method corresponding to the circuit scale to the NUMA Nodes. Specifically, for the circuit of the first scale level, bind its corresponding circuit simulation threads to the same NUMA Node according to the NUMA Node binding order, and bind them to the processor cores according to the processor core binding order corresponding to the NUMA Node. For the circuit of the second scale level, disperse and bind its corresponding circuit simulation threads to multiple NUMA Nodes according to the NUMA Node binding order, and bind them to the processor cores according to the processor core binding order corresponding to each NUMA Node.

2. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 1, characterized in that The method further includes: Obtain and establish the correspondence between the processor cores and the NUMA Nodes by reading the system cpuinfo and sysfs files.

3. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 1, characterized in that, The method further includes: When descendingly sorting each NUMA Node, exclude the NUMA Nodes with free memory less than 10KB.

4. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 3, wherein The method further includes: When ascendingly sorting each processor core, exclude the processor cores with a load greater than 50%.

5. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 1, characterized in that The method further includes: In response to the number of bound circuit simulation threads being less than the number of generated circuit simulation threads, descendingly sort the NUMA Nodes including the excluded NUMA Nodes according to the memory size to form a NUMA Node heavy load binding order. Ascendingly sort each processor core corresponding to the NUMA Nodes including the excluded processor cores according to the load to form a processor core heavy load binding order corresponding to the NUMA Nodes. Disperse and bind the unbound circuit simulation threads to multiple NUMA Nodes according to the NUMA Node heavy load binding order, and bind them to the processor cores according to the processor core heavy load binding order corresponding to the NUMA Nodes.

6. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 1, characterized in that The method further includes: Divide the circuit into multiple circuit sub-blocks and allocate the multiple circuit sub-blocks to each bound circuit simulation thread.

7. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 1, characterized in that, The circuit scale of the first scale level is a circuit scale with the number of circuit devices less than 50,000 and the number of circuit nodes less than 70,000.

8. The binding method of the parallel circuit simulation thread based on the ARM platform according to claim 7, characterized in that, The circuit scale of the second scale level is any circuit scale other than the first scale level.

9. An electronic device, characterized in that, Includes: A processor; A memory, on which one or more computer program instructions running on the processor are stored; Wherein, when the processor runs the computer program instructions, it executes the binding method of the parallel circuit simulation thread based on the ARM platform according to any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, Stored thereon are computer instructions, and when the computer instructions run, the steps of the binding method of the parallel circuit simulation thread based on the ARM platform according to any one of claims 1-8 are executed.

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