A memory management method and a memory management unit

Abstract

This specification discloses a memory management method and a memory management unit. In the memory management method provided in this specification, in response to a historical hit result satisfying a pre-reading condition, the memory management unit MMU inputs a virtual address into a pre-trained prediction model to obtain a predicted address output by the prediction model; wherein the historical hit result refers to a hit result of a virtual address in a redirection bypass cache TLB within a specified historical time period, and the virtual address within the specified historical time period refers to a virtual address carried in a historical redirection request received by the MMU within the specified historical time period; corresponding page table data is obtained based on the predicted address, and the page table cache is updated according to the page table data.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory management method and a memory management unit. Background Art

[0002] In order to improve the conversion speed between virtual addresses and physical addresses in the memory management unit (MMU), there is a pre-reading mechanism in the MMU. However, at present, this pre-reading mechanism is not mature.

[0003] The existing pre-reading is implemented by software perception, which requires the software to inform the MMU of the virtual addresses that it may use at some point in the future in advance during the running process. However, most software itself does not understand memory reading, so the accuracy of the existing pre-reading mechanism implemented by software perception is often very low.

[0004] Therefore, how to improve the accuracy of pre-reading page tables in MMU is an urgent problem to be solved. Summary of the invention

[0005] The present specification provides a memory management method and a memory management unit to at least partially solve the above-mentioned problems existing in the prior art.

[0006] This manual adopts the following technical solutions:

[0007] This specification provides a memory management method, which is applied to a memory management unit MMU, and the method includes:

[0008] In response to the historical hit result satisfying the pre-reading condition, the virtual address is input into the pre-trained prediction model to obtain the predicted address output by the prediction model; wherein the historical hit result refers to the hit result of the virtual address in the redirection bypass cache TLB within the specified historical time period, and the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period;

[0009] Corresponding page table data is obtained based on the predicted address, and a page table cache is updated according to the page table data.

[0010] Optionally, the hit result includes success and failure;

[0011] The pre-reading condition includes at least one of: after a specified period, the number of historical redirection requests with failed hit results is not less than a specified threshold, and the proportion of historical redirection requests with failed hit results in all historical redirection requests is not less than a specified proportion.

[0012] Optionally, inputting the virtual address into a pre-trained prediction model specifically includes:

[0013] Based on the order from the beginning to the end of the time when the MMU receives each historical redirection request within the specified historical time period, using the virtual address carried in each historical redirection request to obtain an address sequence;

[0014] The address sequence is input into a pre-trained prediction model.

[0015] Optionally, pre-train the prediction model, specifically including:

[0016] Obtaining a target redirection request received by the MMU at a specified time in the historical data, and determining a target virtual address included in the target redirection request;

[0017] Obtaining a sample redirection request received by the MMU within a specified sample time period, and determining a sample virtual address carried in the sample redirection request;

[0018] Inputting the sample virtual address into the prediction model to be trained to obtain the prediction address to be optimized output by the prediction model;

[0019] The prediction model is trained with the optimization goal of minimizing the difference between the predicted address to be optimized and the target virtual address.

[0020] Optionally, the specified sample time period is before the specified time moment and differs from the specified time moment by a specified interval.

[0021] Optionally, the historical data is data collected in a scenario where the probability that the hit result of the sample virtual address carried in the sample redirection request received by the MMU in the TLB is a failure is not less than a preset probability.

[0022] Optionally, the method further comprises:

[0023] Receive the current redirection request;

[0024] Determine and record the current virtual address carried in the current redirection request;

[0025] In response to a hit result of the current virtual address in the TLB being successful, outputting a physical address corresponding to the current virtual address;

[0026] In response to a hit result of the current virtual address in the TLB being a failure, a physical address corresponding to the current virtual address is determined according to the current virtual address and the page table cache, and the physical address corresponding to the current virtual address is output.

[0027] This specification provides a memory management unit MMU, the MMU comprising: a prediction module, a page table query module;

[0028] The prediction module is used to input the received virtual address into a pre-trained prediction model when the historical hit result meets the pre-reading condition, obtain the predicted address output by the prediction model, and send the predicted address to the page table query module; wherein the historical hit result refers to the hit result of the virtual address in the redirection bypass cache TLB module within a specified historical time period, and the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period;

[0029] The page table query module is used to determine the page table data corresponding to the predicted address when receiving the predicted address sent by the prediction module.

[0030] Optionally, the MMU further includes: a TLB module and a response module;

[0031] The TLB module is used to receive a redirection request, determine the virtual address carried in the redirection request; in response to the existence of a physical address corresponding to the virtual address carried in the redirection request, determine that the hit result of the virtual address carried in the redirection request is successful, and send the physical address to the response module; in response to the absence of a physical address corresponding to the virtual address carried in the redirection request, determine that the hit result of the virtual address carried in the redirection request is a failure, receive the physical address corresponding to the virtual address sent by the page table query module, and send the physical address to the response module;

[0032] The response module is used to output the physical address.

[0033] Optionally, the MMU further includes: a recording module;

[0034] The recording module is used to record the time when the TLB module receives each redirection request, the virtual address carried in each redirection request, and the hit result of each redirection request in the TLB module.

[0035] Optionally, the MMU further includes: a page table cache module;

[0036] The page table query module is also used to determine the physical address corresponding to the virtual address according to the virtual address and the page table stored in the page table cache module when the TLB module fails to query the physical address corresponding to the virtual address, and send the physical address to the TLB module and send the page table data to the page table cache module;

[0037] The page table cache module is used to store a preset number of page tables with the highest popularity.

[0038] This specification provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned memory management method is implemented.

[0039] This specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned memory management method when executing the program.

[0040] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0041] In the memory management method provided in the present specification, the memory management unit MMU responds to the historical hit result satisfying the pre-reading condition, inputs the virtual address into a pre-trained prediction model, and obtains the predicted address output by the prediction model; wherein the historical hit result refers to the hit result of the virtual address in the redirection bypass cache TLB within a specified historical time period, and the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period; the corresponding page table data is obtained based on the predicted address, and the page table cache is updated according to the page table data.

[0042] When the memory management method provided in this specification is used to implement the pre-reading mechanism in the MMU, the prediction model can be used to predict the predicted address that may be used in the future based on the virtual address and the hit result of the virtual address carried in the historical redirection request received by the MMU in the specified historical time period before the current moment, and the page table data corresponding to the predicted address is read and updated to the page table cache. Compared with the pre-reading method that relies on software perception in the traditional method, this method can predict the virtual address that may be used in the future based on the virtual address and hit result used recently, which greatly improves the accuracy of the prediction and speeds up the efficiency of the MMU in processing redirection requests. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0044] Figure 1 A schematic diagram of a process of converting a virtual address into a physical address in this specification;

[0045] Figure 2 A flowchart of a memory management method in this specification;

[0046] Figure 3 A schematic diagram of a memory management unit provided in this specification;

[0047] Figure 4 The corresponding Figure 2 Schematic diagram of electronic equipment. DETAILED DESCRIPTION

[0048] In the system, MMU is responsible for virtual memory management, that is, the conversion of virtual addresses to physical addresses. In MMU, there is a Translation Lookaside Buffer (TLB), which stores the correspondence between some virtual addresses and physical addresses. When a virtual address stored in TLB is given, TLB can quickly give the corresponding physical address. Similar to cache memory, TLB also only saves the correspondence between some commonly used or most recently used virtual addresses and physical addresses. When MMU receives a redirection request, if the virtual address carried in the redirection request can be found directly in TLB, then it can be considered that the redirection request hits in TLB, that is, the hit result is successful, otherwise the hit result is failed. When the hit result is successful, MMU can respond very quickly and output the corresponding physical address.

[0049] If the hit result is a failure, the MMU needs to perform a more complex translation process to determine the corresponding physical address based on the virtual address. Figure 1 A process of translating virtual addresses into physical addresses in MMU is given. Figure 1 Take the following example to illustrate the translation process. Figure 1 As shown in the figure, the virtual address is divided into multiple segments during the translation process. In this example, it is divided into five segments. The number of segments may be different in actual applications. Each segment of the address corresponds to a query of the first-level page table. The number of segments of the virtual address is the same as that of the Figure 1 In the process shown, there are five levels of page tables in the MMU, wherein the last level of the page table stores the physical address, and the other levels of the page table store the index of the next level of the page table.

[0050] like Figure 1As shown in the figure, it is assumed that the virtual address is 48 bits, which is divided into five segments, namely address segments A to E. The translation starts from the first segment address, that is, address segment A. In the first-level page table, the corresponding page table a is determined according to address segment A. Subsequently, the page table a corresponding to address segment A is used as the index of the next-level page table, that is, the page table b corresponding to address segment B is queried in the page table a corresponding to address segment A. Similarly, the page table c corresponding to address segment C is queried in the page table b corresponding to address segment B... until the final physical address corresponding to address segment E is queried in the page table d corresponding to address segment D. This method of hierarchical storage of page tables can greatly increase the number of physical addresses that can be queried when the available space is limited.

[0051] Limited by the size of the storage space, similar to TLB, the page tables at all levels are stored in a cache during the translation process, and the cache of the page tables at all levels is called the page table cache. Each level of the page table cache also only stores the more commonly used page tables at this level. Therefore, not all required page tables can be found in the page table cache. When the required page table does not exist in the page table cache, it is necessary to search for the required page table in the external memory. This process will definitely find the required page table, but the processing speed is relatively slow. Generally speaking, compared to directly obtaining the corresponding page table from the page table cache, it often takes more than 100 times longer to obtain the page table from the external memory, which is extremely inefficient.

[0052] It is not difficult to imagine that in the MMU, it is inevitable to search for physical addresses that do not exist in the TLB and cannot be matched in the page table cache. Therefore, in order to improve the overall operating efficiency of the MMU, there is a pre-reading mechanism in the MMU. That is, during the running process, the software sends the virtual address that may be used at some point in the future to the MMU in advance, and the MMU pre-acquires the page tables corresponding to the virtual address and stores them in the page table cache. Therefore, when the virtual address is actually used at some point in the future, the MMU can quickly give the physical address corresponding to the virtual address. Since the pre-reading process is parallel to the normal operation of the MMU when there are sufficient computing resources, the two do not affect each other. Therefore, when the pre-reading hits, the working efficiency of the MMU can be effectively improved.

[0053] It can be seen that the accuracy of the page table pre-read according to the pre-given virtual address is crucial. However, in the traditional pre-reading method, the selection of the virtual address is determined by software perception, that is, the software itself sends the virtual address to be pre-read to the MMU. However, most software does not understand memory, and the virtual address that needs to be pre-read is likely not to be used later, or will be used after a long time, which has poor timeliness and low accuracy.

[0054] In order to solve the above technical problems, this specification provides a method that can achieve pre-reading more accurately and effectively.

[0055] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0057] Figure 2 The following is a flow chart of a memory management method applied to an MMU in this specification, which specifically includes the following steps:

[0058] S100: In response to a historical hit result satisfying a pre-read condition, the virtual address is input into a pre-trained prediction model to obtain a predicted address output by the prediction model; wherein the historical hit result refers to a hit result of the virtual address in the redirection bypass cache TLB within a specified historical time period, and the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period.

[0059] All steps in the memory management method provided in this specification can be implemented by any electronic device having computing functions and including a memory management unit, such as a terminal, a server, and other devices.

[0060] The memory management method provided in this specification is mainly applied to the pre-reading stage in the MMU. In the MMU, pre-reading can occur in parallel with the normal conversion of virtual addresses to physical addresses. When computing resources are sufficient, pre-reading will not affect the normal address conversion process.

[0061] In the memory management method provided in this specification, it is hoped that the virtual address contained in the redirection request of the MMU that may be accessed at a future target moment is predicted by using the virtual address contained in the redirection request of the MMU that has been recently accessed. The target moment may be a moment after the current moment of executing this method. At the same time, in order to ensure the timeliness of the prediction, the time interval between the target moment and the current moment is usually short, such as 500ms, 1s, etc. If the time interval between the target moment and the current moment is too long, the pre-read page table may be pushed out of the page table cache by other page tables read in the subsequent address conversion process.

[0062] Based on the above ideas, before executing this method, the MMU can first receive and record the historical redirection requests received by itself within the specified historical time period. Among them, the specified historical time period can be the time period before the current moment of executing this method. Generally, the closer the specified historical time period where the historical redirection requests used for prediction are located is to the predicted target moment, the higher the accuracy of the predicted virtual address. Therefore, in order to ensure the accuracy of the prediction, the end time of the specified historical time period can be the current moment of executing this method, and the start time of the specified historical time period can be set according to specific needs. In other words, the length of the specified historical time period can be set according to specific needs. The longer the length of the specified historical time period, the more historical redirection requests the MMU receives during the period, and the higher the accuracy of the virtual address predicted subsequently, but relatively speaking, the amount of calculation will also increase, and the prediction speed will slow down. Therefore, the length of the specified historical time period can be set according to the specific needs of actual application.

[0063] Each redirection request received by the MMU carries a virtual address, and the MMU's job is to convert the virtual address carried in the redirection request into a physical address and return it. Based on the idea of ​​using the converted virtual address to predict the virtual address that may be used at the target time, the MMU can determine and record the virtual address carried in each historical redirection request while obtaining the historical redirection request.

[0064] At the same time, at the current moment of executing this method, each historical redirection request received by the MMU has been processed, so the MMU can record the hit result of the virtual address carried in each historical redirection request in the TLB when processing each historical redirection request. When predicting the virtual address that may be used at the target moment, in addition to the virtual address itself carried in the historical redirection request, the hit result of each virtual address in the TLB of the MMU is also very critical, which can further improve the accuracy of the predicted virtual address.

[0065] After sufficient data is collected through the above steps, the memory management method provided in this specification can be executed to predict the virtual addresses that may be used at the target time. In this method, when the historical hit results of the historical redirection requests processed by the MMU meet the pre-reading conditions, the MMU can automatically respond and start executing this method. Among them, the pre-reading conditions can be understood as the conditions that enable the MMU to start predicting the virtual addresses that may be used at the future target time.

[0066] In this method, a pre-trained prediction model is used to complete the prediction of the virtual address that may be used at the future target moment. The prediction model is used to determine the predicted address based on the input virtual address. The virtual address carried in each historical redirection request processed by the MMU in a specified historical time period is input into the prediction model to obtain the predicted address output by the prediction model. Among them, the predicted address is the virtual address that may be used at the future target moment.

[0067] It is conceivable that in the process of MMU processing redirection requests, it is not always necessary to execute the pre-reading mechanism. Therefore, in this method, the timing of MMU executing this method is controlled by pre-setting the pre-reading conditions. If the virtual address in the redirection request can hit in the TLB, then there is no need to pre-read to obtain the page table data in advance. Therefore, the pre-reading conditions can be set around the hit results of the virtual address in the TLB in the historical redirection requests within a specified historical time period, that is, the historical hit results.

[0068] The hit results of the virtual address carried by a historical redirection request in the TLB are only success and failure. When there is a physical address corresponding to the virtual address in the TLB, the hit result can be considered to be successful; conversely, when there is no physical address corresponding to the virtual address in the TLB, the hit result can be considered to be a failure. Based on this, the pre-set pre-reading conditions may include the following: after a specified period, the number of historical redirection requests with a hit result of failure is not less than a specified threshold, the proportion of historical redirection requests with a hit result of failure in all historical redirection requests is not less than a specified proportion, etc. Among them, after a specified period can be understood as the MMU automatically executing this method once every fixed period of time; the number of historical redirection requests with a hit result of failure is not less than a specified threshold and the proportion is not less than a specified proportion, which can be understood as when there are too many historical redirection requests with a hit result of failure in the TLB among the historical redirection requests within a specified historical time period, the MMU automatically executes this method. Among them, the specified threshold and the specified proportion can be set according to specific needs. In a specified historical time period, the more virtual addresses with hit results in the TLB, the more likely it is that the hit result of the virtual address in the TLB in the recently received historical redirection request is successful, and the less likely it is that pre-reading is needed. Therefore, when the number of virtual addresses with failed hit results in the TLB in a specified historical time period is large, the possibility that pre-reading will be needed next is greater.

[0069] Of course, in addition to the specific embodiments given in this specification, there may be other forms of pre-reading conditions, and this specification does not impose any specific restrictions on this.

[0070] When the historical hit result meets the pre-reading condition, the virtual address can be input into the pre-trained prediction model. The historical hit result is the hit result of the virtual address carried in the historical redirection request processed by the MMU in the specified historical time period in the TLB; the virtual address input into the prediction model is each virtual address carried in each historical redirection request processed by the MMU in the specified historical time period.

[0071] Preferably, when inputting the virtual address into the prediction model, the order in which the MMU receives each historical redirection request in the specified historical time period can be further taken into account, so that the prediction model can give a more accurate result. Specifically, based on the order from front to back of the time when the MMU receives each historical redirection request in the specified historical time period, the address sequence can be obtained using the virtual address carried in each historical redirection request; and the address sequence can be input into the pre-trained prediction model.

[0072] The address sequence includes the virtual addresses of all historical redirection requests in the order from front to back when the MMU receives the historical redirection requests. When the virtual addresses carried by each historical redirection request are input according to the order in which the historical redirection requests are received, the prediction model can clearly perceive the change trend of the virtual addresses used in the specified historical time period, so as to more accurately predict the virtual addresses that may be used at the target time. Among them, the virtual addresses in the address sequence can be input into the prediction model one by one in the order of the sequence, or the entire address sequence can be input into the prediction model together, and this specification does not make specific restrictions on this.

[0073] S102: Obtain corresponding page table data based on the predicted address, and update the page table cache according to the page table data.

[0074] After the predicted address is determined by the prediction model in step S100, the page table data corresponding to the predicted address can be obtained through the process of translating the virtual address to the physical address in the MMU in this step, and the page table cache is updated according to the page table data. In other words, the page table data corresponding to the predicted address is stored in the page table cache.

[0075] Among them, the process of obtaining page table data can be a process of translating the predicted address into the corresponding physical address through page table query. In this process, the page table corresponding to the predicted address in each level can be obtained. In the process of obtaining page table data, for the page table corresponding to the predicted address in any level of page table, if the page table originally exists in the page table cache of that level, then the page table is updated to the latest position in the page table cache of that level; and if the page table does not exist in the page table cache of that level, then the page table is obtained in the external memory and the page table is updated to the latest position in the page table cache of that level. In the above manner, the pre-reading work can be completed. When the predicted address is used as the virtual address in the redirection request received by the MMU at the target moment in the future, the physical address corresponding to the predicted address can be directly translated through the page table caches of each level without having to obtain the page table data from the external memory.

[0076] When the memory management method provided in this specification is used to implement the pre-reading mechanism in the MMU, the prediction model can be used to predict the predicted address that may be used in the future based on the virtual address carried in the historical redirection request received by the MMU in the specified historical time period before the current moment, and the page table data corresponding to the predicted address is read and updated to the page table cache. Compared with the pre-reading method that relies on software perception in the traditional method, this method can predict the virtual address that may be used in the future based on the virtual address used recently and the hit result, which greatly improves the accuracy of the prediction and speeds up the efficiency of the MMU in processing redirection requests.

[0077] In addition, the prediction model used in this specification can be pre-trained. Specifically, the target redirection request received by the MMU at a specified time can be obtained from the historical data, and the target virtual address contained in the target redirection request can be determined; the sample redirection request received by the MMU in a specified sample time period before the specified time can be obtained, and the sample virtual address carried in the sample redirection request can be determined; the sample virtual address is input into the prediction model to be trained to obtain the prediction address to be optimized output by the prediction model; the prediction model is trained with the optimization goal of minimizing the difference between the prediction address to be optimized and the target virtual address.

[0078] During the training process, the specified time is equivalent to the target time in the actual application process. The target virtual address carried in the target redirection request received at the specified time is the real virtual address corresponding to the predicted address to be optimized that the prediction model predicts during the training process; during the training process, the specified sample time period is equivalent to the specified historical time period in the actual application, and the redirection requests received by the MMU within the specified sample time period are used as sample redirection requests, and the virtual address carried in the sample redirection request is used as the sample virtual address to train the prediction model. Similar to the actual application, the target time and the specified historical time period will differ by a certain interval. In the process of training the prediction model, the specified sample time period should also be before the specified time and differ from the specified time by a specified interval.

[0079] Furthermore, in the process of training the prediction model, the training environment should be ensured to be the same as the working environment of the actual application of the prediction model after the training is completed. Because in this method, the MMU will respond and start to execute this method only when the historical hit result meets the pre-reading condition. Therefore, the method of controlling the collected historical data can be used in the training process to simulate the working environment in actual application to the greatest extent. Specifically, in the process of training the prediction model, the historical data is the data collected in the scenario where the probability that the hit result of the sample virtual address carried in the sample redirection request received by the MMU in the TLB is a failure is not less than the preset probability. In other words, only when the probability that the virtual address carried in the sample redirection request processed by the MMU has a high hit result in the TLB is a failure, the sample redirection request is used as a sample for training the prediction model, so as to simulate the situation where the historical hit result meets the pre-reading condition in actual application.

[0080] In addition, in the memory management method provided in this specification, the pre-reading process can also be used to implement the conversion of virtual addresses to physical addresses in the MMU. Specifically, the memory management method may also include: receiving a current redirection request; determining and recording the current virtual address carried in the current redirection request; in response to the current virtual address hitting the TLB successfully, outputting the physical address corresponding to the current virtual address; in response to the current virtual address hitting the TLB failed, determining the physical address corresponding to the current virtual address based on the current virtual address and the page table cache, and outputting the physical address corresponding to the current virtual address.

[0081] As introduced in this specification, the two processes of processing redirection requests and pre-reading in the MMU can be performed simultaneously. While the MMU is performing the pre-reading process, it is still receiving and processing redirection requests. At this time, the redirection request received by the MMU is the current redirection request, and the current virtual address carried in the current redirection request is determined, and the hit result of the current virtual address in the TLB is judged. At the same time, the current virtual address and its hit result in the TLB are recorded. It can be imagined that the current redirection request at this time will become a historical redirection request in the future and will be used in a future pre-reading. Therefore, each time the MMU processes a redirection request, the virtual address of the redirection request and the hit result in the TLB should be recorded for backup.

[0082] If the hit result of the current virtual address in the TLB is successful, then the physical address corresponding to the current virtual address can be directly output; if the hit result of the current virtual address in the TLB is a failure, then it is necessary to translate the corresponding physical address and output it based on the current virtual address and the page table cache. The hit result of the TLB can be understood as whether the current virtual address can directly find the corresponding physical address in the TLB. Specifically, it can be determined whether the current virtual address has a corresponding physical address in the TLB; when the current virtual address has a corresponding physical address in the TLB, it is determined that the hit result of the current virtual address in the TLB is successful; when the current virtual address does not have a corresponding physical address in the TLB, it is determined that the hit result of the current virtual address in the TLB is a failure.

[0083] The above is the memory management method provided in this specification. Based on the same idea, this specification also provides a corresponding memory management unit, such as Figure 3 shown.

[0084] Figure 3 A schematic diagram of a memory management unit provided for this specification includes:

[0085] Prediction module, page table query module;

[0086] The prediction module is used to input the received virtual address into a pre-trained prediction model when the historical hit result meets the pre-reading condition, obtain the predicted address output by the prediction model, and send the predicted address to the page table query module; wherein the historical hit result refers to the hit result of the virtual address in the redirection bypass cache TLB module within a specified historical time period, and the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period;

[0087] The page table query module is used to determine the page table data corresponding to the predicted address when receiving the predicted address sent by the prediction module.

[0088] Optionally, the MMU further includes: a TLB module and a response module;

[0089] The TLB module is used to receive a redirection request, determine the virtual address carried in the redirection request; in response to the existence of a physical address corresponding to the virtual address carried in the redirection request, determine that the hit result of the virtual address carried in the redirection request is successful, and send the physical address to the response module; in response to the absence of a physical address corresponding to the virtual address carried in the redirection request, determine that the hit result of the virtual address carried in the redirection request is a failure, receive the physical address corresponding to the virtual address sent by the page table query module, and send the physical address to the response module;

[0090] The response module is used to output the physical address.

[0091] Optionally, the MMU further includes: a recording module;

[0092] The recording module is used to record the time when the TLB module receives each redirection request, the virtual address carried in each redirection request, and the hit result of each redirection request in the TLB module.

[0093] Optionally, the MMU further includes: a page table cache module;

[0094] The page table query module is also used to determine the physical address corresponding to the virtual address according to the virtual address and the page table stored in the page table cache module when the TLB module fails to query the physical address corresponding to the virtual address, and send the physical address to the TLB module and send the page table data to the page table cache module;

[0095] The page table cache module is used to store a preset number of page tables with the highest popularity.

[0096] Among them, there may be two different submodules in the recording module, which are respectively used to record the virtual address carried in each redirection request and the hit result of the virtual address in the TLB; the prediction module may include the prediction model used in the memory management method provided in this specification, and the predicted address is determined by the prediction model. Similar to the memory management method provided in this specification, the memory management unit needs to start predicting the virtual address that may be used in the future only when the historical hit result meets the pre-reading condition. In the memory management unit provided in this specification, the work of judging whether the historical hit result meets the pre-reading condition can be completed by the recording module that records the hit result of the virtual address carried in each redirection request, or it can be completed by the prediction module after obtaining the hit result of the virtual address carried in each redirection request. This specification does not impose specific restrictions on this. When the required page table does not exist in the page table cache, the page table query module can interact with the external memory to obtain the required page table.

[0097] This specification also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 2 Provides memory management methods.

[0098] This manual also provides Figure 4 The schematic structure diagram of the electronic device shown in FIG. Figure 4 As mentioned above, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and may also include other hardware required for the business. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to achieve the above Figure 2 Of course, in addition to the software implementation, this specification does not exclude other implementations, such as logic devices or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0099] In the 1990s, it was very clear whether the improvement of a technology was hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with hardware entity modules. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0100] The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (e.g., software or firmware) executable by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, and the memory controller may also be implemented as part of the control logic of the memory. It is also known to those skilled in the art that, in addition to implementing the controller in a purely computer-readable program code manner, the controller may be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, such a controller may be considered as a hardware component, and the devices for implementing various functions included therein may also be considered as structures within the hardware component. Or even, the devices for implementing various functions may be considered as both software modules for implementing the method and structures within the hardware component.

[0101] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0102] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0103] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0104] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0105] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0107] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0108] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0109] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0110] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0111] It should be understood by those skilled in the art that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0112] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0113] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0114] The above description is only an embodiment of this specification and is not intended to limit this specification. For those skilled in the art, this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification should be included in the scope of the claims of this application.

Claims

1. A memory management method, characterized in that: Applied to a memory management unit MMU, the method comprises: In response to the historical hit result satisfying the pre-reading condition, the virtual address is input into the pre-trained prediction model to obtain the predicted address output by the prediction model; wherein the historical hit result refers to the hit result of the virtual address in the redirection bypass cache TLB within the specified historical time period, the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period, the prediction model is trained with the sample virtual address carried in the sample redirection request received by the MMU as the training sample, and with the target virtual address carried in the target redirection request received by the MMU at a specified time as the training label, and the specified time is the time after the MMU receives the sample redirection request; Corresponding page table data is obtained based on the predicted address, and a page table cache is updated according to the page table data.

2. The method according to claim 1, characterized in that The hit results include success and failure; The pre-reading condition includes at least one of: after a specified period, the number of historical redirection requests with failed hit results is not less than a specified threshold, and the proportion of historical redirection requests with failed hit results in all historical redirection requests is not less than a specified proportion.

3. The method according to claim 1, characterized in that Inputting the virtual address into a pre-trained prediction model specifically includes: Based on the order from the beginning to the end of the time when the MMU receives each historical redirection request within the specified historical time period, using the virtual address carried in each historical redirection request to obtain an address sequence; The address sequence is input into a pre-trained prediction model.

4. The method according to claim 1, characterized in that Pre-training prediction models, including: Obtaining a target redirection request received by the MMU at a specified time in the historical data, and determining a target virtual address included in the target redirection request; Obtaining a sample redirection request received by the MMU within a specified sample time period, and determining a sample virtual address carried in the sample redirection request; Inputting the sample virtual address into the prediction model to be trained to obtain the prediction address to be optimized output by the prediction model; The prediction model is trained with the optimization goal of minimizing the difference between the predicted address to be optimized and the target virtual address.

5. The method according to claim 4, characterized in that The specified sample time period is before the specified time and is different from the specified time by a specified interval.

6. The method according to claim 4, characterized in that The historical data is data collected in a scenario where the probability that the hit result of the sample virtual address carried in the sample redirection request received by the MMU in the TLB is a failure is not less than a preset probability.

7. The method according to claim 1, characterized in that The method further comprises: Receive the current redirection request; Determine and record the current virtual address carried in the current redirection request; In response to a hit result of the current virtual address in the TLB being successful, outputting a physical address corresponding to the current virtual address; In response to a hit result of the current virtual address in the TLB being a failure, a physical address corresponding to the current virtual address is determined according to the current virtual address and the page table cache, and the physical address corresponding to the current virtual address is output.

8. A memory management unit MMU, characterized in that: The MMU includes: a prediction module and a page table query module; The prediction module is used to input the received virtual address into a pre-trained prediction model when the historical hit result meets the pre-reading condition, obtain the predicted address output by the prediction model, and send the predicted address to the page table query module; wherein the historical hit result refers to the hit result of the virtual address in the redirection bypass cache TLB module within a specified historical time period, the virtual address within the specified historical time period refers to the virtual address carried in the historical redirection request received by the MMU within the specified historical time period, the prediction model is trained with the sample virtual address carried in the sample redirection request received by the MMU as the training sample, and with the target virtual address carried in the target redirection request received by the MMU at a specified time as the training label, and the specified time is the time after the MMU receives the sample redirection request; The page table query module is used to determine the page table data corresponding to the predicted address when receiving the predicted address sent by the prediction module.

9. The MMU according to claim 8, wherein: The MMU also includes: a TLB module and a response module; The TLB module is used to receive a redirection request, determine the virtual address carried in the redirection request; in response to the existence of a physical address corresponding to the virtual address carried in the redirection request, determine that the hit result of the virtual address carried in the redirection request is successful, and send the physical address to the response module; in response to the absence of a physical address corresponding to the virtual address carried in the redirection request, determine that the hit result of the virtual address carried in the redirection request is a failure, receive the physical address corresponding to the virtual address sent by the page table query module, and send the physical address to the response module; The response module is used to output the physical address.

10. The MMU according to claim 9, wherein: The MMU also includes: a recording module; The recording module is used to record the time when the TLB module receives each redirection request, the virtual address carried in each redirection request, and the hit result of each redirection request in the TLB module.

11. The MMU of claim 9, wherein: The MMU also includes: a page table cache module; The page table query module is also used to determine the physical address corresponding to the virtual address according to the virtual address and the page table stored in the page table cache module when the TLB module fails to query the physical address corresponding to the virtual address, and send the physical address to the TLB module and send the page table data to the page table cache module; The page table cache module is used to store a preset number of page tables with the highest popularity.

12. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any one of claims 1 to 7 is implemented.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method described in any one of claims 1 to 7 is implemented.

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