Data processing method and device, electronic device and storage medium

Abstract

The present disclosure relates to a data processing method and device, an electronic device and a storage medium, the method being applied to a bus interface, comprising: receiving request information carrying a first burst length, and determining to accept the request information, or to block the request information, according to a first vector corresponding to each second burst length supported by the storage space, and the first burst length carried by the received request information, wherein the first vector is used to indicate a starting storage position with a continuous space to be allocated corresponding to the second burst length in the annular storage space of the bus interface. The embodiment of the present disclosure can combine the space at the head and tail of the memory that is prone to fragmentation, logically forming an annular storage space connected to the head and tail, thereby reducing the situation where the acceptance of request information is blocked due to excessive fragmentation of the storage space in the bus interface, and improving the space utilization of the storage space, as well as the working efficiency of the bus interface.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method and device, an electronic device, and a storage medium. Background Art

[0002] With the rapid development of artificial intelligence and big data technologies, the amount of data that processor chips need to process is increasing, and data write and delete operations will be frequently performed on the memory in the processor chip. For example, when writing data, the data will be stored in the specified location in the memory according to the write address; when reading data, the corresponding data can be retrieved from the memory through the read address. Due to the capacity limitations of storage devices, frequent data write and delete operations are performed on the memory, and the storage space of the memory will be divided into many small, discontinuous areas, resulting in the inefficient use of the storage space of the memory. Summary of the invention

[0003] The present disclosure proposes a data processing technology solution.

[0004] According to one aspect of the present disclosure, a data processing method is provided, including: the method is applied to a bus interface, the bus interface is used to receive request information sent by a request end, and read request data from a server end to the request end according to the received request information, including: receiving request information carrying a first burst length, the request information is used to allocate a data space with the first burst length for the request information in a storage space of the bus interface, and the data space is used to cache the request data read from the server end; according to a first vector corresponding to each second burst length supported by the storage space, and the first burst length, determining a processing result of the request information, the processing result including that the bus interface accepts the request information, or that the bus interface blocks the request information, wherein the first vector is used to indicate the starting storage position of the continuous space to be allocated corresponding to the second burst length in the storage space, and the storage space is logically a ring storage space with a head and a tail connected.

[0005] In one possible implementation, the method further includes: obtaining a second vector for indicating free space in the storage space of the bus interface, the bits of the second vector corresponding to storage units of the storage space; determining a third vector based on a maximum second burst length supported by the storage space and the second vector, the third vector being used to indicate a to-be-allocated space of a ring-shaped storage space that logically connects a head and a tail; and determining the first vector corresponding to each second burst length supported by the storage space based on the second vector and the third vector.

[0006] In one possible implementation, obtaining a second vector for indicating free space in the storage space of the bus interface includes: in response to receiving the request information, obtaining a second vector for indicating free space in the storage space of the bus interface; or, periodically obtaining a second vector for indicating free space in the storage space of the bus interface according to a predetermined period.

[0007] In a possible implementation, a third vector is determined based on the maximum second burst length supported by the storage space and the second vector, including: intercepting a sub-vector of the maximum second burst length from the second vector in a direction from low to high; and splicing the second vector and the sub-vector to obtain a spliced ​​third vector.

[0008] In one possible implementation, determining the first vector corresponding to each second burst length supported by the storage space based on the second vector and the third vector includes: taking the logical AND result of the element at the i-th position in the first vector corresponding to the second burst length equal to n and the element at the j-th position in the third vector as the element at the i-th position in the first vector corresponding to the second burst length equal to n+1, wherein j is the sum of i and the second burst length n+1, i is an integer greater than or equal to 0, n is an integer greater than or equal to 0 and less than the maximum second burst length, and the first vector corresponding to the second burst length equal to 0 is determined by the second vector.

[0009] In one possible implementation, the processing result of the request information is determined based on the first vector corresponding to each second burst length supported by the storage space and the first burst length, including: performing a logical OR operation on the first vector corresponding to each second burst length to obtain a logical OR result corresponding to each second burst length; determining the current maximum continuous space to be allocated in the storage space based on the logical OR result corresponding to each second burst length; determining the processing result of the request information based on the current maximum continuous space to be allocated in the storage space and the first burst length.

[0010] In one possible implementation, the processing result of the request information is determined based on the current maximum continuous space to be allocated of the storage space and the first burst length, including: when the first burst length is less than or equal to the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface accepting the request information; or, when the first burst length is greater than the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface blocking the request information.

[0011] In a possible implementation, the method further includes: when the processing result indicates that the bus interface accepts the request information, polling arbitration is performed on each continuous space to be allocated in a preset order to obtain an arbitration result; and according to the arbitration result, allocating the target continuous space to be allocated for the request information.

[0012] In one possible implementation, obtaining a second vector for indicating free space in the storage space of the bus interface includes: determining a state vector based on the space capacity of the storage space, each element in the state vector being used to indicate that a storage unit at the same position in the storage space is in an allocated state or a released state; and performing a negation operation on the state vector to obtain a second vector for indicating free space in the storage space.

[0013] According to one aspect of the present disclosure, a data processing device is provided, the device is applied to a bus interface, the bus interface is used to receive request information sent by a request end, and read request data from a server end to the request end according to the received request information, the device comprising: a receiving module, used to receive request information carrying a first burst length, the request information is used to allocate a data space with the first burst length for the request information in a storage space of the bus interface, the data space is used to cache the request data read from the server end; a determining module, used to determine a processing result of the request information according to a first vector corresponding to each second burst length supported by the storage space, and the first burst length, the processing result comprising that the bus interface accepts the request information, or that the bus interface blocks the request information, wherein the first vector is used to indicate a starting storage position of a continuous space to be allocated corresponding to the second burst length in the storage space, and the storage space is logically a ring storage space with a head and a tail connected.

[0014] In a possible implementation, the device also includes an acquisition module, which is used to: acquire a second vector indicating free space in the storage space of the bus interface, the bits of the second vector corresponding to storage units of the storage space; determine a third vector based on a maximum second burst length supported by the storage space and the second vector, the third vector being used to indicate a to-be-allocated space of a ring-shaped storage space that logically connects a head and a tail; and determine the first vector corresponding to each second burst length supported by the storage space based on the second vector and the third vector.

[0015] In one possible implementation, obtaining a second vector for indicating free space in the storage space of the bus interface includes: in response to receiving the request information, obtaining a second vector for indicating free space in the storage space of the bus interface; or, periodically obtaining a second vector for indicating free space in the storage space of the bus interface according to a predetermined period.

[0016] In a possible implementation, a third vector is determined based on the maximum second burst length supported by the storage space and the second vector, including: intercepting a sub-vector of the maximum second burst length from the second vector in a direction from low to high; and splicing the second vector and the sub-vector to obtain a spliced ​​third vector.

[0017] In one possible implementation, determining the first vector corresponding to each second burst length supported by the storage space based on the second vector and the third vector includes: taking the logical AND result of the element at the i-th position in the first vector corresponding to the second burst length equal to n and the element at the j-th position in the third vector as the element at the i-th position in the first vector corresponding to the second burst length equal to n+1, wherein j is the sum of i and the second burst length n+1, i is an integer greater than or equal to 0, n is an integer greater than or equal to 0 and less than the maximum second burst length, and the first vector corresponding to the second burst length equal to 0 is determined by the second vector.

[0018] In one possible implementation, the determination module is used to: perform a logical OR operation on the first vector corresponding to each second burst length to obtain a logical OR result corresponding to each second burst length; determine the current maximum continuous space to be allocated of the storage space based on the logical OR result corresponding to each second burst length; determine the processing result of the request information based on the current maximum continuous space to be allocated of the storage space and the first burst length.

[0019] In one possible implementation, the processing result of the request information is determined based on the current maximum continuous space to be allocated of the storage space and the first burst length, including: when the first burst length is less than or equal to the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface accepting the request information; or, when the first burst length is greater than the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface blocking the request information.

[0020] In a possible implementation, the device also includes an arbitration module, which is used to: when the processing result indicates that the bus interface accepts the request information, poll and arbitrate each continuous space to be allocated in a preset order to obtain an arbitration result; and allocate the target continuous space to be allocated for the request information according to the arbitration result.

[0021] In one possible implementation, obtaining a second vector for indicating free space in the storage space of the bus interface includes: determining a state vector based on the space capacity of the storage space, each element in the state vector being used to indicate that a storage unit at the same position in the storage space is in an allocated state or a released state; and performing a negation operation on the state vector to obtain a second vector for indicating free space in the storage space.

[0022] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0023] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0024] In the disclosed embodiment, the bus interface can determine whether to accept the request information or block the request information based on the first vector corresponding to each second burst length supported by its own storage space and the first burst length carried by the received request information, wherein the first vector is used to indicate the starting storage position with the continuous space to be allocated corresponding to the second burst length in the storage space of the bus interface, and the storage space is logically a ring storage space connected to the head and the tail. In this way, the space at the head and the tail of the memory that is prone to fragmentation can be combined to form a ring storage space logically connected to the head and the tail, which is conducive to space allocation in a whole way, so that the probability of each space in the storage space of the bus interface being used is equal, reducing the situation where the acceptance of request information is blocked due to excessive fragmentation of the storage space in the bus interface, and improving the space utilization rate of the storage space and the working efficiency of the bus interface.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0027] Figure 1 A schematic diagram showing an application scenario of the data processing method according to an embodiment of the present disclosure.

[0028] Figure 2 A flow chart of a data processing method according to an embodiment of the present disclosure is shown.

[0029] Figure 3 A schematic diagram showing a data processing method according to an embodiment of the present disclosure.

[0030] Figure 4 A schematic diagram of a process for determining a third vector according to an embodiment of the present disclosure is shown.

[0031] Figure 5 A schematic diagram of a process of determining a first vector according to an embodiment of the present disclosure is shown.

[0032] Figure 6 A block diagram of a data processing device according to an embodiment of the present disclosure is shown.

[0033] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0035] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0036] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0037] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0038] Figure 1 A schematic diagram showing an application scenario of the data processing method according to an embodiment of the present disclosure is shown as follows: Figure 1 As shown, the data processing method can be executed by a bus interface (Bus Interface, BIF), and the connection circuit between a device connected to the bus (for example, including a request end and a service end) and the bus can be called a bus interface.

[0039] In one possible implementation, the bus interface may be part of a processor chip, which may include, for example, a graphics processing unit (GPU), a general-purpose computing on graphics processing units (GPGPU), a central processing unit (CPU), a network processor (NP), a multi-core processor (Multi-Core Processor), a digital signal processing unit (DSP), an application-specific integrated circuit (ASIC), a tensor processor (TPU), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The embodiments of the present application do not limit the types of processor chips.

[0040] In a possible implementation, a bus interface can connect an upstream request end and a downstream service end, and the bus interface is used to receive request information sent by the upstream request end, and read request data from the downstream service end to the upstream request end according to the received request information. The request information can be used by the request end to apply for request data of a specified address from the service end. Assuming that the request information initiated by the request end applies for request data with a first burst length (burst length) of L (L≥0), the request data will include L+1 data elements. Among them, the first burst length refers to the number of data elements of the request data that are continuously transmitted starting from the starting address when transmitting the request data.

[0041] When the server is returning the requested data, it needs to obtain each data element of the requested data from the specified page table according to the address information contained in the request information. However, the location of each data element is not necessarily on the same page table. Therefore, the server may return the data elements of the requested data out of order. For example, the data elements sorted later in the request data may be returned first.

[0042] Inside the processor chip, considering that some request ends do not have the ability to reorder the data elements of the received request data, the work of reordering the data elements of the request data returned by the server can be handed over to the bus interface to complete, and the data elements of the request data can be reordered based on the storage space set inside the bus interface.

[0043] In the example, after the bus interface receives the request information from the request end, it pre-allocates a continuous space in the storage space of the bus interface according to the first burst length carried in the request information. The starting position of the continuous space allocated in the storage space is sent to the server together with the request information. The server will increment a position offset for each data element in the request data. When the server returns the request data, the bus interface uses the offset position as the write position of the storage space and stores each data element in the corresponding pre-allocated space. The bus interface will detect whether there is any data element written bit by bit starting from the starting position. When the data element at the front position is not returned to the request end, the data element at the back position will not be returned to the request end.

[0044] Among them, the storage space can be random access memory (Random Access Memory, RAM), dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), cached dynamic random access memory (Cached Dynamic Random Access Memory, CDRAM), enhanced dynamic random access memory (Extended Data Out Dynamic Random Access Memory, EDRAM), etc., and the present disclosure does not limit this.

[0045] Exemplarily, in the case where the processor chip is a GPU, the requesting end may be a data processing unit (datamaster) within the GPU, the server end may be a cache within the GPU, the bus interface may connect an upstream data processing unit and a downstream cache, and the storage space set within the bus interface may be a static random access memory (SRAM).

[0046] In one possible implementation, the first burst length of the request information sent by the request end in the current processor chip is limited to L. When the bus interface receives the current request information, it is necessary to provide L+1 continuous address spaces in the storage space of the bus interface. For example, assuming that the first burst length carried by the request information received by the bus interface is limited to 0x0~0x7 (L=7), the bus interface needs to provide 8 continuous address spaces in the storage space. It should be understood that L can be an integer greater than or equal to 0, and the embodiments of the present disclosure do not specifically limit the size of the first burst length L.

[0047] Among them, the efficiency of the bus interface receiving the request information sent by the requesting end, the storage space in the bus interface collecting the data elements of the request data returned by the server, and the requesting end taking the data elements of the request data from the storage space of the bus interface can be one beat per clock cycle.

[0048] Due to the limitations of the current bus interface's efficiency in receiving request information from the request end, the server's efficiency in returning request data to the bus interface, and the bus interface's efficiency in returning request data to the request end beat by beat, when many request ends frequently send request information with a large first burst length, the space utilization rate in the storage space in the bus interface will be very high. The storage space usage status can be refreshed once per clock cycle. Due to the limitation of the request data return rate, the entire continuous space in the storage space that can accommodate a large value of the first burst length will decrease as the bus interface operation time increases, and the space fragmentation in the storage space will increase significantly, and the probability that the request information with a large value of the first burst length is blocked by the bus interface will also increase accordingly. The head and tail of the current memory can only be used as the starting address and the ending address respectively. When the fragmentation is significant, the probability that the head and tail spaces of the memory are fragmented and cannot be effectively utilized is significantly higher than the middle part of the memory.

[0049] In view of this, in order to make the probability of each space in the storage space of the bus interface being used equally and reduce the situation where the receiving of request information is blocked due to excessive fragmentation of the storage space in the bus interface, an embodiment of the present disclosure provides a data processing method. Figure 2 A flow chart of a data processing method according to an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the method is applied to a bus interface, the bus interface is used to receive request information sent by the request end, and read request data from the service end to the request end according to the received request information. The data processing method includes:

[0050] In step S11, a request message carrying a first burst length is received, the request message is used to allocate a data space having the first burst length for the request message in a storage space of the bus interface, and the data space is used to cache request data read by the request message from a server.

[0051] In step S12, based on the first vector corresponding to each second burst length supported by the storage space and the first burst length, the processing result of the request information is determined, and the processing result includes that the bus interface accepts the request information, or the bus interface blocks the request information; wherein the first vector is used to indicate the starting storage position of the continuous space to be allocated corresponding to the second burst length in the storage space, and the storage space is logically a ring-shaped storage space with a head and a tail connected.

[0052] Exemplarily, in step S11, the requesting end may generate request information for reading the requested data in the server, and send the generated request information to the bus interface, so that it can be subsequently sent to the server via the bus interface.

[0053] The request information may include a first burst length of the request data, which is used to indicate the number of data elements in the request data. For example, assuming that the request information carries a first burst length L, it means that the request data requested by the request information will include L+1 data elements arranged in sequence. The first burst length may be an integer greater than or equal to 0, and the embodiments of the present disclosure do not limit the specific value of the burst length.

[0054] The server will then return the request data to the request end via the bus interface. Since the server may return the data elements of the request data out of order, for example, the data elements sorted later in the request data may be returned first. Considering that the request end does not have the ability to reorder the data elements of the received request data, the request information will also be used to allocate a data space with a first burst length for the request information in the storage space of the bus interface according to the first burst length carried by the request information before the bus interface forwards the request information to the server. The data space is used to cache the request data read from the server by the request information. For example, when the server has not yet returned the data elements sorted earlier in the request data to the bus interface, the data elements sorted later in the request data returned by the server can be cached, so that the work of reordering the data elements of the request data returned by the server is handed over to the bus interface to complete, so that the bus interface can return the data elements in the request data to the request end in order according to the correct order of the data elements in the request data.

[0055] In step S11, the bus interface receives a request message carrying a first burst length. In step S12, the bus interface can obtain whether there is a continuous space to be allocated corresponding to each second burst length in the annular storage space that logically connects the head and the tail based on the first vector corresponding to each second burst length supported by the storage space. Among them, the first vector corresponding to each second burst length can be used to indicate the starting storage position of the continuous space to be allocated corresponding to the second burst length in the storage space. If there is a starting storage position of a continuous space to be allocated of a second burst length in the storage space, and the second burst length is greater than or equal to the first burst length, the bus interface can accept the request message. If there is a second burst length corresponding to the starting storage position of the largest continuous space to be allocated in the storage space that is less than the first burst length, the bus interface can block (for example, wait for acceptance) the request message.

[0056] In this way, since the storage space is logically a ring-shaped storage space connected with the head and the tail, the first vector indicates whether there is a starting storage position of the continuous space to be allocated corresponding to each second burst length in the ring-shaped storage space that logically connects the head and the tail. This is to combine the space at the head and the tail of the physical memory that is prone to fragmentation, and allocate space in a whole, thereby improving the utilization rate of the storage space, reducing the probability of blocking request information carrying a larger first burst length, and improving the performance of the bus interface.

[0057] Figure 3 A schematic diagram of a data processing method according to an embodiment of the present disclosure is shown below. Figure 3 The data processing method of the embodiment of the present disclosure is exemplarily described by taking as an example.

[0058] In one possible implementation, Figure 3 As shown, the method further includes steps S01 to S03:

[0059] In step S01, a second vector for indicating free space in the storage space of the bus interface is obtained, and bits of the second vector correspond to storage cells of the storage space; for example, assuming that the storage space has multiple storage cells, each storage cell can store one data element, the number of bits of the second vector is the same as the number of storage cells, and each bit of the second vector corresponds one-to-one to a storage cell at the same position in the storage space.

[0060] In step S02, a third vector is determined according to the maximum second burst length supported by the storage space and the second vector. For example, based on the maximum second burst length, a vector of the maximum second burst length may be copied from the head of the second vector and concatenated to the tail of the second vector to obtain a third vector, wherein the third vector is used to indicate a space to be allocated in the ring storage space that logically connects the head and the tail.

[0061] In step S03, the first vector corresponding to each second burst length supported by the storage space is determined based on the second vector and the third vector, and each first vector is used to indicate the starting storage position of whether there is a continuous space to be allocated with its own corresponding second burst length in the circular storage space that logically connects the head and the tail.

[0062] In a possible implementation, in response to receiving the request information, a second vector for indicating free space in the storage space of the bus interface is obtained; or the second vector for indicating free space in the storage space of the bus interface is periodically obtained at a predetermined period.

[0063] Optionally, whenever request information enters the bus interface, the bus interface can obtain a second vector once for indicating the free space in the storage space of the bus interface. The first vector corresponding to each second burst length supported by the storage space can be quickly determined through the most recently obtained second vector. These first vectors are used to indicate whether the storage space has a starting storage position of the to-be-allocated continuous space corresponding to each second burst length, so that the bus interface can quickly determine whether to accept the currently input request information.

[0064] Optionally, the bus interface can periodically obtain a second vector indicating free space in the storage space of the bus interface according to the clock cycle of the instructions in the processor (for example, once every microsecond), and quickly determine the first vector corresponding to each second burst length supported by the storage space through the most recently obtained second vector in real time. These first vectors are used to indicate whether the storage space has a starting storage position of a continuous space to be allocated corresponding to each second burst length, so that the bus interface can quickly determine whether to accept the currently input request information.

[0065] In one possible implementation, step S01 may include: determining a state vector A based on the space capacity of the storage space, each element in the state vector A being used to indicate whether a storage unit at the same position in the storage space is in an allocated state or a released state; and performing a negation operation on the state vector A to obtain a second vector B indicating the free space of the storage space.

[0066] In the example, when the bus interface pre-allocates the storage units of the storage space, it maintains a state vector A whose length is equal to the space capacity of the storage space. Each element in the state vector A is used to indicate whether the storage unit at the same position in the storage space is allocated or released. For example, for any element A(i) in the state vector A, if the value of A(i) is 1, it indicates that the storage unit at the i-th position in the storage space is in an allocated state; if the value of A(i) is 0, it indicates that the storage unit at the i-th position in the storage space is in a released state. The initial value of each element in the state vector A can be set to 0.

[0067] The bus interface determines the state vector A, and the state vector A can be inverted bit by bit to obtain the second vector B, which can be used to represent the state of the allocatable space of the current storage space. For example, for any element B(i) in the second vector B, if the value of B(i) is 1, it means that the storage unit at the i-th position in the storage space is free and can be allocated; if the value of B(i) is 0, it means that the storage unit at the i-th position in the storage space is already occupied and cannot be allocated.

[0068] The value range of i is determined by the space capacity of the storage space (that is, the number of storage units included in the storage space), and the embodiments of the present disclosure do not limit the specific value of i.

[0069] In this way, the second vector B indicating the free space in the storage space can be quickly acquired, so that the bus interface can subsequently determine based on the second vector B whether to accept the request information carrying the first burst length.

[0070] In step S01 , a second vector B is determined. In step S02 , the bus interface may determine a third vector C according to the second maximum burst length supported by the storage space and the second vector B.

[0071] In a possible implementation, step S02 may include: extracting a sub-vector S of the maximum second burst length from the second vector B in a direction from low to high; and concatenating the second vector B and the sub-vector S to obtain a concatenated third vector C.

[0072] Figure 4 A schematic diagram of the determination process of the third vector according to an embodiment of the present disclosure is shown as follows: Figure 4 As shown, assuming that the storage space has 0 to 32 position spaces, each position space can represent a storage unit, and the maximum second burst length is 0x7 (where 0x is a hexadecimal representation symbol), it means that the bus interface physically supports the transmission of request data with a maximum of 8 (0x0 to 0x7) data elements, and the lower 7 bits [0,0,0,1,1,1,1] can be taken from the second vector B as a sub-vector, and concatenated with the second vector B to obtain the third vector C. The third vector C is used to represent the actual allocatable state of the ring storage space, and the length of the third vector C is the sum of the length of the second vector B and the maximum second burst length.

[0073] It should be understood that Figure 4 Taking the maximum second burst length of 0x6 as an example, the embodiment of the present disclosure does not impose any specific limitation on the value of the maximum second burst length, which can be determined according to the actual hardware performance of the bus interface.

[0074] like Figure 4As shown in the upper part, assuming that the maximum second burst length acceptable to the current storage space is 0x7, if the splicing process of step S02 is not performed, the continuous space under each second burst length supported by the storage space is directly determined based on the second vector B. For example, the state where there are 1 (corresponding to the second burst length of 0x0) to 8 (corresponding to the second burst length of 0x7) 1s in succession in the second vector B can be searched bit by bit, and the element at the minimum position in the element group that meets the conditions is assigned a value of 1. The head of the storage space can accept request data with a maximum first burst length of 0x3, and the tail space of the storage space can accept request data with a maximum first burst length of 0x1. In essence, it is equivalent to filling 7 1s in the upper 7 bits of the state vector A. In this case, the address space at the tail of the storage space is used as the starting address, and the maximum first burst length that can be passed is relatively limited.

[0075] like Figure 4 As shown in the lower part, assuming that the maximum second burst length acceptable to the current storage space is 0x7, by splicing the second vector B and the subvector S intercepted from the header area of ​​the second vector B, the third vector C obtained can merge the header and tail space of the storage space together to form a ring storage space logically. At this time, the storage space can cache the request data with a maximum first burst length of 0x5, which is greater than Figure 4 The upper part uses the storage space header and tail space as independent spaces, and the supported first burst lengths are 0x1 and 0x3.

[0076] It can be seen that by concatenating the second vector B and the sub-vector S intercepted from the head area of ​​the second vector B, the storage space at the head, tail and middle area of ​​the storage space can have an equal probability of being utilized, which is added together to make it integer, thereby reducing the probability that the request information carrying a larger first burst length is blocked by the bus interface, thereby improving the space utilization of the storage space and the overall operating efficiency of the bus interface.

[0077] In step S02, the third vector C is determined. In step S03, the bus interface can determine the first vector B corresponding to each second burst length n supported by the storage space according to the second vector B and the third vector C. n , thereby determining the support status of the current storage space for the request data of the second burst length n of each scale for caching, and determining whether there is a continuous space to be allocated corresponding to the second burst length n of various scales in the ring storage space that logically connects the head and the tail.

[0078] For example, assuming that the maximum second burst length supported by the storage space is Lmax, the storage space can support a total of Lmax+1 second burst lengths, that is, 0x0~Lmax. The bus interface can determine Lmax+1 first vectors based on the second vector B and the third vector C, that is: the first vector B0 corresponding to the second burst length of 0x0, the first vector B1 corresponding to the second burst length of 0x1, and so on, until the first vector B corresponding to the maximum second burst length of Lmax. Lmax .

[0079] In a possible implementation, step S03 may include: setting the second burst length equal to the first vector B corresponding to n n The element B at position i in n (i) The logical AND result B of the element C(j) at position j in the third vector C n (i) & C(j), as the first vector B corresponding to the second burst length equal to n+1 n+1 The element B at position i in n+1 (i), that is:

[0080] B n+1 (i) = B n (i) & C(j) (1)

[0081] Wherein, & represents logical AND, j is the sum of i and the second burst length n+1 (i.e., j=i+n+1), i is an integer greater than or equal to 0, n is an integer greater than or equal to 0 and less than the maximum second burst length Lmax, and the first vector B0 corresponding to the second burst length equal to 0 is determined by the second vector B.

[0082] For example, the second vector B may be used to represent the support status of the storage space caching the request data with the second burst length of 0x0, and the second vector B may be directly recorded as the first vector B0.

[0083] Then, using formula (1), the first vector B1 can be obtained through the logical AND operation of the first vector B0 and the third vector C, that is, B1(i)=B0(i)&C(i+1), and the first vector B1 is used to characterize the support status of the storage space cache for the request data with the second burst length of 0x1, where the value range of i is determined by the space capacity of the storage space. For example, assuming that the space size of the storage space is 256 bytes, the value range of i is 0 to 255, and & represents logical AND.

[0084] Similarly, using formula (1), the first vector B2 can be obtained through the logical AND operation of the first vector B1 and the third vector C, that is, B2(i)=B1(i)&C(i+1). The first vector B2 is used to characterize the support status of the storage space cache for the request data with the second burst length of 0x2.

[0085] By the recursive method shown in formula (1), the first vector B corresponding to each second burst length n supported by the storage space can be obtained: n .

[0086] Figure 5 A schematic diagram of a process for determining a first vector according to an embodiment of the present disclosure is shown, as shown in FIG. Figure 5 As shown, the third vector C may be the concatenation result of the second vector B and the sub-vector S, and the second vector B may be directly used as the first vector B0.

[0087] For any i-th position element B0(i) in the first vector B0, 0 means that the i-th position corresponding to the element B0(i) in the storage space cannot be used as the starting position to place the request data of the second burst length of 0x0; and 1 means that the i-th position corresponding to the element B0(i) in the storage space can be used as the starting position to place the request data of the second burst length of 0x0. The request data of the second burst length of 0x0 represents the request data composed of 1 (0x0+1) data element.

[0088] Next, we examine the first vector B1. Since the first vector B1 represents the storage space's ability to accommodate request data with two consecutive (0x1+1) data elements when the data space requested from the storage space is the second burst length 0x1, the first vector B1 can be derived from the first vector B0. The first vector B0 shows whether the element B0(i) at each i-th position can be used as the starting position to place the request data with the second burst length of 0x0. The element B1(i) at each i-th position of the first vector B1 should show whether the request data with the second burst length of 0x1 can be used as the starting position to place the request data.

[0089] The element B0(i) at the i-th position of the first vector B0 and the element B0(i+1) at the i+1th position one bit higher can be detected. If the element B0(i) at the i-th position and the element B0(i+1) at the i+1th position in the first vector B0 are both 1, it means that the current storage space can accommodate the request data with 2 consecutive data elements starting from the i-th position, and the element B1(i) at the i-th position of the first vector B1 can be marked as 1; if any of the element B0(i) at the i-th position and the element B0(i+1) at the i+1th position in the first vector B0 is 0, it means that the current storage space cannot accommodate the request data with 2 consecutive data elements starting from the i-th position, and the element B1(i) at the i-th position of the first vector B1 can be marked as 0.

[0090] It should be noted that when i is the Imax position of the tail of the first vector B1 (see Figure 551 part), for the maximum Imax position element B1(Imax) of the first vector B1, it is necessary to detect the maximum Imax position element B0(Imax) corresponding to the first vector B0 and the first position element B(0) of the second vector B, that is, the Imax+1th position element C(Imax+1) of the third vector C.

[0091] Since each element B0(i) in the first vector B0 is equal to each element C(i) in the third vector C, it can also be considered that the element B1(i) corresponding to each i-th position of the first vector B1 is determined by the element B0(i) corresponding to the i-th position of the first vector B0 and the element C(i+1) at the i+1th position in the third vector C, see Figure 5 52 parts.

[0092] Further examining the first vector B2, we can see that each element B2(i) in the first vector B2 shows whether the corresponding i-th position can be used as the starting position to receive the second burst length of 0x2 request data. The second burst length of 0x2 represents request data consisting of 3 (0x2+1) data elements.

[0093] It can be seen that when i is the 0th position of the first vector B2, the 0th position element B2(0) of the first vector B2 is determined by the 0th position element B1(0) of the first vector B1 and the 2nd position element C(0+2) of the third vector C. For example, B2(0)=B1(0)&C(0+2). Figure 5 53 parts.

[0094] Since the 0th position element B1(0) of the first vector B1 is determined by the 0th position element B0(0) of the first vector B0 and the 1st position element B0(1) of the first vector B0, for example, B1(0)=B0(0)&B0(1). The 2nd position element B0(2) of the first vector B0 is equal to the 2nd position element C(2) of the third vector C, for example, C(2)=B0(2).

[0095] Based on this, we can get:

[0096]

[0097] Since the first vector B0 is equal to the second vector B, taking the intermediate process of formula (2), we can get:

[0098] B (0) & B (1) & B (2) = B1(0) & B1(1) = B2(0) (3)

[0099] It can be seen that the element B2(0) at position 0 of the first vector B2 corresponding to the second burst length of 0x2 examines the availability of the three positions 0, 1, and 2 in the storage space. If the three positions 0, 1, and 2 are all available, it means that the current storage space can receive the request data of the second burst length of 0x2 starting at position 0.

[0100] For the highest-order element B2(Imax) of the first vector B2, it is necessary to examine the highest-position element B(Imax) of the second vector B and the 0th-position element B(0) and the 1st-position element B(1) of the second vector B. Among them, to switch to the element on the third vector C, that is, the highest-position element B2(Imax) of the first vector B2, it is necessary to examine the element C(Imax) at the Imaxth position, the element C(Imax+1) at the Imax+1th position, and the element C(Imax+2) at the Imax+2th position in the third vector C, see Figure 5 54 parts.

[0101] Therefore, we can carry out a forward deduction of formula (1) to obtain the first vector B corresponding to the second burst length n+1: n+1 Any element B at position i in n+1 (i) can be expressed as:

[0102]

[0103] Among them, C represents the third vector, B n+1 represents the first vector corresponding to the second burst length n+1, B n Represents the first vector corresponding to the second burst length n, and so on, B0 represents the first vector corresponding to the second burst length 0x0; wherein, the value range of n is determined by the maximum second burst length Lmax, and the value of any second burst length n+1 is greater than or equal to 0 and less than or equal to the maximum second burst length Lmax, and the value range of i is determined by the space capacity of the storage space. For example, assuming that the storage space can store at most Imax+1 data elements and its space capacity is 0 to Imax, then the value range of i is [0,Imax].

[0104] By using formula (1), the first vector corresponding to each second burst length supported by the storage space can be determined quickly and efficiently, thereby determining whether there is a continuous space to be allocated corresponding to the second burst length of various scales in the ring storage space that logically connects the head and the tail. For example, the first vector B corresponding to the second burst length of n+1 n+1 Any i-th element B in n+1 The physical meaning of (i) is: starting from the current position i, the memory is in a receivable state for the second burst length n+1.n+1 The value of (i) is 1, indicating that the memory position i can be used as the starting position to place the request data of the second burst length n+1; if B n+1 The value of (i) is 0, indicating that the i-th position of the memory cannot be used as the starting position to place the request data of the second burst length of n+1.

[0105] In a possible implementation, the bus interface may execute steps S01 to S03 in response to receiving the request information to determine the first vector corresponding to each second burst length supported by the storage space; or the bus interface may periodically execute steps S01 to S03 according to the clock cycle to determine the first vector corresponding to each second burst length supported by the storage space. In this way, whenever the bus interface receives the request information carrying the first burst length in step S11, it may determine in real time in step S12 whether to accept or block the current request information according to the first vector corresponding to each second burst length supported by the storage space and the first burst length obtained in real time.

[0106] In one possible implementation, step S12 may include: performing a logical OR operation on the first vector corresponding to each second burst length to obtain a logical OR result corresponding to each second burst length; determining the current maximum continuous space to be allocated of the storage space based on the logical OR result corresponding to each second burst length; determining the processing result of the request information based on the current maximum continuous space to be allocated of the storage space and the first burst length.

[0107] Exemplarily, assuming that the maximum second burst length is Lmax, the storage space can support a total of Lmax+1 second burst lengths (e.g., 0x0 to Lmax). For Lmax+1 first vectors, for example, they include: a first vector B0 corresponding to a second burst length of 0x0, a first vector B1 corresponding to a second burst length of 0x1, and so on, until a first vector B corresponding to a maximum second burst length of Lmax. Lmax .

[0108] For the first vector B0 to the first vector B Lmax Each bit is ORed. If a first vector B n The logical OR result is 1, indicating that there are unallocated continuous n+1 positions of unallocated continuous space to be allocated in the current storage space, and the storage space can accept cache corresponding to the first burst length of n request data, where n is any integer from 0 to Lmax.

[0109] From the first vector B0 to the first vector B LmaxThe first vector whose logical OR result is 1 is filtered out, and the maximum subscript in the filtered out first vector is used as the burst length threshold. The burst length threshold is the maximum first burst length acceptable to the current storage space, indicating that the current maximum continuous space to be allocated in the storage space can accept the request data of the maximum first burst length for cache.

[0110] After obtaining the current maximum continuous space to be allocated in the storage space, the maximum continuous space to be allocated in the storage space can be compared with the first burst length carried in the request information, and the processing result of whether the bus interface accepts or blocks the request information can be determined based on the comparison result.

[0111] In one possible implementation, the processing result of the request information is determined based on the current maximum continuous space to be allocated of the storage space and the first burst length, including: when the first burst length is less than or equal to the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface accepting the request information; or, when the first burst length is greater than the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface blocking the request information.

[0112] In the example, if the first burst length carried by the current request information is less than or equal to the current maximum continuous space to be allocated, that is, the first burst length is less than or equal to the burst length threshold, it means that there is free continuous space in the storage space that can satisfy the cache of the request data of the first burst length, and the processing result of the current request information can be determined as the bus interface accepting the current request information; if the first burst length carried by the current request information is greater than the current maximum continuous space to be allocated, that is, the first burst length is greater than the burst length threshold, it means that there is free continuous space in the storage space that is insufficient to cache the request data of the first burst length, and the processing result of the current request information can be determined as the bus interface blocking the current request information.

[0113] In this way, the bus interface can quickly and accurately determine the processing result of the current request information.

[0114] In one possible implementation, Figure 3 As shown, the method also includes: in step S14, when the processing result indicates that the bus interface accepts the request information, polling arbitration is performed on each continuous space to be allocated in a preset order to obtain an arbitration result; in step S15, according to the arbitration result, the target continuous space to be allocated is allocated to the request information.

[0115] Exemplarily, for the request information accepted by the bus interface, assuming that there are multiple unallocated continuous spaces in the storage space of the bus interface that can be allocated to the request information, these unallocated continuous spaces can be polled and arbitrated, and based on the arbitration result of the polling arbitration, the target unallocated continuous space can be allocated to the request information.

[0116] According to the first burst length carried by the request information, the first vector corresponding to the second burst length which is the same as the first burst length can be found from the multiple first vectors determined in step S03. Each element of the first vector is used to indicate whether the same position in the storage space can be used as the starting position to place the request data of the first burst length. For example, an element value of 1 indicates that the element is at the same position in the storage space, and the request data of the first burst length can be placed as the starting position; an element value of 0 indicates that the element is at the same position in the storage space, and the request data of the first burst length cannot be placed as the starting position.

[0117] Then, the first vector found by the first burst length can be segmented to obtain multiple segmented vectors, such as segmented vector 1 to segmented vector n. The bus interface can poll and arbitrate the first vector in a preset order (for example, in order from segmented vector 1 to segmented vector n, and in order from low position to high position in each segmented vector) until the first element with a value of 1 is found, and the same position of the element in the storage space is pre-allocated to the request information carrying the first burst length as the starting position.

[0118] For example, assuming that the storage space of the memory can store 0 to 255 data elements at most, the length of the first vector is the same as the size of the storage space of the memory, and also has 0 to 255 elements. In the first vector, every 32 elements can be used as a segment, namely [0:31], [32:63], [64:95], [96:127], [128:159], [160:191], [192:223], [224:255]. After the polling arbitration starts, since the element value in the first vector that can accommodate the data space required by the current request information (such as the space of the first burst length) is set to 1, and the element value that cannot accommodate the data space required by the current request information is set to 0, the bus interface can poll and access these eight segments, and take the lowest position in the segment with an element value of 1 as the starting position of the pre-allocated data space.

[0119] For example, for a certain request information, the storage space has starting positions 20, 42, 50, 224, and 255 to accommodate the data space required by the request information. It is known that 20 is in the first segment, 42 and 50 are in the second segment, and 224 and 255 are in the eighth segment. Assuming that the data space pre-allocated for the last request information is in the fifth segment, the starting position of the data space required for the current request information will be allocated to position 224 of the eighth segment.

[0120] It should be understood that the embodiments of the present disclosure do not limit the size of the storage space and the number of segments of the first vector, which can be set according to actual application scenarios.

[0121] This method helps to make more balanced use of storage space.

[0122] In a possible implementation, in step S16, when the processing result indicates that the bus interface blocks the request information, the process may return to step S12, waiting for the continuous space to be allocated in the storage space to meet the data space required by the request information, and the bus interface accepts the request information.

[0123] The data processing method of the disclosed embodiment can use an address index with one more bit than the physical address space of the memory to represent the storage space, thereby reducing the restrictions of the memory on the head and tail space, making the head and tail of the memory logically connected, and abstracting the linear storage space of the memory into a ring-shaped storage space, reducing the probability of fragmentation of the edge space of the memory, and improving the storage space utilization of the memory.

[0124] Moreover, the data processing method of the embodiment of the present disclosure can use fewer resources and optimize the predetermined space allocation of the memory through smaller changes. Moreover, as the memory capacity is expanded, the request end sends continuous request information with a larger first burst length, and the bus interface and the request end (or service end) and memory throughput are improved, the data processing method of the embodiment of the present disclosure can continue to be used.

[0125] In an embodiment of the present disclosure, a second vector for indicating free space in a storage space of a bus interface can be obtained, and a subvector of the maximum second burst length supported by the storage space is intercepted from the second vector in a direction from low to high, and spliced ​​to the tail of the second vector to obtain a third vector after splicing, and a first vector corresponding to each second burst length supported by the storage space is determined according to the second vector and the third vector, and based on the first vector corresponding to each second burst length supported by the storage space and the first burst length carried by the request information, it is determined whether to accept the request information, and a data space for caching the request data is pre-allocated for the accepted request information. In this way, through a simple method design, the utilization rate of the head and tail space of the memory can be equal to the utilization rate of the middle part, the probability of request information carrying a larger first burst length being blocked is reduced, and the overall performance of the bus interface is improved, the idea is simple, the code engineering workload is small, and it is not limited by physical devices.

[0126] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0127] In addition, the present disclosure also provides a data processing device, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any data processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0128] Figure 6 A block diagram of a data processing device according to an embodiment of the present disclosure is shown as follows: Figure 6 As shown, the device is applied to a bus interface, the bus interface is used to receive request information sent by a request end, and read request data from a service end to the request end according to the received request information, and the device includes:

[0129] A receiving module 61, configured to receive request information carrying a first burst length, wherein the request information is used to allocate a data space having the first burst length for the request information in a storage space of the bus interface, wherein the data space is used to cache request data read from the server;

[0130] A determination module 62 is used to determine a processing result of the request information based on a first vector corresponding to each second burst length supported by the storage space and the first burst length, the processing result including whether the bus interface accepts the request information or the bus interface blocks the request information, wherein the first vector is used to indicate a starting storage position of a continuous space to be allocated in the storage space corresponding to the second burst length, and the storage space is logically a ring-shaped storage space with a head and a tail connected.

[0131] In a possible implementation, the device also includes an acquisition module, which is used to: acquire a second vector indicating free space in the storage space of the bus interface, the bits of the second vector corresponding to storage units of the storage space; determine a third vector based on a maximum second burst length supported by the storage space and the second vector, the third vector being used to indicate a to-be-allocated space of a ring-shaped storage space that logically connects a head and a tail; and determine the first vector corresponding to each second burst length supported by the storage space based on the second vector and the third vector.

[0132] In one possible implementation, obtaining a second vector for indicating free space in the storage space of the bus interface includes: in response to receiving the request information, obtaining a second vector for indicating free space in the storage space of the bus interface; or, periodically obtaining a second vector for indicating free space in the storage space of the bus interface according to a predetermined period.

[0133] In a possible implementation, a third vector is determined based on the maximum second burst length supported by the storage space and the second vector, including: intercepting a sub-vector of the maximum second burst length from the second vector in a direction from low to high; and splicing the second vector and the sub-vector to obtain a spliced ​​third vector.

[0134] In one possible implementation, determining the first vector corresponding to each second burst length supported by the storage space based on the second vector and the third vector includes: taking the logical AND result of the element at the i-th position in the first vector corresponding to the second burst length equal to n and the element at the j-th position in the third vector as the element at the i-th position in the first vector corresponding to the second burst length equal to n+1, wherein j is the sum of i and the second burst length n+1, i is an integer greater than or equal to 0, n is an integer greater than or equal to 0 and less than the maximum second burst length, and the first vector corresponding to the second burst length equal to 0 is determined by the second vector.

[0135] In one possible implementation, the determination module 62 is used to: perform a logical OR operation on the first vector corresponding to each second burst length to obtain a logical OR result corresponding to each second burst length; determine the current maximum continuous space to be allocated of the storage space based on the logical OR result corresponding to each second burst length; determine the processing result of the request information based on the current maximum continuous space to be allocated of the storage space and the first burst length.

[0136] In one possible implementation, the processing result of the request information is determined based on the current maximum continuous space to be allocated of the storage space and the first burst length, including: when the first burst length is less than or equal to the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface accepting the request information; or, when the first burst length is greater than the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface blocking the request information.

[0137] In a possible implementation, the device also includes an arbitration module, which is used to: when the processing result indicates that the bus interface accepts the request information, poll and arbitrate each continuous space to be allocated in a preset order to obtain an arbitration result; and allocate the target continuous space to be allocated for the request information according to the arbitration result.

[0138] In one possible implementation, obtaining a second vector for indicating free space in the storage space of the bus interface includes: determining a state vector based on the space capacity of the storage space, each element in the state vector being used to indicate that a storage unit at the same position in the storage space is in an allocated state or a released state; and performing a negation operation on the state vector to obtain a second vector for indicating free space in the storage space.

[0139] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0140] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0141] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0142] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0143] In one possible implementation, the electronic device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0144] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0145] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0146] Figure 7 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions that can be executed by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0147] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OSXTM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0148] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0149] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0150] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0151] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0152] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0153] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0154] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0155] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0156] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0157] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0158] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0159] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0160] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0161] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data processing method, characterized in that: The method is applied to a bus interface, the bus interface is used to receive request information sent by a request end, and read request data from a service end to the request end according to the received request information, including: receiving request information carrying a first burst length, the request information being used to allocate a data space having the first burst length for the request information in a storage space of the bus interface, the data space being used to cache request data read from a server; determining, according to the first vector corresponding to each second burst length supported by the storage space and the first burst length, a processing result of the request information, the processing result comprising whether the bus interface accepts the request information or whether the bus interface blocks the request information, Among them, the first vector is used to indicate the starting storage position of the continuous space to be allocated corresponding to the second burst length in the storage space, the second burst length is the continuous space length that the storage space can support, and the storage space is logically a ring storage space with a head and a tail connected.

2. The method according to claim 1, characterized in that The method further comprises: Obtaining a second vector for indicating free space in the storage space of the bus interface, wherein bits of the second vector correspond to storage units of the storage space; Determine a third vector according to the maximum second burst length supported by the storage space and the second vector, wherein the third vector is used to indicate a to-be-allocated space of the ring storage space that logically connects the head and the tail; The first vector corresponding to each second burst length supported by the storage space is determined according to the second vector and the third vector.

3. The method according to claim 2, characterized in that Acquiring a second vector for indicating free space in the storage space of the bus interface, comprising: In response to receiving the request information, obtaining a second vector indicating free space in the storage space of the bus interface; or A second vector indicating free space in the storage space of the bus interface is periodically obtained at a predetermined cycle.

4. The method according to claim 2 or 3, characterized in that: Determining a third vector according to a maximum second burst length supported by the storage space and the second vector includes: According to the direction from low bit to high bit, intercepting the sub-vector of the maximum second burst length from the second vector; The second vector and the sub-vector are concatenated to obtain a concatenated third vector.

5. The method according to claim 2 or 3, characterized in that: Determining, according to the second vector and the third vector, the first vector corresponding to each second burst length supported by the storage space includes: The logical AND result of the element at the i-th position in the first vector corresponding to the second burst length being equal to n and the element at the j-th position in the third vector is used as the element at the i-th position in the first vector corresponding to the second burst length being equal to n+1, Among them, j is the sum of i and the second burst length n+1, i is an integer greater than or equal to 0, n is an integer greater than or equal to 0 and less than the maximum second burst length, and the first vector corresponding to the second burst length equal to 0 is determined by the second vector.

6. The method according to claim 1, characterized in that Determining a processing result of the request information according to a first vector corresponding to each second burst length supported by the storage space and the first burst length includes: Performing a logical OR operation on the first vector corresponding to each second burst length to obtain a logical OR result corresponding to each second burst length; Determine the current maximum continuous space to be allocated in the storage space according to the logical OR result corresponding to each second burst length; A processing result of the request information is determined according to the current maximum continuous space to be allocated in the storage space and the first burst length.

7. The method according to claim 6, characterized in that Determining a processing result of the request information according to a current maximum continuous space to be allocated in the storage space and the first burst length includes: In a case where the first burst length is less than or equal to the current maximum continuous space to be allocated, determining the processing result of the request information as the bus interface accepting the request information; Alternatively, when the first burst length is greater than the current maximum continuous space to be allocated, the processing result of the request information is determined as the bus interface blocking the request information.

8. The method according to any one of claims 1 to 3, characterized in that The method further comprises: When the processing result indicates that the bus interface accepts the request information, performing round-robin arbitration on each continuous space to be allocated in a preset order to obtain an arbitration result; According to the arbitration result, a target continuous space to be allocated is allocated to the request information.

9. The method according to claim 2 or 3, characterized in that: Acquiring a second vector for indicating free space in the storage space of the bus interface, comprising: Determine a state vector according to the space capacity of the storage space, wherein each element in the state vector is used to indicate that a storage unit at the same position in the storage space is in an allocation state or a release state; A negation operation is performed on the state vector to obtain a second vector indicating free space in the storage space.

10. A data processing device, characterized in that: The device is applied to a bus interface, the bus interface is used to receive request information sent by a request end, and read request data from a service end to the request end according to the received request information, and the device includes: A receiving module, configured to receive request information carrying a first burst length, wherein the request information is used to allocate a data space having the first burst length for the request information in a storage space of the bus interface, wherein the data space is used to cache request data read from a server; a determination module, configured to determine, according to the first vector corresponding to each second burst length supported by the storage space and the first burst length, a processing result of the request information, wherein the processing result includes whether the bus interface accepts the request information or whether the bus interface blocks the request information, Among them, the first vector is used to indicate the starting storage position of the continuous space to be allocated corresponding to the second burst length in the storage space, the second burst length is the continuous space length that the storage space can support, and the storage space is logically a ring storage space with a head and a tail connected.

11. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 9.

12. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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