Scan driving circuit and display panel
By designing a combined circuit structure of cascaded scanning drive units, the problem of large space occupation in the scanning drive circuit was solved, and the scanning drive circuit was simplified while the signal transmission speed was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGSHA HKC OPTOELECTRONICS CO LTD
- Filing Date
- 2023-12-13
- Publication Date
- 2026-06-05
Smart Images
Figure CN117975895B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to scanning drive circuits and display panels. Background Technology
[0002] Gate Driver Less (GDL) technology utilizes the existing array manufacturing process of liquid crystal display panels to fabricate the driving circuitry for horizontal scan lines on the substrate surrounding the display area. This allows GDL to replace external integrated circuit (IC) boards in driving the horizontal scan lines. GDL technology reduces the soldering steps for external ICs, making liquid crystal display panels more suitable for manufacturing narrow-bezel or bezel-less display products.
[0003] Currently, since the scanning drive circuit is fabricated on the array substrate, the size of the scanning drive circuit directly affects the size of the display panel bezel. Therefore, how to simplify the scanning drive circuit to reduce its space occupation is an urgent problem to be solved. Summary of the Invention
[0004] In view of the shortcomings of the prior art, this application provides a scanning drive circuit and display panel that can effectively simplify the circuit structure and reduce space occupation.
[0005] This application provides a scan driving circuit, including n cascaded scan driving units, where n is an integer greater than 1. The n scan driving units sequentially output corresponding scan signals, which control pixel units to receive data signals for image display and perform image display. The a-th scan driving unit includes an output module, a pull-down module, an output control node, and a scan signal output terminal, where 1 ≤ a ≤ n. The output module is connected to the output control node and the scan signal output terminal. The pull-down module is connected to the output control node and the scan signal output terminal. When the voltage of the output control node is a first potential, the pull-down module controls the scan signal output terminal to stop outputting the scan signal and maintain it at the first potential. When the voltage of the output control node is a second potential, the output module controls the scan signal output terminal to output the scan signal, where the second potential is greater than the first potential.
[0006] Optionally, the output module is also connected to the clock signal terminal, and the pull-down module is also connected to the first low-voltage terminal. When the output control node is at the first potential, the output module stops controlling the scan signal output terminal to output the scan signal according to the clock signal output by the clock signal terminal. At the same time, the pull-down module controls the scan signal output terminal to connect to the first low-voltage terminal so as to transfer the charge in the scan signal output terminal to the first low-voltage terminal.
[0007] Optionally, the output module includes a first switching transistor, which includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the first switching transistor is connected to the output control node, the first conductive terminal of the first switching transistor is connected to the clock signal terminal, and the second conductive terminal of the first switching transistor is connected to the scan signal output terminal. The first switching transistor is turned on when the output control node is at the second potential, and the clock signal is transmitted to the scan signal output terminal through the first conductive terminal and the second conductive terminal and output as the scan signal.
[0008] Optionally, the pull-down module includes a second switch transistor, which includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the second switch transistor is connected to the output control node, the first conductive terminal of the second switch transistor is connected to the scan signal output terminal, and the second conductive terminal of the second switch transistor is connected to the first low-voltage terminal. The second switch transistor is used to turn on when the output control node is at the first potential, so as to connect the scan signal output terminal to the first low-voltage terminal.
[0009] Optionally, the first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor.
[0010] Optionally, the first switch and the second switch are disposed on the same substrate and adjacent to each other. The control terminal of the first switch is disposed on the surface of the substrate, and the first conductive terminal and the second conductive terminal of the first switch are stacked in the same layer on the side of the control terminal of the first switch away from the substrate. The control terminal of the second switch is stacked on the substrate, and the first conductive terminal and the second conductive terminal of the second switch are stacked in the same layer on the side of the control terminal of the second switch away from the substrate. The control terminals of the first switch and the second switch are located in the same layer, and the first and second conductive terminals of the first switch and the second switch are located in the same layer.
[0011] Optionally, the first and second switching transistors are stacked sequentially on a substrate, sharing a common control terminal. The first switching transistor includes a first active layer, and the second switching transistor includes a second active layer. The first active layer, the common control terminal, and the second active layer are stacked sequentially on the substrate. Insulating layers are provided between the first active layer and the common control terminal, and between the second active layer and the common control terminal. The first conductive terminal of the first switching transistor is stacked on the insulating layer on the side away from the first active layer and connected to the first active layer. The second conductive terminal of the first switching transistor is stacked on the insulating layer on the side away from the first active layer and connected to the first active layer. The first and second conductive terminals of the second switching transistor are stacked on the insulating layer on the side away from the common control terminal and are located on opposite sides of the second active layer. The first conductive terminal of the second switching transistor and the second conductive terminal of the first switching transistor are located on the same layer, and the first conductive terminal of the second switching transistor is connected to the second conductive terminal of the first switching transistor.
[0012] Optionally, the scan driving circuit further includes a pull-up module and a reset module. The pull-up module is connected to the scan signal output terminal of the (a-4)th scan driving unit and the output control node, and is used to pull the output control node from the first potential to the second potential under the control of the scan signal output by the (a-4)th scan driving unit. The reset module is connected to the scan signal output terminal of the (a+4)th scan driving unit and the output control node, and is used to pull the output control node from the second potential to the first potential under the control of the scan signal output by the (a+4)th scan driving unit.
[0013] Optionally, the pull-up module includes a third switch, and the reset module includes a fourth switch. The third switch includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal and the first conductive terminal of the third switch are connected to the scan signal output terminal of the (a-4)th scan driving unit, and the second conductive terminal of the third switch is connected to the output control node. It is used to turn on under the control of the scan signal output by the (a-4)th scan driving unit to pull the output control node up to the second potential. The fourth switch includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the fourth switch is connected to the scan signal output terminal of the (a+4)th scan driving unit, the first conductive terminal of the fourth switch is connected to the output control node, and the second conductive terminal of the fourth switch is connected to a second low-voltage terminal. It is used to turn on under the control of the scan signal output by the (a+4)th scan driving unit, controlling the output control node to connect to the second low-voltage terminal, and pulling the output control node down to the first potential.
[0014] This application also provides a display panel, including multiple data lines, multiple scan lines, multiple pixel units arranged in a matrix and disposed in a display area, a data driving circuit disposed in a non-display area, and the aforementioned scan driving circuit. The scan driving circuit is used to output scan signals to the pixel units through the scan lines and to control the pixel units to receive data signals output by the data driving circuit from the data lines for image display.
[0015] Compared to existing technologies, by reducing the number of functional units and circuit elements in the scan drive circuit while maintaining the functionality of the scan drive unit, the size of the scan drive unit is effectively reduced, thereby reducing the space occupied by the scan drive circuit. Furthermore, by reducing the number of components in the scan drive circuit, the signal delay caused by circuit element redundancy is reduced, the signal transmission speed is improved, and thus the driving capability of the scan drive unit is enhanced. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the structure of a display device provided in the first embodiment of this application;
[0018] Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel;
[0019] Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel;
[0020] Figure 4 for Figure 3 A schematic diagram of the scanning drive circuit in the image;
[0021] Figure 5 for Figure 4 Equivalent circuit diagram of the scanning drive unit;
[0022] Figure 6 for Figure 5 A schematic diagram showing the changes in the on-voltage of the first and second switching transistors in the circuit.
[0023] Figure 7 for Figure 5 Timing diagram of the mid-scan signal output;
[0024] Figure 8 for Figure 5 Schematic diagram of the structure of the first and second switching transistors in the middle;
[0025] Figure 9 Provided for the second embodiment, as Figure 5 Schematic diagram of the first and second switching transistors.
[0026] Explanation of reference numerals in the attached drawings: Display device-100, Display panel-10, Power module-20, Support frame-30, Array substrate-10c, Display medium layer-10e, Opposing substrate-10d, Display area-10a, Non-display area-10b, Timing control circuit-11, Data driving circuit-12, Scan driving circuit-13, Pixel unit-P, Backlight module-17, First direction-F1, Second direction-F2, m data lines-S1~Sm, n scan lines-G1~Gn, Clock signal-CLK, Start signal-STV, Reset signal-R, Scan driving unit-GDL, Output module-131, Pull-down module-132, Pull-up module-133, Reset module-134, Clock signal terminal-C K, First Switch - M1, Second Switch - M2, Third Switch - M3, Fourth Switch - M4, Output Control Node - Q, Scan Signal Output Terminal - Gout, First Low Voltage Terminal - Vss1, Second Low Voltage Terminal - Vss2, Gate-Source Voltage - Vgs, Source-Drain Current - Ids, First Time Period - T1, Second Time Period - T2, Third Time Period - T3, Fourth Time Period - T4, First Potential - V1, Second Potential - V2, Third Potential - V3, Control Terminal of First Switch - g1, First Conductive Terminal of First Switch - s1, Second Conductive Terminal of First Switch - d1, Control Terminal of Second Switch - g2, First Conductive Terminal of Second Switch - s2, Second Conductive Terminal of Second Switch - d2, Common Control Terminal - g. Detailed Implementation
[0027] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0028] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.
[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.
[0030] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0032] Please see Figure 1 , Figure 1This is a schematic diagram of a display device according to the first embodiment of this application. The display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images, and the support frame 30 provides fixation and protection for the display panel 10 and the power module 20.
[0033] In other embodiments of this application, the display device 100 may not require the support frame 30, for example, it may be a portable electronic device, such as a mobile phone or tablet computer.
[0034] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel.
[0035] The display panel 10 includes an array substrate 10c and a counter substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the counter substrate 10d. Driving elements are disposed on the array substrate 10c and the counter substrate 10d to generate corresponding electric fields according to data signals, thereby driving the display medium layer 10e to emit light of corresponding brightness to perform image display. The display medium can be liquid crystal molecules, miniLED, Micro-LED, OLED, etc., and this application does not limit its use.
[0036] Taking a liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules. The display panel 10 also includes a back light module 17 (BM), wherein the back light module 17 is used to provide light for display to the display medium layer 10e. The liquid crystal molecules deflect relative angles according to the data signal so as to emit the light transmitted by the back light module 17 to the opposing substrate to perform image display.
[0037] Please refer to the following: Figure 3 , Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel.
[0038] like Figure 3 As shown, the display panel 10 also includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are disposed in the non-display area 10b of the display panel 10.
[0039] The display area 10a of the display panel 10 has m data lines (Source lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a grid pattern. The m data lines S1 to Sm extend along a first direction F1, and the n scan lines G1 to Gn extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are disposed at the intersections of the n scan lines G1 to Gn and the data lines S1 to Sm.
[0040] The timing control circuit 11 receives an image signal representing image information from an external signal source, obtains a clock signal CLK, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn for synchronization, and outputs a gate output control signal Cg for controlling the scan drive circuit 13, a source output control signal Cs for controlling the data drive circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and then transmits the data signal to the data drive circuit 12.
[0041] m data lines S1 to Sm are connected to the data driving circuit 11 and are used to receive data signals provided by the data driving circuit 12, which are stored and transmitted in the form of grayscale values. n scan lines G1 to Gn are connected to the scan driving circuit 13 and are used by the self-scanning driving circuit 13 to receive scan signals.
[0042] Under the control of n scan lines G1 to Gn, the pixel unit P receives the grayscale data voltage of the corresponding data signal provided by the data lines S1 to Sm within a predetermined time period, and drives the display medium layer 10e to deflect by a corresponding angle, thereby emitting light of corresponding brightness according to the corresponding deflection angle, so as to achieve image display by emitting light of corresponding brightness according to the image signal.
[0043] The scan drive circuit 13 receives the gate output control signal Cg from the timing control circuit 11 and outputs scan signals to each scan line G1 to Gn. The data drive circuit 12 receives the source output control signal Cs from the timing control circuit 11 and outputs data signals to each data line S1 to Sm for driving the elements in each pixel unit P in the display area 10a to perform image display. The data signals provided to the display panel 10 are analog grayscale voltages. The scan drive circuit 13 outputs scan signals to control the pixel unit P to receive the data signals output by the data drive circuit 12, thereby controlling the pixel unit P to display the corresponding image.
[0044] Please see Figure 4 , Figure 4 for Figure 3 The circuit structure diagram of the scanning drive circuit is shown in the figure.
[0045] like Figure 4 As shown, the scan drive circuit 13 includes n cascaded scan drive units GDL1 to GDLn, eight clock signals CLK1 to CLK8, a start signal STV, a reset signal R, and a low-voltage terminal Vss, where n is an integer greater than or equal to 1.
[0046] In the exemplary embodiment, the clock signal can also be set to other quantities as needed, and this application does not impose any restrictions.
[0047] In the scanning drive circuit 13, each scanning drive unit outputs a scanning signal to a scan line in the display area 10a. During the display of one frame of image, n scanning drive units output n scanning signals in sequence.
[0048] Eight clock signals CLK1-CLK8 are used to provide scan drive timing for the scan signals output by the scan drive unit. The start signal STV is the enable start signal for the first scan drive unit GDL1, and other scan drive units use the cascaded signal output by the cascaded scan unit as their start signal. The low-voltage terminal Vss is used to provide low voltage to the nodes in the scan drive unit.
[0049] Please see Figure 5 , Figure 5 for Figure 4 A schematic diagram of the equivalent circuit of the scanning drive unit.
[0050] like Figure 5 As shown, taking the a-th scan driving unit as an example, where 5≤a≤n, the scan driving unit GDL includes an output module 131, a pull-down module 132, a pull-up module 133, a reset module 134, and an output control node Q. The output module 131 is connected to the output control node Q and the scan signal output terminal Gout(a), and is used to output the scan signal from the scan signal output terminal Gout(a) under the control of the output control node Q.
[0051] The pull-down module 132 is connected to the output control node Q, the scan signal output terminal Gout(a) and the first low voltage terminal Vss1. It is used to connect the scan signal output terminal Gout(a) to the first low voltage terminal Vss1 under the control of the output control node Q, and to pull down the potential of the scan signal output terminal Gout(a) to a low potential, that is, to control the scan signal output terminal Gout(a) to stop outputting the scan signal.
[0052] The pull-up module 133 is connected to the scan signal output terminal Gout(a-4) of the a-4th level scan drive unit and the output control node Q, and is used to pull up the output control node Q from the first potential to the second potential under the control of the scan signal output by the a-4th level scan drive unit.
[0053] The reset module 134 is connected to the output control node Q, the scan signal output terminal Gout(a+4) of the a+4th level scan drive unit, and the low voltage terminal Vss2. It is used to pull down the output control node Q from the second potential to the first potential under the control of the scan signal output by the a+4th level scan drive unit.
[0054] Specifically, the output module 131 includes a first switch M1, which includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the first switch M1 is connected to the output control node Q, the first conductive terminal is connected to the clock signal terminal CK, and the second conductive terminal is connected to the scan signal output terminal Gout(a). The first switch M1 is used to connect the first conductive terminal and the second conductive terminal when the output control node Q is at the second potential, receive the clock signal from the clock signal terminal CK, and output it as a scan signal from the scan signal output terminal Gout(a).
[0055] The pull-down module 132 includes a second switch M2, which includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the second switch M2 is connected to the output control node Q, the first conductive terminal is connected to the first low-voltage terminal Vss1, and the second conductive terminal is connected to the scan signal output terminal Gout(a). The second switch M2 is turned on when the output control node Q is at the first potential, i.e., the low potential, to electrically connect the scan signal output terminal Gout(a) to the first low-voltage terminal Vss1, thereby pulling down the potential of the scan signal output terminal Gout(a) to the first potential, i.e., the low potential, which means controlling the scan signal output terminal Gout(a) to stop outputting the scan signal.
[0056] The pull-up module includes a third switch M3, which includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal and the first conductive terminal of the third switch M3 are connected to the scan signal output terminal Gout(a-4) of the a-4th level scan drive unit, and the second conductive terminal is connected to the output control node Q. It is used to turn on under the control of the scan signal output by the a-4th level scan drive unit and pull up the potential of the output control node Q to the second potential.
[0057] The reset module 134 includes a fourth switch M4, which includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the fourth switch M4 is connected to the scan signal output terminal Gout(a+4) of the (a+4)th level scan drive unit. The first conductive terminal is connected to the output control node Q, and the second conductive terminal is connected to the second low-voltage terminal Vss2. It is used to turn on under the control of the scan signal output by the (a+4)th level scan drive unit, so that the output control node Q is electrically connected to the second low-voltage terminal Vss2, and to pull down the potential of the output control node Q to the first potential, i.e., the low potential.
[0058] In an exemplary embodiment, the control terminal is the gate of the switching transistor, the first conductive terminal is the source of the switching transistor, and the second conductive terminal is the drain of the switching transistor. When a voltage is applied to the control terminal, the switching transistor is turned on. Of course, the first conductive terminal can also be set at the drain of the switching transistor and the second conductive terminal can be set at the source of the switching transistor as needed. This application does not limit this.
[0059] Please see Figure 6 , Figure 6 for Figure 5 A schematic diagram showing the changes in the on-state voltage of the first and second switching transistors. (See diagram below.) Figure 6 As shown, the first switching transistor M1 and the second switching transistor M2 are transistors with opposite characteristics. The first switching transistor M1 can be an N-type transistor. As the gate-source voltage Vgs increases, the current turned on by the first switching transistor M1, i.e., the source-drain current Ids, gradually increases. That is, it conducts when the control terminal is high and is turned off when the control terminal is low. The second switching transistor M2 can be a P-type transistor. As the gate-source voltage Vgs increases, the current turned on by the second switching transistor M2, i.e., the source-drain current Ids, decreases. That is, it conducts when the control terminal is low and is turned off when the control terminal is high. When the output control node Q is at the second potential, the first switch M1 is turned on and the second switch M2 is turned off, and the scan signal output terminal Gout(a) outputs the scan signal. When the output control node Q is at the first potential, the first switch M1 is turned off and the second switch M2 is turned on, the scan signal output terminal Gout(a) stops outputting the scan signal, and the residual charge is conducted to the second voltage terminal Vss2 through the second switch M2 to avoid the residual charge affecting the output of the scan signal.
[0060] Since the first switch M1 and the second switch M2 are simultaneously controlled by the output control node Q, the first switch M1 and the second switch M2 can synchronously control the scan signal output terminal Gout(a). This allows the scan signal output terminal Gout(a) to be pulled down to a low potential immediately upon stopping the output of the scan signal. This effectively avoids the influence of residual charge on the scan signal during the period from when the scan signal output terminal Gout(a) stops receiving the clock signal to when it is pulled down to a low potential, thus preventing the occurrence of multiple signals in the scan line.
[0061] Furthermore, when the fourth switch M4 is turned on, the output control node Q is connected to the second low-voltage terminal Vss2. That is, the control terminals of the first switch M1 and the second switch M2 are simultaneously connected to the second low-voltage terminal Vss2. This causes the first switch M1 to be turned off under the control of the second low-voltage terminal Vss2, and the second switch M2 to be turned on under the control of the second low-voltage terminal Vss2. This allows the scan signal output terminal Gout(a) to be connected to the first low-voltage terminal Vss1 via the second switch M2 while the first switch M1 stops receiving the clock signal. This enables the scan signal output terminal Gout(a) to stop outputting the scan signal in a very short time and directly transfer the remaining charge to the first low-voltage terminal Vss1. This effectively avoids the decrease in scan signal delay caused by signal transmission delay, which would affect the display effect. Furthermore, a first low-voltage terminal Vss1 and a second low-voltage terminal Vss2 are respectively set. That is, the first switch M1 and the second switch M2 are turned on by the second low-voltage terminal Vss2, and the release of charge at the scan signal output terminal Gout(a) is controlled by the first low-voltage terminal Vss1. This can effectively prevent the charge from affecting the potential of the second low-voltage terminal Vss2 when it is transmitted to the first low-voltage terminal Vss1, thereby affecting the node potential change and causing signal fluctuations at the scan signal output terminal Gout(a) that affect the display effect.
[0062] After the fourth switch M4 is turned on, the output and stop of the scan signal can be realized solely through the internal control of the scan drive unit GDL. There is no need to control the stop of the scan signal through external cascaded signals, which effectively reduces power consumption and the space occupied by the circuit. At the same time, each scan drive unit GDL only requires four switches, which greatly reduces the size of the scan drive unit, thereby effectively reducing the overall size of the scan drive circuit and further reducing the space occupied by the display panel bezel.
[0063] Please see Figure 7 , Figure 7 for Figure 5 Timing diagram of the scanning signal output.
[0064] like Figure 7 As shown, a frame of image display includes a first time period T1, a second time period T2, a third time period T3 and a fourth time period T4. In the first time period T1, the a-4th scan drive unit outputs a scan signal. The output control node Q in the a-4th scan drive unit is pre-charged according to the scan signal output by the a-4th scan drive unit and rises to the second potential V2 due to the first potential V1.
[0065] During the second time period T2, the output control node Q rises from the second potential V2 to the third potential V3. At this time, the first switch M1 is turned on, the clock signal CLK is at a high level, and the scan signal output terminal Gout(a) outputs the scan signal according to the clock signal CLK.
[0066] During the third time period T3, the output control node Q drops from the third potential V3 to the second potential V2, the clock signal CLK drops from high level to low level, and the scan signal output terminal Gout(a) outputs a low-level scan signal according to the decrease of the clock signal.
[0067] In the fourth time period T4, the (a+4)th scan drive unit outputs a scan signal, and the fourth switch M4 in the a-th scan drive unit is turned on, pulling down the potential of the output control node Q to the first potential V1. At this time, the second switch M2 is turned on to connect the scan signal output terminal Gout(a) with the first low voltage terminal Vss1, thereby controlling the scan signal output terminal Gout(a) to stop outputting the scan signal.
[0068] Please see Figure 8 , Figure 8 for Figure 5 Schematic diagram of the first and second switching transistors.
[0069] like Figure 8 As shown, the first switching transistor M1 and the second switching transistor M2 are arranged adjacent to each other and are manufactured in the same process. The control terminal g1 of the first switching transistor is stacked on the substrate u, and the insulating layer in is stacked on the side of the control terminal g1 away from the substrate u. The first conductive terminal s1 and the second conductive terminal d1 of the first switching transistor are stacked on the side of the insulating layer in away from the control terminal g1. The first switching transistor M1 also includes a first active layer a1, which is disposed between the first conductive terminal s1 and the second conductive terminal d1 of the first switching transistor. When a voltage is applied to the control terminal g1 of the first switching transistor, the first conductive terminal s1 and the second conductive terminal d1 of the first switching transistor are connected through the first active layer a1.
[0070] The layer structure of the second switch M2 is the same as that of the first switch M1. The control terminal g2 of the second switch is stacked on the substrate u, and the insulating layer in is stacked on the side of the control terminal g2 away from the substrate u. The first conductive terminal s2 and the second conductive terminal d2 of the second switch are stacked on the side of the insulating layer in away from the control terminal g1. The second switch M2 also includes a second active layer a2, which is disposed between the first conductive terminal s2 and the second conductive terminal d2 of the second switch. When a voltage is applied to the control terminal g2 of the second switch, the first conductive terminal s2 and the second conductive terminal d2 of the second switch are connected via the second active layer a2.
[0071] Among them, the control terminal g1 of the first switch and the control terminal g2 of the second switch are located on the same layer, the first conductive terminal s1 of the first switch and the first conductive terminal s2 of the second switch are located on the same layer, and the second conductive terminal d1 of the first switch and the second conductive terminal d2 of the second switch are located on the same layer.
[0072] Please see Figure 9 , Figure 9 Provided for the second embodiment, as Figure 5 Schematic diagram of the first and second switching transistors.
[0073] like Figure 9 As shown, a first switch transistor M1 and a second switch transistor M2 are stacked sequentially on a substrate u. The first switch transistor M1 and the second switch transistor M2 have a common control terminal structure. The first switch transistor M1 includes a first active layer a1, and the second switch transistor M2 includes a second active layer a2. The first active layer a1, the common control terminal g, and the second active layer a2 are stacked sequentially. An insulating layer in is provided between the first active layer a1 and the common control terminal g, and an insulating layer in is provided between the second active layer a2 and the common control terminal g.
[0074] The first conductive terminal s1 of the first switching transistor M1 is stacked on the insulating layer on the side away from the first active layer a1 and connected to the first active layer a1. The second conductive terminal d1 of the first switching transistor M1 is stacked on the insulating layer on the side away from the first active layer a1 and connected to the first active layer a1. When a second voltage is applied to the common control terminal g, the first conductive terminal s1 and the second conductive terminal d1 of the first switching transistor M1 are turned on through the first active layer a1.
[0075] The first conductive terminal s2 and the second conductive terminal d2 of the second switch transistor M2 are stacked on the side of the insulating layer in away from the common control terminal g, and are respectively located on both sides of the second active layer a2. The first conductive terminal s2 of the second switch transistor M2 is connected to the second conductive terminal of the first switch transistor M1. When a first voltage is applied to the common control terminal g, the first conductive terminal s2 and the second conductive terminal d2 of the second switch transistor M2 are turned on through the second active layer a2.
[0076] By making the first switch M1 and the second switch M2 into a shared control terminal structure, space can be further saved.
[0077] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A scanning drive circuit, comprising n sequentially cascaded scanning drive units, where n is an integer greater than 1, wherein the n scanning drive units are used to sequentially output corresponding scanning signals, and the scanning signals are used to control pixel units to receive data signals for image display and perform image display; Its features are, The a-th scan driving unit includes a pull-up module, a reset module, an output module, a pull-down module, an output control node, and a scan signal output terminal, wherein 1 ≤ a ≤ n. The output module includes only a first switching transistor connected to the output control node and the scan signal output terminal. The pull-down module includes only a second switching transistor connected to the output control node and the scan signal output terminal. The first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor. The pull-up module includes only a third switching transistor connected to the scan signal output terminal and the output control node of the (a-4)-th scan driving unit, used to output the scan signal from the (a-4)-th scan driving unit. Under the control of the signal, the output control node is pulled up from the first potential to the second potential; the reset module includes only a fourth switch, which is connected to the scan signal output terminal of the (a+4)th scan driving unit and the output control node, and is used to pull down the output control node from the second potential to the first potential under the control of the scan signal output by the (a+4)th scan driving unit; when the voltage of the output control node is the first potential, the pull-down module controls the scan signal output terminal to stop outputting the scan signal and maintain it at the first potential; when the voltage of the output control node is the second potential, the output module controls the scan signal output terminal to output the scan signal, and the second potential is greater than the first potential.
2. The scanning drive circuit as described in claim 1, characterized in that, The output module is also connected to the clock signal terminal, and the pull-down module is also connected to the first low-voltage terminal. When the output control node is at the first potential, the output module stops controlling the scan signal output terminal to output the scan signal according to the clock signal output by the clock signal terminal. At the same time, the pull-down module controls the scan signal output terminal to connect to the first low-voltage terminal so as to transfer the charge in the scan signal output terminal to the first low-voltage terminal.
3. The scanning drive circuit as described in claim 2, characterized in that, The first switching transistor includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the first switching transistor is connected to the output control node. The first conductive terminal of the first switching transistor is connected to the clock signal terminal. The second conductive terminal of the first switching transistor is connected to the scan signal output terminal. The first switching transistor is turned on when the output control node is at the second potential. The clock signal is transmitted to the scan signal output terminal through the first conductive terminal and the second conductive terminal and is output as the scan signal.
4. The scanning drive circuit as described in claim 3, characterized in that, The second switch includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the second switch is connected to the output control node, the first conductive terminal of the second switch is connected to the scan signal output terminal, and the second conductive terminal of the second switch is connected to the first low-voltage terminal. The second switch is used to turn on when the output control node is at the first potential, so as to connect the scan signal output terminal to the first low-voltage terminal.
5. The scanning drive circuit as described in claim 4, characterized in that, The first switch and the second switch are disposed on the same substrate and are adjacent to each other. The control terminal of the first switch is disposed on the surface of the substrate. The first conductive terminal and the second conductive terminal of the first switch are stacked in the same layer on the side of the first switch away from the control terminal of the substrate. The control terminal of the second switch is stacked on the substrate, and the first conductive terminal and the second conductive terminal of the second switch are stacked in the same layer on the side of the control terminal of the second switch away from the substrate. The control terminal of the first switch transistor and the control terminal of the second switch transistor are located on the same layer, and the first conductive terminal and the second conductive terminal of the first switch transistor are located on the same layer as the first conductive terminal and the second conductive terminal of the second switch transistor.
6. The scanning drive circuit as described in claim 4, characterized in that, The first switch and the second switch are stacked on a substrate in sequence. The first switch and the second switch share the same control terminal. The first switch includes a first active layer and the second switch includes a second active layer. The first active layer, the common control terminal and the second active layer are stacked on the substrate in sequence. An insulating layer is provided between the first active layer and the common control terminal and between the second active layer and the common control terminal. The first conductive terminal of the first switching transistor is stacked on the insulating layer on the side away from the first active layer and connected to the first active layer; the second conductive terminal of the first switching transistor is stacked on the insulating layer on the side away from the first active layer and connected to the first active layer. The first conductive terminal and the second conductive terminal of the second switching transistor are stacked on the side of the insulating layer away from the common control terminal, and are respectively located on both sides of the second active layer. The first conductive terminal of the second switching transistor and the second conductive terminal of the first switching transistor are located on the same layer, and the first conductive terminal of the second switching transistor is connected to the second conductive terminal of the first switching transistor.
7. The scanning drive circuit as described in any one of claims 1-6, characterized in that, The pull-up module includes a third switch transistor, and the reset module includes a fourth switch transistor. The third switch transistor includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal and the first conductive terminal of the third switch transistor are connected to the scan signal output terminal of the (a-4)th scan driving unit, and the second conductive terminal of the third switch transistor is connected to the output control node. It is used to turn on under the control of the scan signal output by the (a-4)th scan driving unit to pull the output control node up to the second potential. The fourth switch includes a control terminal, a first conductive terminal, and a second conductive terminal. The control terminal of the fourth switch is connected to the scan signal output terminal of the (a+4)th scan driving unit. The first conductive terminal of the fourth switch is connected to the output control node, and the second conductive terminal of the fourth switch is connected to the second low-voltage terminal. It is used to turn on under the control of the scan signal output by the (a+4)th scan driving unit, control the output control node to connect to the second low-voltage terminal, and pull down the output control node to the first potential.
8. A display panel, characterized in that, The device includes multiple data lines, multiple scan lines, multiple pixel units arranged in a matrix, a data driving circuit disposed in a non-display area, and a scan driving circuit as described in any one of claims 1-7. The scan driving circuit is used to output scan signals to the pixel units through the scan lines and to control the pixel units to receive data signals output by the data driving circuit from the data lines for image display.