Method and apparatus for carrying constant bit rate (CBR) client signals

Abstract

A method and apparatus in which a data stream, a cumulative phase shift report (CPOR), and a client rate report (CRR) generated by a previous network node are received. A counter that accumulates a PHY-calibrated stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-calibrated count (CPSC). A PHY-calibrated stream phase offset (PSPO) is calculated, the PSPO indicating the phase difference between a PHY-calibrated stream nominal bit count (LPSD) and an incoming PHY-calibrated count Δ (IPSD), wherein the IPSD indicates a CPSC increment between consecutive CPSC samples. The data stream is demultiplexed to obtain a CBR carrier stream, the CBR carrier stream comprising a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated as a function of the CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier stream is multiplexed into an intermediate network node data stream sent from the intermediate network node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 282,292 filed on November 23, 2021 and U.S. Non-Provisional Patent Application Serial No. 17 / 885,194 filed on August 10, 2022, the contents of each of which are incorporated herein by reference in their entirety. Background Art

[0003] There are three main categories of methods for delivering constant bit rate (CBR) clients over a cell / packet transport network. The first category of methods is fully adaptive, where the sink node monitors the arrival rate of the cell / packet carrying the CBR clients and adjusts its transmit phase-locked loop (TxPLL) to speed up or slow down accordingly. The sink node often implements a FIFO buffer to hold the CBR clients and uses its depth to control the transmit phase-locked loop. This scheme is susceptible to delay variations encountered by CBR clients in the transport network. For example, a reduction in delay will appear as a faster arrival rate to the sink node, and therefore the transmit phase-locked loop may spuriously speed up.

[0004] In the second class of methods, the source node inserts a timestamp based on the arrival time of certain key bits of the CBR client. The timestamp and the CBR client data are bundled into the carrier stream. The bit rate of the CBR client is calculated by dividing the number of CBR client bits between consecutive timestamps by the change in the timestamp value. This approach is exemplified by IETF RFC 4553 SAToP, which requires the source node and the sink node to share a common clock reference. However, the need for a common clock reference at the source node and the sink node increases the deployment cost of the transport network. In addition, in some cases it is not feasible to add a common clock reference.

[0005] The third type of method, illustrated by the International Telecommunication Union (ITU) General Mapping Procedure (GMP), introduces low jitter and drift into the CBR client and does not require a common reference clock. It involves periodically inserting client rate reports (such as GMP overhead) into the carrier stream of the CBR client at the source node. At the input of the intermediate switching node, the rate report is processed to recover the bit rate of each CBR client. At the output of the intermediate node, the bit rate of the corresponding CBR client in the CBR client is re-encoded into a new rate report related to the bit rate of the outlet carrier stream of the intermediate node. When the number of CBR clients at the intermediate node is very large, this solution may be expensive and complicated to implement because the corresponding CBR client in the CBR client requires its own rate reporting digital signal processor (DSP) engine.

[0006] Therefore, there is a need for methods and apparatus that will allow CBR client signals to be communicated without the need to process and regenerate new rate reports for corresponding ones of the CBR clients at the intermediate nodes.Furthermore, there is a need for methods and apparatus that do not require the source node and sink node to share a common reference clock. Summary of the invention

[0007] A method is disclosed, the method comprising receiving a corresponding data stream generated by a previous network node at a corresponding intermediate network node among a plurality of intermediate network nodes. The corresponding data stream comprises a constant bit rate (CBR) carrier stream corresponding to a constant bit rate (CBR) signal received at a source node. A counter that accumulates a PHY-calibrated stream clock (IPSCk) is sampled at a nominal sampling period (Tps) of a local reference clock of the intermediate network node to obtain a cumulative PHY-calibrated count (CPSC) of the received corresponding data stream. IPSCk is generated by calibrating a clock recovered from the received corresponding data stream to a predetermined nominal frequency (Fipsck_nom). The method comprises calculating a PHY-calibrated stream phase offset (PSPO), the PSPO indicating a phase difference between a PHY-calibrated stream nominal bit count (LPSD) and an incoming PHY-calibrated count Δ (IPSD), wherein the IPSD represents an increment between consecutive CPSCs.

[0008] The received corresponding data stream is demultiplexed to obtain a CBR carrier stream. The corresponding CBR carrier stream in the CBR carrier stream includes a previous network node cumulative phase offset report (CPOR-P) indicating a previous network node cumulative phase offset (CPO-P) and a client rate report (CRR) indicating the measured bit count of the corresponding CBR client at the source node. The cumulative phase offset (CPO) of the corresponding CBR carrier stream in the CBR carrier stream is calculated. The calculated CPO is a function of the CPO-P of the corresponding CBR carrier stream and the calculated PSPO. The CPO-P in the corresponding CBR carrier stream in the CBR carrier stream is replaced with the calculated CPO of the corresponding CBR carrier stream or a function of the calculated CPO of the corresponding CBR carrier stream to generate an updated cumulative phase offset report (CPOR) to replace the CPOR-P in the corresponding CBR carrier stream. The corresponding CBR carrier stream is multiplexed into an intermediate network node data stream. The intermediate network node data stream is then sent from a specific intermediate network node.

[0009] An integrated circuit (IC) device includes a PHY link input for receiving a data stream generated by a previous network node, the data stream including a plurality of CBR carrier streams, a corresponding CBR carrier stream of the CBR carrier streams including a CPOR-P indicating a CPO-P and a CRR indicating a measured bit count of the corresponding CBR client at a source node. A clock offset circuit is coupled to the PHY link input to sample a counter accumulating IPSCk with a Tps of a local reference clock of an intermediate network node to obtain a CPSC of the corresponding received data stream, the IPSCk being generated by scaling a clock recovered from the corresponding received data stream to Fipsck_nom; and to calculate a PSPO indicating a phase difference between an LPSD and an IPSD, wherein the IPSD indicates a CPSC increment between consecutive CPSC samples. A demultiplexer is coupled to the PHY link input to demultiplex the received data stream to obtain the plurality of CBR carrier streams. Cumulative phase offset report (CPOR) update logic is coupled to the demultiplexer and the clock offset circuit to calculate the CPO of a corresponding CBR carrier stream in the CBR carrier stream, wherein the calculated CPO is a function of the CPO-P and the calculated PSPO; and to replace the CPO-P with the calculated CPO of the corresponding CBR carrier stream, or with a function of the calculated CPO of the corresponding CBR carrier stream; and to generate an updated CPOR of the corresponding CBR carrier stream to replace the CPOR-P in the corresponding CBR carrier stream. A multiplexer is coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams. An encoder is coupled to the multiplexer to encode the plurality of intermediate network node data streams. A PHY link output is coupled to the encoder to send the plurality of intermediate network node data streams from the IC device.

[0010] A network includes a source node, which includes: an input end, the input end is used to receive multiple CBR signals; a CPOR generating circuit, the CPOR generating circuit is used to generate a CPOR indicating an initial CPO; a CRR generating circuit, the CRR generating circuit is used to generate a CRR indicating a measured bit rate of a corresponding CBR client; a CBR mapper, the CBR mapper is coupled to the input end to generate a corresponding CBR carrier stream for a corresponding CBR signal in the CBR signal and insert the CRR and CBR client data into the corresponding CBR carrier stream; and a source output processing circuit, the source output processing circuit is used to insert the CPOR into the corresponding CBR carrier stream and multiplex the CBR carrier stream to generate multiple source data streams.

[0011] The network includes multiple intermediate network nodes, which are coupled to the source node. The corresponding intermediate network nodes among the intermediate network nodes include an IC device, which includes: a PHY link input end, which is used to receive a data stream generated by a previous network node, and the data stream includes multiple CBR carrier streams. The corresponding CBR carrier stream among the CBR carrier streams includes CRR and CPOR-P indicating CPO-P.

[0012] These intermediate network nodes include a clock offset circuit coupled to the PHY link input so as to: sample a counter accumulating IPSCk with Tps of a local reference clock of the intermediate network node to obtain the CPSC of the corresponding received data stream, wherein the IPSCk is generated by calibrating a clock recovered from the corresponding received data stream to Fipsck_nom; and calculate a PHY-calibrated stream phase offset (PSPO), wherein the PSPO indicates a phase difference between LPSD and IPSD, wherein the IPSD indicates an increment between consecutive CPSCs.

[0013] The intermediate network nodes include a demultiplexer coupled to the PHY link input to demultiplex the received data stream to obtain individual CBR carrier streams; and a CPOR update logic coupled to the demultiplexer and the clock offset circuit. The CPOR update logic is used to calculate the CPO of a corresponding CBR carrier stream in the CBR carrier streams, wherein the calculated CPO is a function of the CPO-P of the particular CBR carrier stream and the calculated PSPO; and to replace the CPO-P of the particular CBR carrier stream with the calculated CPO of the corresponding CBR carrier stream to generate an updated CPOR of the corresponding CBR carrier stream to replace the CPOR-P of the particular CBR carrier stream.

[0014] The intermediate network node includes: a multiplexer coupled to a demultiplexer and CPOR update logic to multiplex a CBR carrier stream into a plurality of intermediate network node data streams; an encoder coupled to the multiplexer to encode the plurality of intermediate network node data streams; and a PHY link output coupled to the encoder to send the plurality of intermediate network node data streams from the IC device.

[0015] The network includes a convergence node coupled to a last intermediate network node among the intermediate network nodes to receive an intermediate network node data stream from the last intermediate network node among the intermediate network nodes, recover a CBR client signal, and output a CBR signal including the recovered CBR client signal from the convergence node.

[0016] The disclosed method and apparatus allow CBR client signals to be communicated without the need to process and regenerate new rate reports for corresponding ones of the CBR clients at intermediate network nodes. Furthermore, the method and apparatus of the present invention do not require source nodes and sink nodes to share a common reference clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate various examples. The drawings referred to in this brief description are not drawn to scale.

[0018] Figure 1 is a diagram illustrating a network including a source node, a sink node, and a plurality of intermediate network nodes.

[0019] Figure 2 is a diagram showing a circuit of a source node.

[0020] Figure 3 is a block diagram showing CPOR.

[0021] Figure 4 is a block diagram showing the data flow.

[0022] Figure 5 It is shown Figure 1 Block diagram of an intermediate network node switch in a network.

[0023] Figure 6 It is shown Figure 5 A diagram of an IC device (switch) of an intermediate network node switch is shown.

[0024] Figure 7 is a diagram showing an example of CPOR update logic that calculates CPO by adding CPO-P to the calculated PSPO.

[0025] Figure 8 is a diagram illustrating an example of CPOR update logic for calculating a CPO, where the calculated CPO is a function of all CPO-Ps received by the intermediate network node since the last initialization of the intermediate network node and all PSPOs calculated by the intermediate network node since the last initialization of the intermediate network node.

[0026] Fig. 9 is a diagram showing the circuitry of a sink node.

[0027] Fig. 10A is a flow chart illustrating a method for coupling a CBR signal over a network.

[0028] FIG. 10B to FIG. 10I is shown for execution Fig. 10A A block diagram of an example of parts of the method. DETAILED DESCRIPTION

[0029] Figure 1 An example of a network 4 is shown, which includes a source node 1, a sink node 2 and a plurality of intermediate network nodes 3 (in Figure 1 3a, the second intermediate network node 3b and the last intermediate network node 3c), which are logically extended between the source node 1 and the sink node 2 to couple the source node 1 to the sink node 2. The corresponding intermediate network nodes can be implemented as switches. The relative parts per million frequency offset (RPPM) (RPPMpath) between the reference clocks of the source node and the sink node can be represented by the following equation:

[0030] RPPMpath=RPPMsw1+RPPMsw2+...RPPMswn+RPPMsk

[0031] Wherein RPPMsw1 is the RPPM between the reference clock of the intermediate network node 3a and the source node 1 and is measured at the first intermediate network node 3a, RPPMsw2 is the RPPM between the intermediate network node 3b and the reference clock of the intermediate network node 3a and is measured at the second intermediate network node 3b, RPPMswn is the RPPM between the intermediate network node 3c and the reference clock of its upstream node and is measured at the nth intermediate network node 3c, and RPPMsk is the RPPM between the reference clock of the immediately previous intermediate network node (e.g., the intermediate network node 3c) and the aggregation node 2, measured at the aggregation node 2.

[0032] Figure 2 An exemplary source node 1 is shown, which includes a local reference clock 20, a reference clock input terminal 27, a plurality of CBR processing circuits 29a to 29c, a source output processing circuit 22 including a transmit PLL 28, a CBR signal input terminal 30, and a PHY link output terminal 7. A respective CBR processing circuit among the CBR processing circuits 29a to 29c includes a CRR timer circuit 23, a CRR generation circuit 24, a CPOR timer circuit 25, a CPOR generation circuit 26, and a CBR mapper 21. The CRR generation circuit 24 can be implemented using a digital signal processor (DSP).

[0033] A corresponding CPOR processing circuit among the CPOR processing circuits 29a to 29c is coupled to the reference clock input terminal 27, a corresponding CBR signal input terminal 30 for receiving a corresponding CBR signal (e.g., CBR signals 30a, 30b, 30c), and the source output processing circuit 22. The CRR generation circuit 24 is coupled to the CRR timer circuit 23 and the CBR mapper 21. The CPOR generation circuit 26 is coupled to the CPOR timer circuit 25 and the source output processing circuit 22. A corresponding CBR mapper among the CBR mappers 21 is coupled to a corresponding CBR signal input terminal (e.g., one of the CBR signal input terminals 30) and the source output processing circuit 22. The source output processing circuit 22 is coupled to the PHY link output terminal 7.

[0034] The reference clock input terminal 27 is coupled to the local reference clock 20 of the source node 1 to supply a reference clock signal 27 a to the CRR timer circuit 23 of the corresponding CBR processing circuit 29 , the CPOR timer circuit 25 of the corresponding CBR processing circuit 29 , and the transmit phase locked loop 28 .

[0035] The CPOR timer circuit 25 receives the reference clock signal 27a at the reference clock input terminal 27 and generates a timing signal Tcpor. The CPOR generation circuit 26 receives the timing signal Tcpor and generates a CPOR in response to the received timing signal Tcpor. The CRR timer circuit 23 receives the reference clock signal 27a and generates a timing signal Tcrr. The CRR generation circuit 24 receives the corresponding CBR signals 30a to 30c at the corresponding CBR signal input terminal 30 and uses the received CBR signals 30a to 30c and the received timing signal Tcrr to generate a CRR indicating the measured clock rate of the corresponding CBR client. The generation cycles of the CRR (in response to the timing signal Tcrr) and the CPOR (in response to the timing signal Tcpor) can be independent.

[0036] Figure 3 An example of a CPOR 40 generated by a CPOR generation circuit 26 including a CPOR header 31 and a CPO 5 is shown. The term "CPO" as used in the present application is one or more values ​​or words indicating a cumulative phase offset. In the present example, it is a single numerical value indicated by the number of bits, bytes or words of the phase offset. The term "CPOR" as used in the present application is a sequence of characters indicating a CPO. The CPO output by the CPOR generation circuit 26 may be referred to as an "initial CPO". In the present example, the initial CPO is not calculated at the source node, but is set to a predetermined value, such as "0", in response to the received timing signal Tcpor.

[0037] Figure 2The CBR mapper 21 receives the corresponding CBR signals 30a to 30c and the CRR from the CRR generating circuit 24, and generates the corresponding CBR carrier stream coupled to the source output processing circuit 22. The CBR mapper 21 formats the CBR client data into a CBR carrier stream using the information in the CRR, and inserts the CRR and the CBR client data into the corresponding CBR carrier stream. The source output processing circuit 22 inserts the CPOR into the corresponding CBR carrier stream, and multiplexes the CBR carrier stream to generate a plurality of source data streams 7a to 7d outputted through the PHY link output terminal 7, respectively. The transmit phase-locked loop (PLL) 28 receives the reference clock signal 27a as input, and generates a timing signal for controlling the timing of the output of the source data streams 7a to 7d. The PHY link output terminal 7 is phase-locked to the local reference clock 20 by the transmit PLL 28.

[0038] Figure 4 An example of a data flow cell or packet 6 including a cell / packet overhead 32, a carrier overhead 33, a CPOR overhead 34, a CRR overhead 35, and a CBR client payload 36 is shown. The CRR overhead 35 is composed of the CRR generated by the CRR generation circuit 24 (e.g., the CRR generated for a specific data flow). Figure 2 When the source data stream 7a to 7d of the packet 6 leaves, the CPOR overhead 34 is composed of the CPOR 40 generated by the CPOR generation circuit 26, so that the CRR and CPOR are carried in-band in the output source data stream 7a to 7d together with the CBR client payload. In this example, in order to be robust to burst errors, the CRR and CPOR in the data stream cell or packet 6 can be distributed over multiple cells / packets.

[0039] Figure 5 An exemplary intermediate network node 3 is shown including an integrated circuit (IC) device 10 and a local reference clock 37. The IC device 10 is coupled to the local reference clock 37 via a reference clock input 39 and includes a PHY link input 8 and a PHY link output 9. The IC device 10 may implement a switch, and in that example, the intermediate network node 3 may be an intermediate network node switch. The local reference clock 37 of the intermediate network node 3 does not need to be phase-locked to the local reference clocks of other intermediate network nodes 3, the local reference clock 20 of the source node 1, or the local reference clock 39a-1 of the sink node.

[0040] Figure 6An example of an IC device 10 (e.g., a "switch") is shown, which includes a reference clock input 39, a PHY link input 8 for receiving a corresponding data stream, a clock offset circuit 11, a demultiplexer 12, a multiplexer 13, a CPOR update logic 14, FIFO registers 52a to 52f, other intermediate network node circuits 53, an encoder 15, and a PHY link output 9. The clock offset circuit 11 is coupled to the CPOR update logic 14, the reference clock input 39, and the PHY link input 8. The demultiplexer 12 is coupled to the PHY link input 8 and the CPOR update logic 14. The CPOR update logic 14 is coupled to first-in-first-out (FIFO) registers 52a to 52c such that a corresponding one of the CBR carrier streams is coupled to a corresponding one of the FIFOs 52a to 52c. More specifically, a first CBR carrier stream 50a is coupled to a FIFO 52a, a second CBR carrier stream 50b is coupled to a FIFO 52b, and a third CBR carrier stream 50c is coupled to a FIFO 52c, it being understood that there may be n CBR carrier streams with n corresponding FIFOs. The multiplexer 13 includes one or more transmit PLLs 16 and is coupled to the FIFOs 52a to 52f and the encoder 15. A corresponding one of the encoders 15 is coupled to a corresponding one of the PHY link outputs 9. The transmit PLL 16 receives a local reference clock signal 39a as an input at a reference clock input 39 and generates a timing signal that controls the timing of the output of the intermediate network node (INN) data streams 9a to 9d. The clock offset circuit 11 includes a sampling pulse generator 41, an accumulation phase counter circuit 42, a clock recovery circuit 43, a clock scaler circuit 44, a current count register 45, a previous count register 46, a first subtraction logic 48, a second subtraction logic 49, and an LPSD register 47. The sampling pulse generator 41 is coupled to the reference clock input terminal 39 and the accumulation phase counter circuit 42. The clock recovery circuit 43 is coupled to the corresponding PHY link input terminal 8 and the clock scaler circuit 44. The accumulation phase counter circuit 42 is coupled to the current count register 45 and the clock scaler circuit 44. The current count register 45 is coupled to the previous count register 46. The first subtraction logic 48 is coupled to the current count register 45, the previous count register 46, and the second subtraction logic 49. The second subtraction logic 49 is coupled to the LPSD register 47 and the CPOR update logic 14. The first subtraction logic 48 and the second subtraction logic 49 may be implemented as corresponding subtraction circuits.

[0041] In this example, IC device 10 is formed on a single integrated circuit die and does not include a corresponding DSP engine for each CBR client. PHY link input 8, clock offset circuit 11, demultiplexer 12, CPOR update logic 14, encoder 15 and PHY link output 9 can be provided in a single integrated circuit die.

[0042] The circuit for demultiplexing and updating the CPOR of the data stream received at the first PHY link input 8 is Figure 6 The other intermediate network node circuits 53 may include identical circuits 54 for demultiplexing and updating the CPORs of the data streams 8b to 8d received at the other PHY link inputs 8, and for coupling the other carrier streams with updated CPORs to the respective FIFOs 52d to 52f.

[0043] A corresponding one of the PHY link inputs 8 (e.g., each PHY link input) receives a data stream generated by a previous network node, which are shown as data streams 8a to 8d (e.g., one of the source data streams 7a to 7d or an INN data stream 9a to 9d from a previous intermediate network node). The sampling pulse generator 41 receives a local reference clock signal 39a at the reference clock input 39 and generates sampling pulses with a sampling period Tps using the local reference clock signal 39a. The nominal period of the sampling pulses is constant across all nodes in the network 4, wherein the actual deviation of the period depends on the actual ppm offset of the corresponding local reference clock signal 39a. The sampling period (i.e., Tps) of the cumulative phase counter circuit 42 is selected to be greater than Figure 2 In one example, Tps>2*Tcpor.

[0044] The clock recovery circuit 43 receives the data stream 8a from the previous network node at the corresponding PHY link input terminal 8 and recovers the PHY link clock signal (i.e., the clock of the data stream 8a). The recovered PHY link clock signal (Rclk) is output to the clock scaler circuit 44. The data bit sequence in the data stream 8a received at the clock recovery circuit 43 is irrelevant to the operation of the clock offset circuit 11 and can be discarded at the clock offset circuit 11.

[0045] The clock calibrator circuit 44 calibrates Rclk to generate a PHY-calibrated stream clock (IPSCk). In one example, the nominal clock rate of the PHY link (PHYck-nom) is used to determine the calibration factor. The term "nominal clock rate of the PHY link" as used in this application is a certain value, and can be a value indicating the clock rate (i.e., the bit rate at which the PHY link input terminal 8 is designed to operate), or a value indicating that the PHY link (not shown) coupled to the PHY link input terminal 8 is designed to operate at a rate such as 10 Gbit / second or 25 Gbit / second. In one example, the calibration factor in 44 is set to (PHYck-nom / Fipsck_nom), where Fipsck_nom is a predetermined nominal frequency. Therefore, the rate of IPSCk = Rclk*(Fipsck_nom / PHYck-nom). Therefore, the nominal clock rate of IPSCk is constant throughout the entire network 4 (all intermediate network nodes and aggregation nodes). Fipsck_nom is a constant defined across all nodes in the transport network and is selected to provide a simple scalar ratio between the PHY link clock rates in the network 4. For example, Fipsck_nom in the network 4 can be set to 1.0 MHz or 10 MHz. In one example, Fipsck_nom represents the nominal rate of IPSCk and is the nominal clock frequency of all "PHY-calibrated stream clocks" in the network, where the clock recovery circuit 43 and the clock calibrator circuit 44 of each clock offset circuit 11 in the network 4 are considered to constitute the "PHY-calibrated stream clock" of the network, but are not limited to this. In one example, a value of 1 MHz is used as Fipsck_nom to perform calibration in all intermediate network nodes of the network and in the aggregation node. In this example, Rclk is divided by the calibration factor in 44 to generate IPSCk. It should be understood that the current use of 1 MHz as the nominal Fipsck_nom is only a single example, and other values ​​may also be used.

[0046] The counter of the cumulative phase counter circuit 42 that accumulates IPSCk (i.e., the cumulative phase counter) is sampled by the cumulative phase counter circuit 42 based on the local reference clock signal 39a provided by the local reference clock 37 with a period Tps to obtain the CPSC of the corresponding data stream received. In one example, the cumulative phase counter circuit 42 accumulates the edge of IPSCk into the free-running counter to generate the CPSC. Logically, the counter can reach infinity. In this example, the counter of the cumulative phase counter circuit 42 is sampled at each pulse (once per Tps) received from the sampling pulse generator 41 to obtain the CPSC of the corresponding data stream received. In one example, the cumulative phase counter circuit 42 is incremented by 1 at each IPSCk clock edge, and the value of the counter in the cumulative phase counter circuit 44 is sampled once per Tps to identify the current bit count including the CPSC. The current CPSC output by the cumulative phase counter circuit 42 at Tps is stored in the current count register 45. When a new CPSC is output in response to the next pulse from the sampling pulse generator 41 (i.e., after Tps), the previous CPSC is stored in the previous count register 46 (e.g., by moving the CPSC stored in the current count register 45 to the previous count register 46) before the new CPSC is stored in the current count register 45. Thus, the current CPSC and the previous CPSC output from the accumulation phase counter circuit 42 are stored in the registers 45 to 46.

[0047] In one example, the counter in the accumulating phase counter circuit 42 is not cleared. It is sampled only at Tps instances. The previous sample value is subtracted from the current sample value to produce an effect similar to clearing at every Tps, but it is not sensitive to the clear signal closely aligned with IPSCk, which causes the counter to increment.

[0048] In this example, the CPSC generated by the cumulative phase counter circuit 42 uses bits (bit counts) to indicate the phase. A bit (bit count) is a convenient unit of measurement, wherein the amount of phase transmitted by the upstream node is a monotonically rising value that reaches infinity in bits, bytes, or radians without limitation. In alternative embodiments, the cumulative phase counter circuit 42 can use bytes, radians, or other measurements to identify the actual delivery of the phase relative to Tps as determined by the local reference clock signal 39a. In alternative examples, a bit rate can be used. However, this may involve one or more division steps, and therefore may not be as effective as staying in the count domain.

[0049] The clock offset circuit 11 calculates a PSPO that indicates the phase difference between a PHY-calibrated stream nominal bit count (LPSD) and an incoming PHY-calibrated count Δ (IPSD). The term "PHY-calibrated stream nominal bit count" (which may also be referred to as "local PHY stream Δ" or "LPSD") as used in this application is a value that indicates a local constant increment of a phase count over a period of time and may be a function of Tps and Fipsck_Bom. LPSD represents the amount of expected increment at an intermediate network node based on Fipsck_nom and Tps. In this example, the LPSD as a function of Fipsck_nom and Tps is stored in the LPSD register 47. In one example, the LPSD is calculated from the product of Fipsck_nom and Tps using the following equation: LPSD=Fipsck_nom*Tps. As described above, the LPSD is stored in the LPSD register 47. Logically, Figure 2 The Tcrr can be expressed in terms of the number of PHY scaled stream bits (Ncrr) using the relationship Ncrr=Tcrr*Fipsck_nom.

[0050] The first subtraction logic 48 subtracts the previous CPSC in register 46 from the current CPSC in register 45 to obtain IPSD. Since IPSD represents the CPSC increment between consecutive CPSCs sampled by the cumulative phase counter circuit 42 (i.e., indicates the increment of the CPSC count within the Tps period), it indicates the increment of the accumulated phase (bit count) within Tps.

[0051] The second subtraction logic 49 subtracts the LPSD from the IPSD to calculate the PHY scaled stream phase offset (PSPO). Therefore, PSPO = (IPSD - LPSD), so that PSPO captures the relative parts per million (PPM) offset (RPPM) between the reference clock at the upstream node used to generate the data stream 8a and the local reference clock 37, the RPPM being encoded in units of phase. Using units of phase is preferred over units of frequency because the phase allows the sink node to be more easily phase locked to the source node. Using units of frequency will only allow frequency locking.

[0052] In one example, given IPSCk = Rclk*(1,000,000 / 10,000,000,000) = Rclk / 10,000 and LPSD = 1,000,000*Tps sampled at Tps, the PHY link is a 10Gbit / s link such that its clock rate is nominally 10,000,000,000 cycles / second, and Fipsck_nom is 1 MHz. The resulting PSPO will therefore capture the difference between what is expected (LPSD) and what is calculated / measured (IPSD) in units of phase.

[0053] The demultiplexer 12 demultiplexes the received data stream 8a to obtain individual CBR carrier streams 50a to 50c, and outputs a first CBR carrier stream 50a at a corresponding demultiplexer output 50 coupled to the CPOR update logic 14, outputs a second CBR carrier stream 50b at a corresponding demultiplexer output 50 coupled to the CPOR update logic 14, and so on to a third CBR carrier stream 50c output at a corresponding demultiplexer output 50 coupled to the CPOR update logic 14. Although three CBR carrier stream outputs are shown, n CBR carrier streams may be output at n corresponding demultiplexer outputs 50.

[0054] A corresponding CBR carrier stream among the CBR carrier streams 50a to 50c (e.g., each CBR carrier stream among the CBR carrier streams 50a to 50c) includes a CRR indicating a measured bit count of a corresponding CBR client at a source node and a CPOR-P indicating a CPO-P (i.e., a CPO of a previous node). A CPO of a corresponding CBR carrier stream among the CBR carrier streams (e.g., each CBR carrier stream among the CBR carrier streams 50a to 50c) is calculated, and the CPO-P of the corresponding CBR carrier stream among the CBR carrier streams 50a to 50c is replaced with the calculated CPO of the corresponding CBR carrier stream, wherein the calculated CPO is a function of the CPO-P of the specific carrier stream and the calculated PSPO.

[0055] exist Figure 7, an example of CPOR update logic 14 is shown as CPOR update logic 14a, which includes a CPOR-P register 55, a PSPO register 95 (e.g., a self-clearing register), an adder circuit 57, a CPO replacement logic 58, and an output terminal 59 coupled to a corresponding FIFO in FIFOs 52a to 52c. The CPOR-P register 55 is coupled to the demultiplexer output terminal 50, which carries the corresponding CBR carrier stream. The adder circuit 57 is coupled to the CPOR-P register 55 and the PSPO register 95. The PSPO register 95 is coupled to the clock offset circuit 11 ( Figure 6 ), where the CPOR update logic input 56 is coupled to the second subtraction logic 49. The CPO replacement logic 58 is coupled to the PSPO register 95, the output of the adder circuit 57, and the output 59 coupled to the corresponding FIFO in the FIFOs 52a to 52c. In one example, the CPO replacement logic 58 indicates that the CPO has been replaced using the CPRO_Updated signal to trigger the PSPO register 95 to be cleared to a value of 0.

[0056] by Figure 7 Continuing, a CPOR-P indicating a CPO-P is received at the CPOR-P register 55. The adder circuit 57 obtains the calculated PSPO from the PSPO register 95 and calculates the CPO of the corresponding CBR carrier stream in the CBR carrier stream by adding the calculated PSPO to the CPO-P of the corresponding CBR carrier stream. The CPOR update logic 14a replaces the CPO-P in the CPOR-P with the calculated CPO of the corresponding CBR carrier stream to generate an updated CPOR for the corresponding CBR carrier stream, which is output to the corresponding FIFOs 52a to 52f. When the CPOR-P is replaced with the calculated CPO, the PSPO register 55 is reset to a value of "0". In this example, there is a single PSPO calculated from the PHY link, and the calculated PSPO is shared by all CBR carriers demultiplexed from a particular PHY link. Alternatively, CPO-P is replaced by a function of the calculated CPO, such as an offset relative to the calculated CPO or an encoding of the calculated CPO.

[0057] exist Figure 7In the example shown, the source node 1 generates a CPOR placeholder, and the corresponding intermediate node in the intermediate nodes updates the CPOR by adding the calculated PSPO indicating the "phase Δ" (e.g., relative phase change) of the PHY-calibrated logical flow derived from the ingress PHY link to what the node expects to see using its own local reference clock signal 39a (i.e., LPSD). The PSPO (e.g., "phase Δ") can be positive or negative, such as +3, -7, +6, but is not limited to this. Whatever the value, the node adds the value to the received CPOR 40 embedded in the corresponding CBR carrier stream by adding the calculated PSPO to the CPO-P and replacing the CPOR 40 with the resulting value. If the PSPO is negative, the addition will result in the calculated CPO in the output CPOR being less than the CPO-P from the previous network node. If the calculated PSPO is positive, the addition will result in the calculated CPO in the output CPOR being greater than the CPO-P from the previous network node. In any case, the CPOR update has the effect of accumulating the PSPO (e.g., "phase delta") as it traverses the network. It is possible for the CPOR to be lost in transit. If this happens, the sink will lose a set of phase deltas from the intermediate nodes between the source and the sink. Figure 8 The method and apparatus shown in are intended to solve this problem.

[0058] exist Figure 8 In the alternative example shown, the calculated CPO is a function of all CPO-Ps received by the intermediate network node 3 since the last initialization of the intermediate network node 3 and a function of all PSPOs calculated by the intermediate network node 3 since the last initialization of the intermediate network node 3. In this example, the CPOR update logic 14b is shown to include a CPOR-P register 55, an accumulator 60, a previous CPOR-P register 61, a subtraction logic 62, an accumulator 63, an adder logic 64, a CPO replacement logic 58, and an output 59 coupled to a corresponding FIFO in the FIFOs 52a to 52c. The subtraction logic 62 can be implemented by a subtraction circuit, and the adder logic 64 can be implemented by an adder circuit. The CPOR-P register 55 is coupled to the demultiplexer output 50 and the previous CPOR-P register 61, which carries the corresponding CBR carrier stream. The subtraction logic 62 is coupled to the CPOR-P register 55, the previous CPOR-P register 61, and the accumulator 63. Adder logic 64 is coupled to accumulator 63, accumulator 60 and CPO replacement logic 58. Accumulator 60 is coupled to clock offset circuit 11 ( Figure 6 ). CPO replacement logic 58 is coupled to the demultiplexer output 50 and to an output 59 of a corresponding one of the FIFOs 52a to 52c.

[0059] The CPOR update logic 14b receives the CPOR-P from the corresponding CBR carrier stream at the CPOR-P register 55. When the next CPOR-P is received, the previous CPOR-P moves to the previous CPOR-P register 61, becomes the "previous CPOR-P", and the received CPOR-P is stored in the CPOR-P register 55. The subtraction logic 62 subtracts the CPO-P in the previous CPOR-P stored in the previous CPOR-P register 61 from the current CPO-P in the CPOR-P register 55 to obtain a delta cumulative phase offset (D-CPO). The accumulator 63 calculates an accumulated delta cumulative phase offset (ADCPO) by accumulating all D-CPOs calculated by the particular intermediate network node since the last initialization of the particular intermediate network node. The accumulator 60 calculates an accumulated PSPO (APSPO) by accumulating all calculated PSPOs received at the input terminal 56 since the last initialization of the particular intermediate network node 3. Adder logic 64 adds ADCPO and APSPO to calculate CPO, which may also be referred to as accumulated CPO (ACPO). CPO replacement logic 58 receives a CBR carrier stream and replaces CPO-P in CPOR-P with ACPO to generate an updated CPOR for the corresponding CBR carrier stream, which is output at output 59 to a corresponding FIFO in FIFOs 52a to 52f.

[0060] In applications where the PHY link may experience high bit error rates, cells and packets carrying CPOR may be discarded due to CRC verification failures. Figure 8 The example shown in tolerates dropped CPOR cells and packets. More specifically, instead of Figure 7 The CPO is calculated by adding the PSPO to the CPO-P as in the embodiment of , using the current incoming CPOR-P and the previous CPOR-P to ensure that the calculated CPO is correct. If the CPOR is lost, the received CPOR-P is not actually the previous CPOR-P, but the previous CPOR-P of the previous CPOR-P. In the example where there is a sequence of CPORs, the latest to the oldest can be marked as: CPOR5, CPOR4, CPOR3, CPOR2, CPOR1. CPRO1 arrives at the last intermediate network node 3c first. CPOR2 is the next to arrive, and CPOR5 is the most recent to arrive. The accumulator 63 accumulates the difference as reflected by each incoming CPOR. Consider the case where CPOR3 is lost due to damage. Figure 8The previous CPOR-P register 61 in will contain CPOR2, and the current CPOR-P register 55 will contain CPOR4. The difference between CPOR4-CPOR2 is equal to (CPRO3-CPOR2)+(CPOR4-CPOR3). Therefore, the value in the accumulator (ADCPO) will catch up to the same value as if there was no CPOR loss. Therefore, the lost CPOR will not be permanently corrupted.

[0061] The CBR carrier streams are multiplexed into the intermediate network node data streams, and these intermediate network node data streams are sent from the corresponding intermediate network nodes. Figure 6 In the embodiment, the multiplexer 13 receives the outputs of the FIFOs 52a to 52f and multiplexes the outputs of the FIFOs 52a to 52f (CBR carrier streams) into the intermediate network node data streams, which are coupled to the corresponding encoders in the encoder 15, which encode the received intermediate network node data streams to output the corresponding INN data streams on the corresponding PHY link output terminal 9. The clock at the PHY link output terminal is phase locked to the local reference clock signal 39a received at the local reference clock input terminal 39 via the transmit PLL 16. The corresponding intermediate network node data stream in the intermediate network node data stream includes the CRR generated by the source node 1, and the intermediate network node 3 is not required to change the content of any CRR in the CRR. In an example, none of the intermediate network nodes 3 changes the content of any CRR in the CRR.

[0062] Fig. 9 A sink node 2 is shown. In the following discussion, many of the operations of the sink node 2 are performed in the same manner as they are performed at the intermediate network nodes. To distinguish the calculations and resulting values ​​at the sink node from those performed at the intermediate network nodes, the corresponding values ​​are indicated as "sink" values ​​and are distinguished from those of the intermediate network nodes by adding an "S" to the end of the relevant terms, and by adding the phrase "sink node" after the corresponding terms, wherein the corresponding terms are distinguished from those of the intermediate network nodes by adding a "-1" to the end of the corresponding terms. Figure 6 to compare the numbers of some similar elements in the sink node with the corresponding numbers of specific elements in Figure 6 Those numbers are distinguished.

[0063] The aggregation node 2 includes a PHY link input terminal 8-1, a local reference clock input terminal 39-1 for receiving a local reference clock signal 39a-1, a clock offset circuit 11-1, a demultiplexer 12-1, a CPOR update logic 14-1, an aggregation output processing circuit 79, other aggregation node circuits 70, and output terminals 78a to 78d. The demultiplexer 12-1 is coupled to the PHY link input terminal 8-1 and the CPOR update logic 14-1. The clock offset circuit 11-1 is coupled to the local reference clock input terminal 39-1, the PHY link input terminal 8-1, and the CPOR update logic 14-1. The aggregation output processing circuit 79 is coupled to the CPOR update logic 14-1 and the output terminal 78. The clock offset circuit 11 includes a sampling pulse generator 41-1, an accumulation phase counter circuit 42-1, a clock recovery circuit 43-1, a clock scalar circuit 44-1, a current count register 45-1, a previous count register 46-1, a first subtraction logic 48-1, a second subtraction logic 49-1, and an LPSD register 47-1. The first subtraction logic 48-1 and the second subtraction logic 49-1 can be implemented as corresponding subtraction circuits. The sampling pulse generator 41-1 is coupled to the reference clock input terminal 39-1 and the accumulation phase counter circuit 42-1. The clock recovery circuit 43-1 is coupled to the corresponding PHY link input terminal 8-1 and the clock scalar circuit 44-1. The accumulation phase counter circuit 42-1 is coupled to the current count register 45-1 and the clock scalar circuit 44-1. The current count register 45-1 is coupled to the previous count register 46-1. The first subtraction logic 48-1 is coupled to the current count register 45-1, the previous count register 46-1, and the second subtraction logic 49-1. The second subtraction logic 49-1 is coupled to the LPSD register 47-1 and the CPOR update logic 14-1.

[0064] The converged output processing circuit 79 includes a CPO extraction logic 71, a read modulator 72, a CRR extraction logic 73, a CBR extraction logic 74, a CRR FIFO 75, a CBR payload FIFO 76, and a transmit PLL 77. The CPO extraction logic 71 is coupled to the output terminal 59-1 of the CPOR update logic 14-1, which outputs the CBR carrier stream 50d with the updated CPOR and is coupled to the read modulator 72. The CRR extraction logic 73 and the CBR extraction logic 74 are coupled to the output terminal 50-1 of the demultiplexer 12-1 to receive one of the CBR carrier streams 50a to 50c. The CRR FIFO 75 is coupled to the read modulator 72, the CRR extraction logic 73, and the transmit PLL 77. The transmit PLL 77 is coupled to the local reference clock input 39-1. The CBR payload FIFO 76 is coupled to the CBR extraction logic 74 and the transmit PLL 77. The other sink node circuits 70 are coupled to the local reference clock input terminal 39 - 1 , the PHY link input terminal 8 , and output terminals 78 b to 78 d .

[0065] The intermediate network node data streams 8e to 8h are received at the aggregation node 2. Fig. 9 In the example, the clock offset circuit 11-1 of the sink node receives the INN data stream at the PHY link input terminal 8-1, and the clock offset circuit 11-1 measures the bit count of the received INN data stream based on the local reference clock signal 39a-1 of the sink node, and calculates the PSPO-S of the received intermediate network node data stream. In this example, the PSPO-S is calculated in the same manner as the PSPO calculated at the intermediate network node, and indicates the difference between the CPSC increment and the LPSD in the specific INN data stream received at the sink node.

[0066] The following is an example illustrating processing of a single INN data stream 8e to obtain a CBR signal with a recovered client signal 78a. The processing of the other INN data streams 8f to 8h may be performed in the same manner as the INN data stream 8e, and Fig. 9Some or all of the devices for processing the INN data stream 8e shown in the figure may be included in other sink node circuits 70 for processing the INN data streams 8f to 8h (for example, the other sink node circuits 70 may include the same set of circuits for processing each of the INN data streams 8f to 8h). The PHY link input terminal 8-1 of the sink node receives the intermediate network node data stream 8e from the last intermediate network node. The clock offset circuit 11-1 of the sink node is coupled to the PHY link input terminal 8-1 of the sink node to: accumulate the counter samples of the IPSCk at the sink node with the Tps of the local reference clock of the sink node to obtain the CPSC at the sink node, the IPSCk being generated by calibrating the clock recovered from the received intermediate network node data stream of the last intermediate network node 8e to Fipsck; and calculate the PSPO (PSPO-S) at the sink node, the PSPO-S indicating the phase difference between the LPSD at the sink node and the IPSD at the sink node, wherein the IPSD at the sink node indicates the CPSC increment between consecutive CPSC samples at the sink node. The demultiplexer 12-1 of the aggregation node is coupled to the PHY link input terminal 8-1 of the aggregation node to demultiplex the intermediate network node data stream received from the last intermediate network node 8e to obtain individual CBR carrier streams at the aggregation nodes 50d to 50f. The CPOR update logic 14-1 of the aggregation node is coupled to the clock offset circuit 11-1 to calculate the CPO (CPO-S) of the corresponding CBR carrier streams 50d to 50f at the aggregation node by adding the PSPO-S to the CPO-P of the corresponding CBR data streams 50d to 50f received at the aggregation node (i.e., received from the last intermediate network node). The aggregation output processing circuit 79 is coupled to the demultiplexer 12-1 of the aggregation node and the CPOR update logic 14-1 of the aggregation node to recover the CBR client signal using the CPO-S and the CRR corresponding to the specific CBR signal. The PHY link output terminal 78 of the aggregation node is coupled to the aggregation output processing circuit 78 to output the CBR signal including the recovered CBR client signal from the aggregation node.

[0067] In one example, CPO-S is associated with Figure 7The CPO-S is calculated in the same manner as shown, where calculating the CPO-S includes adding the calculated PSPO-S to the CPO-P of the corresponding CBR data stream received at the sink node (e.g., the CPO-P from the last intermediate network node). In one example, the intermediate network node data stream 8e includes a CPOR-P indicating the CPO-P from the last intermediate network node, which is demultiplexed to obtain individual CBR carrier streams 50d to 50f output at the corresponding demultiplexer output terminal 50-1. The CPOR update logic 14-1 calculates the CPO-S of the carrier stream 50d, which replaces the CPO-P in the CBR carrier stream 50d to form a first updated CPOR at the sink node 91a. The CPOR update logic 14-1 calculates the CPO-S for the carrier stream 50e, which replaces the CPO-P in the CBR carrier stream 50e to form a second updated CPOR at the sink node 91b, and so on to the nth CPO-S 91c for the nth CBR carrier stream 50f.

[0068] In another example, CPO-S is based on Figure 8 50 d to 50 f, which is the CPOR-P from the last intermediate network node. When the next CPOR-P is received, the previous CPOR-P is moved to the previous CPOR-P register 61, becomes the "previous CPOR-P" at the sink node and the received CPOR-P is stored in the CPOR-P register 55. The subtraction logic 62 subtracts the CPO-P in the previous CPOR-P stored in the previous CPOR-P register 61 from the current CPO-P in the CPOR-P register 55 to obtain the delta cumulative phase offset (D-CPO) at the sink node. The accumulator 63 calculates the aggregated accumulated delta cumulative phase offset (ADCPO-S) by accumulating all D-CPOs calculated by the sink node since the last initialization of the sink node. The accumulator 60 calculates the aggregated accumulated PSPO (APSPO-S) by accumulating all calculated PSPOs received at the input terminal 56 since the last initialization of the aggregation node. The adder logic 64 adds the ADCPO-S to the APSPO-S to calculate the CPO-S. The CPO replacement logic 58 receives the CBR carrier streams 50d to 50f and replaces the CPO-P in the CPOR-P with the calculated CPO-S to generate an updated CPOR for the corresponding CBR carrier stream 50d to 50f, which is output at the output terminal 59 to the CRR extraction logic 71.

[0069] Optionally, the CPO-P received at the aggregation node is replaced with the CPO-S of the corresponding CBR carrier stream (e.g., so that the circuitry of the CPOR update logic 14 is identical to the CPOR update logic 14-1 to simplify design and manufacturing). The aggregation output processing circuit 79 uses the CPO-S and the CRR corresponding to the particular CBR signal to recover the CBR client signal. The PHY link output terminal 78 is coupled to the aggregation output processing circuit 79 to output a CBR signal 78a including the recovered CBR client signal from the aggregation node.

[0070] exist Fig. 9 In the embodiment, a single aggregate output processing circuit 79 is shown for processing of the display 91a and CBR carrier stream 50d. However, in one example, the aggregate output processing circuit 79 includes similar or identical circuits coupled to each output terminal 59 that operate in the same manner as the aggregate output processing circuit 79 shown for processing the first updated CPOR and first carrier stream 50d at the aggregation node 91a.

[0071] In one example, the CRR extraction logic 73 extracts the incoming CRR from the CBR carrier stream 50d and stores it in the CRRFIFO 75. The CRR FIFO 75 is nominally read out at Tcrr as measured by the local reference clock, and the phase value in the CRR is sent to the transmit PLL 77 as a reference input phase. In one example, the CPOR update logic 14-1 generates a new CPOR at the first updated CPOR at the sink node 91a. The new CPOR is coupled to the CPO extraction logic 71, which extracts the CPO-S and indicates the corresponding CPO-S to the read modulator 72. Figure 7 In the example shown, CPO-S may be taken directly from the CPOR update logic 14-1 and used by the read modulator 72 to modulate the instance of the CRR read out from the CRR FIFO 75. Figure 8In the example shown, since CPO is a cumulative value, the previous CPO-S is subtracted from the new CPO-S to identify the CPO-S that will be used by the read modulator 72 to modulate the instance of the CRR read out from the CRR FIFO 75. If the CPO-S indicates that there is a positive ppm offset between the reference clock at the source node relative to the sink node (RPPMpath is positive), the CRR FIFO is read more frequently than Tcrr. Conversely, if the CPO-S indicates that there is a negative ppm offset between the reference clock relative to the sink node (if RPPMpath is negative), the CRR FIFO is read less frequently than Tcrr. The CBR extraction logic 74 receives the CBR carrier stream 50d and extracts the CBR client signals, coupling these CBR client signals to the CBR payload FIFO 76. The transmit PLL 77 is coupled to the local reference clock input 39-1 and receives the reference clock signal 39a-1, and provides a transmit clock signal to the CBR payload FIFO 76 to regenerate a phase-locked copy of the client stream of the source node. Implementation alternatives to the modulated CRR FIFO read example are described in US Patents 8,542,708 and 9,019,997, which are incorporated herein by reference in their entirety.

[0072] Fig. 10A A block diagram of a method 100 is shown in which a data stream generated by a previous network node is received (101). The received data stream includes a CBR carrier stream corresponding to a CBR signal received at a source node. A counter accumulating IPSCk is sampled (102) at Tps of a local reference clock of an intermediate network node to obtain a CPSC of the corresponding received data stream, the IPSCk being generated by calibrating a clock recovered from the corresponding received data stream to Fipsck_nom. A PSPO indicating a phase difference between LPSD and IPSD is calculated (103), wherein IPSD represents an increment between consecutive CPSCs. In one example, LPSD represents the amount of expected increment at the intermediate network node based on Fipck_nom and Tps. Fig. 10B In one example shown in block 103-1, the PSPO is calculated by calculating an IPSD indicating an increase in bit count within Tps (e.g., by subtracting a previous CPSC from a current CPSC); and subtracting LPSD from the IPSD), where the calculated PSPO is in units of phase and the LPSD is a function of Fipsck_nom and Tps.

[0073] The received data stream is demultiplexed (104) to obtain CBR carrier streams, respective ones of which include a CPOR-P indicating a CPO-P. Fig. 10CIn the example shown in block 104-1 of , each CBR carrier stream in the CBR carrier stream also includes a CRR indicating the measured bit count of the corresponding CBR client at the source node. In one example, the intermediate network nodes 3 to 3c do not change the content of the CRR. In one example, the intermediate network nodes are not required to terminate any CRR in the CRR, generate new CRRs, or change the content of any CRR in the CRRs. In one example, the intermediate network nodes 3 to 3c do not terminate any CRR in the CRRs, do not generate new CRRs, or do not change the content of any CRR in the CRRs.

[0074] The CPO of a corresponding one of the CBR carrier streams (e.g., each of the CBR carrier streams) is calculated (105), and the CPO-P of the corresponding one of the CBR carrier streams (e.g., each of the CBR carrier streams) is replaced (106) with the calculated CPO of the corresponding CBR carrier stream, wherein the calculated CPO is a function of the CPO-P of the particular carrier stream and the calculated PSPO. Fig. 10D In the example shown in block 105-1 of , CPO is calculated by adding the calculated PSPO to CPO-P. Fig. 10E In the example shown in block 105-2 of , the CPO is a function of all CPO-Ps received by the intermediate network node since the last initialization of the intermediate network node. Fig.10F In the example shown in box 105-3, CPO is an accumulated PSPO (ACPO) calculated in the following manner: calculating a Δ cumulative phase offset (D-CPO) by subtracting a previously received CPO-P from CPO-P; calculating an accumulated D-CPO (ADCPO) by accumulating all D-CPOs calculated by the intermediate network node since the last initialization of the intermediate network node; calculating an accumulated PSPO (APSPO) by accumulating all PSPOs calculated by the intermediate network node since the last initialization of the intermediate network node; and adding the APSPO to the ADCPO).

[0075] The CBR carrier streams are multiplexed into intermediate network node data streams (107), and these intermediate network node data streams are sent from the respective intermediate network nodes (108).

[0076] Figure 10GA block diagram of a method 100 performed at a sink node is shown. An intermediate network node data stream is received (100-1) from a last intermediate network node at the sink node. A counter that accumulates a PHY-calibrated stream clock (IP SCk-S) at the sink node is sampled (100-2) at a Tps based on a local reference clock of the sink node to obtain a cumulative PHY-calibrated count (CPSC-S) at the sink node, the IPSCk-S being generated by calibrating a clock recovered from the received intermediate network node data stream of the last intermediate network node to Fipsck_nom. A PHY-calibrated stream phase offset (PSPO-S) at the sink node is calculated (100-3) by subtracting the LPSD at the sink node from the incoming PHY-calibrated count Δ (IPSD-S) at the sink node, wherein the IPSD-S represents an increment between consecutive CPSC-Ss, which increment may be referred to as a CPSC-S increment. The received intermediate network node data stream from the last intermediate network node is demultiplexed (100-4) to obtain individual CBR carrier streams.

[0077] The CPO (CPO-S) at the sink node is calculated (100-5) for the corresponding CBR carrier stream in the CBR carrier stream. Fig. 10H In the example shown in block 100-5-1 of , calculating CPO-S includes adding the calculated PSPO-S to the CPO-P of the corresponding CBR data stream received at the sink node. Fig.10I In the example shown in box 100-5-2, the calculated CPO-S is an ACPO calculated in the following manner: calculating the Δ cumulative phase offset (D-CPO) at the aggregation node by subtracting the previous received CPO-P received at the aggregation node from the CPO-P received at the aggregation node; calculating the aggregated cumulative D-CPO (ADCPO-S) by accumulating all D-CPOs calculated by the aggregation node since the last initialization of the aggregation node; calculating the aggregated cumulative PSPO (APSPO-S) by accumulating all PSPOs calculated by the aggregation node since the last initialization of the aggregation node; and adding the APSPO-S to the ADCPO-S.

[0078] The CBR client signal is restored (100-6) using the calculated CPO-S and the CRR corresponding to the specific CBR signal. A CBR signal including the restored CBR client signal is output (100-7) from the sink node.

[0079] According to the method and apparatus of the present invention, the ppm offset of the corresponding node in the node is represented by the CPOR generated by the corresponding node in the node. At the convergence node, the received CPOR is generated by the last switching node, and therefore only the relative ppm offset (RPPMsk) between the last switching node and the convergence node needs to be biased. The CRR is generated by the source node and forwarded to the convergence node verbatim. The ppm offset of the source node is represented by CRR, which can be based on ITU GMP or similar schemes. The convergence node uses the relative ppm offset (RPPMpath) between the source node and the convergence node to bias the processing of the received CRR.

[0080] The method and apparatus of the present invention measure the ppm offset between pairs of nodes, and then sum the measured ppm offsets together to obtain the ppm offset from the source to the sink. In the source node 1, there are actually two ppm offsets at work. One is the ppm offset of the CBR client from its nominal value. This is what the CRR encodes. Unfortunately, when doing this, the measurement is contaminated by the ppm offset of the local reference clock at the source node 1. This is the second ppm offset. For example, when the CBR client is 10ppm faster than its nominal value, if the local reference clock 20 is completely nominal, the CRR will only indicate this 10ppm value. If the source local reference clock 20 is also 10ppm faster, the CRR will falsely report the nominal value.

[0081] The method and apparatus of the present invention uses CPOR to communicate RPPMpath to the converged output processing circuit 79, thereby avoiding the problem of measurement contamination by the reference clock at the source node 1. Because the method and apparatus of the present invention share a common mathematical basis with the ITU GMP scheme, both are expected to have similar jitter and wander performance.

[0082] The following are Figure 1 The network 4 includes an example of intermediate network node switches 3a to 3c. In this example, the PHY-calibrated stream phase offset measured at the first intermediate network node switch 3a is determined by the PSPO 1 Indicates that the PHY-calibrated stream phase offset measured at the second intermediate network node switch 3b is determined by PSPO 2 Indicates that the PHY-calibrated stream phase offset measured at the third intermediate network node switch 3c is determined by PSPO 3 Indicates that the PHY-scaled stream phase offset measured at the aggregation node switch 2 is indicated by PSPO-S. In this example, the CPO sent to the first intermediate network node switch 3a 0 will have an initial value of zero. At the output of the intermediate network node switch 3a, the CPO in the intermediate network node data flow will have a value reflecting 0 (initial CPO value) and PSPO 1The calculated CPO (CPO 1 At the output of the intermediate network node switch 3b, the CPO in the intermediate network node data flow will have a PSPO as 1 +PSPO 2 The calculated CPO (CPO 2 At the output of the intermediate network node switch 3c, the CPO in the intermediate network node data flow will have a PSPO as 1 +PSPO 2 +PSPO 3 The calculated CPO (CPO 3 ). The corresponding CPO-S calculated at sink node 2 will be PSPO 1 +PSPO 2 +PSPO 3 +PSPO-S. Thus, CPO-S will be the accumulation of all relative PPM deviations in the path and will indicate the relative parts per million of the entire path (RPPMpath).

[0083] In one example, the ppm offset of the local reference clock in the source node is PPMsrc relative to the nominal value. The measured rate of the CBR client at the source node is encoded into the period CRR. The nominal period between CRRs is Tcrr, as measured by the local reference clock at the source node 1. The CPOR of the carrier stream is nominally generated once every Tcpor period as measured by the local reference clock of the source node 1. The CPOR can be initialized to 0 or some other predetermined value.

[0084] In this example, the corresponding intermediate network node switch in the intermediate network node switch 3a to 3c demultiplexes the corresponding data stream in the data stream (e.g., each data stream in the data stream) into a set of n CBR carrier streams (each CBR carrier stream is used for a corresponding CBR signal in the CBR signal), and monitors the existence of CPOR in the corresponding carrier stream in the carrier stream. The PSPO shared by all CBR carriers sharing the same PHY link is then summed up by the CPOR update logic 14 to the incoming CPOR. Because CPOR is generated more frequently than PSPO (Tps>Tcpor), there are more CPOR values ​​than PSPO values ​​in any given time period. In one example, once the PSPO has been summed up to the CPOR of the CBR carrier, the subsequent CPOR of the CBR carrier will be retained unmodified until a new PSPO is available. In another example, once the PSPO has been summed up to the CPOR of the CBR carrier, the subsequent CPOR of the CBR carrier will be updated using the same PSPO until a new PSPO is available.

[0085] In one example, the calculated CPO can be a positive number (when the measured bit count is greater than the PHY-calibrated stream nominal bit count value) or a negative number (when the measured bit count is less than the PHY-calibrated stream nominal bit count value). In one example, when the measured bit count is greater than the PHY-calibrated stream nominal bit count value, the CPOR update logic 14 calculates the CPO by adding the PSPO to the P-CPO; and when the measured bit count is less than the PHY-calibrated stream nominal bit count value, the CPOR update logic 14 calculates the CPO by adding the calculated PSPO (negative value) to the CPO-P.

[0086] For the sake of clarity and brevity, and to avoid unnecessary or unhelpful clutter, confusion, obscurity, obstruction, or occlusion of features or elements of the examples of the present disclosure, certain complexities and details commonly known to those of ordinary skill in the relevant art have been omitted or discussed in less exhaustive detail. Any such omission or discussion is deemed unnecessary for describing the examples of the present disclosure and / or not particularly relevant for enabling an understanding of the salient features, functions, elements, and / or aspects of the examples of the present disclosure described herein.

[0087] In the specification and drawings herein, exemplary implementations are described with respect to the claims set forth below. However, the present disclosure is not limited to these examples, and the specification and drawings herein are therefore intended to inspire those skilled in the art of integrated circuit-related technology to understand, appreciate and suggest alternatives and equivalents thereof.

Claims

1. A method, the method include: receiving, at an intermediate network node, a data stream generated by a previous network node, wherein the received data stream comprises a constant bit rate CBR carrier stream corresponding to a constant bit rate CBR signal received at a source node; Sampling a counter accumulating a stream clock IPSCk scaled by the physical layer PHY at a nominal sampling period Tps of a local reference clock of the intermediate network node to obtain a cumulative PHY-scaled count CPSC of the corresponding received data stream, wherein the IPSCk is generated by scaling a clock recovered from the corresponding received data stream to a predetermined nominal frequency Fipsck_nom; calculating a PHY scaled stream phase offset PSPO indicating a phase difference between a PHY scaled stream nominal bit count LPSD and an incoming PHY scaled count ΔIPSD, wherein the IPSD indicates a delta between consecutive CPSCs; demultiplexing the received data streams to obtain the CBR carrier streams, respective ones of the CBR carrier streams comprising a previous network node cumulative phase offset report CPOR-P indicating a previous network node cumulative phase offset CPO-P and a client rate report CRR indicating a measured bit count of a respective CBR client at the source node; Calculating a cumulative phase offset CPO of a corresponding CBR carrier stream among the CBR carrier streams, wherein the CPO is a function of the CPO-P of the corresponding CBR carrier stream and the calculated PSPO; replacing a CPO-P in a corresponding one of the CBR carrier streams with a calculated CPO of the corresponding CBR carrier stream, or a function of the calculated CPO of the corresponding CBR carrier stream, to generate an updated CPOR to replace the CPOR-P in the corresponding CBR carrier stream; multiplexing the CBR carrier stream into an intermediate network node data stream; as well as The intermediate network node data flow is sent from the intermediate network node.

2. The method of claim 1, wherein the LPSD is a function of the Fipsck_nom and the Tps, and wherein the PSPO is in units of phase, and wherein the PSPO is calculated include: calculating the IPSD; as well as The LPSD is subtracted from the IPSD. 3 . The method of claim 1 , wherein the CPO is calculated by adding the calculated PSPO to the CPO-P. 4 . The method of claim 1 , wherein the calculated CPO is a function of all CPO-Ps received by the intermediate network node since a last initialization of the intermediate network node.

5. The method according to claim 1, wherein the CPO is calculated include: Calculating a delta cumulative phase offset D-CPO by subtracting a previously received CPO-P from said CPO-P; Calculate the accumulated D-CPO, ADCPO, by accumulating all the D-CPOs calculated by the intermediate network node since the last initialization of the intermediate network node; Calculate the accumulated PSPO, APSPO, by accumulating all the PSPOs calculated by the intermediate network node since the last initialization of the intermediate network node; and Add the APSPO to the ADCPO.

6. The method according to claim 1, wherein the source node measures the bit rate of the corresponding CBR client in the CBR signal based on the local reference clock of the source node, and encodes the CRR indicating the measured bit rate of the corresponding CBR client into the corresponding CBR carrier stream in the CBR carrier stream, and wherein the intermediate network node does not change the content of the corresponding CRR in the CRR.

7. The method according to claim 1, the method further comprises: Receiving an intermediate network node data stream from the last intermediate network node at the aggregation node; Sampling a counter that accumulates the PHY-scaled stream clock IPSCk-S at the aggregation node at Tps based on the local reference clock of the aggregation node to obtain the accumulated PHY-scaled count CPSC-S at the aggregation node, where the IPSCk-S is generated by scaling the clock recovered from the received intermediate network node data stream from the last intermediate network node to Fipsck_nom; Calculating the PHY-scaled stream phase offset PSPO-S at the aggregation node by subtracting the LPSD from the incoming PHY-scaled count ΔIPSD-S at the aggregation node, where the IPSD-S represents the increment between consecutive CPSC-S; Demultiplexing the received intermediate network node data stream from the last intermediate network node to obtain individual CBR carrier streams; Calculating the CPO, CPO-S, at the aggregation node for the corresponding CBR carrier stream in the CBR carrier stream; Using the calculated CPO-S and the CRR corresponding to the corresponding CBR carrier stream to recover the CBR client signal; and Outputting a CBR signal including the recovered CBR client signal from the aggregation node.

8. The method according to claim 7, wherein calculating the CPO-S includes adding the calculated PSPO-S to the CPO-P received at the aggregation node for the corresponding CBR data stream.

9. The method according to claim 7, wherein calculating CPO-S comprises: Calculating the Δ accumulated phase offset, D-CPO, at the aggregation node by subtracting the previously received CPO-P received at the aggregation node from the CPO-P received at the aggregation node; Calculating the aggregation accumulated D-CPO, ADCPO-S, by accumulating all the D-CPOs calculated by the aggregation node since the last initialization of the aggregation node; calculating an aggregated accumulated PSPOAPSPO-S by accumulating all said PSPOs calculated by said sink node since the last initialization of said sink node; and The APSPO-S and the ADCPO-S are added.

10. An integrated circuit IC device for an intermediate network node, the IC device include: a physical layer PHY link input terminal, the PHY link input terminal being configured to receive a data stream generated by a previous network node, the data stream comprising a plurality of constant bit rate CBR carrier streams, a corresponding CBR carrier stream of the CBR carrier streams comprising a previous network node cumulative phase offset report CPOR-P indicating a previous network node cumulative phase offset CPO-P and a client rate report CRR indicating a measured bit count of a corresponding CBR client at a source node; a clock offset circuit coupled to the PHY link input for sampling a counter accumulating a PHY-scaled stream clock IPSCk with a nominal sampling period Tps of a local reference clock of the intermediate network node to obtain a cumulative PHY-scaled count CPSC of the received corresponding data stream, the IPSCk being generated by scaling a clock recovered from the received corresponding data stream to a predetermined nominal frequency Fipsck_nom; and for calculating a PHY-scaled stream phase offset PSPO indicating a phase difference between the PHY-scaled stream nominal bit count LPSD and an incoming PHY-scaled count ΔIPSD, wherein the IPSD indicates an increment between consecutive CPSCs; a demultiplexer coupled to the PHY link input for demultiplexing the received data stream to obtain the plurality of CBR carrier streams; a cumulative phase offset report (CPOR) update logic coupled to the demultiplexer and the clock offset circuit to calculate a cumulative phase offset (CPO) of a corresponding one of the CBR carrier streams, wherein the calculated CPO is a function of the CPO-P and the calculated PSPO; and to replace the CPO-P with the calculated CPO of the corresponding CBR carrier stream, or with a function of the calculated CPO of the corresponding CBR carrier stream; and to generate an updated CPOR for the corresponding CBR carrier stream to replace the CPOR-P in the corresponding CBR carrier stream; a multiplexer coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams; an encoder coupled to the multiplexer to encode the plurality of intermediate network node data streams; and A PHY link output is coupled to the encoder to transmit the plurality of intermediate network node data streams from the IC device.

11. The IC device of claim 10, wherein the PHY link input, the clock offset circuit, the demultiplexer, the CPOR update logic, the encoder, and the PHY link output are disposed in a single integrated circuit die. 12 . The IC device of claim 10 , wherein the CPOR update logic is to calculate the CPO by adding the calculated PSPO to the CPO-P.

13. The IC device of claim 10, wherein the CPOR update logic calculates the CPO by: Calculating a delta cumulative phase offset D-CPO by subtracting a previously received CPO-P from said CPO-P; calculating an accumulated D-CPOADCPO by accumulating all said D-CPOs calculated by said intermediate network node since a last initialization of said intermediate network node; calculating an accumulated PSPOAPSPO by accumulating all said PSPOs calculated by said intermediate network node since said last initialization of said intermediate network node; and The ADCPO is added to the APSPO.

14. The IC device of claim 10, wherein the clock offset circuit include: A reference clock input terminal, the reference clock input terminal is used to receive a signal of the local reference clock; a sampling pulse generator, the sampling pulse generator being coupled to the reference clock input terminal so as to generate a sampling pulse at Tps; a clock recovery circuit coupled to the PHY link input terminal to recover a PHY link clock signal; a clock scaler circuit coupled to the clock recovery circuit and the sampling pulse generator to scale the recovered PHY link clock signal to the Fipsck_nom to obtain the PHY-scaled stream clock; an accumulative phase counter circuit coupled to the output of the clock scaler circuit and the sampling pulse generator, the accumulative phase counter circuit sampling a counter accumulating the IPSCk at TPs to obtain the CPSC; a first register coupled to the accumulation phase counter circuit to store the CPSC; a second register coupled to the first register to store a previous CPSC; first subtraction logic coupled to the first register and the second register to subtract the previous CPSC from the CPSC to obtain the IPSD; a third register, the third register being used to store the LPSD; and A second subtraction logic is coupled to the first subtraction logic to subtract the LPSD from the IPSD to calculate the PSPO.

15. The IC device of claim 10, wherein the intermediate network nodes do not change the content of corresponding ones of the CRRs.

16. A network, wherein include: A source node, the source node comprising: An input terminal, the input terminal being used to receive a plurality of constant bit rate CBR signals, A cumulative phase offset report CPOR generating circuit, the CPOR generating circuit is used to generate a CPOR indicating an initial cumulative phase offset CPO, a CRR generating circuit for generating a client rate report CRR indicating a measured bit rate of a corresponding CBR client, and a CBR mapper coupled to the input for generating corresponding CBR carrier streams for respective ones of the CBR signals and for inserting the CRR and CBR client data into the respective CBR carrier streams, A source output processing circuit, the source output processing circuit is used to insert the CPOR into a corresponding CBR carrier stream and multiplex the CBR carrier stream to generate a plurality of source data streams; A plurality of intermediate network nodes, the plurality of intermediate network nodes being coupled to the source node, wherein respective ones of the intermediate network nodes include an integrated circuit (IC) device, the IC device including: a physical layer PHY link input terminal, the PHY link input terminal being used to receive a data stream generated by a previous network node, the data stream comprising a plurality of CBR carrier streams, a corresponding CBR carrier stream of the CBR carrier streams comprising the CRR and a previous network node cumulative phase offset report CPOR-P indicating a previous network node cumulative phase offset CPO-P; a clock offset circuit coupled to the PHY link input to: sampling a counter accumulating a PHY-scaled stream clock IPSCk with a nominal sampling period Tps of a local reference clock of the intermediate network node to obtain a cumulative PHY-scaled count CPSC of the corresponding received data stream, the IPSCk being generated by scaling a clock recovered from the corresponding received data stream to a predetermined nominal frequency Fipsck_nom, and calculating a PHY scaled stream phase offset PSPO indicating a phase difference between a PHY scaled stream nominal bit count LPSD and an incoming PHY scaled count ΔIPSD, wherein the IPSD indicates a delta between consecutive CPSCs; a demultiplexer coupled to the PHY link input for demultiplexing the received data stream to obtain individual CBR carrier streams, a cumulative phase offset report (CPOR) update logic coupled to the demultiplexer and the clock offset circuit to calculate a CPO for a corresponding one of the CBR carrier streams, wherein the calculated CPO is a function of the CPO-P of the corresponding CBR carrier stream and the calculated PSPO; and to replace the CPO-P of the corresponding CBR carrier stream with the calculated CPO of the corresponding CBR carrier stream to generate an updated CPOR for the corresponding CBR carrier stream in place of the CPOR-P of the corresponding CBR carrier stream, a multiplexer coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams, an encoder coupled to the multiplexer to encode the plurality of intermediate network node data streams, and a PHY link output coupled to the encoder to transmit the plurality of intermediate network node data streams from the IC device; and A sink node is coupled to a last one of the intermediate network nodes to receive the intermediate network node data stream from the last one of the intermediate network nodes, recover the CBR client signal, and output a CBR signal including the recovered CBR client signal from the sink node.

17. The network of claim 16, wherein the plurality of intermediate network nodes do not change the content of corresponding ones of the CRRs.

18. The network of claim 16, wherein the CPOR update logic calculates the CPO by adding the calculated PSPO to the CPO-P.

19. The network of claim 16, wherein the calculated CPO is a function of all CPO-Ps received since a last initialization of the respective intermediate network node and all the PSPOs calculated since the last initialization of the respective intermediate network node.

20. The network of claim 16, wherein the sink node include: a PHY link input of the aggregation node, the PHY link input being configured to receive the intermediate network node data stream from a last intermediate network node among the plurality of intermediate network nodes; A clock shift circuit of the sink node, the clock shift circuit coupled to the PHY link input of the sink node to: Sampling a counter accumulating a PHY-scaled stream clock IPSCk-S at the sink node with Tps of a local reference clock of the sink node to obtain a cumulative PHY-scaled count CPSC-S at the sink node, the IPSCk-S being generated by scaling a clock recovered from a received intermediate network node data stream of a last intermediate network node among the plurality of intermediate network nodes to Fipsck_nom; and calculating a PSPOPSPO-S at the sink node, the PSPO-S indicating a phase difference between an LPSD and an incoming PHY-scaled count ΔIPSD-S at the sink node, wherein the IPSD-S indicates a delta between consecutive CPSC-Ss; a demultiplexer of the aggregation node, the demultiplexer coupled to the PHY link input of the aggregation node for demultiplexing the intermediate network node data stream received from a last intermediate network node of the plurality of intermediate network nodes to obtain the individual CBR carrier streams at the aggregation node; CPOR update logic of the sink node, the CPOR update logic coupled to the clock offset circuit to calculate the CPOCPO-S of a corresponding one of the CBR carrier streams at the sink node by adding the PSPO-S to the CPO-P of the corresponding CBR data stream received at the sink node; an aggregate output processing circuit coupled to the demultiplexer of the aggregation node and the CPOR update logic of the aggregation node to recover the CBR client signal using the CPO-S and the CRR corresponding to the corresponding CBR data stream; and A PHY link output terminal of the aggregation node is coupled to the aggregation output processing circuit to output a CBR signal including the recovered CBR client signal from the aggregation node.

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