Display panel, preparation method thereof and display device

Abstract

Embodiments of the present application provide a display panel, a preparation method thereof and a display device. The display panel comprises a first substrate and a second substrate arranged oppositely, and a plurality of spacers between the first substrate and the second substrate; the first substrate comprises a first base, a plurality of gate lines and a plurality of data lines, the gate lines are arranged on one side of the first base, the data lines are arranged on a side of the gate lines away from the first base, and the orthographic projection of the gate lines on the first base and the orthographic projection of the data lines on the first base have an intersection region; at least one data line is provided with a receiving cavity, the orthographic projection of the receiving cavity on the first base is located in the intersection region, the orthographic projection of at least one spacer on the first base is located in the intersection region, and an end of the spacer located in the intersection region away from the second substrate is arranged in the receiving cavity. Embodiments of the present application solve the technical problem that the color film substrate and the array substrate are prone to relative deviation in the prior art, resulting in uneven thickness.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Under the influence of gravity or external pressure, the color filter substrate and array substrate of existing display panels are prone to relative displacement, resulting in uneven thickness between the color filter substrate and array substrate, causing poor display quality. Summary of the Invention

[0003] This application addresses the shortcomings of existing methods by proposing a display panel, its manufacturing method, and a display device to solve the technical problem that, under the action of gravity or external pressure, the color filter substrate and the array substrate of the display panel are prone to relative displacement, resulting in uneven thickness between the color filter substrate and the array substrate and causing poor display image.

[0004] In a first aspect, embodiments of this application provide a display panel, comprising: a first substrate and a second substrate disposed opposite to each other, and a plurality of spacers located between the first substrate and the second substrate; the first substrate includes a first base, a plurality of gate lines and a plurality of data lines, the gate lines being disposed on one side of the first base, the data lines being disposed on the side of the gate lines away from the first base, and the orthographic projections of the gate lines on the first base and the orthographic projections of the data lines on the first base having an intersecting region; at least one data line is provided with a receiving cavity, the orthographic projection of the receiving cavity on the first base being located within the intersecting region, at least one spacer having its orthographic projection on the first base being located within the intersecting region, and the end of the spacer located within the intersecting region away from the second substrate passing through the receiving cavity.

[0005] Optionally, the orthographic projection of the receiving cavity on the first substrate covers the orthographic projection of the septum on the first substrate, and along a direction parallel to the first substrate, there is a first preset distance between the inner wall of the receiving cavity and the outer wall of the septum, the first preset distance being greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

[0006] Optionally, the data line with the receiving cavity includes a first sub-data line, a blocking structure, and a second sub-data line arranged sequentially. The blocking structure includes a first blocking line and a second blocking line, which form the receiving cavity. One end of the first blocking line is connected to the first sub-data line, and the other end of the first blocking line is connected to the second sub-data line. The second blocking line is connected to at least one of the first sub-data line and the second sub-data line. The second blocking line is multiplexed as the source of the pixel thin-film transistor of the first substrate.

[0007] Optionally, one end of the second blocking line is connected to the first sub-data line, and the other end of the second blocking line is connected to the second sub-data line; along the extension direction of the gate line, the sum of the widths of the first blocking line and the second blocking line is equal to the width of the first sub-data line; or, the second blocking line is connected to one of the first sub-data line and the second sub-data line; along the extension direction of the gate line, the width of the first blocking line is equal to the width of the first sub-data line.

[0008] Optionally, the width of the first blocking line is greater than or equal to 6 micrometers along the direction of the grid line extension.

[0009] Optionally, the first substrate further includes a passivation layer disposed on the side of the data line away from the first substrate. The orthographic projection of the passivation layer on the first substrate covers the orthographic projection of the gate line and the data line on the first substrate. The end of the spacer located in the intersection area away from the second substrate is located in the receiving cavity and abuts against the passivation layer. Corresponding to the blocking structure, the gate line includes a first sub-gate line and a second sub-gate line connected together. The orthographic projection of the first sub-gate line on the first substrate overlaps with the orthographic projection of the first blocking line on the first substrate, and the orthographic projection of the second sub-gate line on the first substrate overlaps with the orthographic projection of the receiving cavity on the first substrate. Along the extension direction of the data line, the width of the first sub-gate line is smaller than the width of the second sub-gate line.

[0010] Optionally, along the data line extension direction, the width of the first sub-gate line is greater than or equal to 6 micrometers; and / or, the orthographic projection of the second sub-gate line on the first substrate covers the orthographic projection of the spacer on the first substrate.

[0011] Optionally, the first substrate further includes a floating gate line disposed between the first substrate and the data line; the orthographic projection of the floating gate line on the first substrate does not overlap with the orthographic projection of the gate line on the first substrate; the orthographic projection of the floating gate line on the first substrate overlaps with the orthographic projection of the data line on the first substrate.

[0012] Optionally, along the extension direction of the gate line, the width of the floating gate line is greater than the width of the data line; and / or, along the extension direction of the data line, there is a second preset distance between the orthographic projection of the floating gate line on the first substrate and the orthographic projection of the spacer on the first substrate, the second preset distance being greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

[0013] Optionally, the floating gate line and the gate line are disposed on the same layer, and the orthographic projection of the floating gate line on the first substrate and the orthographic projection of the gate line on the first substrate are spaced apart along the data line extension direction.

[0014] Optionally, the second substrate includes a second base and a black matrix. The black matrix is ​​disposed on the side of the second base facing the first substrate, and the spacers are disposed on the side of the black matrix away from the second base. The orthographic projection of the black matrix on the first base covers the orthographic projection of the spacers, gate lines, and data lines on the first base.

[0015] Secondly, embodiments of this application provide a display device, including: a display panel as described above.

[0016] Thirdly, embodiments of this application provide a method for manufacturing a display panel, comprising: providing a first substrate and a second substrate; fabricating a plurality of grid lines on one side of the first substrate, and fabricating a plurality of data lines on the side of the grid lines away from the first substrate, wherein the orthographic projections of the grid lines on the first substrate and the orthographic projections of the data lines on the first substrate intersect in an area, and at least one data line is provided with a receiving cavity, wherein the orthographic projection of the receiving cavity on the first substrate is located within the intersecting area; fabricating a plurality of spacers on one side of the second substrate; aligning the first substrate and the second substrate, wherein during alignment, the plurality of spacers face the first substrate, and at least one spacer's orthographic projection on the first substrate is located within the intersecting area, and the end of the spacer located within the intersecting area away from the second substrate passes through the receiving cavity.

[0017] The beneficial technical effects of the technical solutions provided in this application include:

[0018] In this embodiment, a spacer is disposed between a first substrate and a second substrate, supporting the first and second substrates and creating a predetermined thickness between them. At least one data line has a receiving cavity, the orthographic projection of which onto the first substrate lies within an intersecting region. At least one spacer's orthographic projection onto the first substrate also lies within this intersecting region, with the end of the spacer located away from the second substrate passing through the receiving cavity. The data line acts as a barrier, preventing the spacer from moving relative to the first substrate. This reduces the displacement of the spacer relative to the first substrate, confining it within a certain position. This avoids uneven thickness distribution between the two substrates due to large displacement of the spacer relative to the first substrate, thus effectively supporting the first and second substrates, improving the uniformity of thickness between them, and mitigating display defects.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a partial film layer structure of a display panel provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0024] Figure 4 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application.

[0025] Figure label:

[0026] 10-First substrate; 11-First base; 12-Gate line; 121-First sub-gate line; 122-Second sub-gate line; 13-Data line; 131-Receiving cavity; 132-First sub-data line; 133-Blocking structure; 134-Second sub-data line; 135-First blocking line; 136-Second blocking line; 14-Floating gate line; 15-Passivation layer; 16-Pixel thin film transistor; 17-Drain; 18-Gate insulating layer; 22-Black matrix; 30-Spacer. Detailed Implementation

[0027] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0028] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0030] With the continuous development of display technology, in order to highlight the expression of details to the extreme and improve the customer's viewing experience, TV (Television) display panel resolution has fully entered the 8K era.

[0031] Display products with 8K resolution and high PPI (Pixels Per Inch) have smaller pixel size and a significantly increased density. As a result, 8K resolution display panels have lower transmittance and are more prone to defects caused by the relative displacement of PS (PhotoSpacer) and the substrate. More serious defects include greening when pressed.

[0032] The essence of the "press-induced greening" defect is that when the panel is placed vertically perpendicular to the ground at the viewing angle, gravity causes a certain relative displacement between the array substrate and the color filter substrate. When any point in the middle of the panel is pressed, forcing it to flex and deform, the panel deformation angle is 4.1° to 5.7°. Due to the presence of LC (Liquid Crystal) inside the cell, the array substrate and the color filter substrate undergo a significant relative displacement. When viewed from the front, the BM (Black Matrix) blocking position shifts, failing to completely block light leakage caused by poor alignment in weak areas. The Green pixels with the largest aperture ratio experience the most severe light leakage, manifesting as the "press-induced greening" defect, thus easily leading to a more serious "press-induced greening" problem.

[0033] Specifically, in an 8K display product, a barrier is formed on the top and bottom of the PS. The barrier is set between two adjacent data lines and is located in the pixel opening area. When the Panel is subjected to gravity or external force, which forces the Array substrate and CF substrate to undergo a large relative displacement, the PS will come into contact with the barrier to prevent the relative displacement from increasing further. This prevents the PS from sliding into the opening area and causing green and red-blue spots when pressed.

[0034] The barrier is made of two layers of metal stacked together, and its height is higher than the surrounding structures. The area around the barrier is prone to light leakage due to the weak alignment caused by the step difference (the step difference refers to the mismatch caused by the machining accuracy deviation of the parting surface of the two mold inserts or the front and rear molds).

[0035] In the existing technology, the distance between the barrier and the PS is 25μm, and the distance between the BM border and the PS is 45μm. The greening effect when pressed is too strong and cannot meet the customer's evaluation standards.

[0036] To avoid the aforementioned problems, the BM Mask (Black Matrix Mask) is typically modified by increasing its width to cover a larger area, thereby reducing the green tint caused by pressing. However, this technology has the disadvantage of reduced transmittance, which is particularly significant for 8K display products. It can lead to a 5% reduction in the aperture ratio of Red pixels, a 4% reduction in the aperture ratio of Blue pixels, and an overall panel transmittance reduction of nearly 7%.

[0037] The display panel, its manufacturing method, and the display device provided in this application are intended to solve at least one of the above-mentioned technical problems in the prior art.

[0038] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0039] This application provides a display panel, the structural schematic diagram of which is shown below. Figures 1 to 3 As shown, the display panel includes: a first substrate 10 and a second substrate disposed opposite to each other, and a plurality of spacers 30 located between the first substrate 10 and the second substrate; the first substrate 10 includes a first base 11, a plurality of gate lines 12 and a plurality of data lines 13, the gate lines 12 are disposed on one side of the first base 11, the data lines 13 are disposed on the side of the gate lines 12 away from the first base 11, and the orthographic projections of the gate lines 12 and the data lines 13 on the first base 11 intersect in an area; at least one data line 13 is provided with a receiving cavity 131, the orthographic projection of the receiving cavity 131 on the first base 11 is located in the intersecting area, at least one spacer 30 is located in the orthographic projection of the first base 11 is located in the intersecting area, and the end of the spacer 30 located in the intersecting area away from the second substrate passes through the receiving cavity 131.

[0040] In this embodiment, a spacer 30 is disposed between the first substrate 10 and the second substrate, supporting the first substrate 10 and the second substrate, thereby creating a predetermined thickness between the first substrate 10 and the second substrate. Both the gate line 12 and the data line 13 are disposed on one side of the first substrate 11, which supports the data line 13 and the gate line 12. At least one data line 13 has a receiving cavity 131. The orthographic projection of the receiving cavity 131 on the first substrate 11 is located in the intersecting area. At least one spacer 30 has its orthographic projection on the first substrate 11 located in the intersecting area. The end of the spacer 30 located in the intersecting area away from the second substrate passes through the receiving cavity 131. The data line 13 can block the spacer 30, preventing the spacer 30 from moving relative to the first substrate 11. By blocking the spacer 30 with the data line 13, the displacement of the spacer 30 relative to the first substrate 10 is reduced, and the spacer 30 is confined within a certain position range. This avoids the problem of uneven thickness distribution between the two substrates due to large displacement of the spacer relative to the first substrate. Thus, the spacer 30 effectively supports the first substrate 10 and the second substrate, improves the uniformity of thickness between the first substrate 10 and the second substrate, and improves the problem of poor display image.

[0041] In this embodiment, the orthographic projection of the receiving cavity 131 on the first substrate 11 is located in the intersecting area, and the orthographic projection of at least one spacer 30 on the first substrate 11 is located in the intersecting area. The data line 13 plays a major blocking role for the spacer 30. Therefore, there is no need to set a blocking structure in the pixel opening area, thereby reducing the coverage area of ​​the black matrix, increasing the aperture ratio, and thus improving the transmittance of the display panel.

[0042] Optionally, such as Figure 2 As shown in the embodiment of this application, the first substrate 10 further includes a passivation layer 15. The passivation layer 15 is disposed on the side of the data line 13 away from the first substrate 11. The orthographic projection of the passivation layer 15 on the first substrate 11 covers the orthographic projection of the gate line 12 and the data line 13 on the first substrate 11. The spacer 30 located in the intersection area has one end away from the second substrate located in the receiving cavity 131 and abuts against the passivation layer 15.

[0043] In this embodiment, the spacer 30 passes through the receiving cavity 131 and abuts against the passivation layer 15. The friction between the spacer 30 and the passivation layer 15 provides further blocking, further preventing the spacer 30 from moving relative to the first substrate 11. In addition, the passivation layer 15 also serves to stabilize and flatten the surface.

[0044] In this embodiment, the orthographic projection of the spacer 30 on the first substrate 11 is located in the intersecting region corresponding to the spacer 30. Since the film thickness of the gate line 12 and the data line 13 is higher than that of the pixel opening region, the spacer 30 abuts against the passivation layer 15. The spacer 30 is always in a high-step support and pressure state, with large friction. In addition, the spacer 30 is inserted into the receiving cavity 131, and the sliding distance of the spacer 30 is short.

[0045] In this embodiment, by placing the spacer 30 at the position corresponding to the intersection area of ​​the gate line 12 and the data line 13, and combining it with the gate line 12 and the data line 13 to form a perimeter barrier, the relative displacement of the first substrate 10 and the second substrate is effectively reduced without sacrificing the pixel aperture ratio, fundamentally improving problems such as poor greening upon pressing. This embodiment improves greening upon pressing by reducing the relative displacement of the first substrate 10 and the second substrate during pressing, while also increasing the pixel aperture ratio.

[0046] Optionally, in this embodiment, the spacer 30 is disposed on the side of the second substrate facing the first substrate 10. The second substrate can drive the spacer 30 to move relative to the first substrate 10. Conversely, since the data line 13 and the passivation layer 15 can block the spacer 30, they can prevent the second substrate from moving relative to the first substrate 10, reduce the relative displacement between the second substrate and the first substrate 10, thereby improving the uniformity of the thickness between the first substrate 10 and the second substrate and improving the technical problem of poor display image.

[0047] Optionally, in this embodiment of the application, the second substrate includes a second base and a black matrix 22. The black matrix 22 is disposed on the side of the second base facing the first substrate 10, and the spacer 30 is disposed on the side of the black matrix 22 away from the second base. The orthographic projection of the black matrix 22 on the first base 11 covers the orthographic projection of the spacer 30, the gate line 12 and the data line 13 on the first base 11.

[0048] Optionally, such as Figure 1 As shown in the embodiment of this application, when the resolution of the display panel is 8K, the size d3 of the orthographic projection of the black matrix 22 located between two adjacent data lines 13 on the first substrate 11 along the extension direction of the data line 13 is greater than or equal to 68.4 micrometers and less than or equal to 72.4 micrometers.

[0049] In this embodiment, the spacer 30 is disposed in the intersection area of ​​the data line 13 and the gate line 12. Therefore, there is no need to set a blocking structure in the pixel opening area, thereby causing the black matrix to shrink in the corresponding position, which can reduce the coverage area of ​​the black matrix, increase the aperture ratio, and thus improve the transmittance of the display panel.

[0050] If the size of the orthographic projection of the black matrix 22 located between two adjacent data lines 13 on the first substrate 11 along the extension direction of the data line 13 is less than 68.4 micrometers, the coverage area of ​​the black matrix is ​​small, which easily leads to light leakage; if the size of the orthographic projection of the black matrix 22 located between two adjacent data lines 13 on the first substrate 11 along the extension direction of the data line 13 is greater than 72.4 micrometers, the coverage area of ​​the black matrix is ​​large, resulting in a low aperture ratio and affecting the light transmittance of the display panel.

[0051] In this embodiment, the size d3 of the orthographic projection of the black matrix 22 located between two adjacent data lines 13 on the first substrate 11 along the extension direction of the data line 13 is greater than or equal to 68.4 micrometers and less than or equal to 72.4 micrometers. This effectively avoids light leakage and ensures sufficient light transmittance, with an estimated aperture ratio increase of 2.3%.

[0052] The technical solution of this application optimizes the green color on press while minimizing load changes and improving pixel aperture ratio. Compared to the solution that increases BM width by changing the BM Mask, the aperture ratio of this application is increased by nearly 8%, resulting in higher transmittance.

[0053] Optionally, in this embodiment of the application, the first substrate 10 is an array substrate and the second substrate is a color filter substrate.

[0054] It should be noted that in the embodiments of this application, the structure and specific arrangement of the second substrate and the spacer 30 are similar to those of the prior art, and will not be described again here.

[0055] Optionally, such as Figure 1 As shown in the embodiment of this application, the orthographic projection of the receiving cavity 131 on the first base 11 covers the orthographic projection of the spacer 30 on the first base 11. Along the direction parallel to the first base 11, there is a first preset distance d1 between the inner wall of the receiving cavity 131 and the outer wall of the spacer 30. The first preset distance d1 is greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

[0056] Related research indicates that the key to improving pressure-induced greening is to increase the barrier height, decrease the distance between the barrier and the PS (power supply), and increase the height of the Pillow (support pad) outside the barrier range. This maximizes the barrier's resistance effect when the PS slides, minimizes relative displacement, and ensures the PS remains in a stable compressed state. Stable friction is provided between the array substrate and the CF substrate through the compression and contact of the PS and Pillow. Under the same pressing position and load, the severity of pressure-induced greening is evaluated by assessing the size of the greened area, the intensity of the brightness, and the speed of greening recovery after unloading.

[0057] If the first preset distance d1 is less than 10 micrometers, the distance between the inner wall of the receiving cavity 131 and the outer wall of the spacer 30 is small, and the spacer 30 is easy to detach from the receiving cavity 131, resulting in poor blocking effect. If the first preset distance d1 is greater than 20 micrometers, the distance between the inner wall of the receiving cavity 131 and the outer wall of the spacer 30 is large, the spacer 30 moves a large range relative to the first substrate 11, the blocking effect of the data line 13 on the spacer 30 is weak, and uneven thickness between the first substrate 10 and the second substrate is easily generated.

[0058] In this embodiment, the first preset distance d1 is greater than or equal to 10 micrometers and less than or equal to 20 micrometers. This not only enables the data line 13 to effectively block the spacer 30, but also effectively limits the movement range of the spacer 30, thereby ensuring the uniformity of the thickness between the first substrate 10 and the second substrate.

[0059] Optionally, such as Figure 1 and Figure 3 As shown in the embodiment of this application, the data line 13 with a receiving cavity 131 includes a first sub-data line 132, a blocking structure 133, and a second sub-data line 134 arranged sequentially. The blocking structure 133 includes a first blocking line 135 and a second blocking line 136, which form the receiving cavity 131. One end of the first blocking line 135 is connected to the first sub-data line 132, and the other end of the first blocking line 135 is connected to the second sub-data line 134. The second blocking line 136 is multiplexed as the source of the pixel thin-film transistor 16 of the first substrate 10.

[0060] In this embodiment of the application, the first blocking line 135 and the second blocking line 136 form a receiving cavity 131, and the first blocking line 135 and the second blocking line 136 are used to block the spacer 30.

[0061] In this embodiment of the application, the first preset distance d1 refers to the distance between the inner wall of the first blocking line 135 and the outer wall of the spacer 30, and the distance between the inner wall of the second blocking line 136 and the outer wall of the spacer 30.

[0062] It should be noted that, as Figure 2 As shown in the embodiment of this application, the second blocking line 136 is reused as the source of the pixel thin film transistor 16 of the first substrate 10. The second blocking line 136 and the drain 17 form a source-drain junction. The structure and specific arrangement of other components of the pixel thin film transistor 16 of the first substrate 10 are similar to those in the prior art, and will not be described in detail here.

[0063] Optionally, in this embodiment of the application, the width of the first blocking line 135 along the extending direction of the gate line 12 is greater than or equal to 6 micrometers.

[0064] This configuration ensures that the linewidth of the first blocking line 135 meets the minimum process resolution, thus guaranteeing load stability.

[0065] Optionally, such as Figure 1 and Figure 3 As shown in this embodiment, when passing through the intersecting area, the data line 13 splits into two lines, one of which is a first blocking line 135 and the other is a second blocking line 136. The two lines form a receiving cavity 131, and the second blocking line 136 is also reused as the source of the pixel thin film transistor 16.

[0066] In one alternative implementation, such as Figure 1 As shown, one end of the second blocking line 136 is connected to the first sub-data line 132, and the other end of the second blocking line 136 is connected to the second sub-data line 134.

[0067] Optionally, such as Figure 1 As shown in the embodiment of this application, when one end of the second blocking line 136 is connected to the first sub-data line 132 and the other end of the second blocking line 136 is connected to the second sub-data line 134, the sum of the width of the first blocking line 135 and the width of the second blocking line 136 along the extension direction of the gate line 12 is equal to the width of the first sub-data line 132.

[0068] In this embodiment of the application, when passing through the intersecting area, the data line 13 is split into two strands, but the bus width remains unchanged. That is, along the extension direction of the gate line 12, the sum of the width of the first blocking line 135 and the width of the second blocking line 136 is equal to the width of the first sub-data line 132. This setting can not only ensure that the single strand width meets the minimum resolution of the process, but also ensure load stability.

[0069] In another alternative implementation, such as Figure 3 As shown, the second blocking line 136 is only connected to the second sub-data line 134.

[0070] Of course, in an alternative implementation, the second blocking line 136 may be connected only to the first sub-data line 132, depending on actual needs.

[0071] Optionally, such as Figure 3 As shown in the embodiment of this application, when the second blocking line 136 is connected to one of the first sub-data line 132 and the second sub-data line 134, the width of the first blocking line 135 is equal to the width of the first sub-data line 132 along the extension direction of the gate line 12.

[0072] In this embodiment, the second blocking line 136 between the first sub-data line 132 and the second sub-data line 134 is broken, retaining only the source structure of the pixel thin-film transistor 16. This ensures that the blocking effect of the second blocking line 136 on the spacer 30 remains unchanged, while reducing Cgd (parasitic capacitance) and lightening the load. This solution can be used when the data line width is small, and the width after being divided into two strands is less than the resolution limit of the exposure machine, making the process infeasible. In this case, along the extension direction of the gate line 12, the width of the first blocking line 135 is equal to the width of the first sub-data line 132, and the process is feasible.

[0073] Optionally, such as Figure 1 and Figure 3As shown in the embodiment of this application, corresponding to the blocking structure 133, the gate line 12 includes a first sub-gate line 121 and a second sub-gate line 122 connected to each other. The orthographic projection of the first sub-gate line 121 on the first substrate 11 overlaps with the orthographic projection of the first blocking line 135 on the first substrate 11, and the orthographic projection of the second sub-gate line 122 on the first substrate 11 overlaps with the orthographic projection of the receiving cavity 131 on the first substrate 11. Along the extension direction of the data line 13, the width of the first sub-gate line 121 is smaller than the width of the second sub-gate line 122.

[0074] In this embodiment, the first sub-gate line 121 is narrowed, reducing its orthogonal area to lower Cgd. The second sub-gate line 122 is widened, increasing its orthogonal area to increase Cgd. The width of the first sub-gate line 121 is smaller than the width of the second sub-gate line 122. This design ensures load stability while maintaining constant gate line resistance. Furthermore, widening the second sub-gate line 122 better supports the spacer 30, ensuring the support strength and stability of the display panel.

[0075] It should be noted that the orthographic projection of the receiving cavity 131 on the first base 11 refers to the area enclosed by the orthographic projections of the first blocking line 135 and the second blocking line 136 on the first base 11.

[0076] Optionally, in this embodiment of the application, the width of the first sub-gate line 121 along the extension direction of the data line 13 is greater than or equal to 6 micrometers.

[0077] This configuration ensures that the linewidth of the first sub-gate line 121 meets the minimum process resolution.

[0078] Optionally, such as Figure 1 and Figure 3 As shown in the embodiment of this application, the orthographic projection of the second sub-gate line 122 on the first substrate 11 covers the orthographic projection of the spacer 30 on the first substrate 11.

[0079] In this embodiment, the end of the spacer 30 away from the second substrate abuts against the passivation layer 15. The friction between the spacer 30 and the passivation layer 15 can prevent the spacer 30 from moving. The orthogonal projection of the second sub-gate line 122 on the first substrate 11 covers the orthogonal projection of the spacer 30 on the first substrate 11. This not only enables the second sub-gate line 122 to provide stable support for the passivation layer 15 and the spacer 30, but also increases the friction area between the passivation layer 15 and the spacer 30, thereby improving the blocking effect of the passivation layer 15 on the spacer 30.

[0080] Optionally, such as Figure 1 and Figure 3As shown in the embodiment of this application, the first substrate 10 further includes a floating gate line 14, which is disposed between the first substrate 11 and the data line 13; the orthographic projection of the floating gate line 14 on the first substrate 11 does not overlap with the orthographic projection of the gate line 12 on the first substrate 11; the orthographic projection of the floating gate line 14 on the first substrate 11 overlaps with the orthographic projection of the data line 13 on the first substrate 11.

[0081] Optionally, such as Figure 1 and Figure 3 As shown in the embodiment of this application, the data line 13 is disposed on the side of the gate line 12 away from the first substrate 11. The data line 13 and the gate line 12 are arranged in rows and columns. After the spacer 30 passes through the receiving cavity 131, it abuts against the passivation layer 15 located above the gate line 12. The data line 13 plays a major blocking role against the spacer 30. The friction between the passivation layer 15 located above the gate line 12 and the spacer 30 plays a further blocking role. When the external force is too great, causing the spacer 30 to come out of the receiving cavity 131, the end of the spacer 30 away from the second substrate can abut against the passivation layer 15 on the first sub-data line 132 or the second sub-data line 134 of the data line 13. The friction between the passivation layer 15 on the first sub-data line 132 or the second sub-data line 134 and the spacer 30 prevents the spacer 30 from moving further. The end of the spacer 30 away from the second substrate can also abut against the passivation layer 15 on a portion of the gate line 12 outside the receiving cavity 131. The friction between the passivation layer 15 on the gate line 12 and the spacer 30 prevents the spacer 30 from moving further.

[0082] Specifically, such as Figures 1 to 3 As shown in the embodiment of this application, the orthographic projection of the floating gate line 14 on the first substrate 11 overlaps with the orthographic projection of the first sub-data line 132 on the first substrate 11. The floating gate line 14 provides support for the first sub-data line 132, enabling the passivation layer 15 located on the first sub-data line 132 to contact the spacer 30, thereby ensuring that the spacer 30 can act as a barrier.

[0083] Optionally, such as Figure 1 and Figure 3 As shown in this embodiment, along the extension direction of the gate line 12, the width of the floating gate line 14 is greater than the width of the data line 13.

[0084] In this embodiment, along the extension direction of the gate line 12, the width of the floating gate line 14 is greater than the width of the first sub-data line 132. This arrangement maximizes the overlap between the floating gate line 14 and the first sub-data line 132, thereby increasing the contact area between the passivation layer 15 and the spacer 30 on the first sub-data line 132 and improving the blocking effect.

[0085] Optionally, such as Figure 1 As shown in this embodiment, along the extension direction of the data line 13, the orthographic projection of the floating gate line 14 on the first substrate 11 and the orthographic projection of the spacer 30 on the first substrate 11 have a second preset distance d2, which is greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

[0086] If the second preset distance d2 is less than 10 micrometers, the distance between the floating gate line 14 and the spacer 30 is small, meaning the floating gate line 14 is closer to the gate line 12. If the spacer 30 comes out of the receiving cavity 131 and moves along the first sub-data line 132, the spacer 30 can easily pass over the portion of the first sub-data line 132 supported by the floating gate line 14. The first sub-data line 132 on the side of the floating gate line 14 away from the gate line 12 has no support, making it difficult for the first sub-data line 132 to effectively support the spacer 30, which can easily cause problems such as poor blocking effect, uneven thickness, and poor display. If the second preset distance d2 is greater than 20 micrometers, the distance between the floating gate line 14 and the spacer 30 is large, meaning the floating gate line 14 is farther from the gate line 12, and the blocking effect of the first sub-data line 132 on the spacer 30 is weak.

[0087] In this embodiment, the second preset distance d2 is greater than or equal to 10 micrometers and less than or equal to 20 micrometers, so that the floating gate line 14 can effectively support the first sub-data line 132, thereby enabling the first sub-data line 132 to effectively block the spacer 30.

[0088] In this embodiment, after the spacer 30 is properly aligned with the box, the grid line 12 is flat and its film thickness is lower than that of the data line 13. When a pressing load is applied, the spacer 30 will quickly come into contact with the blocking structure 133, preventing the spacer 30 from moving outside the receiving cavity 131. Even if the spacer 30 is forced to break through the restriction of the blocking structure 133 by a momentary large pressing load, the film thickness of the first sub-data line 132 and the second sub-data line 134 outside the receiving cavity 131 is the same as the film thickness of the blocking structure 133, and the film thickness of other parts of the grid line 12 is the same as the film thickness of the second sub-grid line 122. Its step height is consistent with the initially aligned second sub-grid line 122. The passivation layer 15 located on other parts of the grid line 12 and the second sub-grid line 122 can all abut against the spacer 30. The spacer 30 still has a large compressibility, and the friction will not be lost quickly, effectively improving the greening upon pressing.

[0089] Optionally, in this embodiment, the floating gate line 14 and the gate line 12 are disposed on the same layer.

[0090] This setup simplifies the production process and improves production efficiency.

[0091] It should be noted that the same-layer configuration can refer to the floating gate line 14 and the gate line 12 being formed through a single patterning process.

[0092] Optionally, such as Figure 1 and Figure 3 As shown in the embodiment of this application, the orthographic projection of the floating gate line 14 on the first substrate 11 and the orthographic projection of the gate line 12 on the first substrate 11 are spaced apart along the extension direction of the data line 13. This arrangement avoids the problem of mutual interference and influence between the floating gate line 14 and the gate line 12.

[0093] Optionally, such as Figure 2 As shown in the embodiment of this application, the first substrate 10 further includes a gate insulating layer 18, which is disposed between the gate line 12 and the data line 13 to achieve an insulating connection.

[0094] Optionally, in this embodiment, the first substrate 11 is a glass substrate.

[0095] In an optional embodiment, a PI (polyimide) layer may be provided on the side of the passivation layer 15 away from the first substrate 11, as needed. The orthogonal projection of the PI layer on the first substrate 11 covers the orthogonal projection of the passivation layer 15 on the first substrate 11. In this case, after the cassette is assembled, the spacer 30 abuts against the PI layer.

[0096] The display panel of this application can be applied to the field of large-size TV display panel technology, and especially to high PPI display products with a resolution of 8K series.

[0097] Based on the same inventive concept, an embodiment of this application provides a display device, including: a display panel as described above.

[0098] Specifically, the display device can be any of the following: LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode), Micro LED (Micro Light Emitting Diode), or Mini LED (Mini Light Emitting Diode). The display device can also be any product or component with display function, such as a monitor, television, digital camera, mobile phone, or tablet computer.

[0099] It should be noted that since the display device of this application includes the display panel of this application, the display device of this application also has the above-mentioned beneficial effects of the display panel of this application, which will not be repeated here.

[0100] Based on the same inventive concept, this application provides a method for manufacturing a display panel, the flowchart of which is as follows: Figure 4 As shown, the preparation method includes:

[0101] S101, providing a first substrate 11 and a second substrate;

[0102] S102. Multiple gate lines 12 are formed on one side of the first substrate 11, and multiple data lines 13 are formed on the side of the gate lines 12 away from the first substrate 11. The orthographic projection of the gate lines 12 on the first substrate 11 and the orthographic projection of the data lines 13 on the first substrate 11 have an intersecting area. At least one data line 13 is provided with a receiving cavity 131. The orthographic projection of the receiving cavity 131 on the first substrate 11 is located in the second substrate within the intersecting area.

[0103] S103, Make a plurality of spacers 30 on one side of the second base;

[0104] S104. Align the first base 11 and the second base into a box, such that a plurality of spacers 30 face the first base 11, and such that the orthographic projection of at least one spacer 30 on the first base 11 is located in the intersecting area, and the end of the spacer 30 located in the intersecting area away from the second base passes through the receiving cavity 131.

[0105] The display panel is fabricated using the above-described preparation method.

[0106] In this embodiment, a spacer 30 is disposed between the first substrate 10 and the second substrate, supporting the first substrate 10 and the second substrate, thereby creating a predetermined thickness between the first substrate 10 and the second substrate. Both the gate line 12 and the data line 13 are disposed on one side of the first substrate 11, which supports the data line 13 and the gate line 12. At least one data line 13 has a receiving cavity 131. The orthographic projection of the receiving cavity 131 on the first substrate 11 is located in the intersecting area. At least one spacer 30 has its orthographic projection on the first substrate 11 located in the intersecting area. The end of the spacer 30 located in the intersecting area away from the second substrate passes through the receiving cavity 131. The data line 13 can block the spacer 30, preventing the spacer 30 from moving relative to the first substrate 11. By blocking the spacer 30 with the data line 13, the displacement of the spacer 30 relative to the first substrate 10 is reduced, and the spacer 30 is confined within a certain position range. This avoids the problem of uneven thickness distribution between the two substrates due to large displacement of the spacer relative to the first substrate. Thus, the spacer 30 effectively supports the first substrate 10 and the second substrate, improves the uniformity of thickness between the first substrate 10 and the second substrate, and improves the problem of poor display image.

[0107] Optionally, in this embodiment, the execution order of steps S102 and S103 is not limited. Step S102 can be executed first or step S103 can be executed first, depending on actual needs.

[0108] Optionally, in this embodiment of the application, the method for manufacturing the display panel further includes: providing a passivation layer 15 on the side of the data line 13 away from the first substrate 11, wherein the orthographic projection of the passivation layer 15 on the first substrate 11 covers the orthographic projection of the gate line 12 and the data line 13 on the first substrate 11, and one end of the spacer 30 located in the intersecting area away from the second substrate is located in the receiving cavity 131 and abuts against the passivation layer 15.

[0109] In this embodiment, the spacer 30 passes through the receiving cavity 131 and abuts against the passivation layer 15. The friction between the spacer 30 and the passivation layer 15 provides further blocking, further preventing the spacer 30 from moving relative to the first substrate 11. In addition, the passivation layer 15 also serves to stabilize and flatten the surface.

[0110] Optionally, in this embodiment of the application, the method for manufacturing the display panel further includes: fabricating a black matrix 22 on one side of the second substrate using a patterning process. A spacer 30 is disposed on the side of the black matrix 22 away from the second substrate, such that during assembly, the orthographic projection of the black matrix 22 onto the first substrate 11 covers the orthographic projections of the spacer 30, the gate lines 12, and the data lines 13 onto the first substrate 11.

[0111] Optionally, in this embodiment of the application, a data line 13 with a receiving cavity 131 is fabricated using a patterning process, such that the data line 13 includes a first sub-data line 132, a blocking structure 133, and a second sub-data line 134 arranged sequentially. The blocking structure 133 includes a first blocking line 135 and a second blocking line 136, which together form the receiving cavity 131. One end of the first blocking line 135 is connected to the first sub-data line 132, and the other end is connected to the second sub-data line 134. The second blocking line 136 forms a first base. The source of the pixel thin-film transistor 16 of the plate 10; when one end of the second blocking line 136 is connected to the first sub-data line 132 and the other end of the second blocking line 136 is connected to the second sub-data line 134, the sum of the width of the first blocking line 135 and the width of the second blocking line 136 along the extension direction of the gate line 12 is equal to the width of the first sub-data line 132; when the second blocking line 136 is connected to one of the first sub-data line 132 and the second sub-data line 134, the width of the first blocking line 135 along the extension direction of the gate line 12 is equal to the width of the first sub-data line 132.

[0112] It should be noted that, in this embodiment, the method for fabricating the pixel thin-film transistor 16 of the first substrate 10 is similar to that of the prior art, and will not be described again here.

[0113] Optionally, in this embodiment of the application, before fabricating the data line 13, the method for fabricating the display panel further includes: fabricating a floating gate line 14 on one side of the first substrate 11, such that the orthographic projection of the floating gate line 14 on the first substrate 11 does not overlap with the orthographic projection of the gate line 12 on the first substrate 11, the floating gate line 14 is located between the first substrate 11 and the data line 13, and the orthographic projection of the floating gate line 14 on the first substrate 11 overlaps with the orthographic projection of the data line 13 on the first substrate 11.

[0114] The method for preparing the display panel in this application embodiment can be used to manufacture the display panel in this application embodiment.

[0115] It should be noted that the above patterning process includes the coating, exposure, development, etching of photoresist, and the removal of part or all of the photoresist.

[0116] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0117] In this embodiment, a spacer is disposed between a first substrate and a second substrate, supporting the first and second substrates and creating a predetermined thickness between them. At least one data line has a receiving cavity, the orthographic projection of which onto the first substrate lies within an intersecting region. At least one spacer's orthographic projection onto the first substrate also lies within this intersecting region, with the end of the spacer located away from the second substrate passing through the receiving cavity. The data line acts as a barrier, preventing the spacer from moving relative to the first substrate. This reduces the displacement of the spacer relative to the first substrate, confining it within a certain position. This avoids uneven thickness distribution between the two substrates due to large displacement of the spacer relative to the first substrate, thus effectively supporting the first and second substrates, improving the uniformity of thickness between them, and mitigating display defects.

[0118] In this embodiment, the orthographic projection of the receiving cavity on the first substrate is located within the intersecting area, and the orthographic projection of at least one spacer on the first substrate is located within the intersecting area. The data line plays a major blocking role for the spacer. Therefore, there is no need to set a blocking structure in the pixel opening area, thereby reducing the coverage area of ​​the black matrix, increasing the aperture ratio, and thus improving the transmittance of the display panel.

[0119] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0120] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0121] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0122] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0123] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0124] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0125] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: A first substrate and a second substrate disposed opposite to each other, and a plurality of spacers located between the first substrate and the second substrate; The first substrate includes a first base, multiple gate lines and multiple data lines. The gate lines are disposed on one side of the first base, and the data lines are disposed on the side of the gate lines away from the first base. The orthographic projection of the gate lines on the first base and the orthographic projection of the data lines on the first base have an intersecting area. At least one of the data lines is provided with a receiving cavity, the orthographic projection of the receiving cavity on the first substrate is located in the intersecting area, the orthographic projection of the receiving cavity on the first substrate is a closed structure, at least one of the spacers is located in the intersecting area, and the end of the spacer located in the intersecting area away from the second substrate passes through the receiving cavity; The data line with the receiving cavity includes a first sub-data line, a blocking structure, and a second sub-data line arranged sequentially. The blocking structure includes a first blocking line and a second blocking line, and the first blocking line and the second blocking line form the receiving cavity. Corresponding to the blocking structure, the grid line includes a first sub-grid line and a second sub-grid line connected to each other. The orthographic projection of the first sub-grid line on the first substrate overlaps with the orthographic projection of the first blocking line on the first substrate, and the orthographic projection of the second sub-grid line on the first substrate overlaps with the orthographic projection of the receiving cavity on the first substrate. Along the extension direction of the data line, the width of the first sub-gate line is smaller than the width of the second sub-gate line; The orthographic projection of the second sub-grid line onto the first substrate covers the orthographic projection of the spacer onto the first substrate.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the receiving cavity onto the first substrate covers the orthographic projection of the spacer onto the first substrate. Along a direction parallel to the first substrate, there is a first preset distance between the inner wall of the receiving cavity and the outer wall of the spacer, the first preset distance being greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

3. The display panel according to claim 1 or 2, characterized in that, One end of the first blocking line is connected to the first sub-data line, and the other end of the first blocking line is connected to the second sub-data line; The second blocking line is connected to at least one of the first sub-data line and the second sub-data line; The second blocking line is reused as the source of the pixel thin-film transistor of the first substrate.

4. The display panel according to claim 3, characterized in that, One end of the second blocking line is connected to the first sub-data line, and the other end of the second blocking line is connected to the second sub-data line; along the extending direction of the gate line, the sum of the width of the first blocking line and the width of the second blocking line is equal to the width of the first sub-data line; or... The second blocking line is connected to one of the first sub-data line and the second sub-data line; along the extension direction of the gate line, the width of the first blocking line is equal to the width of the first sub-data line.

5. The display panel according to claim 3, characterized in that, Along the direction of the extension of the gate line, the width of the first blocking line is greater than or equal to 6 micrometers.

6. The display panel according to claim 3, characterized in that, The first substrate further includes a passivation layer disposed on the side of the data line away from the first substrate. The orthographic projection of the passivation layer on the first substrate covers the orthographic projection of the gate line and the data line on the first substrate. The end of the spacer located in the intersection area away from the second substrate is located in the receiving cavity and abuts against the passivation layer.

7. The display panel according to claim 6, characterized in that, Along the direction of the data line, the width of the first sub-gate line is greater than or equal to 6 micrometers.

8. The display panel according to claim 1 or 2, characterized in that, The first substrate further includes a floating gate line, which is disposed between the first substrate and the data line; The orthographic projection of the floating gate line on the first substrate does not overlap with the orthographic projection of the gate line on the first substrate; The orthographic projection of the floating gate line on the first substrate overlaps with the orthographic projection of the data line on the first substrate.

9. The display panel according to claim 8, characterized in that, Along the extending direction of the gate line, the width of the floating gate line is greater than the width of the data line; and / or, Along the extension direction of the data line, there is a second preset distance between the orthographic projection of the floating gate line on the first substrate and the orthographic projection of the spacer on the first substrate, the second preset distance being greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

10. The display panel according to claim 8, characterized in that, The floating gate line is disposed on the same layer as the gate line, and the orthographic projection of the floating gate line on the first substrate and the orthographic projection of the gate line on the first substrate are spaced apart along the extension direction of the data line.

11. The display panel according to claim 1 or 2, characterized in that, The second substrate includes a second base and a black matrix. The black matrix is ​​disposed on the side of the second base facing the first substrate, and the spacer is disposed on the side of the black matrix away from the second base. The orthographic projection of the black matrix on the first base covers the orthographic projection of the spacer, the gate line, and the data line on the first base.

12. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 11.

13. A method for manufacturing a display panel, characterized in that, include: A first substrate and a second substrate are provided; Multiple grid lines are fabricated on one side of the first substrate, and multiple data lines are fabricated on the side of the grid lines away from the first substrate. The orthographic projection of the grid lines on the first substrate and the orthographic projection of the data lines on the first substrate have an intersecting area. At least one of the data lines is provided with a receiving cavity. The orthographic projection of the receiving cavity on the first substrate is located within the intersecting area, and the orthographic projection of the receiving cavity on the first substrate is a closed structure. Multiple spacers are fabricated on one side of the second substrate; The first base and the second base are aligned, such that the plurality of spacers face the first base, and the orthographic projection of at least one of the spacers on the first base is located within the intersection area, and the end of the spacer located within the intersection area that is away from the second base passes through the receiving cavity; The data line with the receiving cavity includes a first sub-data line, a blocking structure, and a second sub-data line arranged sequentially. The blocking structure includes a first blocking line and a second blocking line, and the first blocking line and the second blocking line form the receiving cavity. Corresponding to the blocking structure, the grid line includes a first sub-grid line and a second sub-grid line connected to each other. The orthographic projection of the first sub-grid line on the first substrate overlaps with the orthographic projection of the first blocking line on the first substrate, and the orthographic projection of the second sub-grid line on the first substrate overlaps with the orthographic projection of the receiving cavity on the first substrate. Along the extension direction of the data line, the width of the first sub-gate line is smaller than the width of the second sub-gate line; The orthographic projection of the second sub-grid line onto the first substrate covers the orthographic projection of the spacer onto the first substrate.

Images