Die position detection for a packet memory die

Abstract

This application relates to die location detection for a package of memory dies. A memory device can include a plurality of memory dies coupled with a shared bus. In some examples, each memory die can include circuitry configured to output an identifier associated with a location of the respective memory die. For example, a first memory die can output, based on receiving one or more signals, a first identifier that identifies a location of the first memory die. Identifying the location of the respective memory die can allow the dies to be individually accessed even though coupled with a shared bus.

Description

[0001] Cross Reference

[0002] This patent application is a national phase filing of International Patent Application No. PCT / US2022 / 074748, filed by Lee et al. on August 10, 2022, entitled “DIE LOCATION DETECTION FOR GROUPED MEMORY DIES,” which claims the benefit of U.S. Patent Application No. 17 / 818,413, filed by Lee et al. on August 9, 2022, entitled “DIE LOCATION DETECTION FOR GROUPED MEMORY DIES,” and U.S. Provisional Patent Application No. 63 / 232,973, filed by Lee et al. on August 13, 2021, entitled “DIE LOCATION DETECTION FOR GROUPED MEMORY DIES,” each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to die location detection for grouping memory dies. Background Art

[0004] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory devices such as FeRAM can maintain their stored logic state for a long time even in the absence of external power. Volatile memory devices such as DRAM may lose their stored state when disconnected from an external power source. Summary of the Invention

[0005] An apparatus is described. The apparatus can include a command / address channel; a first memory die coupled with the command / address channel and comprising a first circuit configured to output a first identifier of the first memory die based at least in part on receiving a first signal to enable the first circuit and detecting a first value of a second signal; a first register coupled with the first circuit and configured to store the first identifier of the first memory die based at least in part on the first circuit outputting the first identifier; a second memory die coupled with the command / address channel and comprising a second circuit configured to output a second identifier of the second memory die based at least in part on receiving the first signal to enable the second circuit and detecting a second value of a third signal; and a second register coupled with the second circuit and configured to store the second identifier of the second memory die based at least in part on the second circuit outputting the second identifier.

[0006] A method is described. The method can include receiving, at a first memory die and a second memory die, a first signal to enable circuits of the first memory die and the second memory die; detecting, by a first circuit of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal; storing, at a register associated with the first memory die, a first identifier of the first position of the first memory die based at least in part on detecting the first value of the second signal; detecting, by a second circuit of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal; and storing, at a register associated with the second memory die, a second identifier of the second position of the second memory die based at least in part on detecting the second value of the third signal.

[0007] An apparatus is described. The apparatus can include a first memory die coupled with a command / address channel and comprising a first circuit, a second memory die coupled with the command / address channel and comprising a second circuit, a register coupled with the first circuit and the second circuit, a controller coupled with the first memory die and the second memory die, wherein the controller is configured to cause the apparatus to receive, at the first memory die and the second memory die, a first signal to enable the first circuit and the second circuit, detect, by the first circuit of the first memory die, based at least in part on receiving the first signal, a first value of a second signal associated with a first position of the first memory die relative to the second memory die, store, at the register, based at least in part on detecting the first value of the second signal, a first identifier of the first position of the first memory die, detect, by the second circuit of the second memory die, based at least in part on receiving the first signal, a second value of a third signal associated with a second position of the second memory die relative to the first memory die, and store, at the register, based at least in part on detecting the second value of the third signal, a second identifier of the second position of the second memory die.

[0008] An apparatus is described. The apparatus can include means for receiving, at a first memory die and a second memory die, a first signal to enable circuits of the first memory die and the second memory die, means for detecting, by a first circuit of the first memory die, based at least in part on receiving the first signal, a first value of a second signal associated with a first position of the first memory die relative to the second memory die, means for storing, at a register associated with the first memory die, based at least in part on detecting the first value of the second signal, a first identifier of the first position of the first memory die, means for detecting, by a second circuit of the second memory die, based at least in part on receiving the first signal, a second value of a third signal associated with a second position of the second memory die relative to the first memory die, and means for storing, at a register associated with the second memory die, based at least in part on detecting the second value of the third signal, a second identifier of the second position of the second memory die.

[0009] A non-transitory computer-readable medium storing code includes instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive, at a first memory die and a second memory die, a first signal to enable circuitry of the first memory die and the second memory die; based at least in part on receiving the first signal, detect, by a first circuit of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die; based at least in part on detecting the first value of the second signal, store a first identifier of the first position of the first memory die in a register associated with the first memory die; based at least in part on receiving the first signal, detect, by a second circuit of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die; and based at least in part on detecting the second value of the third signal, store a second identifier of the second position of the second memory die in a register associated with the second memory die. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting die location detection of grouped memory dies according to examples disclosed herein is shown.

[0011] Figure 2 An example of a memory die supporting die location detection for grouped memory dies according to examples disclosed herein is shown.

[0012] Figure 3 An example of a memory die configuration supporting die location detection for grouped memory dies according to examples disclosed herein is shown.

[0013] Figure 4 An example of a circuit diagram supporting die location detection for grouped memory dies according to examples disclosed herein is shown.

[0014] Figure 5 A block diagram illustrating a memory device supporting die location detection for grouped memory dies according to examples disclosed herein.

[0015] Figure 6 A flow chart is shown illustrating one or more methods supporting die location detection for grouped memory dies according to examples disclosed herein. DETAILED DESCRIPTION

[0016] A memory device may include a collection of multiple memory dies that can be grouped together for command and control operations and data access operations. Each memory die in the group may be coupled to the same command / address (CA) channel (sometimes referred to as a CA bus) and may each be operated on by the same command transmitted via the CA channel. For example, if the CA channel transmits a register write command, each memory die in the group may respond by performing a register write operation (e.g., as indicated by the register write command). However, some commands may be specific to one memory die in the group, but each memory die in the group may execute die-specific commands, for example, because the memory dies share the CA channel.

[0017] To support access to one memory die in a group or a subset of the memory die in a group, the present disclosure provides techniques for identifying the location of a specific memory die (or multiple memory die) in the group. For example, each memory die in the group may include circuitry (e.g., location detection circuitry as described herein) configured to output an identifier associated with its location. In some cases, the memory die may output the respective identifier based on its circuitry receiving one or more signals. After outputting the identifier, the identifier may be stored in a non-volatile read-only memory associated with the memory die, so that the identifier can be used to identify the location of the memory die during subsequent operations (e.g., access operations). In other words, storing the location of the memory die in the non-volatile read-only memory allows the execution of die-specific commands. As a result, each memory die in the group can be individually accessed even when coupled to a shared CA channel, which can improve the overall efficiency of the memory system.

[0018] As reference Figure 1 and 2 As described, the features of the present disclosure are first described in the context of systems and dies. Figure 3 and 4 Features of the present disclosure are described in the context of the memory die configuration and circuit diagrams described. Figure 5 and 6 The described apparatus diagrams and flow diagrams relating to die location detection for grouped memory dies further illustrate and describe these and other features of the present disclosure.

[0019] Figure 1An example of a system 100 that supports die location detection for grouped memory dies according to examples disclosed herein is shown. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., memory device 110).

[0020] System 100 may include a portion of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, etc. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

[0021] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0022] Memory device 110 may be a standalone device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to operate with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme for modulating signals, various pin configurations for transmitting signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0023] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as a secondary or slave device (e.g., by external memory controller 120 responding to and executing commands provided by host device 105) of host device 105. Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0024] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. Components of host device 105 can be coupled with each other using bus 135.

[0025] Processor 125 can be operable to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In this example, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by processor 125 or be a portion of the processor.

[0026] BIOS component 130 can be a software component that includes a BIOS that operates as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and the various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0027] The memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 can be a set of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sections), where each memory cell is operable to store at least one bit of data. A memory device 110 that includes two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0028] The memory dies 160 can be an example of a two-dimensional (2D) array of memory cells, or can be an example of a three-dimensional (3D) array of memory cells. A 2D memory die 160 can include a single memory array 170. A 3D memory die 160 can include two or more memory arrays 170 that can be stacked together or positioned in close proximity to one another (e.g., with respect to a substrate). In some examples, the memory arrays 170 in a 3D memory die 160 can be referred to as tiers, levels, layers, or dies. A 3D memory die 160 can include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high stacked memory arrays). In some 3D memory dies 160, different tiers can share at least one common access line, such that some tiers can share at least one of a word line, a digit line, or a plate line.

[0029] The device memory controller 155 can include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 can include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and can be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 can be operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 can control the operation of the memory device 110 described herein in conjunction with the local memory controllers 165 of the memory dies 160.

[0030] A local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., to receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120, which may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0031] The external memory controller 120 is operable to enable one or more of information, data, or commands to be transferred between components of the system 100 or host device 105 (e.g., processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or their functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0032] Components of host device 105 can use one or more channels 115 to exchange information with memory device 110. Channels 115 can be used to support communication between external memory controller 120 and memory device 110. Each channel 115 can be an example of a transmission medium that carries information between host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path can be an example of a conductive path operable to carry a signal. For example, channel 115 can include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be used to serve as part of a channel.

[0033] Channels 115 (and associated signal paths and terminals) can be dedicated to transmitting one or more types of information. For example, channels 115 may include one or more CA channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be transmitted on channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both the rising and falling edges of a clock signal).

[0034] In some examples, CA channel 186 is operable to communicate commands between host device 105 and memory device 110, the commands including control information associated with the commands (e.g., address information). For example, the commands carried by CA channel 186 may include a read command with the address of the desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) to decode one or more of the address or command data. As described herein, CA channel 186 may be coupled to more than one memory array 170. In some cases, memory arrays 170 can be individually accessed even when coupled to a shared CA channel, which can improve the overall efficiency of memory device 110.

[0035] Memory device 110 may be an example of a CXL device, and memory device memory controller 155 may be an example of a device configured to access memory die 160 or one or more memory arrays 170 of memory die 160. For example, memory die 160-a may include multiple memory arrays 170 coupled to a shared channel (e.g., CA channel 186). During the manufacture of memory die 160, each individual memory die 160 may not be assigned a location. That is, memory die 160-a (or the memory arrays 170-a of memory die 160-a) may not be individually accessible. Therefore, commands transmitted via CA channel 186 may be received by each memory die 160 coupled to the bus, which may increase processing overhead for memory device 110.

[0036] As described herein, each memory die 160 may include circuitry configured to output an identifier associated with its location (e.g., location detection circuitry as described herein). In some cases, a memory die 160 may output a respective identifier based on its circuitry receiving one or more signals. Furthermore, the identifier may be stored in a non-volatile read-only memory associated with the memory die 160 so that during subsequent operations (e.g., access operations), the identifier can be used to identify the location of the memory die 160. In other words, storing the location of the memory die 160 in the non-volatile read-only memory may allow the device memory controller 155 to access a particular memory die 160 based on its location. Thus, each memory die 160 can be individually accessed even when coupled to a shared CA channel 186, which may improve the overall efficiency of the memory device 110.

[0037] Figure 2 An example of a memory die 200 supporting die location detection for grouped memory dies according to examples disclosed herein is shown. The memory die 200 may be a reference Figure 1 1 . An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205 that may each be programmed to store a different logical state (e.g., programmed to one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, as shown in FIG. Figure 1 Memory array 170 is depicted.

[0038] Memory cell 205 can store a charge representing a programmable state in a capacitor. DRAM architectures may include capacitors comprising dielectric materials to store the charge representing the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be used. Memory cell 205 may include a logic storage component, such as capacitor 230, and a switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

[0039] Memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, may be interchangeable without affecting understanding or operation. A memory cell 205 may be positioned at the intersection of a word line 210 and a digit line 215.

[0040] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting one or more access lines, such as word lines 210 or digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or digit lines 215), a single memory cell 205 can be accessed at their intersection. The intersection of the word lines 210 and digit lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205.

[0041] Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word lines 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and activate the digit lines 215 based on the received column address.

[0042] Selection or deselection of memory cell 205 can be achieved by activating or deactivating switch component 235 using word line 210. Capacitor 230 can be coupled to digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 can be coupled to digit line 215.

[0043] Sense component 245 is operable to detect a state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine a logic state of memory cell 205 based on the stored state. Sense component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing memory cell 205. Sense component 245 may compare the signal detected from memory cell 205 to reference 250 (e.g., a reference voltage). The detected logic state of memory cell 205 may be provided as an output of sense component 245 (e.g., to input / output 255) and may be indicated to another component of a memory device including memory die 200.

[0044] The local memory controller 260 can control access to the memory cell 205 through various components (eg, row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on the one or more operations performed. The local memory controller 260 can generate row signals and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating memory die 200 .

[0045] The local memory controller 260 may be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0046] Memory die 200 can be an example of a CXL device (or a portion of a CXL device), and local memory controller 260 can be an example of a processing unit configured to access memory die 200. For example, memory die 200 can be located in a memory system having a plurality of memory dies (e.g., memory dies 160 as described with reference to FIG. 1) coupled with a CA channel (e.g., CA channel 186 as described with reference to Figure 1 FIG. 1). In some cases, CA channel can be an example of a channel that couples (e.g., is shared among) a plurality of memory dies 200. During manufacturing of a memory system that includes memory dies 200, memory dies 200 are not assigned a location. That is, memory dies 200 can not be individually accessible. Thus, commands transmitted via CA channel can be received by each memory die (e.g., including memory dies 200) coupled with CA channel, which can increase processing overhead for the associated memory system. Figure 1 As described herein, memory die 200 can include circuitry configured to output an identifier associated with its location (e.g., location detection circuitry as described herein). In some cases, memory die 200 can output a respective identifier based on one or more signals received by its circuitry. Further, the identifier can be stored to a non-volatile read-only memory associated with memory die 200, such that during subsequent operations (e.g., access operations), the identifier can be used to identify the location of memory die 200. That is, storing the location of a memory die to a non-volatile read-only memory can allow local memory controller 260 to access memory die 200 based on its location. Thus, memory die 200 (and other memory dies included in the same memory system) can be individually accessible even though coupled with a shared CA channel, which can improve the overall efficiency of the associated memory system.

[0047]

[0048] An example of a memory die configuration 300 that supports die location detection for grouped memory dies in accordance with examples as disclosed herein is shown. Memory die configuration 300 can represent a portion or a portion of a memory system as described herein with reference to Figure 3 FIG. 1 and FIG. 2. For example, memory die configuration 300 can include a group 305 of memory dies 310, where each of memory dies 310 can represent memory dies 160 as described with reference to Figure 1 FIG. 1 and FIG. 2. For example, memory die configuration 300 can include a group 305 of memory dies 310, where each of memory dies 310 can represent memory dies 160 as described with reference to 2 FIG. 1 and FIG. 2. For example, memory die configuration 300 can include a group 305 of memory dies 310, where each of memory dies 310 can represent memory dies 160 as described with reference to Figure 1 FIG. 1 and FIG. 2. For example, memory die configuration 300 can include a group 305 of memory dies 310, where each of memory dies 310 can represent memory dies 160 as described with reference to 2The corresponding memory die (e.g., memory die 160) described above. The group 305 of memory dies 310 can include a number of memory dies 310 (e.g., four memory dies 310) that can share the same CA channel 315 (e.g., can each be coupled to the same CA channel 315). The CA channel 315 can represent a reference Figure 1 Additionally or alternatively, CA channel 315 may represent a chip select (CS) channel that may be used to select one or more memory chips of a memory device (eg, in addition to being used as a CA channel, a CK channel, or both).

[0049] If through Figure 3 As shown, each memory die 310 can be coupled to a CA channel 315, for example, via one or more electrical connections, traces, or electrodes (among other examples). In some cases, each memory die 310 can be directly coupled to a CA channel 315, while in some other cases, each memory die 310 can be coupled to a CA channel 315 via another memory die 310. As described herein, memory dies 310 coupled to a CA channel 315 via direct connections 325 (e.g., traces or electrodes) can be referred to as interface dies 310 (or one interface die 310), while memory dies 310 indirectly coupled to a CA channel 315 can be referred to as link dies 310 (or one link die 310). For example, memory die 310-a may be coupled to CA channel 315 via connection 325-a (e.g., traces or electrodes) and may therefore be referred to as interface die 310-a, while memory die 310-b may be coupled to memory die 310-a via connection 325-g and may therefore be referred to as linking die 310-b. Each of memory dies 310-a through 310-d may be either an interface die 310 or a linking die 310, depending on how the respective die is coupled to CA channel 315. Memory die 310-b may be coupled to CA channel 315 via connector 325-a and connector 325-b; memory die 310-c may be coupled to CA channel 315 via connector 325-a, connector 325-b, and connector 325-c; and memory die 310-d may be coupled to CA channel 315 via connector 325-a, connector 325-b, connector 325-c, and connector 325-d.

[0050] Each memory die 310 can be coupled to a corresponding DQ channel 320. A first set of memory dies 310 (e.g., memory die 310-a and memory die 310-b) can share a first DQ channel (e.g., can both be coupled to DQ channel 320-a), and a second set of memory dies 310 (e.g., memory die 310-c and memory die 310-d) can share a second DQ channel (e.g., can both be coupled to DQ channel 320-b). Each memory die 310 can be coupled to a corresponding DQ channel 320 via one or more electrical connections, traces, or electrodes (e.g., and other examples). In some cases, each memory die 310 can be directly coupled to a corresponding DQ channel 320, while in some other cases, each memory die 310 can be coupled to a corresponding DQ channel 320 via another memory die 310.

[0051] For example, memory die 310-a may be coupled to DQ channel 320-a via connector 325-e, and memory die 310-b may be coupled to DQ channel 320-a via connector 325-g and connector 325-e. Similarly, memory die 310-c may be coupled to DQ channel 320-b via connector 325-f, and memory die 310-d may be coupled to DQ channel 320-b via connector 325-h and connector 325-f.

[0052] For example, grouping the memory dies 310 in a group 305 can be referred to as one group 305 per rank per channel, based on each memory die 310 in the group 305 being coupled to (e.g., and operable by) the same CA channel 315 (e.g., a CA channel, a CK channel, a CS channel, or any combination). Because the memory dies 310 share the same CA channel 315, the memory dies 310 can receive the same command (e.g., simultaneously) via the CA channel 315 and can all operate on the received command.

[0053] In some cases, memory die configuration 300 can be part of, or represent an example of, a CXL configuration for a memory device. For example, the interface for group 305 of memory dies, represented by CA channel 315 and DQ channels 320-a and 320-b, can be an interface configured for the CXL protocol. While some examples described herein refer to memory die 310 configured according to one or more CXL protocols, the same examples are applicable to any configuration of memory die 310 coupled to the same CA channel 315.

[0054] As described herein, memory dies 310 may be independently accessed (e.g., by reference to a CA channel 315) even when coupled to the same CA channel 315. Figure 1310 ). In some cases, during the manufacture of the group 305, the associated memory dies 310 may not be assigned a location. For example, the memory dies may be manufactured in batches and may be assembled in the memory system in any order. Thus, the location of any given memory die in the memory system (relative to the other memory dies) may not be known until after the system is assembled. Therefore, to support individual access at a memory die 310 (e.g., or a subset of the memory dies 310 of the group 305), the present disclosure provides techniques for identifying and outputting identifiers associated with the locations of the respective memory dies 310 from one or more memory dies 310. Thus, commands transmitted via the CA channel 315 may be received by each memory die 310 coupled to the CA channel 315, which may increase the processing overhead of the associated memory device.

[0055] Each memory die 310 may include circuitry configured to output an identifier associated with its location (e.g., location detection circuitry as described herein). In some cases, the memory die 310 may output the respective identifier based on its circuitry receiving one or more signals. Furthermore, the identifier may be stored in a non-volatile read-only memory associated with the memory die 310 so that during subsequent operations (e.g., access operations), the identifier can be used to identify the location of the memory die 310. In other words, storing the location of the memory die 310 in the non-volatile read-only memory may allow individual access to the memory die 310 based on its location. Thus, each memory die 310 can be individually accessed even when coupled to a CA channel 315, which may improve the overall efficiency of the associated memory device or memory system.

[0056] Figure 4 An example of a circuit diagram 400 supporting die location detection for grouped memory dies according to examples disclosed herein is shown. The circuit diagram 400 may illustrate communication with a host system (e.g., a reference system) via a CA channel (not shown). Figure 1 1 and 10. A host device 105 (described above) may be coupled to a first memory die 405-a and a second memory die 405-b. In some examples, a CA channel may be coupled to multiple memory dies 405, and each memory die 405 may be individually accessed by the host system. For example, the first memory die 405-a and the second memory die 405-b may each include respective circuitry 410 (e.g., respective location detection circuitry 410) operable to identify the location of the respective memory die 405 after assembly. By individually accessing one or more memory dies 405, the overall efficiency of the associated memory system may be improved.

[0057] Circuit diagram 400 may illustrate a first memory die 405-a and a second memory die 405-b. Each memory die 405 may include circuitry 410 (e.g., position detection circuitry 410) operable to identify the location of the respective memory die 405 relative to the other memory die in the system. The locations of the memory dies may be used to indicate which memory die is to enter single-die access mode. The first memory die 405-a may include a first position detection circuit 410-a operable to identify the location of the first memory die 405-a so that the first memory die 405-a may be individually accessed by the host system (e.g., the host system may transmit commands directly to the first memory die using a shared CA channel). Similarly, the second memory die 405-b may include a second location detection circuit 410-b, which is operable to identify the location of the second memory die 405-b so that the second memory die 405-b can be individually accessed by the host system (for example, the host system can use the shared CA channel to transmit commands directly to the first memory die).

[0058] Each position detection circuit 410 may include an inverter 415, a latch 420, a pull-down circuit 425, and an anode 430. The inverter 415 may be configured to invert the value of the signal received by the corresponding position detection circuit 410. In some cases, the inverter 415 may be configured to invert the value of the signal received from the corresponding pull-down circuit 425. The pull-down circuit 425, which may be or may be referred to as a weak pull-down circuit 425, may adjust (e.g., adjust downward) the value of the signal received by the corresponding position detection circuit 410. In some cases, the pull-down circuit 425 may include one or more resistors (e.g., connected in parallel or in series) that adjust the value of the received signal.

[0059] Additionally or alternatively, latches 420 may be coupled to respective nodes 430 and may be configured to latch the value of a received signal and output the signal to respective multiplexers 435. For example, latch 420-a may receive a signal based on the voltage of first node 430-a, and the voltage of first node 430-a may be based on a signal received from pull-down circuit 425-a or from another source. Similarly, latch 420-b may receive a signal based on the voltage of second node 430-b, and the voltage of second node 430-b may be based on a signal received from pull-down circuit 425-b or from another source. Each latch 420 stores a respective received signal (e.g., a value associated with the respective received signal) and may output a received signal (e.g., an identifier associated with the respective memory die 405) to the respective multiplexers 435. As described herein, the respective multiplexers 435 may output a signal indicating the location of the respective memory die 405.

[0060] Each memory die 405 can include at least one multiplexer 435. For example, the first memory die 405-a can include a multiplexer 435-a (e.g., a first multiplexer 435-a) coupled with a first input 480-a, a second input 485-a, and a control signal 475-a (e.g., a first signal). Similarly, the second memory die 405-b can include a multiplexer 435-b (e.g., a second multiplexer 435-b) coupled with a first input 480-b, a second input 485-b, and a control signal 475-b. In some cases, the control signal 475-a and the control signal 475-b can be the same control signal that is activated to initiate a location detection operation for the memory dies 405 (e.g., the control signal 475 can activate the respective location detection circuit 410 and also cause the respective multiplexer 435 to output the first input 480).

[0061] In some examples, the multiplexer 435 can be coupled with the first input 480, which is associated with an output from the respective latch 420. That is, each latch 420 can output a respective identifier that can be received at the first input 480 of the respective multiplexer 435. During a location detection operation for the memory dies 405, each multiplexer 435 can receive the control signal 475, which can cause the multiplexer 435 to output the first input 480 (e.g., via the output 490). For example, the latch 420-a can output an identifier of the first memory die 405-a (e.g., an identifier indicative of a location of the first memory die 405-a). Based on the multiplexer 435-a receiving the control signal 475-a, the multiplexer 435-a can output the identifier of the first memory die 405-a.

[0062] In some cases, the output 490 of each multiplexer can be coupled with one or more registers (e.g., a mode register; not shown). Thus, in response to the multiplexer 435 outputting an identifier of the respective memory die 405, the identifier can be stored to the register (or respective registers) and can subsequently be stored to a non-volatile read-only memory associated with the respective memory die 405. For example, a portion of each memory die 405 can include a non-volatile read-only memory, which can be or can include a set of fuses or anti-fuses. Thus, storing an identifier of the respective memory die 405 can include applying a current to one or more fuses or anti-fuses to alter a state of the respective fuse or anti-fuse. In some cases, this operation can be referred to as “blowing a fuse” or “blowing an anti-fuse.”

[0063] Thus, after performing a location detection operation for a memory die 405 (e.g., after one or more identifiers are stored in the corresponding non-volatile read-only memory), control signal 475 may no longer be applied to multiplexer 435, which may cause multiplexer 435 to output a second input 485 (e.g., via output 490). For example, multiplexer 435-a may output the identifier of the first memory die 405-a stored in its non-volatile read-only memory (e.g., multiplexer 435-a may output the fzDieLoc[0] signal). Thus, during subsequent operations (e.g., access operations), memory die 405 may be configured to output their respective location information, which may allow the memory die 405 to be individually accessed even when coupled to a shared CA channel.

[0064] In some cases, the control signal 475 may also be associated with one or more other operations of the corresponding memory die 405. For example, the control signal 475-a may be coupled to the circuit system 440-a, which is associated with or configured to perform other operations (e.g., access operations) on the first memory die 405-a. Thus, in response to the control signal 475-a being enabled, the first position detection circuit 410-a may be enabled and the circuit system 440-a may be disabled, and vice versa. Similarly, the control signal 475-b may be coupled to the circuit system 440-b, which is associated with or configured to perform other operations (e.g., access operations) on the second memory die 405-b. Thus, in response to the control signal 475-b being enabled, the second position detection circuit 410-b may be enabled and the circuit system 440-b may be disabled, and vice versa.

[0065] The position detection circuit 410 described herein can be configured to output an identifier based on receiving one or more signals. In some cases, the memory die 405 can be coupled to one or more pins, pads, or voltage sources that are configured to initiate, receive, or relay signals. Furthermore, in some cases, the first memory die 405-a can be coupled to the second memory die 405-b via bond wires 457.

[0066] In some examples, the first position detection circuit 410-a may be coupled to a pin 445. In some cases, the pin 445 may actually be a pad 445 coupled to a voltage source. The pin 445 may be configured to receive a signal having a first value (e.g., the second signal). For example, the pin 445 may be configured to receive a signal having a negative voltage value (e.g., -1.0V). Additionally or alternatively, the first position detection circuit 410-a may be coupled to a voltage source 450. In some cases, the voltage source 450 may be a negative or ground voltage source coupled to the first node 430-a. Thus, based on the voltage source 450, the voltage of the first node 430-a may be at or below zero volts (0V).

[0067] The first memory die 405-a may also include a pin 455 that is coupled to a pin 460 of the second memory die 405-b via a bond wire 457. In some cases, pins 455 and 460 may actually be pads (e.g., pads 455 and 460) coupled to bond wire 457. Pin 455 may be configured to receive an inverted signal from inverter 415-a. The signal may be inverted relative to the signal received by pin 445 and may also have been pulled down by pull-down circuit 425-a. For example, pin 455 may be configured to receive a signal with a slightly lower positive voltage value than the signal received by pin 445 (e.g., the signal may be approximately 0.8V).

[0068] Additionally or alternatively, the second position detection circuit 410-b can be coupled to a voltage source 465. In some cases, the voltage source 465 can be a positive voltage source (e.g., Vcc) coupled to the second node 430-b. Thus, based on the voltage source 465, the voltage at the second node 430-b can be higher than zero volts (0V). The second position detection circuit 410-b can also include a pin 470 configured to receive an inverted signal from the inverter 415-b. The pin 470 can be coupled to other components of the second memory die 405-b or another memory die 405 (not shown).

[0069] Using the location detection circuit 410, various methods and configurations may be employed to identify the location of the memory die 405. Each of the different methods and different configurations for the location detection circuit 410 are described herein.

[0070] In a first embodiment, an inverter and bond wires may be used to identify the location of the memory die. A control signal 475 (e.g., a tmfzLinkDetect signal) may be enabled, which may disable the circuitry 440 and enable the location detection circuit 410. Enabling the control signal 475 may also configure the multiplexer 435 to output the first input 480.

[0071] When the enable control signal 475 is activated, the pin 445 can receive a second signal having a first value. For example, the second signal can have a value of -1.0 V. In the first implementation, the position detection circuit 410 can not include a corresponding pull-down circuit 425, so the second signal can be present at a first node 430-a, which is coupled with the latch 420-a and the inverter 415-a. The second signal at the first node 430-a can be sensed by the latch 420-a, and the latch 420-a can output a first identifier associated with the second signal (e.g., via the first input 480-a). In some examples, the first identifier can be associated with a logical "0," which can be used to identify the first memory die 405-a. As described herein, the multiplexer 435-a can output the first identifier (e.g., via the output 490-a) to a register. The host device can then read the register and can cause the first identifier to be stored to a non-volatile read-only memory associated with the first memory die 405-a.

[0072] A portion of the signal transmitted to the inverter 415-a can be inverted, resulting in a signal having a second value (e.g., the signal can be inverted from -1.0 V to 1.0 V). The signal can be transmitted to the pin 455, which can be coupled with the pin 460 via the bond wire 457. Thus, the signal can be transmitted from the first memory die 405-a to the second memory die 405-b. At the second memory die 405-b, the signal can be present at a second node 430-b, which is coupled with the latch 420-b. In some cases, the signal received by the second node 430-b can be referred to as a third signal, even though it is the same signal as the second signal (or as an inverted version of the second signal).

[0073] The latch 420-b can output a second identifier associated with the signal (e.g., via the first input 480-b). In some examples, the second identifier can be associated with a logical "1," which can be used to identify the second memory die 405-b. As described herein, the multiplexer 435-b can output the first identifier (e.g., via the output 490-b) to a register, and the first identifier can be stored to a non-volatile read-only memory associated with the first memory die 405-a. In some examples, the signal received by the second memory die 405-b can be inverted by the inverter 415-b and transmitted to the pin 470. As described herein, the pin 470 can be coupled with other components of the second memory die 405-b or another memory die 405 (not shown).

[0074] In some cases, after the identifier is stored in the register or in the corresponding non-volatile read-only memory, control signal 475 can be disabled. Consequently, circuit 440 can be enabled, and other operations (e.g., access operations) can be performed on the corresponding memory die 405. During this operation, for example, multiplexer 435-a of first memory die 405-a can receive the identifier stored in the non-volatile read-only memory (e.g., via second input 485-a). Consequently, multiplexer 435-a can output a third identifier (e.g., via output 490-a), which can be the same identifier as the first identifier and can be used to identify first memory die 405-a for the corresponding access operation. In some cases, the first identifier can identify first memory die 405-a as an interface die. Second memory die 405-b can perform similar operations and, in some cases, can output a fourth identifier that can identify second memory die 405-b as a linking die.

[0075] In a second embodiment, a pull-down circuit, an inverter, and a bond wire can be used to identify the location of the memory die. A control signal 475 (e.g., a tmfzLinkDetect signal) can be enabled, which can enable the location detection circuit 410. Enabling the control signal 475 can also configure the multiplexer 435 to output the first input 480.

[0076] When control signal 475 is enabled, pin 445 may receive a second signal having a first value (or may be floating). For example, the second signal may have a value of -1.0V. In a second embodiment, position detection circuit 410 may include a corresponding pull-down circuit 425, so that the second signal may be pulled down by pull-down circuit 425-a at first node 430-a (e.g., if the node is floating), which is coupled to latch 420-a and inverter 415-a. The second signal at first node 430-a may be sensed by latch 420-a, and latch 420-a may output a first identifier associated with the second signal (e.g., via first input 480-a). In some examples, the first identifier may be associated with a logic "0" that can be used to identify first memory die 405-a. As described herein, multiplexer 435-a may output the first identifier (e.g., via output 490-a) to a register. The host device may then read the register and may cause the first identifier to be stored to non-volatile read-only memory associated with the first memory die 405 - a .

[0077] A portion of the signal transmitted to inverter 415-a can be inverted, thereby generating a signal having a second value. The signal can be transmitted to pin 455, which can be coupled to pin 460 via bonding wire 457. Thus, the signal can be transmitted from the first memory die 405-a to the second memory die 405-b. At the second memory die 405-b, a pull-down circuit 425-b can be used to pull down the signal at the second node 430-b. However, under the condition that the signal is inverted, the pull-down circuit 425-b can be configured as a weak pull-down circuit that may not be able to cause the signal to change the logic state it is detecting. In some cases, the signal received by the second node 430-b can be referred to as a third signal, even if it is the same signal as the second signal (or an inverted version of the second signal).

[0078] Latch 420-b can output a second identifier associated with the signal (e.g., via first input 480-b). In some examples, the second identifier can be associated with a logic "1" that can be used to identify the second memory die 405-b. As described herein, multiplexer 435-b can output the first identifier to a register (e.g., via output 490-b), and the first identifier can be stored in a non-volatile read-only memory associated with the first memory die 405-a. In some examples, the signal received by the second memory die 405-b can be inverted by inverter 415-b and transmitted to pin 470. As described herein, pin 470 can be coupled to other components of the second memory die 405-b or another memory die 405 (not shown).

[0079] In some cases, after the identifier is stored in the register or in the corresponding non-volatile read-only memory, control signal 475 can be deactivated. During a subsequent access operation, for example, multiplexer 435-a of first memory die 405-a can receive the first identifier stored in the non-volatile read-only memory (e.g., via second input 485-a). Consequently, multiplexer 435-a can output the first identifier (e.g., via output 490-a), which can be used to identify first memory die 405-a for the corresponding access operation. In some cases, the first identifier can identify first memory die 405-a as an interface die. Second memory die 405-b can perform similar operations and, in some cases, can output a fourth identifier that can identify second memory die 405-b as a linking die.

[0080] In a third embodiment, connections to one or more voltage sources can be used to identify the location of the memory die. A control signal 475 (e.g., a tmfzLinkDetect signal) can be enabled, which can enable the location detection circuit 410. Enabling the control signal 475 can also configure the multiplexer 435 to output the first input 480.

[0081] In a third embodiment, the second node 430-b of the second memory die 405-b can be coupled to a voltage source 465 (e.g., Vcc), and the first node 430-a of the first memory die 405-a can be left floating. Each position device circuit (e.g., position detection circuits 410-a and 410-b) can include a pull-down circuit (e.g., pull-down circuits 425-a and 425-b) coupled to the first node 430-a and the second node 430-b and configured as a weak pull-down circuit. Pull-down circuit 425-a can be configured to pull the first node 430 down to ground voltage. In contrast, pull-down circuit 425-b (because it is a weak pull-down circuit) may not be configured to pull the second node 430-b to a voltage different from the voltage of voltage source 465. In a third embodiment, the position detection circuits 410-a and 410-b of the memory dies 405-a and 405-b may not be coupled via bond wire 457. In some examples of the third embodiment, bond wires 457 may continue to be used for circuitry 440 - a and circuitry 440 - b In some examples of the third embodiment, position detection circuits 410 - a and 410 - b may not include inverters 415 - a and 415 - b .

[0082] In some examples, pin 445 may receive a second signal having a first value. In some examples, pin 445 may remain floating. In a third embodiment, position detection circuit 410 may include a corresponding pull-down circuit 425, so that the second signal present at first node 430-a can be pulled down by pull-down circuit 425-a. The second signal at first node 430-a may be sensed or stored by latch 420-a, and latch 420-a may output a first identifier associated with the second signal (e.g., via first input 480-a). In some examples, the first identifier may be associated with a logic "0" that can be used to identify first memory die 405-a. As described herein, multiplexer 435-a may output the first identifier (e.g., via output 490-a) to a register, and the first identifier may be stored in a non-volatile read-only memory associated with first memory die 405-a.

[0083] In a third embodiment, second node 430-b may be coupled to voltage source 465 (e.g., Vcc). Voltage source 465 may be associated with a voltage value greater than the voltage of node 430 (e.g., due to the signal being pulled down by pull-down circuit 425b). Thus, based on voltage source 465, the voltage of second node 430-b may increase (e.g., to a voltage value at or near Vcc). The signal at second node 430-b may be sensed or stored by latch 420-b.

[0084] Latch 420-b can output a second identifier associated with the signal (e.g., via first input 480-b). In some examples, the second identifier can be associated with a logic "1" that can be used to identify the second memory die 405-b. As described herein, multiplexer 435-b can output the first identifier to a register (e.g., via output 490-b), and the first identifier can be stored in a non-volatile read-only memory associated with the first memory die 405-a. In some examples, the signal received by the second memory die 405-b can be inverted by inverter 415-b and transmitted to pin 470. As described herein, pin 470 can be coupled to other components of the second memory die 405-b or another memory die 405 (not shown).

[0085] In some cases, after the identifier is stored in the register or in the corresponding non-volatile read-only memory, control signal 475 can be disabled. During a subsequent access operation, for example, multiplexer 435-a of first memory die 405-a can receive the identifier stored in the non-volatile read-only memory (e.g., via second input 485-a). Consequently, multiplexer 435-a can output a third identifier (e.g., via output 490-a), which can be the same identifier as the first identifier and can be used to identify first memory die 405-a for the corresponding access operation. In some cases, the first identifier can identify first memory die 405-a as an interface die. Second memory die 405-b can perform similar operations and, in some cases, can output a fourth identifier that can identify second memory die 405-b as a linking die.

[0086] In a fourth embodiment, connections to one or more voltage sources can be used to identify the location of the memory die. A control signal 475 (e.g., a tmfzLinkDetect signal) can be enabled, which can enable the location detection circuit 410. Enabling the control signal 475 can also configure the multiplexer 435 to output the first input 480.

[0087] In a third embodiment, the second node 430-b of the second memory die 405-b may be coupled to a voltage source 465 (e.g., Vcc), and the first node 430-a of the first memory die 405-a may be coupled to a voltage source 450 (e.g., a ground voltage, sometimes designated GND). When the control signal 475 is enabled, the latch 420-a of the first position detection circuit 410-a may detect a signal at the first node 430-a (e.g., GND), and the latch 420-b of the second position detection circuit 410-b may detect a signal at the second node 430-b (e.g., Vcc). In some examples of the fourth embodiment, the position detection circuits 410-a and 410-b of the memory dies 405-a and 405-b may not be coupled via a bond wire 457. In this embodiment, the bond wire 457 may continue to be used for the circuit system 440-a and the circuit system 440-b. In some examples of the fourth embodiment, the position detection circuits 410 - a and 410 - b may not include the inverters 415 - a and 415 - b or the pull-down circuits 425 - a and 425 - b .

[0088] First node 430-a can be coupled to voltage source 450 and can receive a second signal having a first value from voltage source 450 (e.g., GND). For example, the second signal can have a value at or below 0V. The second signal can be transmitted from first node 430-a to latch 420-a, and latch 420-a can output a first identifier associated with the second signal (e.g., via first input 480-a). In some examples, the first identifier can be associated with a logic "0" that can be used to identify first memory die 405-a. As described herein, multiplexer 435-a can output the first identifier (e.g., via output 490-a) to a register, and the first identifier can be stored in a non-volatile read-only memory associated with first memory die 405-a.

[0089] The second node 430-b can be coupled to a voltage source 465 (e.g., Vcc) and can receive a signal (e.g., a third signal) from the voltage source 465. The latch 420-b can output a second identifier associated with the signal (e.g., via the first input 480-b). In some examples, the second identifier can be associated with a logic "1" that can be used to identify the second memory die 405-b. As described herein, the multiplexer 435-b can output the first identifier (e.g., via the output 490-b) to a register, and the first identifier can be stored in a non-volatile read-only memory associated with the first memory die 405-a.

[0090] In some cases, control signal 475 can be disabled after the identifier is stored to the register or to the respective non-volatile read-only memory. During a subsequent access operation, for example, multiplexer 435-a of first memory die 405-a can receive the identifier stored to the non-volatile read-only memory (e.g., via second input 485-a). Accordingly, multiplexer 435-a can output a third identifier (e.g., via output 490-a), which can be the same identifier as the first identifier and can be used to identify first memory die 405-a for the respective access operation. In some cases, the first identifier can identify first memory die 405-a as an interface die. Second memory die 405-b can perform similar operations, and in some cases, can output a fourth identifier, which can identify second memory die 405-b as a link die. Accordingly, by detecting the location of the respective memory dies 405 using the circuitry and methods described herein, the memory dies 405 can be individually accessed (e.g., by a host system) even though they are coupled with a shared CA channel and receive the same commands therefrom.

[0091] Figure 5 A block diagram 500 showing a memory device 520 that supports die location detection for grouped memory dies in accordance with examples as disclosed herein is shown. Memory device 520 can be an example of the memory device 100 described with reference to Figures 1 to 4 Examples of aspects of the described memory device are described. Memory device 520, or various components thereof, can be examples of means for performing various aspects for die location detection for grouped memory dies described herein. For example, memory device 520 can include a signal receiving component 525, a detecting component 530, a storing component 535, a comparing component 540, a command component 545, a signal inverting component 550, an outputting component 555, a current applying component 560, a signal disabling component 565, a reading component 570, an accessing component 575, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0092] Signal receiving component 525 can be configured as or otherwise support a means for receiving, at a first memory die and a second memory die, a first signal that enables circuitry of the first memory die and the second memory die. In some examples, signal receiving component 525 can be configured as or otherwise support a means for receiving, via a command / address channel coupled with the first memory die and the second memory die, an access command including one or more bits that indicate to access the second memory die.

[0093] The detection component 530 can be configured as or otherwise support a means for detecting, by first circuitry of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal. In some examples, the detection component 530 can be configured as or otherwise support a means for detecting, by second circuitry of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal.

[0094] The storage component 535 can be configured as or otherwise support a means for storing, at a register associated with the first memory die, a first identifier of the first position of the first memory die based at least in part on detecting the first value of the second signal. In some examples, the storage component 535 can be configured as or otherwise support a means for storing, at a register associated with the second memory die, a second identifier of the second position of the second memory die based at least in part on detecting the second value of the third signal. In some examples, the storage component 535 can be configured as or otherwise support a means for storing the first identifier or the second identifier, or both, in a non-volatile read-only memory associated with the first memory die and the second memory die based at least in part on storing the first identifier in the register and storing the second identifier in the register.

[0095] In some examples, the comparison component 540 can be configured as or otherwise support a means for comparing the first identifier and the second identifier to one or more values of a non-volatile read-only memory associated with the first memory die and the second memory die.

[0096] In some examples, the command component 545 can be configured as or otherwise support a means for refraining from issuing a command to alter a value of a non-volatile read-only memory associated with the first memory die or the second memory die based at least in part on comparing the first identifier and the second identifier to the one or more values of the non-volatile read-only memory.

[0097] In some examples, the first circuitry of the first memory die and the second circuitry of the second memory die are coupled with a bond wire, and the signal inversion component 550 can be configured as or otherwise support a means for inverting, at the first circuitry of the first memory die, the first value of the second signal to a second value in response to storing the first identifier of the first memory die, where the third signal includes the inverted second signal.

[0098] In some examples, the output component 555 can be configured as or otherwise support means for outputting a first identifier from a first circuit of a first memory die based at least in part on receiving the first signal. In some examples, the output component 555 can be configured as or otherwise support means for outputting a second identifier from a second circuit of a second memory die based at least in part on receiving the first signal.

[0099] In some examples, the output component 555 can be configured as or otherwise support means for outputting a third identifier from the first circuit of the first memory die based at least in part on the first signal being disabled. In some examples, the output component 555 can be configured as or otherwise support means for outputting a fourth identifier from the second circuit of the second memory die based at least in part on the first signal being disabled.

[0100] In some examples, to support storing the first identifier or the second identifier, or both, in a non-volatile read-only memory, the current application component 560 may be configured as or otherwise support means for applying a current to the fuse or antifuse that satisfies a threshold and changes the resistance of the fuse or antifuse.

[0101] In some examples, the signal disabling component 565 can be configured as or otherwise support means for disabling the first circuit and the second circuit. In some examples, the signal disabling component 565 can be configured as or otherwise support means for disabling the first circuit of the first memory die and the second circuit of the second memory die, wherein the second signal including the second value is associated with one or more operations for the first memory die and the second memory die based at least in part on disabling the first circuit of the first memory die and the second circuit of the second memory die.

[0102] In some examples, read component 570 can be configured as or otherwise support means for reading a non-volatile read-only memory associated with the second memory die based at least in part on receiving the access command.

[0103] In some examples, access component 575 can be configured as or otherwise support means for accessing the second memory die and reading nonvolatile read-only memory associated with the second memory die based at least in part on the value of one or more bits of the access command.

[0104] In some examples, the nonvolatile read-only memory includes a fuse array or an antifuse array. In some examples, the second circuit of the second memory die is coupled to the first voltage source. In some examples, the second circuit of the second memory die is configured to receive a third signal based at least in part on the first voltage source. In some examples, the first circuit of the first memory die is coupled to the second voltage source. In some examples, the first circuit of the first memory die is configured to receive a second signal based at least in part on the second voltage source.

[0105] In some examples, the first circuit and the second circuit are coupled to a ground node via a weak pull-down circuit.In some examples, the first identifier includes an indication that the first memory die is an interface die, and the second identifier includes an indication that the second memory die is a link die.

[0106] Figure 6 A flow chart illustrating a method 600 for supporting die location detection for grouped memory dies according to examples disclosed herein is shown. The operations of the method 600 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 5 The memory device described herein performs the functions described herein. In some examples, the memory device may execute an instruction set to control the functional elements of the device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform various aspects of the functions described herein.

[0107] At 605, the method may include receiving, at a first memory die and a second memory die, a first signal enabling circuitry of the first memory die and the second memory die. The operations of 605 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 605 may be described with reference to Figure 5 The signal receiving component 525 is described as performing.

[0108] At 610, the method may include detecting, by a first circuit of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal. The operations of 610 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 610 may be described with reference to Figure 5 The detection component 530 is described as performing.

[0109] At 615, the method may include storing a first identifier of a first location of the first memory die at a register associated with the first memory die based at least in part on detecting the first value of the second signal. The operations of 615 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 615 may be described with reference to Figure 5 The storage component 535 is described as performing.

[0110] At 620, the method may include detecting, by a second circuit of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal. The operations of 620 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 620 may be described with reference to Figure 5 The detection component 530 is described as performing.

[0111] At 625, the method may include storing a second identifier of a second location of the second memory die at a register associated with the second memory die based at least in part on detecting the second value of the third signal. The operations of 625 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 625 may be described with reference to Figure 5 The storage component 535 is described as performing.

[0112] In some examples, an apparatus described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a first memory die and a second memory die, a first signal that enables circuitry of the first memory die and the second memory die; detecting, by a first circuit of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal; storing, at a register associated with the first memory die, a first identifier of the first position of the first memory die based at least in part on detecting the first value of the second signal; detecting, by a second circuit of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal; and storing, at a register associated with the second memory die, a second identifier of the second position of the second memory die based at least in part on detecting the second value of the third signal.

[0113] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for storing the first identifier or the second identifier, or both, in a non-volatile read-only memory associated with the first memory die and the second memory die based at least in part on storing the first identifier in a register and storing the second identifier in a register.

[0114] In some examples of the method 600 and apparatus described herein, the nonvolatile read-only memory includes a fuse array or an antifuse array.

[0115] In some examples of the method 600 and apparatus described herein, storing the first identifier or the second identifier, or both, in a non-volatile read-only memory may include operations, features, circuitry, logic, means, or instructions for applying a current to the fuse or antifuse that satisfies a threshold and changes the resistance of the fuse or antifuse.

[0116] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: disabling the first circuit and the second circuit; receiving an access command including one or more bits indicating access to the second memory die via a command / address channel coupled to the first memory die and the second memory die; reading a non-volatile read-only memory associated with the second memory die based at least in part on receiving the access command; and accessing the second memory die and reading the non-volatile read-only memory associated with the second memory die based at least in part on the value of the one or more bits of the access command.

[0117] Some examples of the method 600 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for: comparing the first and second identifiers to one or more values ​​of non-volatile read-only memory associated with the first and second memory dies; and refraining from issuing a command to change the value of the non-volatile read-only memory associated with the first or second memory die based at least in part on comparing the first and second identifiers to the one or more values ​​of the non-volatile read-only memory.

[0118] In some examples of the method 600 and apparatus described herein, a first circuit of a first memory die and a second circuit of a second memory die may be coupled with a bond wire, and the methods, apparatus, and non-transitory computer-readable media may include other operations, features, circuit systems, logic, means, or instructions for inverting a first value of a second signal to a second value at the first circuit of the first memory die in response to storing a first identifier of the first memory die, wherein the third signal includes the inverted second signal.

[0119] Some instances of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for disabling a first circuit of a first memory die and a second circuit of a second memory die, wherein based at least in part on disabling the first circuit of the first memory die and the second circuit of the second memory die, a second signal including a second value may be associated with one or more operations for the first memory die and the second memory die.

[0120] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for outputting, from a first circuit of a first memory die, a first identifier based at least in part on receiving the first signal, and outputting, from a second circuit of a second memory die, a second identifier based at least in part on receiving the first signal.

[0121] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for outputting, from a first circuit of a first memory die, a third identifier based at least in part on the first signal being deactivated, and outputting, from a second circuit of a second memory die, a fourth identifier based at least in part on the first signal being deactivated.

[0122] In some examples of the method 600 and the apparatus described herein, the second circuit of the second memory die can be coupled with a first voltage source, and the second circuit of the second memory die can be configured to receive the third signal based at least in part on the first voltage source.

[0123] In some examples of the method 600 and the apparatus described herein, the first circuit of the first memory die can be coupled with a second voltage source, and the first circuit of the first memory die can be configured to receive the second signal based at least in part on the second voltage source.

[0124] In some examples of the method 600 and the apparatus described herein, the first circuit and the second circuit can be coupled with a ground node via a weak pull-down circuit.

[0125] In some examples of the method 600 and the apparatus described herein, the first identifier includes an indication that the first memory die can be an interface die, and the second identifier includes an indication that the second memory die can be a link die.

[0126] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods can be combined.

[0127] An apparatus is described. The apparatus may include: a command / address channel; a first memory die coupled to the command / address channel and including a first circuit configured to output a first identifier of the first memory die based at least in part on receiving a first signal to enable the first circuit and detecting a first value of a second signal; a first register coupled to the first circuit and configured to store the first identifier of the first memory die based at least in part on the first circuit outputting the first identifier; a second memory die coupled to the command / address channel and including a second circuit configured to output a second identifier of the second memory die based at least in part on receiving the first signal to enable the second circuit and detecting a second value of a third signal; and a second register coupled to the second circuit and configured to store the second identifier of the second memory die based at least in part on the second circuit outputting the second identifier.

[0128] In some examples of the apparatus, the first circuit includes: a first pull-down circuit coupled to a first node of the first circuit and configured to adjust a value of a second signal, wherein the second signal includes a second value based at least in part on the first pull-down circuit adjusting the value of the second signal; a first latch coupled to the first node and configured to receive the second signal including the second value and output a first identifier based at least in part on the first pull-down circuit adjusting the value of the second signal; and an inverter coupled to the first node and configured to invert the second signal including the second value based at least in part on the first latch receiving the first signal.

[0129] In some examples of the apparatus, the first circuit includes: a multiplexer including a first input coupled to the first latch and a second input coupled to the non-volatile memory, the multiplexer configured to select an output of the first circuit from the first input or the second input based at least in part on a value of a first signal received by the multiplexer.

[0130] In some examples, an apparatus may include a fuse or antifuse array coupled with the second input of the multiplexer and configured to store a value for the first identifier, wherein the nonvolatile memory includes the fuse or antifuse array.

[0131] In some examples of the apparatus, the second circuit includes: a second pull-down circuit coupled to the second node of the first circuit and configured to adjust a value of the inverted second signal, wherein the third signal includes the inverted second signal; and a second latch coupled to the second node and configured to receive the third signal and output the second identifier based at least in part on the second pull-down circuit adjusting the value of the inverted second signal.

[0132] In some examples of the apparatus, the first memory die may be coupled to the second memory die via a bond wire; and the bond wire may be coupled to an output of an inverter of the first circuit, and the second node of the second circuit may be coupled to the bond wire.

[0133] In some examples, an apparatus can include a latch that enables a first circuit, causes a multiplexer of the first circuit to output a first input of the multiplexer or a second input of the multiplexer, and disables one or more other circuits coupled with a bond wire.

[0134] In some examples, an apparatus can include a first voltage source coupled to a second circuit of a second memory die, wherein the second circuit can be configured to receive a third signal based at least in part on coupling to the first voltage source.

[0135] In some examples, an apparatus may include a second voltage source coupled to the first circuit of the first memory die, wherein the first circuit may be configured to receive a second signal including a second value based at least in part on coupling with the second voltage source.

[0136] In some examples of an apparatus, a first memory die and a second memory die may be coupled to a host device and accessible by a peripheral device coupled to the host device via an interface configured for a Compute Express Link (CXL) protocol, and the first memory die and the second memory die may be coupled to the peripheral device and accessible by the host device via the interface.

[0137] In some examples of the apparatus, the first identifier includes an indication that the first memory die may be an interface die, and the second identifier includes an indication that the second memory die may be a link die.

[0138] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may show a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0139] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intervening components such as switches or transistors.

[0140] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which signals cannot currently pass between the components through a conductive path, to a closed circuit relationship between the components, in which signals can pass between the components through the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path through which signals were not previously permitted to flow.

[0141] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, components that are separated by a switch positioned between the two components are isolated from each other when the switch is open. If a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using a conductive path through which signals were previously permitted to flow.

[0142] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0143] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material such as a metal. The source and drain can be conductive and can include heavily doped, such as a degenerate semiconductor region. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET can be referred to as a p-type FET. The channel can be terminated by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "cut off" or "deactivated."

[0144] The exemplary configurations described herein in conjunction with the detailed description set forth in the accompanying drawings are not intended to represent all embodiments that may be implemented or that fall within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred over" or "superior to" other embodiments. The detailed description includes specific details to provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0145] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0146] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted on a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0147] By way of example, various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor; but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0148] As used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” is not meant to be limiting. For example, a step described as being “based on condition A” can also be based on condition B. In other words, as used herein, the phrase “based on” should be interpreted as meaning “based at least in part on.”

[0149] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0150] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Command / address channel; a first memory die coupled to the command / address channel and comprising a first circuit configured to output a first identifier of the first memory die based at least in part on receiving a first signal to enable the first circuit and detecting a first value of a second signal; a first register coupled to the first circuit and configured to store the first identifier of the first memory die based at least in part on the first circuit outputting the first identifier; a second memory die coupled to the command / address channel and comprising a second circuit configured to output a second identifier of the second memory die based at least in part on receiving the first signal to enable the second circuit and detecting a second value of a third signal; as well as A second register, coupled with the second circuit and configured to store the second identifier of the second memory die based at least in part on the second circuit outputting the second identifier.

2. The apparatus of claim 1 , wherein the first circuit comprises: a first pull-down circuit coupled to the first node of the first circuit and configured to adjust a value of the second signal, wherein the second signal comprises the second value based at least in part on the first pull-down circuit adjusting the value of the second signal; a first latch coupled to the first node and configured to receive the second signal including the second value and output the first identifier based at least in part on adjusting the value of the second signal by the first pull-down circuit; as well as An inverter is coupled to the first node and configured to invert the second signal including the second value based at least in part on the first latch receiving the first signal.

3. The apparatus of claim 2, wherein the first circuit comprises: a multiplexer including a first input coupled to the first latch and a second input coupled to a non-volatile memory, the multiplexer configured to select an output of the first circuit from the first input or the second input based at least in part on a value of the first signal received by the multiplexer.

4. The apparatus according to claim 3, further comprising: A fuse or antifuse array coupled to the second input of the multiplexer and configured to store a value for the first identifier, wherein the nonvolatile memory includes the fuse or antifuse array.

5. The apparatus of claim 2, wherein the second circuit comprises: a second pull-down circuit coupled to a second node of the first circuit and configured to adjust a value of the inverted second signal, wherein the third signal includes the inverted second signal; as well as A second latch is coupled to the second node and configured to receive the third signal and output the second identifier based at least in part on the second pull-down circuit adjusting the value of the inverted second signal.

6. The apparatus according to claim 5, wherein: the first memory die is coupled to the second memory die via bond wires; and The bond wire is coupled to an output of the inverter of the first circuit, and the second node of the second circuit is coupled to the bond wire.

7. The apparatus of claim 6, wherein the first signal is configured to: enabling the first latch of the first circuit; causing a multiplexer of the first circuit to output either the first input of the multiplexer or the second input of the multiplexer; and One or more other circuits coupled to the bond wire are disabled.

8. The apparatus of claim 1 , further comprising: A first voltage source is coupled to the second circuit of the second memory die, wherein the second circuit is configured to receive the third signal based at least in part on coupling to the first voltage source.

9. The apparatus of claim 8, further comprising: A second voltage source is coupled to the first circuit of the first memory die, wherein the first circuit is configured to receive the second signal including the second value based at least in part on coupling to the second voltage source.

10. The apparatus of claim 1, wherein: The first memory die and the second memory die are coupled to a host device and are accessible by a peripheral device coupled to the host device via an interface configured for a Compute Link Express (CXL) protocol; or The first memory die and the second memory die are coupled with the peripheral device and are accessible by the host device via the interface.

11. The apparatus of claim 1 , wherein: The first identifier includes an indication that the first memory die is an interface die, and The second identifier includes an indication that the second memory die is a linking die.

12. A method comprising: receiving, at a first memory die and a second memory die, a first signal enabling circuitry of the first memory die and the second memory die; detecting, by first circuitry of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal; storing a first identifier of the first location of the first memory die at a register associated with the first memory die based at least in part on detecting the first value of the second signal; detecting, by second circuitry of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal; as well as Based at least in part on detecting the second value of the third signal, a second identifier of the second location of the second memory die is stored at a register associated with the second memory die.

13. The method according to claim 12, further comprising: Based at least in part on storing the first identifier in the register and storing the second identifier in the register, storing the first identifier or the second identifier or both in nonvolatile read-only memory associated with the first memory die and the second memory die.

14. The method of claim 13, wherein the nonvolatile read-only memory comprises a fuse array or an antifuse array.

15. The method of claim 13, wherein storing the first identifier or the second identifier or both in the non-volatile read-only memory comprises: A current is applied to the fuse or antifuse that satisfies a threshold and changes the resistance of the fuse or antifuse.

16. The method of claim 13, further comprising: deactivating the first circuit and the second circuit; receiving, via a command / address channel coupled to the first memory die and the second memory die, an access command including one or more bits indicating access to the second memory die; reading the nonvolatile read-only memory associated with the second memory die based at least in part on receiving the access command; as well as The second memory die is accessed based at least in part on the value of the one or more bits of the access command, and the nonvolatile read-only memory associated with the second memory die is read.

17. The method of claim 12, further comprising: comparing the first identifier and the second identifier to one or more values ​​of nonvolatile read-only memory associated with the first memory die and the second memory die; as well as Based at least in part on comparing the first and second identifiers to the one or more values ​​of the nonvolatile read-only memory, issuing a command to change a value of the nonvolatile read-only memory associated with the first memory die or the second memory die is avoided.

18. The method of claim 12, wherein the first circuit of the first memory die and the second circuit of the second memory die are coupled with bond wires, the method further comprising: In response to storing the first identifier of the first memory die, the first value of the second signal is inverted to the second value at the first circuit of the first memory die, wherein the third signal includes the inverted second signal.

19. The method of claim 18, further comprising: and disabling the first circuit of the first memory die and the second circuit of the second memory die, wherein the second signal including the second value is associated with one or more operations for the first memory die and the second memory die based at least in part on disabling the first circuit of the first memory die and the second circuit of the second memory die.

20. The method of claim 12, further comprising: outputting the first identifier from the first circuit of the first memory die based at least in part on receiving the first signal; as well as Based at least in part on receiving the first signal, the second identifier is output from the second circuit of the second memory die.

21. The method of claim 20, further comprising: outputting a third identifier from the first circuit of the first memory die based at least in part on the first signal being disabled; as well as Based at least in part on the first signal being disabled, outputting a fourth identifier from the second circuit of the second memory die.

22. The method of claim 12, wherein: The second circuit of the second memory die is coupled to a first voltage source, and The second circuit of the second memory die is configured to receive the third signal based at least in part on the first voltage source.

23. The method of claim 22, wherein: The first circuit of the first memory die is coupled to a second voltage source, and The first circuit of the first memory die is configured to receive the second signal based at least in part on the second voltage source.

24. The method of claim 12, wherein the first circuit and the second circuit are coupled to a ground node via a weak pull-down circuit.

25. The method of claim 12, wherein the first identifier comprises an indication that the first memory die is an interface die, and the second identifier comprises an indication that the second memory die is a link die.

26. An apparatus comprising: a first memory die coupled to the command / address channel and comprising a first circuit; a second memory die coupled to the command / address channel and comprising a second circuit; a register coupled to the first circuit and the second circuit; as well as a controller coupled to the first memory die and the second memory die, wherein the controller is configured to cause the apparatus to: receiving, at the first memory die and the second memory die, a first signal to enable the first circuit and the second circuit; detecting, by the first circuit of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal; storing, at the register, a first identifier of the first location of the first memory die based at least in part on detecting the first value of the second signal; detecting, by the second circuit of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal; as well as Based at least in part on detecting the second value of the third signal, a second identifier of the second location of the second memory die is stored at the register.

27. The apparatus of claim 26, wherein the controller is configured to cause the apparatus to: Based at least in part on storing the first identifier in the register and storing the second identifier in the register, storing the first identifier or the second identifier or both in nonvolatile read-only memory associated with the first memory die and the second memory die.

28. The apparatus of claim 27, wherein the nonvolatile read-only memory comprises a fuse array or an antifuse array.

29. The apparatus of claim 27, wherein To store the first identifier or the second identifier or both in the non-volatile read-only memory, the controller is operable to cause the device to: A current is applied to the fuse or antifuse that satisfies a threshold and changes the resistance of the fuse or antifuse.

30. The apparatus of claim 27, wherein the controller is configured to cause the apparatus to: deactivating the first circuit and the second circuit; receiving, via the command / address channel, an access command including one or more bits indicating access to the second memory die; reading the nonvolatile read-only memory associated with the second memory die based at least in part on receiving the access command; as well as The second memory die is accessed based at least in part on the value of the one or more bits of the access command, and the nonvolatile read-only memory associated with the second memory die is read.

31. The apparatus of claim 26, wherein the controller is configured to cause the apparatus to: comparing the first identifier and the second identifier to one or more values ​​of nonvolatile read-only memory associated with the first memory die and the second memory die; and Based at least in part on comparing the first and second identifiers to the one or more values ​​of the nonvolatile read-only memory, issuing a command to change a value of the nonvolatile read-only memory associated with the first memory die or the second memory die is avoided.

32. The apparatus of claim 26, wherein the first circuit of the first memory die and the second circuit of the second memory die are coupled with bond wires, and wherein the controller is configured to cause the apparatus to: In response to storing the first identifier of the first memory die, the first value of the second signal is inverted to the second value at the first circuit of the first memory die, wherein the third signal includes the inverted second signal.

33. The apparatus of claim 32, wherein the controller is configured to cause the apparatus to: and disabling the first circuit of the first memory die and the second circuit of the second memory die, wherein the second signal including the second value is associated with one or more operations for the first memory die and the second memory die based at least in part on disabling the first circuit of the first memory die and the second circuit of the second memory die.

34. An apparatus comprising: means for receiving, at a first memory die and a second memory die, a first signal to enable circuitry of the first memory die and the second memory die; means for detecting, by first circuitry of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal; means for storing a first identifier of the first location of the first memory die at a register associated with the first memory die based at least in part on detecting the first value of the second signal; means for detecting, by second circuitry of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal; as well as Means for storing a second identifier of the second location of the second memory die at a register associated with the second memory die based at least in part on detecting the second value of the third signal.

35. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving, at a first memory die and a second memory die, a first signal to enable circuitry of the first memory die and the second memory die; detecting, by first circuitry of the first memory die, a first value of a second signal associated with a first position of the first memory die relative to the second memory die based at least in part on receiving the first signal; storing a first identifier of the first location of the first memory die at a register associated with the first memory die based at least in part on detecting the first value of the second signal; as well as detecting, by second circuitry of the second memory die, a second value of a third signal associated with a second position of the second memory die relative to the first memory die based at least in part on receiving the first signal; as well as Based at least in part on detecting the second value of the third signal, a second identifier of the second location of the second memory die is stored at a register associated with the second memory die.

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