Driving circuit of display panel, display panel and display device

Abstract

The application relates to a driving circuit of a display panel, the display panel and a display device. The driving circuit comprises a plurality of gate lines and a timing controller. A signal selection module is arranged in the driving circuit, and the signal selection module is connected with the gate line G4n+2, the gate line G4n+3 and the timing controller respectively, n is an integer greater than or equal to 0, and the signal selection module is used for exchanging the outputs of the gate line G4n+2 and the gate line G4n+3 when a double-line gate function selection signal sent by the timing controller is received, so that 4n+1 rows and 4n+2 rows are scanned at a time or 4n+3 rows and 4n+4 rows are scanned at a time when the timing controller outputs a gate line scanning signal according to a target timing, and the DLG function is realized. The output of the gate line G4n+2 and the gate line G4n+3 is exchanged through the signal selection module, so that the double-line gate function can be realized by scanning every two rows, and the technical problem that the driving voltage of the data line must be changed row by row in a frame, resulting in a long-short-hand double-gate pixel structure and the existing timing being unable to realize the double-line gate function is solved.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a driving circuit for a display panel, a display panel, and a display device. Background Technology

[0002] Dual-Gate driving architecture is widely used in various display panels because it effectively reduces panel costs by doubling the number of gate lines and reducing the number of data lines and source ICs, eliminating the need for additional driver ICs. However, in existing common dual-gate pixel structures, the uneven spatial distribution of pixel polarity and data lines can lead to vertical flickering and other artifacts. Furthermore, since each data line in existing dual-gate pixel structures connects to a different color pixel, the driving voltage of the data line must change line by line within a frame. This timing limitation makes it impossible to implement DLG (Dual Line Gate) functionality when required.

[0003] There is currently no effective solution to the problem that the driving voltage of the data line must change line by line in a frame, which makes it impossible for the dual-gate pixel structure with long and short hands and the existing timing to realize the dual-gate function. Summary of the Invention

[0004] This application provides a driving circuit, display panel, and display device for a display panel, in order to solve the technical problem that the driving voltage of the data line must change line by line in a frame, which makes it impossible for the dual-gate pixel structure with long and short hands and the existing timing to realize the dual-gate function.

[0005] According to one aspect of the embodiments of this application, this application provides a driving circuit for a display panel, including multiple gate lines and a timing controller. The driving circuit is provided with a signal selection module, which is connected to gate line G4n+2, gate line G4n+3 and the timing controller respectively, where n is an integer greater than or equal to 0. The signal selection module is used to exchange the outputs of gate line G4n+2 and gate line G4n+3 when it receives a dual-line gate function selection signal issued by the timing controller.

[0006] Optionally, the signal selection module includes a first transistor and a second transistor. The control terminal of the first transistor is connected to the timing controller. The first terminal of the first transistor is connected to the start terminal of the gate line G4n+2. The second terminal of the first transistor is connected to the gate line G4n+3. The control terminal of the second transistor is connected to the timing controller. The first terminal of the second transistor is connected to the start terminal of the gate line G4n+3. The second terminal of the second transistor is connected to the gate line G4n+2.

[0007] Optionally, gate lines G4n+1 and G4n+3, and gate lines G4n+2 and G4n+4 are turned on alternately, with gate lines G4n+1 and G4n+3 turned on simultaneously, and gate lines G4n+2 and G4n+4 turned on simultaneously.

[0008] Optionally, the signal selection module further includes a third transistor and a fourth transistor. The control terminal of the third transistor is connected to the timing controller. The first terminal of the third transistor is connected to the start terminal of the gate line G4n+2, and the second terminal of the third transistor is connected to the gate line G4n+2 as a part of the gate line G4n+2. The control terminal of the fourth transistor is connected to the timing controller. The first terminal of the fourth transistor is connected to the start terminal of the gate line G4n+3, and the second terminal of the fourth transistor is connected to the gate line G4n+3 as a part of the gate line G4n+3.

[0009] Optionally, the signal selection module is further configured to maintain the original outputs of the gate line G4n+2 and the gate line G4n+3 when receiving a normal display selection signal from the timing controller, so that the gate lines are scanned line by line when the timing controller outputs the gate line scanning signal according to a preset timing sequence, wherein the preset timing sequence includes the gate lines G4n+1, G4n+2, G4n+3 and G4n+4 being turned on sequentially.

[0010] Optionally, the driving circuit further includes multiple source lines, multiple data lines, and multiple TFT transistors. The multiple source lines are arranged vertically between the pixel array. Each source line is connected to two adjacent columns of pixel units. Two adjacent pixels in the same row are connected to different gate lines. Pixels in the same row connected to the same source line have the same polarity. Adjacent pixels in any column of pixel units have opposite polarities. The source lines are connected to multiple data lines through the TFT transistors. The TFT transistors are used to select the corresponding data lines to be input into the source lines according to a preset data mapping relationship.

[0011] Optionally, the timing controller is further configured to: during normal display, output pixel data to the display panel according to a first data mapping relationship, wherein the first data mapping relationship is the data mapping relationship between source line data and data line data required for normal display.

[0012] Optionally, the timing controller is further configured to: output pixel data to the display panel according to a second data mapping relationship when the dual-line grid function is displayed, wherein the second data mapping relationship is the data mapping relationship between the source line data and the data line data required for the dual-line grid function display.

[0013] According to another aspect of the embodiments of this application, this application provides a display panel, including an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate includes the driving circuit described above.

[0014] According to another aspect of the embodiments of this application, this application provides a display device, including a backlight module and the aforementioned display panel. The backlight module is disposed on the backlight side of an array substrate and is used to provide a light source to the display panel.

[0015] Compared with related technologies, the technical solutions provided in this application have the following advantages:

[0016] This application provides a driving circuit for a display panel, including multiple gate lines and a timing controller. The driving circuit includes a signal selection module connected to gate lines G4n+2 and G4n+3, and the timing controller, where n is an integer greater than or equal to 0. The signal selection module, upon receiving a dual-gate function selection signal from the timing controller, swaps the outputs of gate lines G4n+2 and G4n+3. This application uses the signal selection module to swap the outputs of gate lines G4n+2 and G4n+3, enabling scanning every two lines to achieve the DLG (Digital Line Gauge) function. This solves the technical problem that the driving voltage of the data lines must change line by line within a frame, which prevents the implementation of dual-gate pixel structures with varying lengths and existing timing mechanisms from achieving the dual-gate function. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the driving circuit structure of the display panel provided in Embodiment 1 of this application;

[0020] Figure 2 This is a schematic diagram of the driving circuit for the display panel provided in Embodiment 1 of this application;

[0021] Figure 3 This is a schematic diagram of the signal flow path under the dual-line gate function provided in Embodiment 1 of this application;

[0022] Figure 4 The timing diagram of the driving circuit of the display panel provided in Embodiment 1 of this application during dual-line grid function display;

[0023] Figure 5 This is a schematic diagram of the signal flow path under the normal display function provided in Embodiment 1 of this application;

[0024] Figure 6 The timing diagram of the driving circuit of the display panel provided in Embodiment 1 of this application during normal display function display;

[0025] Figure 7 A schematic diagram of a driving circuit for another display panel provided in Embodiment 1 of this application;

[0026] Figure 8 This is an example diagram of the first data mapping relationship provided in Embodiment 1 of this application;

[0027] Figure 9 This is an example diagram of the second data mapping relationship provided in Embodiment 1 of this application;

[0028] Figure 10 This is a schematic diagram of another display panel provided in Embodiment 2 of this application;

[0029] Figure 11 This is a schematic diagram of the display device according to Embodiment 3 of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module" and "part" may be used interchangeably.

[0032] In related technologies, the commonly used dual-gate pixel structure (i.e., DRD architecture, dual-gate architecture) suffers from uneven spatial distribution of pixel polarity and data lines, leading to vertical head-shaking patterns and flickering. Furthermore, because each data line in the existing dual-gate pixel structure (with varying lengths) is connected to a pixel of a different color, the driving voltage of the data line must change line by line within a frame. This makes it impossible to implement the existing timing mechanism when DLG functionality is required.

[0033] To address the problems mentioned in the background art, according to one aspect of the embodiments of this application, an embodiment of a driving circuit for a display panel is provided, such as... Figure 1 As shown, the driving circuit includes multiple gate lines (gate lines G4n+2 and G4n+3 are shown in the figure) and a timing controller Tcon. The driving circuit is equipped with a signal selection module T, which is connected to gate lines G4n+2, G4n+3 and the timing controller Tcon, respectively. n is an integer greater than or equal to 0. When the signal selection module receives a dual-gate function selection signal from the timing controller, it swaps the outputs of gate lines G4n+2 and G4n+3, so that when the timing controller outputs the gate line scanning signal according to the target timing, it scans to rows 4n+1 and 4n+2 at a time, or scans to rows 4n+3 and 4n+4 at a time, thus realizing the dual-gate function.

[0034] This application uses a signal selection module to exchange the outputs of gate line G4n+2 and gate line G4n+3, enabling the timing controller to scan every two lines when outputting the gate line scanning signal according to the target timing. Even with the limitation that the data line driving voltage must change line by line within a frame, scanning every two lines can be cleverly achieved through data exchange. This solves the technical problem that the driving voltage of the data line must change line by line within a frame, which prevents the dual-gate pixel structure with long and short hands and the existing timing from realizing the dual-gate function. As a result, on a 4K*2K screen (3840*2160), where each frame of image originally required a total of 2160 lines to be scanned, and 60 frames per second, the front end will process the image into a 4K*1K screen (3840*1080), at which point only 1080 scans are needed, reducing the time by half, and 120 frames per second can be scanned, thus doubling the refresh rate.

[0035] In an optional embodiment, such as Figure 2 As shown, the signal selection module includes a first transistor T1 and a second transistor T2. The control terminal of the first transistor T1 is connected to the timing controller Tcon. The first terminal of the first transistor T1 is connected to the start terminal of the gate line G4n+2. The second terminal of the first transistor T1 is connected to the gate line G4n+3. The control terminal of the second transistor T2 is connected to the timing controller Tcon. The first terminal of the second transistor T2 is connected to the start terminal of the gate line G4n+3. The second terminal of the second transistor T2 is connected to the gate line G4n+2.

[0036] In this embodiment, a high-level signal from the timing controller Tcon to A2 is considered a DLG function selection signal from the timing controller. Under the action of this DLG function selection signal, such as Figure 3 As shown, the first transistor T1 and the second transistor T2 are turned on, and the signal flow path is shown by the arrow in the figure. The outputs of G4n+2 and G4n+3 are switched.

[0037] In an optional embodiment, such as Figure 4 As shown, gate lines G4n+1 and G4n+3, and gate lines G4n+2 and G4n+4 are alternately turned on. Gate lines G4n+1 and G4n+3 are turned on simultaneously, and gate lines G4n+2 and G4n+4 are turned on simultaneously, so that when gate lines G4n+1 and G4n+3 are turned on simultaneously, rows 4n+1 and 4n+2 are scanned in one go, and when gate lines G4n+2 and G4n+4 are turned on simultaneously, rows 4n+3 and 4n+4 are scanned in one go.

[0038] In the embodiments of this application, such as Figure 4 As shown, when using the DLG function, G1 and G3 need to be turned on simultaneously on the gate side, G2 and G4 need to be turned on simultaneously on the next row, and so on. Gate lines G4n+1 and G4n+3, and gate lines G4n+2 and G4n+4 are turned on alternately. Gate lines G4n+1 and G4n+3 are turned on simultaneously, and gate lines G4n+2 and G4n+4 are turned on simultaneously. When G1 and G3 are turned on simultaneously, the outputs of G2 and G3 are swapped, so the first and second rows are actually scanned. When G2 and G4 are turned on simultaneously, the outputs of G2 and G3 are swapped, so the third and fourth rows are actually scanned. Therefore, it is possible to scan rows 4n+1 and 4n+2 or rows 4n+3 and 4n+4 in one scan, thus realizing the DLG function.

[0039] In this embodiment, the driving circuit can also operate in a normal display mode, i.e., using progressive scanning. This will be explained below.

[0040] In an optional embodiment, such as Figure 2 As shown, the signal selection module further includes a third transistor T3 and a fourth transistor T4. The control terminal of the third transistor T3 is connected to the timing controller Tcon. The first terminal of the third transistor T3 is connected to the start terminal of the gate line G4n+2, and the second terminal of the third transistor T3 is connected to the gate line G4n+2 as a part of the gate line G4n+2. The control terminal of the fourth transistor T4 is connected to the timing controller Tcon. The first terminal of the fourth transistor T4 is connected to the start terminal of the gate line G4n+3, and the second terminal of the fourth transistor T4 is connected to the gate line G4n+3 as a part of the gate line G4n+3.

[0041] In this embodiment, a high-level signal from the timing controller Tcon to A1 is considered a normal display selection signal from the timing controller. Under the action of this normal display selection signal, such as Figure 5 As shown, the third transistor T3 and the fourth transistor T4 are turned on, and the signal flow path is shown by the arrow in the figure. G4n+2 and G4n+3 maintain their original output.

[0042] In an optional embodiment, the signal selection module is further configured to maintain the original outputs of gate lines G4n+2 and G4n+3 when receiving a normal display selection signal from the timing controller, so that the gate lines are scanned line by line when the timing controller outputs the gate line scanning signal according to a preset timing sequence. Figure 6 As shown, the preset timing includes the sequential opening of gate line G4n+1, gate line G4n+2, gate line G4n+3 and gate line G4n+4.

[0043] In the embodiments of this application, such as Figure 6 As shown, when using the normal display function, G1-G2-G3-G4 need to be turned on sequentially on the gate side, and so on, with gate lines G4n+1, G4n+2, G4n+3, and G4n+4 turned on sequentially. As each row of gate lines is turned on, since G4n+2 and G4n+3 maintain their original output, the normal display function is achieved.

[0044] In an optional embodiment, such as Figure 7As shown, the driving circuit also includes multiple source lines (S1 to S6 shown in the figure), multiple data lines (D1 to D6 shown in the figure), and multiple TFT transistors (multiple A0 and A1 shown in the figure). The multiple source lines are vertically arranged between the pixel array. Each source line is connected to two adjacent columns of pixel units. Two adjacent pixels in the same row are connected to different gate lines. Pixels in the same row connected to the same source line have the same polarity. Adjacent pixels in any column have opposite polarities. The source lines are connected to the multiple data lines through the TFT transistors. The TFT transistors are used to select the corresponding data lines to input into the source lines according to a preset data mapping relationship. Specifically, as shown... Figure 7 As shown, each source line can be connected to two data lines through two TFT transistors. Each TFT transistor is used to select the corresponding data line to input into the source line according to the preset data mapping relationship.

[0045] In this embodiment of the application, based on Figure 7 The in-plane polarity setting shown is in accordance with Figure 6 When the driving timing is shown, the vertical pixel units in any column are arranged in a 1-line inversion (+-+-+-) cyclic pattern. If D1 or D2 is selected to input S1 according to the timing of the TFT tubes A0 / A1 below, S1 will always maintain the same polarity, becoming column inversion, reducing power consumption, and the display effect is equivalent to dot inversion. When EVA (Extended Viewing Angle, which works by displaying different grayscale brightness on adjacent sub-pixels, such as controlling odd-numbered sub-pixels to be brighter and even-numbered sub-pixels to be darker, and so on) is enabled, because the horizontal is equivalent to 2 inversion, the brightness and darkness of the EVA effect can be evenly distributed in the polarity of a single line, resulting in the best effect.

[0046] In the embodiments of this application, such as Figure 7 As shown, each source line is connected to two data lines through two TFT tubes. Each TFT tube is used to select the corresponding data line to input into the source line according to the preset data mapping relationship. For example, the data of source line S1 comes from data lines D1 and D2. The TFT tubes A0 and A1 connected to D1 and D2 select which data line to input. The data of S2 also comes from data lines D1 and D2. The data of S3 and S4 come from data lines D3 and D4. The data of S5 and S6 come from data lines D5 and D6, and so on.

[0047] In an optional embodiment, the timing controller is further configured to: during normal display, output pixel data to the display panel according to a first data mapping relationship, wherein the first data mapping relationship is the data mapping relationship between source line data and data line data required for normal display.

[0048] In this embodiment of the application, the first data mapping relationship can be specifically as follows: Figure 8 As shown, taking the first sourceline as an example, the output data needs to be G11, B11, R21, B22 in sequence. The first letter indicates the R / G / B color, the first number in the subscript indicates the physical row number, and the second number indicates which pixel. For example, B21 represents the blue data of the first pixel in the second row.

[0049] Of course, under normal display conditions, the mapping method of Tcon output data can be adjusted to meet display requirements. If Tcon output is limited (not all mapping methods are supported by Tcon), the order of gate lines can be swapped to better match display requirements.

[0050] In an optional embodiment, the timing controller is further configured to: output pixel data to the display panel according to a second data mapping relationship when the DLG function is displayed, wherein the second data mapping relationship is the data mapping relationship between the source line data and the data line data required for the DLG function display.

[0051] In this embodiment of the application, the second data mapping relationship can be specifically as follows: Figure 9 As shown, taking the first sourceline as an example, the data to be output is G11 (G21 sends the value of G11), B11 (B21 sends the value of B11), etc., that is, both gates are opened at the same time. This halves the vertical resolution, and half of the data in the source IC will also be lost. Therefore, the previous G21 needs to send the data of G11 again, and the original data of G21 is discarded. Each data output is held for two lines.

[0052] The first data mapping relationship mentioned above is the data mapping relationship between source line data and data line data required for normal display. The second data mapping relationship is the data mapping relationship between source line data and data line data required for DLG function display. Figure 8 and Figure 9 The examples are alternative implementation methods, which can be adjusted according to actual needs in practical applications.

[0053] Based on the driving circuit, specific operating timing, and specific data mapping relationship provided in this application, it can achieve both EVA effect and DLG function.

[0054] According to another aspect of the embodiments of this application, this application provides an embodiment of a display panel, such as... Figure 10As shown, the display panel includes an array substrate 100, a color filter substrate 300, and a liquid crystal layer 400 disposed between the array substrate 100 and the color filter substrate 300. The array substrate 100 includes the driving circuit described above.

[0055] According to another aspect of the embodiments of this application, this application provides an embodiment of a display device, such as... Figure 11 As shown, the display device includes a backlight module 200 and the aforementioned display panel. The backlight module 200 is disposed on the backlight side of the array substrate 100 and is used to provide a light source to the display panel.

[0056] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A driving circuit for a display panel, comprising multiple gate lines and a timing controller, characterized in that, The driving circuit includes a signal selection module, which is connected to gate line G4n+2, gate line G4n+3, and the timing controller, where n is an integer greater than or equal to 0. The signal selection module, upon receiving a dual-line gate function selection signal from the timing controller, swaps the outputs of gate line G4n+2 and gate line G4n+3. This ensures that when the timing controller outputs the gate line scanning signal according to the target timing sequence, it scans to rows 4n+1 and 4n+2 in one pass, or to rows 4n+3 and 4n+4 in one pass. The dual-line gate function is implemented in the following manner: the target timing is that gate lines G4n+1 and G4n+3, and gate lines G4n+2 and G4n+4 are alternately turned on; gate lines G4n+1 and G4n+3 are turned on simultaneously; and gate lines G4n+2 and G4n+4 are turned on simultaneously. When gate lines G4n+1 and G4n+3 are turned on simultaneously, rows 4n+1 and 4n+2 are scanned in one pass; when gate lines G4n+2 and G4n+4 are turned on simultaneously, rows 4n+3 and 4n+4 are scanned in one pass.

2. The driving circuit for the display panel according to claim 1, characterized in that, The signal selection module includes a first transistor and a second transistor. The control terminal of the first transistor is connected to the timing controller. The first terminal of the first transistor is connected to the start terminal of the gate line G4n+2. The second terminal of the first transistor is connected to the gate line G4n+3. The control terminal of the second transistor is connected to the timing controller. The first terminal of the second transistor is connected to the start terminal of the gate line G4n+3. The second terminal of the second transistor is connected to the gate line G4n+2.

3. The driving circuit for the display panel according to claim 1, characterized in that, The signal selection module further includes a third transistor and a fourth transistor. The control terminal of the third transistor is connected to the timing controller. The first terminal of the third transistor is connected to the start terminal of the gate line G4n+2, and the second terminal of the third transistor is connected to the gate line G4n+2 as a part of the gate line G4n+2. The control terminal of the fourth transistor is connected to the timing controller. The first terminal of the fourth transistor is connected to the start terminal of the gate line G4n+3, and the second terminal of the fourth transistor is connected to the gate line G4n+3 as a part of the gate line G4n+3.

4. The driving circuit for the display panel according to claim 3, characterized in that, The signal selection module is also used to maintain the original output of the gate line G4n+2 and the gate line G4n+3 when it receives the normal display selection signal issued by the timing controller, so that the gate line is scanned line by line when the timing controller outputs the gate line scanning signal according to the preset timing sequence, wherein the preset timing sequence includes the gate line G4n+1, the gate line G4n+2, the gate line G4n+3 and the gate line G4n+4 being turned on in sequence.

5. The driving circuit for the display panel according to any one of claims 1 to 4, characterized in that, The driving circuit also includes multiple source lines, multiple data lines, and multiple TFT transistors. The multiple source lines are arranged vertically between the pixel array. Each source line is connected to two adjacent columns of pixel units. Two adjacent pixels in the same row are connected to different gate lines. Pixels in the same row connected to the same source line have the same polarity. The polarities of adjacent pixels in any column of pixel units are opposite. The source lines are connected to multiple data lines through the TFT transistors. The TFT transistors are used to select the corresponding data lines to input into the source lines according to a preset data mapping relationship.

6. The driving circuit for the display panel according to claim 5, characterized in that, The timing controller is further configured to: during normal display, output pixel data to the display panel according to a first data mapping relationship, wherein the first data mapping relationship is the data mapping relationship between source line data and data line data required for normal display.

7. The driving circuit for the display panel according to claim 5, characterized in that, The timing controller is further configured to: output pixel data to the display panel according to a second data mapping relationship when the dual-line grid function is displayed, wherein the second data mapping relationship is the data mapping relationship between the source line data and the data line data required for the dual-line grid function display.

8. A display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, characterized in that, The array substrate includes the driving circuit as described in any one of claims 1 to 7.

9. A display device, characterized in that, It includes a backlight module and a display panel as described in claim 8, wherein the backlight module is disposed on the backlight side of the array substrate and is used to provide a light source to the display panel.

Images