Error detection scheme for emulating content-addressable memory

Abstract

The present disclosure relates to error detection schemes for analog content addressable memories. Examples of the disclosed techniques provide new circuits for detecting errors in aCAMs with improved efficiency. Designed specifically around the structure and operation of an aCAM array, these circuits include a counter subcircuit electrically connected to a match line of an aCAM row so that the counter subcircuit receives a match-related signal output from the aCAM row. The value stored by the counter subcircuit can be changed in response to receiving a match signal, or can remain unchanged in response to receiving a mismatch signal. As will be described in detail below, after a set of (particularly calculated) error detection input vectors are sequentially applied to the circuit, the value stored by the counter subcircuit can be used to detect / identify errors in its associated aCAM row.

Description

Background Art

[0001] A content-addressable memory ("CAM") is a computational memory in which stored data is searched by its content rather than by its location. When a "word" is input into the CAM, the CAM searches for the word within its contents. If the CAM finds the word (i.e., "returns a match"), the CAM returns the address of the location where the word was found.

[0002] An analog CAM ("aCAM") is a special type of CAM that can use the programmable conductance of a memristor to store and search a range of values ​​(in contrast to more traditional digital-based CAMs that are only able to store / search 0s and 1s).

[0003] Individual aCAM cells may be arranged into an aCAM array consisting of rows and columns of aCAM cells. Words may be stored along rows of the aCAM array (rows of the aCAM array may be referred to as "match lines"), where each aCAM cell of a given row stores an entry of the stored word. When the aCAM array receives an input word (e.g., a series of analog voltage signals, each analog voltage signal representing an entry of the input word), the aCAM array may search for the input word entry by entry along the columns of the aCAM array (i.e., the first entry of the input word may be searched along the first column of the aCAM array, the second entry of the input word may be searched along the second column of the aCAM array, etc.). The aCAM array will "find" the input word in a given row if all of the aCAM cells of the given row return a match for their corresponding entries of the input word. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure according to one or more various examples is described in detail with reference to the following drawings. The drawings are provided for illustration purposes only and depict examples only.

[0005] Figure 1 An example aCAM array is depicted according to an example of the presently disclosed techniques.

[0006] Figure 2 Depicted are example circuits according to examples of the presently disclosed techniques.

[0007] Figure 3 An example table depicting an example according to the techniques of this disclosure.

[0008] Figure 4 Another example table is depicted according to an example of the techniques of this disclosure.

[0009] Figure 5 Another example table is depicted according to an example of the techniques of this disclosure.

[0010] Figure 6Depicted are example circuits according to examples of the presently disclosed techniques.

[0011] Figure 7 Depicted are example circuits according to examples of the presently disclosed techniques.

[0012] Figure 8 Depicted are example circuits according to examples of the presently disclosed techniques.

[0013] Fig. 9 Depicted is a block diagram of an example computer system in which various examples described herein may be implemented.

[0014] The drawings are not exhaustive and do not limit the disclosure to the precise forms disclosed. DETAILED DESCRIPTION

[0015] Content addressable memory (CAM) is powerful, efficient, and fast. However, traditional CAM (i.e., digital / non-analog CAM) is also relatively large, consumes a lot of power, and is relatively expensive. These shortcomings have historically limited the applicability of CAM to applications where the power, efficiency, and speed of the CAM are sufficient to outweigh its size, cost, and power consumption.

[0016] However, recent developments involving analog CAM (aCAM) have achieved significant reductions in size, cost, and power consumption (as used herein, aCAM can be considered a special type of CAM). As a result, aCAM has recently been introduced as a valuable accelerator for a variety of computing tasks, including matrix multiplication, machine learning tasks (such as tree-based inference), analog signal processing, scientific computing, etc.

[0017] Although aCAMs are generally more powerful, efficient, and faster than other non-CAM memories / memory processing circuits, they are susceptible to errors from several sources, including: (1) inaccurate programming of memristor conductance values ​​(e.g., the conductance value to which the memristor is actually programmed may be different from the intended conductance value); (2) drift of stored conductance values ​​over time (e.g., the conductance value to which the memristor was initially programmed may drift over time, causing the conductance value actually stored by the memristor to be different from the value originally programmed); (3) manufacturing defects (e.g., shorted cells or open cells); etc. When one or more aCAM cells of an aCAM row contain errors, the aCAM row may (a) erroneously return a match for an input word that was not programmed / intended to be stored in the aCAM row; or (b) erroneously return a mismatch for an input word that was actually programmed / intended to be stored in the aCAM row. These erroneous match line outputs can negatively impact the performance of the aCAM array. For example, the aCAM array may not be able to accurately / efficiently perform a specified computational task. For this reason, the ability to detect errors in the aCAM array can be very important.

[0018] However, there is currently a lack of technology for detecting errors in this emerging technology field (partly because the technology used to detect errors in other memory devices is not applicable to aCAM due to differences in functionality). Relatedly, available (and unsophisticated) methods for detecting errors in aCAM arrays are generally inefficient and can consume a large amount of computing resources. For example, while errors in an aCAM array can be detected by sequentially reading the conductance values ​​stored in the constituent cells of the aCAM array using the read circuit of the aCAM array, this approach can require a large number of reads of a larger aCAM array. For example, in an aCAM array comprising 512 rows and 50 columns, detecting errors by sequentially reading the conductance values ​​using the read circuit of the aCAM array would require 25,600 reads, which, as mentioned, would consume a large amount of computing resources. Therefore, there is a need for more efficient technology for detecting errors in this emerging and valuable technology field.

[0019] In this context, examples of the disclosed technology provide new circuits for detecting errors in aCAMs with improved efficiency. Designed specifically around the structure and operation of an aCAM array, these circuits include counter subcircuits (e.g., modulo-2 counter subcircuits) electrically connected to match lines of an aCAM row, such that the counter subcircuits receive match-related signals output from the aCAM row (i.e., a given counter subcircuit receives a match-related signal output from an aCAM row electrically connected to the same match line to which the given counter subcircuit is electrically connected). The match-related signal output from the aCAM row may include a match signal when each aCAM cell of the aCAM row returns a match in response to an input vector applied to the circuit, and the match-related signal output from the aCAM row may include a mismatch signal when at least one of the aCAM cells of the aCAM row returns a mismatch in response to an input vector applied to the circuit (such an input vector may include multiple analog voltage signals, each analog voltage signal applied along a different column of the aCAM array, or a digital signal / series of digital signals that are converted into analog voltage signals before being applied along the columns of the aCAM array). The value stored by the counter subcircuit may change in response to receiving a match signal, and may remain unchanged in response to receiving a mismatch signal. As will be described in more detail below, the value stored by the counter subcircuit may be used to detect / identify errors in its associated aCAM row after a set of (specially calculated) error detection input vectors are sequentially applied to the circuit.

[0020] In certain embodiments, the circuit may also include "redundant aCAM cells" that are programmed to store (specifically calculated) redundant values ​​for error detection purposes (as will be described below, in other embodiments these redundant values ​​may be stored in a memory external to the aCAM array and then applied to the circuit by strategically initializing and reinitializing the values ​​stored by the counter subcircuit prior to and / or during application of the error detection input vector). For example, the redundant values ​​may be programmed into an aCAM row by programming the conductance of a memristor in one or more redundant aCAM cells added to the aCAM row (these redundant aCAM cells are electrically connected to a match line along with the non-redundant aCAM cells and may therefore be considered part of the aCAM row). Here, the non-redundant aCAM cells of an aCAM row (i.e., the task-driven aCAM cells) may be freely programmed according to the requirements of the computational task that the aCAM array is being used to perform. As will be described in more detail below, a parity check matrix (H) may be used to calculate redundancy values ​​(as used herein, a parity check matrix may refer to a matrix or similar representation that describes conditions that a codeword of a code must satisfy, and the parity check matrix (H) may be calculated based on the number of columns in the aCAM array and the maximum number of errors to be detected per aCAM row (τ). By using the parity check matrix (H), the redundancy values ​​may be calculated such that each row of the aCAM array is programmed to "representatively" store at least one codeword of a code (C) (the aCAM cells effectively store an analog voltage threshold - the value of which may be programmed by programming the conductance of the constituent memristors of the aCAM cells). Here, the codeword may be (representatively) programmed across all aCAM cells of an aCAM row or across a subset of aCAM cells of an aCAM row. The code (C) may be related to the number of programmable levels of the aCAM cells of the aCAM array (as will be described in more detail below, a The number of programmable levels of an aCAM cell may be proportional to the number of unique / discrete conductance values ​​to which the constituent memristors of that aCAM cell may be reliably programmed). In certain implementations (e.g., internal redundancy implementations of the bit interleaving scheme described below), computing redundancy values ​​such that each row of the aCAM array is programmed to (representatively) store at least one codeword of a code (C) may correspond to computing redundancy values ​​such that each row of the binary array representing words (representatively) programmed across a given aCAM row in binary digits (i.e., 1s and 0s) includes sequences of 1s and 0s specified by a parity check matrix (H). These sequences, applied to a given aCAM row by programming redundant analog voltage thresholds in the redundant aCAM cells of the given aCAM row, ensure that each row of the binary array representing words (representatively programmed across the given aCAM row) in binary digits includes at least one codeword of a code (C) associated with the binary parity check matrix (H).

[0021] As described above, utilizing applied redundancy values ​​(e.g., applied via "internal redundancy," where redundant aCAM cells are added to the aCAM array, or applied via "external redundancy," where redundant values ​​are stored in external memory and applied to the circuit by strategically initializing / reinitializing the stored values ​​of the counter subcircuits), the circuits of the disclosed techniques detect errors in aCAM rows based on the stored values ​​of the counter subcircuits associated with the aCAM rows after a set of (specially calculated) error detection input vectors are sequentially applied to the circuit. Similar to the redundancy values ​​described above, the set of error detection input vectors may be calculated based on a parity check matrix (H). In certain implementations (e.g., an internally redundant implementation of a bit interleaving scheme), the circuit detects an error in an aCAM row when: (a) if the binary parity check matrix (H) specifies even parity, then the value stored by a counter subcircuit (electrically connected to a match line of the aCAM row) after sequentially applying the set of error detection input vectors is different from the value stored by the counter subcircuit before sequentially applying the set of error detection input vectors (as described above, this can correspond to the counter subcircuit receiving an even number of match signals); and (b) if the binary parity check matrix (H) specifies odd parity, then the value stored by the counter subcircuit after sequentially applying the set of error detection input vectors is the same as the value of the counter subcircuit before sequentially applying the set of error detection input vectors (as described above, this can correspond to the counter subcircuit receiving an odd number of match signals).

[0022] Referring again to the error detection input vectors, each error detection input vector may include a plurality of analog voltage input signals, each analog voltage input signal being applied to one of the columns of the aCAM array (when initially received by the circuit, the error detection input vector may include a digital input signal / multiple digital input signals that are converted by the circuit to a plurality of analog voltage signals before being applied to the aCAM columns). Each error detection input vector may include only one "non-wildcard" analog voltage input signal, the "wildcard" analog voltage input signal being calculated such that any aCAM cell of the aCAM array always returns a match when the wildcard analog voltage input signal is applied thereto (by this construction, each error detection input vector effectively checks one column of the aCAM array). In part through its relationship to the parity check matrix (H) (the parity check matrix (H) itself is calculated based on the number of columns in the aCAM array and the maximum number of errors to be detected per aCAM row (τ)), a set of error detection input vectors can be calculated based on: (a) the number of columns in the aCAM array, where the number of error detection vectors in a set of error detection vectors is an integer multiple of the number of columns in the aCAM array; (b) the number of programmable levels that each aCAM cell of the aCAM array can be programmed to store; and (c) the maximum number of errors to be detected (τ) across a single row of aCAM cells.

[0023] As described above, the circuits of the disclosed technology can detect errors in an aCAM array more efficiently than existing / conventional techniques. For example, as described above, detecting errors by sequentially reading conductance values ​​using a read circuit of a 512x50 aCAM array (i.e., an aCAM array having 512 rows and 50 columns) would require 25,600 reads. In contrast, the circuits of the disclosed technology can detect up to one error per row of a 512x50 aCAM array with only 357 reads (i.e., applying 357 error detection input vectors distributed across multiple sets of error detection input vectors), where the aCAM cells each have 8 programmable levels, or with 765 reads (i.e., applying 765 error detection input vectors distributed across multiple sets of error detection input vectors), where the aCAM cells each have 16 programmable levels (in an "internal redundancy" implementation such circuitry may include adding a redundant column to the aCAM array). Similarly, the circuitry of the disclosed techniques can detect up to three errors per row of a 512x50 aCAM array with only 1309 reads (i.e., applying 1309 error detection input vectors distributed across multiple sets of error detection input vectors), where the aCAM cells each have 8 programmable levels, or with 2805 reads (i.e., applying 2805 error detection input vectors distributed across multiple sets of error detection input vectors), where the aCAM cells each have 16 programmable levels (in an "internal redundancy" implementation such circuitry may include adding 3 redundant columns to the aCAM array). As demonstrated by either of these exemplary comparisons, the circuitry of the disclosed techniques can detect errors in an aCAM array significantly more efficiently than existing / conventional techniques. Such improved efficiency can reduce the time, power consumption, computational resources, costs, etc. associated with detecting errors in an aCAM array.

[0024] It should also be appreciated how the circuits of the disclosed techniques exploit the unique construction / operation of aCAM circuits in their error detection schemes. In particular, the example circuits exploit the parallel operation of the aCAM array (i.e., a given error detection input vector can be applied to all aCAM rows of the aCAM array simultaneously, and by extension, each aCAM row of the aCAM array produces its match line output simultaneously) so that the time complexity of the error detection cycle will not depend on the number of aCAM rows. Thus, the examples can greatly reduce the time complexity associated with detecting errors in very large aCAM arrays having, for example, thousands of aCAM rows.

[0025] Before describing examples of the presently disclosed techniques in more detail, it may be helpful to briefly introduce (1) certain notations used in the ensuing description; and (2) the basic operation of the aCAM.

[0026] For integers a ≤ b, where [a:b] denotes a subset of integers [a:b> means the set [a:b-1]; this document will use the shorthand notation [b] and [b> to mean [1:b] and [0:b>, respectively.

[0027] q≥2 may be a positive integer representing the alphabet size (as described above, q may also / relatedly represent the number of programmable levels of each aCAM cell of the aCAM array). Here, q comparators (e.g., aCAM cells of the disclosed techniques) may be implemented as a two-variable function Γ defined by the following equation (1): q :[q> 2 →{0, 1} circuit.

[0028]

[0029] The independent variable x may represent an input signal applied to the q-comparator (e.g., an individual signal component of the input signal), and θ may represent a threshold value stored (or representatively stored) by the q-comparator (i.e., herein, the q-comparator is synonymous with the aCAM unit in the technology of the present disclosure).

[0030] As mentioned above, for some threshold θ i，j , recent designs of nanoscale aCAMs use q comparator blocks arranged in an m × n array (i.e., an aCAM array with m rows and n columns), where each entry (i, j) ∈ [m> × [n>] implements the function The input vector (eg, error detection input vector) applied to the aCAM array can be represented as a vector x=(x j ) j∈[n> ∈[q> n , where x j Used as input to all comparators along column j. Each row (“match line”) in the aCAM array computes the conjunction (“AND”, “∧”) of the outputs of the comparators along the row, and the output vector v∈{0,1} from the aCAM array m The non-zero entries in v are called "matches", and in practice, one may be interested in finding all matches (i.e. knowing the entire vector v), or only in whether there is at least one match, or only in the number of matches. Each aCAM cell (i, j) may include a threshold value θ set / programmed to its conductance. i，j (or with threshold θ i，j It is assumed that the frequency of change of these conductances is much lower than the frequency of change of the input vector x.

[0031] Figure 1A conceptual schematic diagram of an aCAM array 100 is presented. The aCAM array 100 consists of an m×n array of aCAM cells. Each aCAM cell acts as a comparator (represented by a triangular shape). Each comparator has two q-ary input terminals and one output binary terminal. For a given comparator / aCAM cell, one input terminal is associated with a threshold analog voltage stored by the aCAM cell and is fed by the memristor of the aCAM cell (here, the memristor of the aCAM cell stores a conductance value proportional to the analog voltage threshold stored by the aCAM cell). The second input terminal of the comparator is connected to an entry of the input vector x through a column conductor (i.e., it is connected to an input analog voltage signal). The output terminals of the n comparators along each row i∈[m> are "ANDed" together to produce a match line value ML i Under normal operation of the aCAM array 100, the output value v of row i i Equal to ML i .

[0032] As described above, the operation of an aCAM (e.g., aCAM array 100) is susceptible to errors from the following aspects, including: (1) inaccurate programming of the conductance value of a memristor (e.g., the conductance value to which the memristor is actually programmed may be different from the expected conductance value); (2) drift of the stored conductance value over time (e.g., the conductance value to which the memristor is initially programmed may drift over time, such that the conductance value actually stored by the memristor is different from the value originally programmed); (3) manufacturing defects (e.g., shorted cells or open cells); etc. When one or more aCAM cells of an aCAM row contain errors, the aCAM row may (a) erroneously return a match for an input word that was not programmed / intended to be stored in the aCAM row; or (b) erroneously return a mismatch for an input word that was actually programmed / intended to be stored in the aCAM row. These erroneous match line outputs may negatively impact the performance of the aCAM array. For example, the aCAM array may not be able to accurately / efficiently perform a specified computing task. For this reason, the ability to detect errors in an aCAM array can be very important. Because available / less sophisticated error detection techniques for aCAMs are generally ineffective, examples of the presently disclosed techniques fill an important need for effective error detection in this emerging and valuable technology area.

[0033] As described above, examples of the disclosed techniques provide several schemes for detecting errors in aCAM (and circuits for implementing these schemes). These schemes generally involve: (1) circuit hardware addition (e.g., counter subcircuits, redundant aCAM cells for internal redundancy schemes, etc.); (2) redundant encoding (which in some examples can be performed during programming of non-redundant / task-driven aCAM cells of an aCAM array); and (3) error detection (which can be performed periodically), which includes applying one or more sets of specially calculated error detection input vectors to the aCAM array, where errors in a given aCAM row of the aCAM array can be detected after applying the final error detection input vector in a set. For example: (1) after applying the final error detection input vector in the first set of error detection input vectors, the disclosed circuit can detect errors in the first aCAM row; (2) after applying the final error detection input vector in the second set of error detection input vectors, the disclosed circuit can detect errors in the second aCAM row; (3) after applying the final error detection input vector in the third set of error detection input vectors, the disclosed circuit can detect errors in the third aCAM row; etc.

[0034] As described above, in order for the disclosed scheme to work, in addition to the task-driven thresholds of the aCAM array (i.e., the thresholds of the aCAM array that are programmed according to the specified computational task of the aCAM array), redundant values ​​are imposed on the aCAM array. These calculated redundant values ​​can be stored in one of two ways: (1) through "internal redundancy", in which the calculated redundant values ​​are programmed as thresholds in redundant columns of the aCAM array (as described above, this can include programming the conductance of the memristors of the redundant aCAM cells so that the redundant aCAM cells effectively store threshold analog voltage values ​​representing the calculated redundant values); and (2) "external redundancy", in which the calculated redundant values ​​are stored in a memory (e.g., SRAM) external to the aCAM array and the redundant values ​​are imposed on the aCAM array by initializing (and in some cases strategically reinitializing) the values ​​stored in the counter subcircuit described above.

[0035] During error detection (i.e., applying an error detection input vector to the aCAM array), aCAM rows containing errors (i.e., aCAM rows returning error / unexpected match related signals) may be detected / identified based on the values ​​stored by the counter subcircuit described above. Each of the disclosed schemes may have different tradeoffs between the range of properties they provide: (a) the amount of changes and additions to circuit hardware; (b) the number of redundant columns, and (c) the time complexity (or latency) of the detection cycle.

[0036] As described above, these schemes typically exploit the parallel operation of aCAMs, in which all aCAM rows of an aCAM array are simultaneously fed with an error detection input vector and produce their corresponding match line outputs. Therefore, the time complexity of the detection cycle in these schemes may not depend on the number of aCAM rows in the aCAM array.

[0037] Here, for convenience, the threshold θ i，j Viewed as a ring of integers modulo q Then the aCAM array (e.g., aCAM array 100) can be viewed as An m×n array on which θ i =(θ i，j ) j∈[n> represents the vector of thresholds along i∈[m>. As mentioned above, encoding can usually be performed so that each θ i form Some codes (subset) For a given k (which depends on the code ), θ i The first k entries in may comprise task-driven thresholds, which may be freely selected (during the programming phase) according to the desired computational task of the aCAM array. The remaining r=nk entries may form a redundant portion of the aCAM array (i.e., redundant columns storing computed redundant values ​​or representationally storing them as thresholds) and may be used by a processor for Here, the example may seek to minimize r according to a specified number of errors expected to be detected per aCAM row.

[0038] With reference to the errors thus far, this document (implicitly) assumes the Hamming metric, where an error event means that the threshold is incorrect, without taking into account the (integer) difference between the correct value and the incorrect value. The Hamming metric can be conservative because it can model various error sources, such as failures of comparators or drifts in programmed thresholds. If only drift errors are expected, it may be beneficial to consider the K1 metric, so that the final detection scheme will require less redundancy. Under the K1 metric, an error event can be defined as changing the threshold by ±1 (larger changes are interpreted as having multiple errors at the same threshold).

[0039] The subsequent description of examples of the disclosed techniques is organized as follows. Section I will summarize definitions and properties related to codes. Section II will describe "internal redundancy" implementations of two detection schemes for the Hamming metric: the bit interleaving scheme (Construction A in Section II-A) and the shift and count scheme (Construction B in Section II-B). Section II-C will describe "external redundancy" implementations of both schemes. Section III will describe example circuits constructed according to Sections I-II.

[0040] In all of the disclosed detection schemes, the number of test vectors grows linearly with the alphabet size q and grows superlinearly with the number of columns of the aCAM array, and is independent of the number of rows of the aCAM array. As described above, this feature allows examples of the disclosed techniques to reduce the time complexity for detecting errors in large aCAM arrays with many rows.

[0041] I. Definitions and Notation

[0042] Examples can be used in The code is linear and systematic That is, in There exists a k×n matrix G on , called the generator matrix, such that:

[0043] (Linear properties)

[0044]

[0045] The operation is Executed in

[0046] (Systematic properties) G includes The reversible k×k submatrix of

[0047] In such a code, the rows of G form the basis of C, i.e., they are linearly independent on G, and each codeword in C can be represented as a (unique) linear combination of the rows of G; therefore, |C| = q k The parameters n, k, and r=nk are respectively referred to as the length, dimension, and redundancy of C. By permuting the columns of G and applying reversible linear operations to the rows of G, the example can obtain a generator matrix of the form:

[0048] (I k |A), (2)

[0049] Among them I k is the k×k identity matrix. Encoding in this case can be performed by the following mapping:

[0050]

[0051] where u forms part of the codeword. For this reason, the example may require a systematic condition (on top of linearity, which will also be useful for the detection process). In order to exploit the full functionality of the aCAM, the coding scheme may not impose any constraints on the first, for example, k, task-driven thresholds in each aCAM row. It may be noted that when q is prime, linearity always implies the systematic property.

[0052] The minimum (Hamming) distance of C, usually denoted by d, is the minimum number of positions at which any two different codewords differ. Equivalently, d is the minimum Hamming weight of any non-zero codeword in C. If a codeword has any pattern of no more than τ = d - 1 errors, then such an event can always be detected (since errors cannot change one codeword into another). Furthermore, if a codeword has no more than If any pattern of errors is not known, the codeword can always be recovered. The length n, dimension k, and minimum distance d of a systematic linear code are usually written as a triple [n, k, d].

[0053] code The parity check matrix is The r×n matrix on the right, such that C forms its right kernel:

[0054]

[0055] (where 0 r express The all-zero columns in the represents the transpose of a vector or matrix). Every systematic linear [n, k = nr, d] code has an r×n parity check matrix consisting of reversible r×r submatrices; in particular, when G has the form (2), then

[0056]

[0057] is such a matrix. Conversely, the matrix consisting of the reversible r×r submatrices Any r×n matrix on is The minimum distance of such a code can be characterized by any one of its parity check matrices H as follows: it is such that every d-1 columns in H are The largest integer d that is linearly independent on the

[0058] Given a row vector y relative to code The syndrome vector of y of the r×n parity check matrix C is the column r vector

[0059]

[0060] Therefore, the codeword of C is the one whose syndrome is all zeros. All vectors in .

[0061] The concept of systematic linear codes is extended in a straightforward way to the ring of integers (except in this case the code will have infinite size). Every linear code on is also systematic (similar to what was said for prime numbers q).

[0062] II. Coding and Detection Schemes

[0063] This section presents two error detection coding schemes for aCAM arrays under the Hamming metric. In this section, m and n denote the number of rows and columns in the array, respectively, and τ is the maximum number of errors that can be detected in a given row. Each scheme uses some systematic linear [n, k = nr, d = τ + 1] code C. In construction A (Section II-A) the code is binary, while in construction B (Section II-B) the code is on. In each encoding scheme, the encoding algorithm can be the same for all rows and can be performed by an encoder of the form of equation (3). In addition, the examples can exploit the nature of the operation of the aCAM, which is that the detection process will apply the same set of (particularly calculated) error detection input vectors to all aCAM rows in parallel (in particular, the latency of the process will not depend on the number of aCAM rows). This section will first describe a scheme using an internal redundancy implementation, in which r columns (out of n) in the aCAM array are reserved for storing redundant values ​​as thresholds (as described above, these redundant values ​​can be programmed / stored by programming the conductance of the memristors in the redundant aCAM cells). Here r can be referred to as the column redundancy of the aCAM array. External redundancy implementations will be discussed in Section III-C.

[0064] Since the encoding and detection process can be consistent across aCAM rows, this document uses the notation θ = (θ j ) j∈[n> denoted by a vector of threshold values ​​along a generic aCAM row in the aCAM array, with the index i of the aCAM row omitted.

[0065] A. Construction A: Bit Interleaving Scheme

[0066] The coding scheme presented in this section (referred to as the bit interleaving scheme or construction A) is applicable to the case where the alphabet size q is a power of 2. Assuming τ is much smaller than n, then It can be [n, k = nr, d = τ + 1] binary alternating code (especially BCH code), whose redundancy is given by the following equation (4):

[0067]

[0068] Writing b = log2 q (which is a positive integer), the row vector θ can be represented as a b×n binary array (i.e., a binary array that represents the vector θ in binary digits)

[0069] Φ=Φ(θ)=(φ s，j ) (s，j)∈[b>×[n>， (5)

[0070] where column j in Φ is the integer θ representing base 2 j {0, 1} b The b vector in:

[0071]

[0072] can be encoded so that for each s∈[b>, the row s in Φ (i.e., φ s =(φ s，j ) j∈[n> ) is a codeword of C (hence the name bit interleaving). Therefore, for r = r(τ,n) in equation (4), the first k = nr entries in θ can be freely selected (depending on the computational task). The remaining r entries can be determined by encoding / computing redundant values. In other words (and as will be described in more detail below), the example can determine a sequence of 1s and 0s for each row s in Φ such that each row s in Φ is a codeword of C. The example can implement this sequence by encoding / computing redundant values ​​to be stored (or representatively stored) in redundant aCAM cells of the aCAM array.

[0073] The basic principle of the detection process is as follows: Given C's r×n binary parity check matrix H = (H l，j ) (l，j)∈[r>×[n> , error detection is achieved by testing the following equation for each s∈[b>:

[0074]

[0075] (where the equation is To this end, an example circuit constructed according to the bit interleaving scheme adds a modulo-2 counter subcircuit (i.e., a toggle bit) to each match line of the aCAM array (i.e., the modulo-2 counter subcircuit can be electrically connected to the match line of the aCAM row so that the modulo-2 counter receives a match-related signal output from the aCAM row). The modulo-2 counter subcircuit can be synchronized with the clock of the n-vector input to the aCAM and can flip its value each time its input is 1 (e.g., each time it receives a match signal output from the aCAM row that shares a match line with it).

[0076] Figure 2 An example aCAM array 200 is depicted with counter subcircuits added (these counter subcircuits may be modulo-2 counter subcircuits or other types of counter subcircuits). In some examples, "REG" therein may represent single-bit memory, and the circled "+" may represent addition modulo-2. In other words, each modulo-2 counter subcircuit may have one input bit and one output bit, and may include a single-bit memory element (REG). During each clock cycle, the contents of the REG may be updated by XORing the contents of the REG with the input. The output may be the contents of the REG (where XOR is equivalent to addition modulo-2).

[0077] As mentioned above, during the detection cycle, a group of The error detection input vectors are applied to the aCAM array 200. The set of error detection input vectors will be described in more detail below after introducing some notations.

[0078] For j∈[n>, let e j is a standard unit vector that includes (only) “1” at position j and for each l∈[r> by J l Express support from Bank of China

[0079] J l ={j∈[n>:H l，j ≠0}

[0080] Moreover, for (l, s)∈[r>×[b>, let For n The following subset of:

[0081]

[0082] (Its size is 2 b-s-1 ·|J l |). Collection Now it is defined as a union:

[0083]

[0084] therefore;

[0085]

[0086] where ‖H‖ denotes the total number of 1s in the matrix H. This number is at most r·n, and for r>1, it is typically close to r·n / 2.

[0087] The following algorithm (9) presents a detection cycle where The elements of are applied to the aCAM array 200 as error detection input vectors.

[0088]

[0089] As depicted, ML i and MODC i denote the (binary) contents of the match line and modulo-2 counter subcircuit of row i, respectively. In each iteration on (l, s), Error detection in the input vector calculation vector The entry l in (see equation (7)). If at some aCAM row the vector If non-zero, an error is marked at that line (see Figure 2 During the detection cycle, the example can take the output v of row i i Switch to MODC i Instead of ML i ). It can be observed that at the beginning of each iteration of the loop over s, MODC i = 0 is an invariant, and therefore, at the end of each iteration MODC i The values ​​of are the same, as if Considered to be a larger set

[0090] {α·2 s ·e j : α∈[1:2 b-s >, j∈J l}

[0091] (In other words, for a given (l, s), Algorithm (9) reuses the previous computation for (l, s′>s)).

[0092] In summary, an example detection process according to the techniques of this disclosure may include applying at most (q-1)·r·n test vectors to the aCAM array 200 (and typically half that number). The required column redundancy is determined by equation (4).

[0093] Example 1: As an illustrative example, an aCAM array with m=512 rows and k=50 columns may be susceptible to errors. As described above, an existing / conventional method for detecting errors would involve periodically reading thresholds directly across the aCAM array, which would require m·k=25600 reads. In contrast, Figure 3 Table 300 of φ presents the column redundancy r and the error detection input vector used in construction A, where q = 8, 16 and τ = 1, 2, 3. As described above, equation (8) can be used to calculate the error detection input vector (As described above, this may include multiple sets of error detection input vectors.) For τ=1, the matrix H is a 1×51 all-1 vector (11…1). For τ=2, it is a 6×56 parity check matrix for a shortened binary Hamming code, where the columns range over the lightest (Hamming weight) non-zero binary 6-vector. And for τ=3, it is a 7×57 parity check matrix for a shortened extended binary Hamming code, where the columns range over the lightest binary 7-vector with odd Hamming weight.

[0094] This can be done by changing the radix 2 to have q = ρ for some positive integer b. b The construction A can be generalized to any cardinality ρ ≥ 2. Accordingly, the counter subcircuit in each aCAM row will now be modulo ρ and the code C will be in In this example, C will have a 0-1 parity check matrix, i.e., its entries are constrained to Otherwise, implementing the check of equation (7) would require a different (and potentially larger) set of test vectors

[0095] In this more general setting, the set It can be defined by the following formula:

[0096]

[0097] B. Construction B: Shift and Count Scheme

[0098] The configuration presented in this section (referred to as the shift-and-count scheme or Configuration B) can have less column redundancy than Configuration A, at the expense of using a more complex counter subcircuitry that electrically connects the match lines to the aCAM rows. Configuration B may require that q be prime, i.e., is a finite field GF(q) (as described above, q represents the alphabet size of the code and, relatedly, the number of programmable levels of the aCAM cells of the aCAM array). To be clear, in construction B q is prime and this section will use the symbol p instead of q. In contrast to construction A, which involves using base-2 representation (i.e., a binary array) to represent the threshold vector θ, construction B uses a base-2 representation of the entries of the parity check matrix that defines the underlying code of the scheme. The threshold vector will be the codeword of C.

[0099] Let C be The linear [n, k = nr, d = τ + 1] code on the l，j ) (l，j)∈[r>x[n> for The r×n parity check matrix of C on . Write And for l∈[r>, let b l In order to make The smallest positive integer (for this purpose, the example will be the entry H l，j is considered to be an integer in [p>). Therefore, for all l∈[r>, b l ≤b. For each (l, j)∈[r>×[n>, let is (integer) H l，j The basis 2 represents:

[0100]

[0101] Then, for any

[0102]

[0103] (exist above), if and only if the following equality holds for every l∈[r>

[0104]

[0105] (exist The shift and count scheme involves computing redundant values ​​such that equation (11) holds, and a detection cycle that detects a set of errors by inputting a vector Applied to the aCAM array (as before) to verify equation (12). As mentioned above, detection may require a modulo-p counter subcircuit (as opposed to a modulo-2 counter subcircuit) which may also multiply by 2 (modulo-p).

[0106] This section will now describe the collection To do this, we transform each entry H l，j Replace with column vector It is convenient to define r obtained from H * ×n 0-1 matrix H * . Specifically, H * With r * =∑ l∈[r> b l rows (indexed by pairs (l,s), where l∈[r> and s∈[b l >) and n columns (indexed by j∈[n>, and (H * ) (l，s)，j =(h l，s，j )).Depend on Indicates H * Support for (l, s) in the bank, set can be defined as a union:

[0107]

[0108] where for each l∈[r) and s∈[b l >,

[0109]

[0110] therefore,

[0111]

[0112] The following algorithm (14) presents the detection cycle, which for each l∈[r> and s∈[b l >Verify equation (12). Symbol MODSC i represents the stored value of the counter subcircuit, which can also be multiplied by 2 modulo p. (Note that by replacing b with b l , so that the cycle on s is consistent over all l∈[r>, and accordingly, for s∈[b l +1, b> take ).

[0113]

[0114]

[0115] Example 2: Access the aCAM array of Example 1 again. Figure 4 Table 400 of FIG. 4 presents the parameters used to construct B. The values ​​q=8,16 have become prime numbers p=11,17, respectively (as described above, the value of q may represent the number of programmable levels of the aCAM cells of the aCAM array, which may need to be prime in this case). For τ=1, the matrix H is again an all-ones vector. For τ=2, it is The 3×53 parity check matrix of the shortened Hamming code (while choosing the lightest possible columns), and for τ=3, the 4×54 parity check matrix of the (shortened) code (presented in Problem 3.44 of RM Roth’s article “Fault-tolerant dot-product engines”, IEEE Trans. Inf. Theory, vol. 65, 2046–2057, 2019), while minimizing ‖H over all possible choices of the irreducible polynomial f(·,·) therein and the entries in the second and third rows. * ‖, and add to the fourth row all possible linear combinations of the first three rows.

[0116] If C represents Normalized alternating code on Under the assumption of ), then:

[0117]

[0118] For large p, this expression is approximately (1 / 2)log2p less than the column redundancy of construction A represented by equation (4). * The number of rows in r * As defined above:

[0119]

[0120] Therefore, if ‖H * ‖ is estimated to be r·b / n / 2, and accordingly in equation (8) ‖H‖ is estimated to be r·n / 2, then in equation (13) The size of is constructed in A It can be noted that these estimates are somewhat conservative, for example, for τ = 4, for p = 17 The size is actually smaller than Figure 3 For q=16 in Table 300 The corresponding size.

[0121] Figure 5 Table 500 summarizes the (approximate) values ​​of column redundancy and number of false detection input vectors for constructions A and B (note the different bases of the logarithms). * The estimate of ‖ is based on H and H * The assumption is that half of the entries in are equal to 1. These estimates may be conservative.

[0122] C. External Redundancy

[0123] In the manner they are presented in Sections III-A and III-B, respectively, Constructions A and B use columns of the aCAM array (i.e., redundant columns containing redundant aCAM cells) to store computed redundant values ​​in each row of the aCAM array. These redundant values ​​are programmed as thresholds, similar to the task-driven thresholds of the aCAM array (i.e., the redundant values ​​are effectively stored as analog voltage thresholds of the respective redundant aCAM cells, where the (redundant) analog voltage thresholds are programmed / tuned by programming the conductance of the memristors in the redundant aCAM cells).

[0124] In contrast, in an external redundancy implementation, the redundant values ​​are stored in a separate memory (e.g., random access memory (RAM), static RAM (SRAM), etc.) external to the aCAM array. This approach is applicable to both structures A and B. For simplicity, this section will describe the external redundancy implementation for structure A (i.e., the bit interleaving scheme), but the same / similar principles will apply to the external redundancy implementation for structure B (i.e., the shift and count scheme).

[0125] Various embodiments utilizing external memory may pre-compute the contribution of the redundant values ​​to the left side of equation (7) in the external memory, thereby eliminating the need for redundant columns in the aCAM array. However, such external redundancy schemes assume that the redundant values ​​are arranged in columns (similar to the aCAM array) and that they are susceptible to errors like any aCAM cell. However, these assumptions may not always apply. For example, examples may arrange the redundant values ​​in the external memory in various ways, and therefore various error correction and error detection techniques may be used to protect those stored redundant values ​​from errors. Therefore, for the purpose of error detection in the aCAM, it may be assumed that the stored redundant values ​​are error-free.

[0126] In doing so (with the same parity check matrix H), the example can use the full m×n aCAM array (rather than just an m×k array) for task-driven thresholds (i.e., those thresholds used to perform a specified computational task of the aCAM array), where each row is (freely) filled with a threshold vector Instead of requiring equation (7), encoding may involve computing φ with respect to the r×n parity check matrix H for each s∈[b) s The syndrome vector of :

[0127]

[0128] Here, each syndrome vector σ s can be a ρ-ary r vector, and thus each difference is

[0129] Δ s，i =(Δ l，s，i )l∈[r＞ =σ s+1 -σ s , s∈[b>,

[0130] Here the example defines σ b =0, and the symbol Δ s，i The dependence on the row index i in aCAM is made explicit. These differences (whose magnitudes are br symbols) can be stored in external memory. Now, the role of the detection cycle will be to verify equation (16) (rather than equation (7)). This is done by incrementing the modulo p counter MODC for each i∈[m> and for each (l,s)∈[r>×[b> i The initialization is changed to:

[0131] MODC i ←Δ l，s，i，

[0132] To achieve.

[0133] There are several advantages to using external memory for redundancy. First, the length of the code used by the example does not need to exceed the number of aCAM columns used to compute the task (i.e., all programmed thresholds of the aCAM array can be "task-driven" thresholds). This in turn reduces the number of error detection input vectors that need to be applied for detection, since there are no redundant columns to test. In addition, as shown in Example 3 below, shorter codes sometimes mean less redundancy. Second, using external memory allows the redundant alphabet to be larger than the local alphabet of the aCAM, for example, if the local alphabet is 8 and we want to use construction B, then we need to take p=11. The freely selectable task-driven threshold can still be constrained to [8>, however the redundancy (or syndrome) value can also take a value in [8:11>, i.e., outside the range of thresholds that can be programmed into the individual cells of the aCAM. In other words, the example can apply construction B in the case where the number of programmable levels of the constituent cells of the array is not a prime number.

[0134] When using construction A, utilizing external memory provides an additional advantage in allowing unequal error protection for less significant bits relative to more significant bits. For example, lower bits may require less (or no) protection if they do not affect the result; or they may require higher protection because they are more susceptible to drift in the value of the programmed threshold. Different indices s∈[b> can be selected with respective (binary) parity check matrices H by denoting different indices s∈[b> for the cardinality ρ of the thresholds. s and redundancy r s Different codes C s (all length n) to achieve this flexibility. In this case, equation (16) becomes

[0135]

[0136] Since each row φ in Φ s The syndromes of are now computed with respect to different parity check matrices, so an iteration in Algorithm (14) for a given pair (l, s) cannot reuse the computations previously made for (l, s′>s). Therefore, The definition can be modified as follows:

[0137]

[0138] Among them J l，s Yes H s The support of line l in . The expression (8) is also changed accordingly to

[0139]

[0140] Using different codes, examples can reduce the total number of redundancy / syndrome values.

[0141] Storing the (error-free) syndromes in external memory may also allow the example to use a code C with (the same minimum distance but still with) less redundancy. This can be demonstrated in Example 3 below.

[0142] Example 3: Example 3 may involve the 512×50 aCAM array of Example 1, but with an alphabet size of q=7, and may consider construction B with τ=3. Using internal redundancy, the example would require C to be On the other hand, using external redundancy / syndrome, the example can be obtained by taking H to be A 4×50 parity check matrix of a linear [n=50, k=46, d=4] code on φ with redundancy r=4.

[0143] III. Example Circuit

[0144] Example 6 depicts an example circuit 600 for detecting errors in an aCAM array according to various examples of the disclosed techniques. Circuit 600 may be an example circuit implementing an internal redundancy implementation of the bit interleaving scheme (ie, Configuration A) described above.

[0145] As depicted, circuit 600 includes an aCAM array 610. aCAM array 610 includes a plurality of rows (e.g., aCAM rows 610(A), 610(B) ... 610(X), 610(Y), etc.) and a plurality of columns (e.g., aCAM columns 610(0), 610(1), 610(2) ... 610(n-1), etc.) of aCAM cells.

[0146] The aCAM column 610(n-1) may be a redundant column, and the aCAM cell 610(A)(n-1) may include the redundant aCAM cell of the aCAM row 610(A). In various examples, the aCAM array 610 may include additional redundant columns. In other words, the aCAM row 610(A) may include additional redundant aCAM cells.

[0147] As described above, each aCAM cell of an aCAM row 610(A), including redundant aCAM cells 610(A)(n-1), can be programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the aCAM row 610(A). As described above, each aCAM cell of an aCAM row 610(A) can include a memristor. The aCAM cells of an aCAM row 610(A) can be programmed to store their associated analog voltage threshold by programming the conductance of their associated memristors. The number of programmable levels that an aCAM cell of an aCAM array 610 can store can be proportional to the number of conductance values ​​to which their associated memristors can be reliably programmed.

[0148] The memristors of the redundant aCAM cells 610(A)(n-1) may be programmed such that the aCAM cells 610(A)(n-1) store calculated redundant analog voltage thresholds (i.e., analog voltage thresholds representing calculated redundant values). As described above, the redundant analog voltage thresholds / redundant values ​​may be calculated such that each row of a binary array of words represented by binary digits (representatively programmed across aCAM rows 610(A)) includes a sequence of 1s and 0s as specified by a binary parity check matrix (H) (i.e., a parity check matrix consisting of 1s and 0s). As described above, a parity check matrix may refer to a matrix or similar representation that describes conditions that codewords of a code must satisfy. Thus, the sequence of 1s and 0s dictated by the binary parity check matrix (H) applied to aCAM row 610(A) by programming redundant analog voltage thresholds in redundant aCAM cells of aCAM row 610(A) ensures that each row in the binary array of words represented in binary digits (representatively programmed across aCAM row 610(A)) includes at least one codeword of a code (C) associated with the binary parity check matrix (H). In some cases (e.g., where the maximum number of errors to be detected per aCAM row (T) is equal to 1), this may mean calculating the redundant analog voltage thresholds for aCAM cells 610(A)(n-1) such that each column of a given row of the binary array is an entry of a codeword (i.e., the codeword is representedly programmed across all aCAM cells of aCAM row 610(A)). However, in other cases (e.g., where the maximum number of errors to be detected per aCAM row (T) is greater than 1), this may mean that only a subset of the columns of a given row of the binary array are entries of a codeword (i.e., the codeword is representatively programmed across a subset of the aCAM cells of aCAM row 610(A)). For example, a codeword may be representatively programmed across aCAM cells 610(A)(0), 610(A)(2), and 610(A)(n-1) (i.e., the columns of the binary array representing the analog voltage thresholds stored by aCAM cells 610(A)(0), 610(A)(2), and 610(A)(n-1) may include a codeword stack).

[0149] The parity check matrix (H) may be calculated based on the number of columns of the aCAM array 610 (including redundant columns) and the maximum number of errors to be detected per aCAM row (T). For example, in the case of (T=1), the parity check matrix (H) may be an "all-ones" vector of length (n) (i.e., the number of columns of the aCAM array 610; or for T=1, the aCAM array 610 includes only one redundant column). Thus, if the parity check matrix (H) specifies even parity, the redundant analog voltage thresholds of the redundant aCAM cells 610(A)(n-1) may be calculated such that each row of the binary array of binary digital representation words (representatively programmed across the aCAM rows 610(A)) includes an even number of ones. Relatedly, if the parity check matrix (H) specifies odd parity, the redundant analog voltage thresholds of the redundant aCAM cells 610(A)(n-1) may be calculated such that each row of the binary array of binary digital representation words (representatively programmed across the aCAM rows 610(A)) includes an odd number of ones. As a simplified example to illustrate the concept, if the "words" representatively stored across aCAM row 610(A) include the following sequence of thresholds / entries:

[0150] 2 3 6 4 [Redundancy value to be calculated]

[0151] Then the binary array representing the thresholds / entries in binary numbers would include the following:

[0152] 0 0 1 1 [bits of redundant value to be calculated]

[0153] 1 1 1 0 [bits of redundant value to be calculated]

[0154] 0 1 0 0 [bits of redundant value to be calculated]

[0155] Here, if the parity check matrix (H) specifies even check, then each row of the binary array representing the threshold in binary digits should include an even number of 1s. Therefore, the calculated redundancy value of the redundant aCAM cell 610(A)(n-1) will be 3 (and the redundant analog voltage threshold will be the analog voltage threshold representing the calculated redundancy value of 3) to ensure that each row of the binary array representing the word in binary digits includes an even number of 1s, that is: 0 0 1 1 0 1 1 1 0 1 0 1 0 0 1

[0159] In contrast, if the parity check matrix (H) specifies odd check, then each row of the binary array representing the word in binary digits should include an odd number of 1s. Therefore, the calculated redundancy value of the redundant aCAM cell 610(A)(n-1) will be 4 (and the redundant analog voltage threshold will be the analog voltage threshold representing the calculated redundancy value of 4) to ensure that each row of the binary array representing the word in binary digits contains an odd number of 1s, i.e.: 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0

[0163] It may be noted here that when the binary parity check matrix (H) is a single row of "all 1" vectors, the parity check condition (i.e., even or odd) is applied to all columns of the binary array. However, if the binary parity check matrix (H) is more complex (e.g., the maximum number of errors to be detected (T) per aCAM row is greater than 1), the binary parity check matrix (H) may have multiple rows. Relatedly, (1) a first row of the binary parity check matrix (H) may specify a parity check condition (i.e., even or odd) for a first subset of columns of the binary array, wherein the first subset of columns of the binary array includes at least one column representing a redundant value (in examples where (T) is greater than 1, there may be multiple redundant columns, and thus multiple columns of the binary array may represent redundant values / thresholds); (2) a second row of the binary parity check matrix (H) may specify the same parity check condition (i.e., even or odd) for a second subset of columns of the binary array, wherein the second subset of columns of the binary array includes at least one column representing a redundant value; (3) a third row of the binary parity check matrix (H) may specify the same parity check condition (i.e., even or odd) for a third subset of columns of the binary array, wherein the third subset of columns of the binary array includes at least one column representing a redundant value; and so on. Furthermore, in some examples, the first row of the binary parity check matrix (H) may specify a first parity check condition (e.g., even check), and the second row of the binary parity check matrix (H) may specify a second (different) parity check condition (e.g., odd check). For these reasons, the redundant analog voltage thresholds of the redundant aCAM cells 610(A)(n-1) are more generally calculated so that each row of a binary array of binary digital representation words (which are representatively programmed across aCAM rows 610(A)) includes a sequence of 1s and 0s specified by a binary parity check matrix (H).

[0164] As depicted, circuit 600 also includes a counter subcircuit associated with each aCAM row of aCAM array 610. For example, counter subcircuit 620 is electrically connected to a match line of aCAM row 610(A) such that counter subcircuit 620 receives a match-related signal output from aCAM row 610(A). As described above, when each aCAM cell of aCAM row 610(A) returns a match in response to an input vector applied to circuit 600, the match-related signal output from aCAM row 610(A) may include a match signal, and when at least one of the aCAM cells of aCAM row 610(A) returns a mismatch in response to an input vector applied to circuit 600, the match-related signal output from aCAM row 610(A) may include a mismatch signal.

[0165] As described above, the counter subcircuit 620 may be a modulo-2 counter subcircuit that stores a first value or a second value (e.g., 0 or 1). The value stored by the counter subcircuit 620 may switch in response to the counter subcircuit 620 receiving a match signal, and may remain unchanged in response to the counter subcircuit 620 receiving a mismatch signal.

[0166] As described above, in response to a first set of error detection input vectors being sequentially applied to circuit 600, circuit 600 can detect errors in aCAM row 610 (A) when: (a) if the binary parity check matrix (H) specifies even parity, then the value stored by the counter subcircuit 620 after the first set of error detection input vectors are sequentially applied is different from the value stored by the counter subcircuit 620 before the first set of error detection input vectors are sequentially applied (as described above, this can correspond to the counter subcircuit 620 receiving an even number of match signals); and (b) if the binary parity check matrix (H) specifies odd parity, then the value stored by the counter subcircuit 620 after the first set of error detection input vectors are sequentially applied is the same as the value stored by the counter subcircuit 620 before the first set of error detection input vectors are sequentially applied (as described above, this can correspond to the counter subcircuit 620 receiving an odd number of match signals).

[0167] Similar to the redundancy values ​​described above, a first set of error detection input vectors may be calculated based on the parity check matrix (H). When applied to the aCAM array 610, each error detection input vector may include a plurality of analog voltage input signals, each analog voltage input signal being applied to one of the columns of the aCAM array 610 (when initially received by the circuit 600, the error detection input vector may include a digital input signal / multiple digital input signals that are converted by the circuit 600 using, for example, a digital-to-analog conversion circuit component before being applied to the columns of the aCAM array 610). When applied to the aCAM array 610, each error detection input vector may include only one "non-wildcard" analog voltage input signal, wherein the "wildcard" analog voltage input signal is calculated such that when the wildcard analog voltage input signal is applied to any aCAM cell of the aCAM array 610, that any aCAM cell always returns a match (by this construction, each error detection vector effectively checks one column of the aCAM array 610). In part through its relationship to the parity check matrix (H) (the parity check matrix itself is calculated based on the number of columns of the aCAM array 610 and the maximum number of errors to be detected across a single aCAM row (T)), the first set of error detection input vectors can be calculated based on: (a) the number of columns of the aCAM array 610, where the number of error detection vectors in the first set of error detection vectors is an integer multiple of the number of columns in the aCAM array; (b) the number of programmable levels that each aCAM cell of the aCAM array 610 can be programmed to store; and (c) the maximum number of errors to be detected across a single aCAM row (T).

[0168] As described above, in some examples, detecting errors in the aCAM array 610 may include applying multiple sets of error detection input vectors to the circuit 600, wherein an error in a given aCAM row of the aCAM array 610 is detected after applying a final error detection input vector of a set. For example, after applying a final error detection input vector of a first set of error detection input vectors, the circuit 600 may detect an error in the aCAM row 610(A); after applying a final error detection input vector of a second set of error detection input vectors, the circuit 600 may detect an error in the aCAM row 610(B); after applying a final error detection input vector of a third set of error detection input vectors, the circuit 600 may detect an error in the aCAM row 610(C); and so on. Here, each set of error detection input vectors may be calculated in the same / similar manner using a binary parity check matrix (H).

[0169] Figure 7An example circuit 700 for detecting errors in an aCAM array according to various examples of the presently disclosed techniques is depicted. Circuit 700 may be an example circuit implementing an external redundancy implementation of the bit interleaving scheme described above (ie, Configuration A).

[0170] As shown, circuit 700 includes an aCAM array 710. aCAM array 710 includes a plurality of rows (e.g., aCAM rows 710(A), 710(B) ... 710(X), 710(Y), etc.) and a plurality of columns (e.g., aCAM columns 710(0), 710(1), 710(2) ... 710(n-1), etc.) of aCAM cells.

[0171] and Figure 6 Unlike the aCAM array 610 of FIG. 7 , the aCAM array 710 may not include redundant columns / redundant aCAM cells. Therefore, each column / aCAM cell of the aCAM array 710 may be programmed to be used / dedicated to a computing task. In other words, all programmed thresholds of the aCAM array 710 may be "task driven" thresholds.

[0172] Similar to combining Figure 6 As described above, the aCAM cells of aCAM row 610(A), each aCAM cell of aCAM row 710(A) may be programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the aCAM row 710(A). Each aCAM cell of aCAM row 710(A) may include a memristor. The aCAM cells of aCAM row 710(A) may be programmed to store their analog voltage thresholds by programming the conductance of their memristors. The number of programmable levels that an aCAM cell of aCAM array 710 is capable of storing may be proportional to the number of conductance values ​​to which its memristor may be reliably programmed.

[0173] As described above, in an external redundancy implementation, the calculated redundancy values ​​are stored in a memory (e.g., RAM) external to the aCAM array. Thus, the redundancy values ​​of circuit 700 may be stored in a memory (not shown) external to aCAM array 710. In some examples, the memory may be part of circuit 700, but in other examples, the memory may be external to circuit 700. Here, the redundancy values ​​may be stored in a memory (not shown) external to aCAM array 710. Figure 6 The redundancy values ​​stored in the (external) memory are calculated in the same / similar way as described in Parts I-III.

[0174] Similar to circuit 600, circuit 700 includes a counter subcircuit associated with each aCAM row of aCAM array 710. For example, counter subcircuit 720 is electrically connected to a match line of aCAM row 710(A) so that counter subcircuit 720 receives a match-related signal output from aCAM row 710(A). As described above, when each aCAM cell of aCAM row 710(A) returns a match in response to an input vector applied to circuit 700, the match-related signal output from aCAM row 710(A) may include a match signal, and when at least one of the aCAM cells of aCAM row 710(A) returns a mismatch in response to an input vector applied to circuit 700, the match-related signal output from aCAM row 710(A) may include a mismatch signal.

[0175] As described above, counter subcircuit 720 may be a modulo-2 counter subcircuit that stores a value of 1 or 0. The value stored by counter subcircuit 720 may switch in response to counter subcircuit 720 receiving a match signal and may remain unchanged in response to counter subcircuit 720 receiving a mismatch signal.

[0176] As described in conjunction with Section II-C, in an external redundancy implementation, redundant values ​​stored in external memory may be applied to circuit 700 by strategically initializing (and in some cases reinitializing) values ​​stored by a counter subcircuit of circuit 700 .

[0177] For example, before the first set of error detection input vectors are sequentially applied to the circuit 700 (the first set of error detection input vectors may be combined with Figure 6 1 and 2. In some embodiments, the counter subcircuit 720 may be initialized based on at least one calculated syndrome vector (σ) of a binary array of words represented by binary digits (representatively programmed across aCAM rows 710 (A)). In some of these examples (and as described above), the value may be set to the value of a bit of a stored syndrome comparison vector (Δ) calculated by performing an XOR operation between two calculated syndrome vectors of the binary array (e.g., σs and σs-1), the two calculated syndrome vectors being associated with adjacent rows of the binary array. As described above, the at least one calculated syndrome vector (σ) may be calculated based on the binary array and a binary parity check matrix (H).

[0178] As described above, in response to the first set of error detection input vectors being sequentially applied to the circuit 700, the circuit 700 detects an error in the aCAM row 710 (A) in the following cases: (a) if the binary parity check matrix (H) specifies a first type of parity check (e.g., even check or odd check), then the value stored by the counter subcircuit 720 after the first set of error detection input vectors are sequentially applied is 0, and (b) if the binary parity check matrix specifies a second type of parity check (e.g., the other of even check or odd check), then the value stored by the counter subcircuit 720 after the first set of error detection input vectors are sequentially applied is 1.

[0179] Figure 8 An example circuit 800 for detecting errors in an aCAM array according to various examples of the presently disclosed techniques is depicted. Circuit 800 may be an example circuit implementing the shift and count scheme described above (ie, Configuration B).

[0180] As depicted, circuit 800 includes an aCAM array 810. aCAM array 810 includes a plurality of rows (e.g., aCAM rows 810(A), 810(B) ... 810(X), 810(Y), etc.) and a plurality of columns (e.g., aCAM columns 810(0), 810(1), 810(2) ... 810(n-1), etc.) of aCAM cells.

[0181] Similar to combining Figure 6 and 7 As described above, the aCAM cells of aCAM row 610(A) and aCAM row 710(A), each aCAM cell of aCAM row 810(A) may be programmed to store an analog voltage threshold representing an entry of a word representatively programmed across aCAM row 810(A). Each aCAM cell of aCAM row 810(A) may include a memristor. The aCAM cells of aCAM row 810(A) may be programmed to store their analog voltage thresholds by programming the conductance of their memristors. The number of programmable levels that an aCAM cell of aCAM array 810 is capable of storing may be proportional to the number of conductance values ​​to which its memristor may be reliably programmed.

[0182] In an example where circuit 800 implements an internal redundancy implementation, one or more of the columns of aCAM array 810 may include redundant columns. In other words, one or more of the aCAM cells of aCAM row 810 (A) may include redundant aCAM cells. As described above, the redundant aCAM cells may be programmed to store calculated redundant analog voltage thresholds. As described above, the redundant analog voltage thresholds (or more specifically, the redundant values ​​represented by the redundant analog voltage thresholds) may be calculated using a parity check matrix (H) such that a word includes at least one codeword of a code (C) associated with the parity check matrix (H) (as described above, the codewords of code (C) may be greater than the alphabet size w). Thus, circuit 800 differs from certain embodiments of circuits 600 and 700 (i.e., circuits implementing construction A) in that each row of a binary array representing a word (representatively stored across aCAM rows) includes at least one codeword.

[0183] In other examples, circuit 800 may implement an external redundancy implementation, and all aCAM cells of aCAM array 810 may be programmed as task-driven thresholds (ie, thresholds / aCAM cells dedicated to a given computing task).

[0184] Similar to circuits 600 and 700, circuit 800 includes a counter subcircuit associated with each aCAM row of aCAM array 810. However, instead of using a modulo-2 counter subcircuit, the counter subcircuit of circuit 800 may be a modulo-q counter subcircuit capable of multiplying by 2 modulo-q. Figure 6 to Figure 7 Unlike the Modulo-2 Counter Subcircuit of FIG. 1 , the Modulo-q Counter Subcircuit is capable of storing "q" unique values. Furthermore, the multiplication by 2 is performed by a shift calculation of the bits in the Modulo-q Counter Subcircuit (described in more detail in the following paragraphs). This is why the Modulo-q Counter Subcircuit is denoted as "MODSC" and may be referred to as a "Modulo-q Shift Counter Subcircuit" or a "Modulo-q Shift+ Counter Subcircuit".

[0185] The modulo-Q counter subcircuit may include an input data bit, an input control bit, an output bit, and a cascade of b single-bit memories, the contents of which are considered to be 0 to 2. b-1The binary representation of an integer between . The number b can be selected as the smallest number that allows the representation of q levels 0, 1..., q-1. The input control bit can determine whether the modulo q counter subcircuit is in "counting mode" or in "shifting mode". In "counting mode", during each clock cycle, the input data bit is added (using a standard adder circuit) to the integer represented by b memory bits. If the result is q, the contents of all memory bits are reset. Otherwise, the result is written to the memory bit. In "shifting mode", the contents of each memory bit are shifted to the next (more significant) bit in the cascade, where the most significant bit becomes the "carry bit" and 0 is inserted into the least significant bit. If the resulting content of b+1 bits (=b memory bits and carry bit) represents a number of at least q, q is subtracted (using a standard subtraction circuit) from the number represented by those b+1 bits. The output bit is the logical OR (inclusive-OR) of all b memory bits.

[0186] As described above, q may correspond to the number of programmable levels of an aCAM cell of the aCAM array 810. The number q of programmable levels that an aCAM cell of the aCAM array 810 can store may be proportional to the number of conductance values ​​to which its memristor can be reliably programmed. Here, the value of q may also be the alphabet size of the code (C).

[0187] As depicted, the counter subcircuit 820 is electrically connected to the match line of the aCAM row 810(A) such that the counter subcircuit 820 receives a match-related signal output from the aCAM row 810(A). The match-related signal output from the aCAM row 810(A) may include a match signal when each aCAM cell of the aCAM row 810(A) returns a match in response to an input vector applied to the circuit 800, and the match-related signal output from the aCAM row 810(A) may include a mismatch signal when at least one of the aCAM cells of the aCAM row 810(A) returns a mismatch in response to an input vector applied to the circuit 800.

[0188] Here, the value stored by the counter subcircuit 820 may change in response to the counter subcircuit 820 receiving a match signal and remain unchanged in response to the counter subcircuit 820 receiving a mismatch signal.

[0189] When the value stored by the counter subcircuit 820 after sequentially applying a set of error detection input vectors is non-zero, the circuit 800 can detect an error. In other words, the value stored by the counter subcircuit 820 after sequentially applying a set of error detection input vectors is zero if and only if all b bits are zero, so a zero output bit is equivalent to having b memory bits representing the integer 0.

[0190] Fig. 9 A block diagram of an example computer system 900 is depicted in which various examples described herein may be implemented. For example, the computer system 900 may be used to program the thresholds of the circuits 600, 700, and 800. The computer system 900 may also be used to calculate redundancy values ​​and error detection input vectors. The computer system 900 may also be used to initialize and reinitialize the values ​​stored by the counter subcircuit.

[0191] Computer system 900 includes a bus 912 or other communication mechanism for communicating information, coupled to bus 912 are one or more hardware processors 904 for processing information. Hardware processor(s) 904 may be, for example, one or more general-purpose microprocessors.

[0192] The computer system 900 also includes a main memory 906, such as a random access memory (RAM), a cache, and / or other dynamic storage device, coupled to the bus 912 for storing information and instructions to be executed by the processor 904. The main memory 906 may also be used to store temporary variables or other intermediate information during execution of instructions to be executed by the processor 904. When stored in a storage medium accessible to the processor 904, such instructions cause the computer system 900 to become a special-purpose machine customized to perform the operations specified in the instructions.

[0193] The computer system 900 also includes a read only memory (ROM) 908 or other static storage device coupled to the bus 912 for storing static information and instructions for the processor 904. A storage device 910, such as a magnetic disk, optical disk, or USB thumb drive (flash drive), is provided and coupled to the bus 912 for storing information and instructions.

[0194] The computer system 900 may be coupled to a display 912, such as a liquid crystal display (LCD) (or touch screen), via bus 912 for displaying information to a computer user. An input device 914, including alphanumeric and other keys, is coupled to bus 912 for communicating information and command selections to processor 904. Another type of user input device is a cursor control 916, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to processor 904 and for controlling cursor movement on display 912. In some embodiments, the same direction information and command selections as cursor control may be implemented via receiving touches on a touch screen without a cursor.

[0195] The computing system 900 may include a user interface module to implement a GUI, which may be stored in a mass storage device as an executable software code executed by the computing device. This module and other modules may include, for example, components such as software components, object-oriented software components, class components and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0196] In general, as used herein, the terms "component", "engine", "system", "database", "data store", etc. may refer to logic embodied in hardware or firmware, or to a collection of software instructions written in a programming language (such as, for example, Java, C or C++) that may have entry points and exit points. Software components may be compiled and linked into an executable program, installed in a dynamic link library, or may be written in an interpreted programming language, such as, for example, BASIC, Perl or Python. It will be appreciated that software components may be called by other components or by themselves, and / or may be called in response to detected events or interrupts. Software components configured for execution on a computing device may be provided on a computer-readable medium, such as a compact disc, a digital video disc, a flash drive, a disk, or any other tangible medium, or as a digital download (and may be initially stored in a compressed or installable format that requires installation, decompression or decryption prior to execution). Such software code may be stored in part or in whole on a memory device of an executing computing device for execution by the computing device. Software instructions may be embedded in firmware, such as an EPROM. It will be further understood that hardware components may be composed of connected logic units (such as gates and flip-flops) and / or may be composed of programmable units (such as a programmable gate array or a processor).

[0197] The computer system 900 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, makes the computer system 900 a special purpose machine or programs the computer system 900 to be a special purpose machine. According to one embodiment, the techniques herein are performed by the computer system 900 in response to the processor 904 executing one or more sequences of one or more instructions contained in the main memory 906, such instructions may be read into the main memory 906 from another storage medium such as the storage device 910, and executing the sequences of instructions contained in the main memory 906 causes the processor 904 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0198] As used herein, the term "non-transitory medium" and similar terms refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 910. Volatile media include dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a pattern of holes, RAM, PROMs, and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or boxes, and networked versions thereof.

[0199] Non-transitory media are distinct from, but may be used in conjunction with, transmission media. Transmission media participate in the transmission of information between non-transitory media. For example, transmission media include coaxial cables, copper wire, and optical fiber, including the wires that comprise bus 912. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0200] The computer system 900 also includes a communication interface 918 coupled to the bus 912. The network interface 918 provides a two-way data communication coupled to one or more network links connected to one or more local networks. For example, the communication interface 918 can be an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem to provide a data communication connection to a telephone line of a corresponding type. As another example, the network interface 918 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN (or a WAN component communicating with a WAN). A wireless link can also be implemented. In any such implementation, the network interface 918 sends and receives electrical, electromagnetic, or optical indicators that carry digital data streams representing various types of information.

[0201] A network link typically provides data communication to other data devices through one or more networks. For example, a network link may provide a connection through a local network to a host computer or to data equipment operated by an Internet Service Provider (ISP). The ISP, in turn, provides data communication services through the global packet data communication network now commonly referred to as the "Internet". Both the local network and the Internet use electrical, electromagnetic, or optical indicators that carry digital data streams. Indicators through various networks and indicators on network links and indicators through communication interface 918 (which carry digital data to and from computer system 900) are example forms of transmission media.

[0202] Computer system 900 can send messages and receive data (including program code) through the network, network links and communications interface 918. In the Internet example, a server can send the requested code for an application program through the Internet, an ISP, a local network and communications interface 918.

[0203] The received code may be executed by processor 904 as it is received, and / or stored in storage device 910 or other non-volatile storage for later execution.

[0204] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in a code component executed by one or more computer systems or computer processors including computer hardware, and fully or partially automated by it. The one or more computer systems or computer processors may also operate to support the execution of related operations in a "cloud computing" environment or as "software as a service" (SaaS). The processes and algorithms may be implemented in part or in whole in application-specific circuits. The various features and processes described above may be used independently of one another, or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of the present disclosure, and certain methods or process blocks may be omitted in some embodiments. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states associated therewith may be executed in other appropriate sequences, or may be executed in parallel or in some other ways. Blocks or states may be added to or removed from the disclosed example embodiments. The execution of certain operations or processes may be distributed among computer systems or computer processors, not only residing in a single machine, but also deployed on multiple machines.

[0205] As used herein, any form of hardware, software or combination thereof can be utilized to implement circuits. For example, one or more processors, controllers, ASIC, PLA, PAL, CPLD, FPGA, logic components, software routines or other mechanisms can be implemented to form circuits. In an embodiment, the various circuits described herein can be implemented as discrete circuits, or the functions and features described can be shared in part or in whole in one or more circuits. Although the elements of various features or functions can be described or claimed as separate circuits separately, these features and functions can be shared in one or more common circuits, and such description should not require or imply that separate circuits are needed to implement such features or functions. In the case of using software to implement circuits in whole or in part, such software can be implemented to operate together with a computing or processing system that can perform the functions described therein, such as computer system 900.

[0206] As used herein, the term "or" may be interpreted in an inclusive or exclusive sense. In addition, the description of a resource, operation, or structure in the singular should not be interpreted as excluding the plural. Unless otherwise explicitly stated, or otherwise understood in the context of use, conditional language such as "can", "could", "might", "may", etc. is generally intended to convey that some embodiments include and other embodiments do not include certain features, elements, and / or steps.

[0207] Unless expressly stated otherwise, the terms and phrases used in this document and variations thereof should be construed as open ended and not restrictive. Adjectives such as "conventional," "traditional," "normal," "standard," "known," and terms of similar meaning should not be construed as limiting the items described to a given time period or to items available at a given time, but rather should be interpreted as covering conventional, traditional, normal, or standard technology that may be available or known at any time now or in the future. In some instances, the presence of expansive words and phrases (such as, "one or more," "at least," "but not limited to," or other similar phrases) should not be interpreted to mean that a narrower case is intended or required where such expansive phrases may not be present.

Claims

1. A circuit, comprising: An analog content addressable memory (aCAM) array comprising rows of aCAM cells electrically connected along match lines, each aCAM cell of the rows of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the rows of aCAM cells, wherein: The aCAM cell row includes redundant aCAM cells programmed to store a calculated redundant analog voltage threshold, and The redundant analog voltage thresholds are calculated such that each row of a binary array representing the word in binary digits includes a sequence of ones and zeros specified by a binary parity check matrix.

2. The circuit according to claim 1, further comprising: a counter subcircuit electrically connected to the match line such that the counter subcircuit receives a match-related signal output from the aCAM cell row, the match-related signal output from the aCAM cell row comprising a match signal when each aCAM cell in the aCAM cell row returns a match in response to an input vector applied to a circuit, and the match-related signal output from the aCAM cell row comprises a mismatch signal when at least one of the aCAM cells in the aCAM cell row returns a mismatch in response to the input vector applied to the circuit.

3. The circuit of claim 2, wherein: The counter subcircuit stores a first value or a second value; the value stored by the counter subcircuit switches in response to the counter subcircuit receiving a match signal and remains unchanged in response to the counter subcircuit receiving a mismatch signal; as well as In response to a set of error detection input vectors sequentially applied to the circuit, the circuit detects an error in the aCAM cell row when: If the binary parity check matrix (H) specifies even parity, the value stored by the counter subcircuit after sequentially applying the set of error detection input vectors is different from the value of the counter subcircuit before sequentially applying the set of error detection input vectors, and If the binary parity check matrix (H) specifies odd check, the value stored by the counter subcircuit after sequentially applying the set of error detection input vectors is the same as the value of the counter subcircuit before sequentially applying the set of error detection input vectors.

4. The circuit according to claim 3, wherein: When applied to the aCAM cell row, each error detection input vector includes a plurality of analog voltage input signals, each of the plurality of analog voltage signals being applied to one of the aCAM cells in the aCAM cell row.

5. The circuit according to claim 4, wherein: When applied to the aCAM cell row, each error detection input vector includes only one non-wildcard analog voltage input signal, the wildcard analog voltage input signal being calculated such that any aCAM cell of the aCAM array always returns a match when the wildcard analog voltage input signal is applied to the aCAM cell row.

6. The circuit of claim 5 , wherein the set of error detection input vectors is calculated based on: a number of aCAM cells in the aCAM cell row, wherein the number of error detection vectors in the set of error detection vectors is an integer multiple of the number of aCAM cells in the aCAM cell row; the number of programmable levels that each aCAM cell of the aCAM cell row can store; and The maximum number of errors to be detected across this row of aCAM cells.

7. The circuit of claim 6, wherein: each row of said binary array representing said representatively programmed words in binary digits comprises a codeword of a code; The binary parity check matrix associated with the code and the code are selected based on the number of aCAM cells in the aCAM cell row and a maximum number of errors to be detected; and The set of error detection input vectors are calculated using rows of the binary parity check matrix.

8. The circuit of claim 7, wherein the set of error detection input vectors is a first set of error detection input vectors among a plurality of sets of error detection input vectors calculated to detect errors stored by the aCAM array.

9. The circuit of claim 5, wherein: Each aCAM cell of the row of aCAM cells comprises a memristor; and The aCAM cells of the aCAM cell row are programmed to store their analog voltage thresholds by programming the conductance of their memristors.

10. The circuit of claim 9, wherein: The number of programmable levels that the aCAM cells of the aCAM cell row can store is proportional to the number of conductance values ​​to which its memristor can be reliably programmed.

11. A circuit, comprising: an analog content addressable memory (aCAM) array comprising rows of aCAM cells electrically connected along match lines, each aCAM cell of the rows of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the rows of aCAM cells; as well as a counter subcircuit electrically connected to the match line such that the counter subcircuit receives a match-related signal output from the aCAM cell row, the match-related signal output from the aCAM cell row comprising a match signal when each aCAM cell of the aCAM cell row returns a match in response to an input vector applied to a circuit, and the match-related signal output from the aCAM cell row comprises a mismatch signal when at least one of the aCAM cells of the aCAM cell row returns a mismatch in response to the input vector applied to the circuit, wherein: The counter subcircuit stores a value of 0 or a value of 1; The value stored by the counter subcircuit switches in response to the counter subcircuit receiving a match signal and remains unchanged in response to the counter subcircuit receiving a mismatch signal.

12. The circuit of claim 11, wherein: The value stored by the counter subcircuit is initialized based on at least one calculated syndrome vector of a binary array representing the word in binary digits before a set of error detection input vectors are sequentially applied to the circuit.

13. The circuit of claim 12, wherein: The values ​​stored by the counter subcircuit initialized according to the at least one calculated syndrome vector are set to values ​​of bits of a stored syndrome comparison vector calculated by performing an exclusive-OR operation between two calculated syndrome vectors of the binary array, the two calculated syndrome vectors being associated with adjacent rows of the binary array.

14. The circuit of claim 12, wherein: The at least one calculated syndrome vector is calculated based on the binary array and a binary parity check matrix.

15. The circuit of claim 14, wherein: In response to the set of error detection input vectors being sequentially applied to the circuit, the circuit detects an error in the aCAM cell row when: If the binary parity check matrix specifies a first type of parity check, the value stored by the counter subcircuit after sequentially applying the set of error detection input vectors is zero, and If the binary parity-check matrix specifies a second type of parity check, then the value stored by the counter subcircuit after sequentially applying the set of error detection input vectors is 1.

16. The circuit of claim 11, wherein: Each aCAM cell of the row of aCAM cells comprises a memristor; and The aCAM cells of the aCAM cell row are programmed to store their analog voltage thresholds by programming the conductance of their memristors.

17. A circuit, comprising: an analog content addressable memory (aCAM) array comprising rows of aCAM cells electrically connected along match lines, each aCAM cell of the rows of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the rows of aCAM cells; and a modulo-q counter subcircuit electrically connected to the match line such that the modulo-q counter subcircuit receives a match-related signal output from the aCAM cell row, the match-related signal output from the aCAM cell row comprising a match signal when each aCAM cell of the aCAM cell row returns a match in response to an input vector applied to a circuit, and the match-related signal output from the aCAM cell row comprises a mismatch signal when at least one of the aCAM cells of the aCAM cell row returns a mismatch in response to the input vector applied to the circuit, wherein: q is the number of programmable levels of a given aCAM cell of the aCAM cell row, and q is also a prime number, and The value stored by the modulo-q counter subcircuit changes in response to the counter subcircuit receiving a match signal and remains unchanged in response to the counter subcircuit receiving a mismatch signal.

18. The circuit of claim 17, wherein: The aCAM cell row includes redundant aCAM cells programmed to store a calculated redundant analog voltage threshold; The redundant analog voltage threshold is calculated using a parity check matrix such that the word includes at least one codeword of a code associated with the parity check matrix; and The alphabet size of the code is q.

19. The circuit of claim 18, wherein: Each aCAM cell of the row of aCAM cells comprises a memristor; and The aCAM cells of the aCAM cell row are programmed to store their analog voltage thresholds by programming the conductance of their memristors.

20. The circuit of claim 19, wherein: The number q of programmable levels that an aCAM cell of the aCAM cell row can store is proportional to the number of conductance values ​​to which its memristor can be reliably programmed.

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