Communication method and test method based on multi-core MCU test storage chip

Abstract

The present invention discloses a communication method and a test method based on a multi-core MCU test memory chip, the communication method comprising: configuring an external device node to be able to send a test control message; configuring two receiving IDs of each multi-core MCU node to be ID1 and ID2 respectively, and sending ID to be ID3, the ID1 and ID3 of multiple multi-core MCU nodes are different, and the ID2 is the same, configuring the main core of the multi-core MCU to only receive the test control message whose message ID value in the bus is equal to its ID1 and ID2; configuring the main core of the multi-core MCU to receive the message when the value of the message ID of the test control message in the CAN bus is equal to its ID1 or ID2 value, parse the message to obtain a forwarding object and test control information, and forward the test control information to the corresponding slave core according to the forwarding object. The present invention can realize parallel testing of memory chips by multi-core MCU, improve test efficiency, and can also display various test information to the outside of the chip, so that the external device can display the test information of all kernels.

Description

Technical Field

[0001] The present invention belongs to the field of memory chip testing, and more specifically, relates to a communication method and a testing method for testing a memory chip based on a multi-core MCU. Background Art

[0002] The life test of a memory chip generally requires thousands of hours of testing time. Existing technologies mostly use a single-core MCU, which can only test one memory chip at a time, resulting in low testing efficiency.

[0003] In order to improve the test efficiency, a communication method is needed to form a network of multiple multi-core MCUs and organize orderly communication between the cores inside the multi-core MCU to achieve parallel testing of memory chips. Summary of the invention

[0004] The purpose of the present invention is to propose a communication method and a testing method based on a multi-core MCU to test a memory chip, so that when the multi-core MCU tests the memory chip in parallel, various test information in the parallel testing process can be displayed to the outside of the chip, so that an external device can display the test information of all cores.

[0005] To achieve the above object, in a first aspect, the present invention proposes a communication method for testing a storage chip based on a multi-core MCU, comprising:

[0006] Connecting multiple multi-core MCUs and an external device to the same CAN bus to form a local area network, wherein the multi-core MCU includes a master core and multiple slave cores, wherein the master core communicates with the CAN bus through a CAN interface, and the master core and the multiple slave cores are respectively connected to a storage chip through a test interface;

[0007] The external device node is configured to be able to send a test control message to all multi-core MCU nodes on the bus and receive feedback messages from all multi-core MCU nodes on the bus, wherein the test control message includes a message ID, a forwarding object, and test control information;

[0008] The two receiving IDs of each multi-core MCU node are configured to be ID1 and ID2 respectively, and the sending ID is ID3. The ID1 and ID3 of multiple multi-core MCU nodes are different, and the ID2 is the same. The main core of the multi-core MCU is configured to only receive the test control message whose message ID value in the bus is equal to its ID1 and ID2;

[0009] Configuring an inter-core communication mechanism between a master core and a plurality of slave cores in the multi-core MCU;

[0010] The master core of the multi-core MCU is configured to receive the test control message when it is identified that the value of the message ID of the test control message in the CAN bus is equal to the value of its ID1 or ID2, parse the test control message to obtain the forwarding object and test control information, and forward the test control information to the corresponding slave core according to the forwarding object.

[0011] Optionally, it also includes: configuring the main core to determine whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested after obtaining the test control information; if so, execute the test on the connected memory chip according to the test control information; otherwise, feedback the refusal to execute and the reason for the refusal.

[0012] Optionally, it also includes: configuring the slave core to determine whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested after obtaining the test control information; if so, execute the test on the connected memory chip according to the test control information; otherwise, feedback the refusal to execute and the reason for the refusal to execute to the master core.

[0013] Optionally, it also includes: configuring the master core to form a message with message ID=ID3 and then feed back the feedback rejection information of the master core and / or the slave core and the test information of the chip to the external device.

[0014] Optionally, configuring the inter-core communication mechanism between the master core and the multiple slave cores in each of the multi-core MCUs includes:

[0015] Configuring a master core of the multi-core MCU and multiple slave cores to perform inter-core communication based on a mailbox mechanism;

[0016] The sending address of the master core is configured as each slave core, and the sending address of the slave core is configured as the master core.

[0017] In a second aspect, the present invention provides a memory chip testing method, based on the communication method for testing a memory chip based on a multi-core MCU according to any one of the first aspects, the testing method comprising:

[0018] The external device sends a test control message to the CAN bus;

[0019] The main core of each multi-core MCU determines whether the message ID of the test control message is equal to its ID1 or ID2. When the value of the message ID of the test control message is equal to the value of ID2, the main cores of all multi-core MCUs receive the test control message. When the value of the message ID of the test control message is equal to the value of ID1 of a certain multi-core MCU, only the main core of the multi-core MCU whose ID1 value is equal to the message ID receives the test control message.

[0020] After receiving the test control message, the master core parses the test control message to obtain a forwarding object and test control information, and forwards the test control information to a corresponding slave core according to the forwarding object. The slave core tests the connected storage chip based on the test control information.

[0021] Optionally, it also includes: after obtaining the test control information, the main core determines whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested; if so, execute the test on the connected memory chip according to the test control information; otherwise, feedback the refusal to execute and the reason for the refusal.

[0022] Optionally, it also includes: after obtaining the test control information, the slave core determines whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested; if so, execute the test on the connected memory chip according to the test control information; otherwise, feedback the refusal to execute and the reason for the refusal to execute is sent to the master core.

[0023] Optionally, it further includes: the master core forms a message with message ID=ID3 by forming the feedback rejection information of the master core and / or the slave core and the test information of the chip and then feeds it back to the external device.

[0024] In a third aspect, the present invention provides a memory chip test system, comprising: a plurality of multi-core MCUs connected to the same CAN bus and an external device, the multi-core MCU comprising a master core and a plurality of slave cores, wherein the master core communicates with the CAN bus via a CAN interface, and the master core and the plurality of slave cores are respectively connected to a memory chip via a test interface;

[0025] The memory chip testing system tests the memory chip using the memory chip testing method described in any one of the second aspects.

[0026] The beneficial effects of the present invention are:

[0027] The method of the present invention configures two receiving IDs and one sending ID in each multi-core MCU node, establishes an inter-core communication mechanism between a master core and a slave core, and realizes data interaction between a network composed of multiple multi-core MCUs and internal multi-cores based on a mechanism in which the master core of the multi-core MCU only receives test control messages whose message ID values ​​are equal to its ID1 and ID2 in a bus, so that the multi-core MCU can perform parallel testing on storage chips, improve the testing efficiency, and display various test information in the parallel testing process to the outside of the chip during testing, so that an external device can display the test information of all cores. At the same time, the present invention can make only one external device in the entire test network, control the test behaviors of all multi-core MCU nodes, display the test information of all tested storage chips, simplify the network structure, and save costs.

[0028] The system of the present invention has other characteristics and advantages, which will be apparent from the drawings incorporated herein and the following detailed description, or will be described in detail in the drawings incorporated herein and the following detailed description, which together serve to explain the specific principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0030] Figure 1 A schematic diagram of a network structure used in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0031] Figure 2 A schematic diagram of the internal structure of a multi-core MCU in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0032] Figure 3 A schematic diagram of a network node ID configuration in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0033] Figure 4 A schematic diagram of a multi-core MCU inter-core communication configuration in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0034] Figure 5 A communication schematic diagram of batch testing control of multiple multi-core MCUs in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0035] Figure 6 A communication schematic diagram of performing separate test control on a single multi-core MCU in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0036] Figure 7 A communication schematic diagram of testing and controlling a slave core of a multi-core MCU in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown.

[0037] Figure 8 A communication schematic diagram of information feedback from core test control, etc. in a communication method based on a multi-core MCU testing storage chip according to an embodiment of the present invention is shown.

[0038] Fig. 9A communication schematic diagram of information feedback such as main core test control in a communication method for testing a storage chip based on a multi-core MCU according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0039] The present invention will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0040] Example 1

[0041] This embodiment provides a communication method for testing a storage chip based on a multi-core MCU, including:

[0042] S1: Connect multiple multi-core MCUs and an external device to the same CAN bus to form a local area network, wherein the multi-core MCU includes a master core and multiple slave cores, wherein the master core communicates with the CAN bus through a CAN interface, and the master core and the multiple slave cores are respectively connected to a storage chip through a test interface;

[0043] Specifically, Figure 1 As shown, the network structure of this embodiment adopts multiple multi-core MCUs and external devices connected to the same CAN bus to form a local area network. The number of multi-core MCUs is not limited and can be networked according to actual needs. This embodiment takes a network including 4 multi-core MCUs as an example for explanation. Figure 2 As shown, the core inside the multi-core MCU is functionally divided into a master core and multiple slave cores. In this implementation, a multi-core MCU with a master core and four slave cores (slave core 1-slave core 4) is taken as an example, where the master core communicates with the outside through the CAN interface, and is responsible for testing a memory chip through the test interface. Each slave core is responsible for testing a memory chip through the test interface, and communicates with the master core at the same time. In the specific implementation process, each test interface can be connected to a memory chip, or only some test interfaces can be connected to the memory chip for testing. The external device can be a host computer device such as an industrial computer.

[0044] S2: Configuring the external device node to be able to send a test control message to all multi-core MCU nodes on the bus and to receive feedback messages from all multi-core MCU nodes on the bus, wherein the test control message includes a message ID, a forwarding object, and test control information;

[0045] Specifically, the configuration of the receiving ID and sending ID of the external device node is not restricted, and the external device node can receive messages of all IDs on the bus, and can also send messages of any ID. Usually, the ID of the CAN message is a binary frame ID, which is used to point to the receiving node on the CAN network.

[0046] S3: configure the two receiving IDs of each multi-core MCU node to be ID1 and ID2 respectively, and the sending ID to be ID3, the ID1 and ID3 of the multiple multi-core MCU nodes are different, and the ID2 is the same, and configure the main core of the multi-core MCU to only receive the test control message whose message ID value in the bus is equal to its ID1 and ID2;

[0047] Specifically, two receiving IDs are configured on each multi-core MCU node, namely ID1 and ID2; and one sending ID, recorded as ID3. The ID1 value of each multi-core MCU node is different, the ID2 value is the same, and the ID3 value is different. That is, the multi-core MCU node can only receive messages on the bus whose ID values ​​are equal to ID1 and ID2. Figure 3 As shown, this embodiment includes multi-core MCU1-multi-core MCU4, wherein the ID1 of multi-core MCU1-multi-core MCU4 is 101-104 respectively, the ID2 is 100, and the ID3 is 301-304 respectively. In actual use, the values ​​of the above IDs are binary, and decimal representation is used for ease of explanation.

[0048] S4: configuring an inter-core communication mechanism between a master core and a plurality of slave cores in the multi-core MCU;

[0049] Specifically, Figure 4 As shown, the inter-core communication configuration of the multi-core MCU core of this embodiment is implemented by a mailbox mechanism. Among them, the master core sending address is configured as all slave cores, and the slave core sending address is configured as the master core. Based on the above configuration, the master core of the multi-core MCU can communicate bidirectionally with each slave core.

[0050] S5: Configure the master core of the multi-core MCU to receive the test control message when it recognizes that the value of the message ID of the test control message in the CAN bus is equal to the value of its ID1 or ID2, parse the test control message to obtain the forwarding object and test control information, and forward the test control information to the corresponding slave core according to the forwarding object.

[0051] Specifically, the test control of this embodiment includes the parameter setting of the multi-core MCU on the bus by the external device (including the scope of testing the memory chip, setting the algorithm for executing the test, etc.), the start or stop control of the test, the reading of the data in the memory chip, etc. The data direction is from the external device to the master core in the multi-core MCU. Based on the communication mechanism configuration of steps S2-S4, the batch test control, independent test control and test control of the slave core of multiple multi-core MCUs by the external device can be realized, that is, the external device can test and control multiple multi-core MCUs at the same time, and can also control a multi-core MCU on the bus to test the memory chip separately, and can also test and control the slave core of any multi-core MCU.

[0052] Among them, batch test control includes: Figure 5 As shown, the external device sends a setup message (test control message) with an ID value equal to ID2. Since the multi-core MCUs are all configured to receive messages with ID=ID2, and the ID2 value is the same, and the main core inside the multi-core MCU is connected to the CAN interface, a setup message sent by the external device can be received by the main cores of all multi-core MCUs on the CAN bus.

[0053] Independent test control includes: if a multi-core MCU needs to be set up separately for testing, the external device sends a setting message with ID = ID1, such as Figure 6 As shown, for example, when the external device sends a setting message with message ID=101, only the multi-core MCU1 can receive the message.

[0054] Test control of slave cores includes: Figure 7 As shown, since the forwarding object information is defined in the CAN message, after the message containing the test control information reaches the master core, the master core parses the CAN message (test control message) and knows which slave core the message needs to be forwarded to, thereby setting the test control information of the slave core to the storage chip, and the data direction is from the master core to the slave core.

[0055] In this embodiment, step S6 is further included: after obtaining the test control information, the main core is configured to determine whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested; if so, the connected memory chip is tested according to the test control information; otherwise, the execution is rejected and the rejection reason is fed back;

[0056] After obtaining the test control information, the slave core is configured to determine whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested, and if so, to execute the test on the connected memory chip according to the test control information; otherwise, to feed back the refusal to execute and the reason for the refusal to execute to the master core;

[0057] The master core is configured to form a message with message ID=ID3 and then feed back the feedback rejection information of the master core and / or the slave core and the test information of the chip to the external device.

[0058] Specifically, after step S5, the test control information has reached the master core and the slave core. The master core and the slave core agree and execute according to the test control information based on the feedback of the memory chip actually tested, or refuse to execute. For example, the control information requires that the test range of the memory chip is from the starting address to the address space of 8M, but the capacity of the memory chip actually connected to the master core or the slave core is 1M, then the master core will feedback the rejection of the test control information sent by the external device, and feedback the reason for the rejection. The slave core will feedback the rejection of the test control information forwarded by the master core, and the master core will feedback the rejection information fed back by the slave core to the external device through the CAN interface using the message with ID=ID3. The information feedback such as test progress and test failure is the same as the test control result feedback communication mechanism. Among them, the information feedback communication such as slave core test control feedback, test progress, test failure, etc. is as follows: Figure 8 As shown in the figure, the main core test control feedback, test progress, test failure and other information feedback communication is as follows Fig. 9 shown.

[0059] According to the communication method of this embodiment, only one external device can be used to control multiple multi-core MCUs and each core of the MCU to complete the test and data access of the memory chip, and at the same time display the test progress, test failure and other information of all tested memory chips. This communication method can make only one external device in the entire test network, control the test behavior of all multi-core MCU nodes, display the test information of all tested memory chips, simplify the network structure, and save costs.

[0060] Example 2

[0061] This embodiment provides a memory chip testing method, based on the communication method for testing a memory chip based on a multi-core MCU described in Embodiment 1, the testing method includes:

[0062] The external device sends a test control message to the CAN bus;

[0063] The main core of each multi-core MCU determines whether the message ID of the test control message is equal to its ID1 or ID2. When the value of the message ID of the test control message is equal to the value of ID2, the main cores of all multi-core MCUs receive the test control message. When the value of the message ID of the test control message is equal to the value of ID1 of a certain multi-core MCU, only the main core of the multi-core MCU whose ID1 value is equal to the message ID receives the test control message.

[0064] After receiving the test control message, the master core parses the test control message to obtain a forwarding object and test control information, and forwards the test control information to a corresponding slave core according to the forwarding object. The slave core tests the connected storage chip based on the test control information.

[0065] In this embodiment, the method further includes:

[0066] After obtaining the test control information, the main core determines whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested. If so, the main core executes the test on the connected memory chip according to the test control information. Otherwise, the main core feeds back the refusal to execute and the reason for the refusal.

[0067] After obtaining the test control information, the slave core determines whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested. If so, the slave core executes the test on the connected memory chip according to the test control information. Otherwise, the slave core feeds back the refusal to execute and the reason for the refusal to execute to the master core.

[0068] The master core forms a message with message ID=ID3 by forming the feedback rejection information of the master core and / or the slave core and the test information of the chip and then feeds it back to the external device.

[0069] Example 3

[0070] This embodiment provides a memory chip test system, including: multiple multi-core MCUs connected to the same CAN bus and an external device, the multi-core MCU including a master core and multiple slave cores, wherein the master core communicates with the CAN bus through a CAN interface, and the master core and the multiple slave cores are respectively connected to a memory chip through a test interface;

[0071] The memory chip testing system of this embodiment uses the memory chip testing method described in Embodiment 2 to test the memory chip.

[0072] The system architecture of this embodiment refers to Figure 1 The entire test network uses only one external device to control the test behavior of all multi-core MCU nodes and display the test information of all tested memory chips. It can realize batch testing of multiple memory chips, and can also realize separate testing of any number of memory chips under a multi-core MCU, thereby improving test efficiency and test flexibility. At the same time, the network structure of this system is simple and the cost is lower.

[0073] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A communication method for testing storage chips based on multi-core MCU, characterized in that: include: Connecting multiple multi-core MCUs and an external device to the same CAN bus to form a local area network, wherein the multi-core MCU includes a master core and multiple slave cores, wherein the master core communicates with the CAN bus through a CAN interface, and the master core and the multiple slave cores are respectively connected to a storage chip through a test interface; The external device node is configured to be able to send a test control message to all multi-core MCU nodes on the bus and receive feedback messages from all multi-core MCU nodes on the bus, wherein the test control message includes a message ID, a forwarding object, and test control information; The two receiving IDs of each multi-core MCU node are configured to be ID1 and ID2 respectively, and the sending ID is ID3. The ID1 and ID3 of multiple multi-core MCU nodes are different, and the ID2 is the same. The main core of the multi-core MCU is configured to only receive the test control message whose message ID value in the bus is equal to its ID1 and ID2; Configuring an inter-core communication mechanism between a master core and a plurality of slave cores in the multi-core MCU; The master core of the multi-core MCU is configured to receive the test control message when it is identified that the value of the message ID of the test control message in the CAN bus is equal to the value of its ID1 or ID2, parse the test control message to obtain the forwarding object and test control information, and forward the test control information to the corresponding slave core according to the forwarding object.

2. The communication method according to claim 1, characterized in that: Also includes: After the main core obtains the test control information, it is configured to determine whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested. If so, it executes the test on the connected memory chip according to the test control information. Otherwise, it feeds back the refusal to execute and the reason for the refusal.

3. The communication method according to claim 1, characterized in that: Also includes: After the slave core obtains the test control information, it is configured to determine whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested. If so, it executes the test on the connected memory chip according to the test control information. Otherwise, it feeds back the refusal to execute and the reason for the refusal to the master core.

4. The communication method according to claim 2 or 3, characterized in that: Also includes: The master core is configured to form a message with message ID=ID3 and then feed back the feedback rejection information of the master core and / or the slave core and the test information of the chip to the external device.

5. The communication method according to claim 1, characterized in that: The inter-core communication mechanism between the master core and the multiple slave cores in each of the multi-core MCUs is configured to include: Configuring a master core of the multi-core MCU and multiple slave cores to perform inter-core communication based on a mailbox mechanism; The sending address of the master core is configured as each slave core, and the sending address of the slave core is configured as the master core.

6. A memory chip testing method, based on the communication method for testing memory chips based on a multi-core MCU according to any one of claims 1 to 5, characterized in that: The test method includes: The external device sends a test control message to the CAN bus; The main core of each multi-core MCU determines whether the message ID of the test control message is equal to its ID1 or ID2. When the value of the message ID of the test control message is equal to the value of ID2, the main cores of all multi-core MCUs receive the test control message. When the value of the message ID of the test control message is equal to the value of ID1 of a certain multi-core MCU, only the main core of the multi-core MCU whose ID1 value is equal to the message ID receives the test control message. After receiving the test control message, the master core parses the test control message to obtain a forwarding object and test control information, and forwards the test control information to a corresponding slave core according to the forwarding object. The slave core tests the connected storage chip based on the test control information.

7. The testing method according to claim 6, characterized in that: Also includes: After obtaining the test control information, the main core determines whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested. If so, the main core executes the test on the connected memory chip according to the test control information. Otherwise, the main core feeds back the refusal to execute and the reason for the refusal.

8. The testing method according to claim 6, characterized in that: Also includes: After obtaining the test control information, the slave core determines whether to execute the test on the corresponding memory chip according to the test control information and the information of the memory chip to be tested. If so, the slave core executes the test on the connected memory chip according to the test control information. Otherwise, the slave core feeds back the refusal to execute and the reason for the refusal to execute to the master core.

9. The testing method according to claim 7 or 6, characterized in that: Also includes: The master core forms a message with message ID=ID3 by forming the feedback rejection information of the master core and / or the slave core and the test information of the chip and then feeds it back to the external device.

10. A memory chip testing system, characterized in that: include: Multiple multi-core MCUs and an external device connected to the same CAN bus, the multi-core MCU comprising a master core and multiple slave cores, wherein the master core communicates with the CAN bus via a CAN interface, and the master core and the multiple slave cores are respectively connected to a storage chip via a test interface; The memory chip testing system tests the memory chip using the memory chip testing method described in any one of claims 6-9.

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