A SATA data DMA transmission system and method based on FPGA

Abstract

The present invention discloses an FPGA-based SATA data DMA transmission system and method. The system utilizes a register configuration module, a first FIFO storage module, a second FIFO storage module, a DMA state machine module, a SATA controller module, and an MB bus to AXI bus conversion module. The register configuration module is configured to send startup and read / write operation instructions to the DMA state machine module and receive a "busy" signal; send startup and read / write operation instructions and user data length to the SATA controller module and receive a "SATA_done" signal; the first FIFO storage module is configured to store discrete user memory space base addresses and corresponding space sizes; the DMA state machine module is configured to monitor the status of the DMA state machine; the second FIFO storage module is configured to store SATA read / write data; and the SATA controller module is configured to implement SATA interface functions. The present invention improves transmission rate and CPU performance.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed data transmission, and in particular discloses a SATA data DMA transmission system based on FPGA and a method thereof. Background Art

[0002] like Figure 1 As shown, the existing method for the operating system to perform read and write operations on the SATA disk is as follows:

[0003] 1) The system allocates discrete memory (len0, len1, ..., lenN) to user tasks, such as Figure 2 As shown;

[0004] 2) The SATA task process allocates memory space in the kernel space, whose size is len0+len1+…+lenN;

[0005] 3) The CPU copies the contents of the user discrete memory space to the kernel space (memorycopy);

[0006] 4) The DMA state machine transfers the kernel space data to FIFO_2, and the SATA controller takes the data from FIFO_2 and transfers it to the SATA disk.

[0007] The disadvantages of existing operating systems in reading and writing SATA disks are that kernel space operations are involved, which takes up a lot of system time.

[0008] Therefore, the existing operating system's reading and writing operations on SATA disks take up a lot of system time, which is a technical problem that needs to be solved urgently. Summary of the Invention

[0009] The present invention provides a SATA data DMA transmission system and method based on FPGA, aiming to solve the technical problem that a large amount of system time is occupied when the existing operating system performs read and write operations on a SATA disk.

[0010] One aspect of the present invention relates to a SATA data DMA transmission system based on FPGA, comprising a register configuration module, a first FIFO storage module, a second FIFO storage module, a DMA state machine module, a SATA controller module and an MB bus and AXI bus conversion module, wherein:

[0011] The register configuration module is connected to the DMA state machine module and the SATA controller module respectively, and is used to send startup, read and write operation instructions to the DMA state machine module and receive a busy signal; send startup, read and write operation instructions and user data length to the SATA controller module and receive a SATA_done signal;

[0012] A first FIFO storage module is connected to the register configuration module and is used to store discrete user memory space base addresses and corresponding space sizes;

[0013] A DMA state machine module, connected to the first FIFO storage module, for monitoring the state of the DMA state machine;

[0014] A second FIFO storage module is connected to the DMA state machine module and is used to store SATA read and write data;

[0015] The SATA controller module is connected to the register configuration module, the second FIFO storage module and the SATA disk respectively, and is used to realize the SATA interface function;

[0016] The MB bus and AXI bus conversion module is connected to the DMA state machine module and the CPU respectively, and is used to realize the conversion between the MB bus and the AXI bus.

[0017] Another aspect of the present invention relates to a DMA read operation method of the FPGA-based SATA data DMA transmission system as described above, which is used to transfer CPU data to a SATA disk, comprising the following steps:

[0018] The register configuration module receives the DMA read operation instruction sent by the CPU, and writes the N-bit user data into the first FIFO storage module in sequence by combining the base address of the discrete user memory space and the corresponding space size;

[0019] When the total memory space of the first FIFO storage module reaches a set storage capacity threshold, the register configuration module sends a start instruction and a read operation instruction to the DMA state machine module and the SATA controller module respectively;

[0020] When the DMA state machine module receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module and initiates a busrt read operation. The CPU data is written from the memory space to the second FIFO storage module through the MB bus and AXI bus conversion module. At the same time, when the SATA controller module receives the read operation instruction and detects that the second FIFO storage module is not empty, it takes the CPU data from the second FIFO storage module and writes it to the SATA disk through the SATA interface.

[0021] The base address and size of the first user memory space are retrieved from the first FIFO storage module, and a busrt read operation is initiated. The CPU data is written from the memory space to the second FIFO storage module via the MB bus and AXI bus conversion module. The SATA controller module retrieves the CPU data from the second FIFO storage module and writes it to the SATA disk.

[0022] After all CPU data in the first FIFO storage module is retrieved and all read busrt operations are completed, the DMA state machine module returns to the initial state, completing the DMA read operation, and the SATA controller module pulls up the SATA_done signal to indicate that the data transmission has been completed.

[0023] Furthermore, when the total memory space of the first FIFO storage module reaches a set storage capacity threshold, the register configuration module sends a startup instruction and a read operation instruction to the DMA state machine module and the SATA controller module respectively, and the storage capacity threshold is the sum of the sizes of each segment of the user discrete memory space.

[0024] Furthermore, the register configuration module receives the DMA read operation instruction sent by the CPU, and writes the base address and corresponding space size of the discrete user memory space into an N-bit user data into the first FIFO storage module in sequence. The address bit width of the N-bit user data is 32 bits, and the data length bit width is 32 bits.

[0025] Furthermore, when the DMA state machine module receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module and initiates a read busrt operation. The CPU data is written from the memory space to the second FIFO storage module through the MB bus and the AXI bus conversion module. At the same time, when the SATA controller module detects that the second FIFO storage module is not empty, it takes the CPU data from the second FIFO storage module and writes it to the SATA disk through the SATA interface. When the length of the data transmitted by the busrt is equal to the size of the first user memory space, the process proceeds to the next step.

[0026] Furthermore, the base address and size of the first user memory space are retrieved from the first FIFO storage module, and a busrt read operation is initiated; user data is written from the memory space to the second FIFO storage module via the MB bus and the AXI bus conversion module, and the SATA controller module takes the CPU data from the second FIFO storage module and writes it to the SATA disk. When the length of the data transmitted by the busrt is equal to the size of the second user memory space, the process proceeds to the next step.

[0027] Another aspect of the present invention relates to a DMA write operation method of the FPGA-based SATA data DMA transmission system as described above, which is used to transmit SATA disk data to a CPU, comprising the following steps:

[0028] The register configuration module receives the DMA write operation instruction sent by the CPU, and writes the N-bit user data into the first FIFO storage module in sequence by combining the base address of the discrete user memory space and the corresponding space size;

[0029] When the total memory space of the first FIFO storage module reaches a set storage capacity threshold, the register configuration module sends a start instruction and a write operation instruction to the DMA state machine module and the SATA controller module respectively;

[0030] When the SATA controller module receives a write operation instruction, it reads the SATA disk data from the SATA disk and writes it into the second FIFO storage module. When the DMA state machine module receives a start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module, initiates a write busrt operation, reads the SATA disk data from the second FIFO storage module, and writes it into the memory space through the MB bus and AXI bus conversion module.

[0031] The base address and size of the second user memory space are retrieved from the first FIFO storage module, and a write busrt operation is initiated; the SATA disk data in the second FIFO storage module is read and written into the memory space through the MB bus and AXI bus conversion module;

[0032] After all SATA disk data in the first FIFO storage module is retrieved and all write busrt operations are completed, the DMA state machine module returns to the initial state, completing the DMA write operation, and the SATA controller module pulls up the SATA_done signal to indicate that the data transmission is completed.

[0033] Furthermore, when the total memory space of the first FIFO storage module reaches a set storage capacity threshold, in the step in which the register configuration module sends a startup instruction and a write operation instruction to the DMA state machine module and the SATA controller module respectively, the storage capacity threshold is the sum of the sizes of each segment of the user discrete memory space.

[0034] Furthermore, when the SATA controller module receives a write operation instruction, it reads the SATA disk data from the SATA disk and writes it into the second FIFO storage module; when the DMA state machine module receives a start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module, initiates a write busrt operation, reads the SATA disk data in the second FIFO storage module and writes it into the memory space through the MB bus and AXI bus conversion module. When the length of the data transmitted by the write busrt is equal to the size of the first user memory space, the process proceeds to the next step.

[0035] Furthermore, the base address and size of the second user memory space are taken out from the first FIFO storage module, and a write busrt operation is initiated; the SATA disk data in the second FIFO storage module is read out and written into the memory space through the MB bus and AXI bus conversion module. When the length of the data transmitted by the write busrt is equal to the size of the second user memory space, the next step is entered.

[0036] The beneficial effects achieved by the present invention are:

[0037] The present invention provides a SATA data DMA transmission system and method based on FPGA. The system adopts a register configuration module, a first FIFO storage module, a second FIFO storage module, a DMA state machine module, a SATA controller module and an MB bus and AXI bus conversion module. The register configuration module is used to send startup and read / write operation instructions to the DMA state machine module and receive a busy signal; send startup and read / write operation instructions and user data length to the SATA controller module and receive a SATA_done signal; the first FIFO storage module is used to store discrete user memory space base addresses and corresponding space sizes; the DMA state machine module is used to monitor the state of the DMA state machine; the second FIFO storage module is used to store SATA read / write data; the SATA controller module is used to implement SATA interface functions; and the MB bus and AXI bus conversion module is used to implement conversion between an MB bus and an AXI bus. The FPGA-based SATA data DMA transmission system and method provided by the present invention implement SATA data transmission through DMA. At the same time, the flexibility of the FPGA is utilized to avoid the core space operation of the CPU, reducing the process tasks that the CPU needs to handle, and improving the transmission rate and CPU performance to a certain extent. The intermediate core space operation is removed, and the base address of the user discrete memory space is directly stored in the FPGA's FIFO. The DMA state machine retrieves the base address from the FIFO and directly operates the user memory space, saving a lot of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A flowchart of an existing method for an operating system to perform read and write operations on a SATA disk;

[0039] Figure 2 A schematic diagram of the system's work in allocating discrete memory to user tasks in the prior art;

[0040] Figure 3 This is a system block diagram of the FPGA-based SATA data DMA transmission system of the present invention;

[0041] Figure 4 This is a flow chart of the DMA read operation in the FPGA-based SATA data DMA transmission method of the present invention;

[0042] Figure 5 This is a flow chart of the DMA write operation in the FPGA-based SATA data DMA transmission method of the present invention.

[0043] Description of Figure Numbers:

[0044] 10. Register configuration module; 20. First FIFO storage module; 30. Second FIFO storage module; 40. DMA state machine module; 50. SATA controller module; 60. MB bus and AXI bus conversion module. DETAILED DESCRIPTION

[0045] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0046] like Figure 3As shown, the first embodiment of the present invention proposes a SATA (Serial ATA) data DMA (Direct Memory Access) transmission system based on FPGA (Field Programmable Gate Array), including a register configuration module 10, a first FIFO (First Input First Output) storage module 20, a second FIFO storage module 30, a DMA state machine module 40, a SATA controller module 50, and an MB (Modbus, a serial communication protocol) bus and an AXI (Advanced eXtensible Interface, which is a bus protocol), a bus conversion module 60, wherein the register configuration module 10 is connected to the DMA state machine module 40 and the SATA controller module 50 respectively, and is used to send startup and read and write operation instructions to the DMA state machine module 40 and receive a busy signal; send startup and read and write operation instructions and user data length to the SATA controller module 50 and receive a SATA_done signal; a first FIFO storage module 20 is connected to the register configuration module 10 and is used to store discrete user memory space base addresses and corresponding space sizes; the DMA state machine module 40 is connected to the first FIFO storage module 20 and is used to monitor the status of the DMA state machine; a second FIFO storage module 30 is connected to the DMA state machine module 40 and is used to store SATA read and write data; the SATA controller module 50 is connected to the register configuration module 10, the second FIFO storage module 30 and the SATA disk respectively, and is used to implement SATA interface functions; an MB bus and AXI bus conversion module 60 is connected to the DMA state machine module 40 and the CPU respectively, and is used to implement conversion between the MB bus and the AXI bus.

[0047] In this embodiment, the register configuration module 10 is used to send startup and read / write operation instructions to the DMA state machine module 40 and receive a "busy" signal. It also sends startup and read / write operation instructions and user data length to the SATA controller module 50 and receives a "SATA_done" signal. The first FIFO storage module 20 is used to store the discrete user memory space base address and corresponding space size. The DMA state machine module 40 is used to monitor the DMA state machine status. The second FIFO storage module 30 is used to store SATA read / write data. The MB bus to AXI bus conversion module 60 is used to implement conversion between the MB bus and the AXI bus. The SATA controller module 50 is used to implement SATA interface functions.

[0048] like Figure 3As shown, the SATA data DMA transmission system based on FPGA provided by this embodiment has signal descriptions as follows:

[0049] 1) APP_Addr_len: user memory space base address and corresponding space size.

[0050] 2) Start: DMA state machine start instruction.

[0051] 3) Wr_rd: DMA state machine read and write instructions.

[0052] 4) busy: DMA state machine status feedback signal.

[0053] 5) SATA_start: SATA controller startup command.

[0054] 6) SATA_wr_rd: SATA controller reads the command.

[0055] 7) App_data_len: user memory space base address and corresponding space size.

[0056] 8) SATA_done: SATA controller completion indication signal.

[0057] Further, see Figures 3 to 5 The DMA read operation method of the FPGA-based SATA data DMA transmission system provided in this embodiment is used to transfer CPU data to a SATA disk, including the following steps:

[0058] Step 110 : The register configuration module 10 receives the DMA read operation instruction sent by the CPU, and writes N-bit user data into the first FIFO storage module 20 in sequence by combining the base address of the discrete user memory space and the corresponding space size.

[0059] The DMA read operation is to read data from the user memory space and write data to the SATA disk through the SATA controller.

[0060] The CPU uses the register configuration module 10 to write the base address and corresponding space size of the discrete user memory space into a 64-bit data in sequence into the first FIFO storage module 20 (the base address bit width is 32 bits, and the space size bit width is 32 bits).

[0061] Step 120 : When the total memory space of the first FIFO storage module 20 reaches the set storage capacity threshold, the register configuration module 10 sends a start instruction and a read operation instruction to the DMA state machine module 40 and the SATA controller module 50 respectively.

[0062] When the total memory space in the first FIFO storage module 20 reaches a set threshold (Len0+len1+…+lenN=threshold), the register configuration module 10 sends a start instruction and a read operation instruction to the DMA state machine module 40 and the SATA controller module 50 .

[0063] Among them, len0, len1...lenN represent the size of each segment of the user discrete memory space, for example, Figure 1 Where len0 = 1KByte, len1 = 2KByte, len2 = 4KByte, len3 = 2KByte; len0 represents the size of the first segment of the user discrete memory space, such as Figure 1 , len0=1KByte.

[0064] Step 130: When the DMA state machine module 40 receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module 20 and initiates a read busrt operation. The CPU data is written from the memory space to the second FIFO storage module 30 via the MB bus and AXI bus conversion module 60. At the same time, when the SATA controller module 50 receives the read operation instruction and detects that the second FIFO storage module 30 is not empty, it removes the CPU data from the second FIFO storage module 30 and writes it to the SATA disk through the SATA interface.

[0065] After receiving the start command, the DMA state machine module 40 reads BaseAddr0 and len0 (the base address and size of the first user memory space) from the first FIFO storage module 20 and initiates a busrt read operation. The user data is written from the memory space to the second FIFO storage module 30 via the MB bus and AXI bus conversion module 60. Simultaneously, when the SATA controller module 50 detects that the second FIFO storage module 30 is not empty, it removes the data from the second FIFO storage module 30 and writes it to the SATA disk via the SATA interface. When the busrt transfer (burst transfer) data length equals len0 (N*busrt_len=len0), the process proceeds to the next step.

[0066] Step 140: Retrieve the base address and size of the first user memory space from the first FIFO storage module 20 and initiate a busrt read operation. The CPU data is written from the memory space to the second FIFO storage module 30 via the MB bus and AXI bus conversion module 60. The SATA controller module 50 removes the CPU data from the second FIFO storage module 30 and writes it to the SATA disk.

[0067] BaseAddr1 and Len1 are retrieved from the first FIFO storage module 20, and a busrt read operation is initiated. The user data is written from the memory space to the second FIFO storage module 30 via the MB bus and AXI bus conversion module 60. The SATA controller module 50 then retrieves the data from the second FIFO storage module 30 and writes it to the SATA disk. When the length of the data transferred by busrt equals len1, the process proceeds to the next step.

[0068] Step 150: After all CPU data in the first FIFO storage module 20 is retrieved and all read busrt operations are completed, the DMA state machine module 40 returns to the initial state, completing the DMA read operation, and the SATA controller module 50 pulls up the SATA_done signal to indicate that the data transmission has been completed.

[0069] Repeat step 140 to retrieve all data from the first FIFO storage module 20 and complete all read busrt operations. The DMA state machine module 40 returns to the initial state, completing the DMA read operation. The SATA controller module 50 pulls up the SATA_done signal to indicate that the data transmission has been completed.

[0070] Preferably, see Figures 3 to 5 Another aspect of the present invention provided in this embodiment relates to a DMA write operation method of the FPGA-based SATA data DMA transmission system as described above, which is used to transmit SATA disk data to a CPU, comprising the following steps:

[0071] Step 210 : The register configuration module 10 receives the DMA write operation instruction sent by the CPU, and writes N-bit user data composed of the base address of the discrete user memory space and the corresponding space size into the first FIFO storage module 20 in sequence.

[0072] The DMA write operation is to write data to the user memory space through DMA and read the SATA disk through the SATA controller.

[0073] The CPU uses the register configuration module 10 to form a 64-bit data consisting of the base address of the discrete user memory space and the corresponding space size and writes it into the first FIFO storage module 20 (the address bit width is 32 bits and the data length bit width is 32 bits).

[0074] Step 220 : When the total memory space of the first FIFO storage module 20 reaches the set storage capacity threshold, the register configuration module 10 sends a start instruction and a write operation instruction to the DMA state machine module 40 and the SATA controller module 50 respectively.

[0075] When the total memory space in the first FIFO storage module 20 reaches a set threshold, the register configuration module 10 sends a start instruction and a write operation instruction to the DMA state machine module 40 and the SATA controller module 50 .

[0076] Step 230: When the SATA controller module 50 receives the write operation instruction, it reads the SATA disk data from the SATA disk and writes it into the second FIFO storage module 30; when the DMA state machine module 40 receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module 20, initiates a write busrt operation, reads the SATA disk data in the second FIFO storage module 30, and writes it into the memory space through the MB bus and AXI bus conversion module 60.

[0077] After receiving the instruction, the SATA controller module 50 reads the data from the SATA disk and writes it into the second FIFO storage module 30. After receiving the start instruction, the DMA state machine module 40 reads BaseAddr0 and len0 (the base address and size of the first user memory space) from the first FIFO storage module 20, initiates a write busrt operation, reads the data in the second FIFO storage module 30, and writes it into the memory space through the MB bus and AXI bus conversion module 60. When the length of the data transmitted by the write busrt is equal to len0, the process proceeds to the next step.

[0078] BUSRT operation: In DMA data transfer, the basic unit is BUSRT transfer. Once data transfer is initiated, it is calculated according to the number of BUSRT transfers.

[0079] Burst transmission: Burst transmission refers to the method of continuous data transmission between adjacent storage units in the same row. The period of continuous transmission is the burst length.

[0080] Step 240 , retrieve the base address and size of the second user memory space from the first FIFO storage module 20 , initiate a write busrt operation; read the SATA disk data in the second FIFO storage module 30 and write it into the memory space through the MB bus and AXI bus conversion module 60 .

[0081] BaseAddr1 and Len1 are taken out from the first FIFO storage module 20, a write busrt operation is initiated, the data in the second FIFO storage module 30 is read out and written into the memory space through the MBtoAXI module. When the length of the data transmitted by the write busrt is equal to len1, the next step is entered.

[0082] Step 250: After all SATA disk data in the first FIFO storage module 20 is retrieved and all write busrt operations are completed, the DMA state machine module 40 returns to the initial state, completing the DMA write operation, and the SATA controller module 50 pulls up the SATA_done signal to indicate that the data transmission is completed.

[0083] Repeat step 240 to retrieve all data from the first FIFO storage module 20 and complete all write busrt operations. Then, 0 returns to the initial state, completing the DMA write operation. The SATA controller module 50 pulls up the SATA_done signal, indicating that the data transmission is completed.

[0084] Note:

[0085] DMA write operation: The SATA controller reads the SATA disk, and the DMA state machine writes data to the user memory space, that is, transfers the SATA disk data to the CPU.

[0086] DMA read operation: transfers CPU data to SATA disk.

[0087] BaseAddr: user memory space base address;

[0088] Len: memory space size;

[0089] Busrt: burst transmission;

[0090] Busrtlen: The length of data in a burst (also known as the size of the space).

[0091] bLeftWords: The current byte size that needs to be transferred.

[0092] The FPGA-based SATA data DMA transmission system and method provided in this embodiment, compared with the prior art, employs a register configuration module, a first FIFO storage module, a second FIFO storage module, a DMA state machine module, a SATA controller module, and an MB bus to AXI bus conversion module. The register configuration module is configured to send startup and read / write operation instructions to the DMA state machine module and receive a busy signal; send startup and read / write operation instructions and user data length to the SATA controller module and receive a SATA_done signal; the first FIFO storage module is configured to store discrete user memory space base addresses and corresponding space sizes; the DMA state machine module is configured to monitor the status of the DMA state machine; the second FIFO storage module is configured to store SATA read / write data; the SATA controller module is configured to implement SATA interface functions; and the MB bus to AXI bus conversion module is configured to implement conversion between the MB bus and the AXI bus. The FPGA-based SATA data DMA transmission system and method provided in this embodiment implement SATA data transmission through DMA. At the same time, the flexibility of the FPGA is utilized to avoid CPU kernel space operations, reducing the number of process tasks that the CPU needs to handle, and improving the transmission rate and CPU performance to a certain extent. The intermediate kernel space operations are removed, and the base address of the user discrete memory space is directly stored in the FPGA FIFO. The DMA state machine retrieves the base address from the FIFO and directly operates the user memory space, saving a lot of time.

[0093] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such changes and modifications as fall within the scope of the claims and their equivalents.

Claims

1. A DMA read operation method of a SATA data DMA transmission system based on FPGA, used to transfer CPU data to a SATA disk, characterized in that: The invention is applied to a SATA data DMA transmission system based on an FPGA. The SATA data DMA transmission system based on the FPGA comprises a register configuration module (10), a first FIFO storage module (20), a second FIFO storage module (30), a DMA state machine module (40), a SATA controller module (50), and an MB bus and AXI bus conversion module (60). The register configuration module (10) is connected to the DMA state machine module (40) and the SATA controller module (50) respectively. The first FIFO storage module (20) is connected to the register configuration module (10). The DMA state machine module (40) is connected to the first FIFO storage module (20). The second FIFO storage module (30) is connected to the DMA state machine module (40). The SATA controller module (50) is connected to the register configuration module (10), the second FIFO storage module (30), and a SATA disk respectively. The MB bus and AXI bus conversion module (60) is connected to the DMA state machine module (40) and a CPU respectively. The DMA read operation method comprises the following steps: The register configuration module (10) receives the DMA read operation instruction sent by the CPU, and writes the base address of the discrete user memory space and the corresponding space size into an N-bit user data into the first FIFO storage module (20) in sequence; When the total memory space of the first FIFO storage module (20) reaches a set storage capacity threshold, the register configuration module (10) sends a start instruction and a read operation instruction to the DMA state machine module (40) and the SATA controller module (50) respectively; When the DMA state machine module (40) receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module (20) and initiates a busrt read operation. The CPU data is written from the memory space to the second FIFO storage module (30) via the MB bus and AXI bus conversion module (60). At the same time, when the SATA controller module (50) receives the read operation instruction and detects that the second FIFO storage module (30) is not empty, it takes the CPU data from the second FIFO storage module (30) and writes it to the SATA disk via the SATA interface. The base address and size of the first user memory space are retrieved from the first FIFO storage module (20), and a busrt read operation is initiated; user data is written from the memory space to the second FIFO storage module (30) via the MB bus and AXI bus conversion module (60); the SATA controller module (50) retrieves the CPU data from the second FIFO storage module (30) and writes it to the SATA disk; After all CPU data in the first FIFO storage module (20) is retrieved and all read busrt operations are completed, the DMA state machine module (40) returns to the initial state, completing the DMA read operation, and the SATA controller module (50) pulls up the SATA_done signal to indicate that the data transmission has been completed.

2. The DMA read operation method of the SATA data DMA transmission system based on FPGA according to claim 1, characterized in that: In the step of sending a start instruction and a read operation instruction to the DMA state machine module (40) and the SATA controller module (50) respectively when the total memory space of the first FIFO storage module (20) reaches a set storage capacity threshold, the storage capacity threshold is the sum of the sizes of each segment of the user discrete memory space.

3. The DMA read operation method of the SATA data DMA transmission system based on FPGA according to claim 1, characterized in that: The register configuration module (10) receives a DMA read operation instruction sent by the CPU, and sequentially writes N-bit user data composed of a base address of the discrete user memory space and a corresponding space size into the first FIFO storage module (20), wherein the address bit width of the N-bit user data is 32 bits, and the data length bit width is 32 bits.

4. The DMA read operation method of the SATA data DMA transmission system based on FPGA according to claim 1, wherein: When the DMA state machine module (40) receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module (20) and initiates a read busrt operation. The CPU data is written from the memory space to the second FIFO storage module (30) through the MB bus and AXI bus conversion module (60). At the same time, when the SATA controller module (50) detects that the second FIFO storage module (30) is not empty, the CPU data is taken from the second FIFO storage module (30) and written into the SATA disk through the SATA interface. When the length of the data transmitted by the busrt is equal to the size of the first user memory space, the next step is entered.

5. The DMA read operation method of the SATA data DMA transmission system based on FPGA according to claim 1, wherein: The base address and size of the first user memory space are retrieved from the first FIFO storage module (20), and a busrt read operation is initiated; CPU data is written from the memory space into the second FIFO storage module (30) via the MB bus and AXI bus conversion module (60); the SATA controller module (50) retrieves the CPU data from the second FIFO storage module (30) and writes it into the SATA disk; when the length of the data transmitted by the busrt is equal to the size of the second user memory space, the next step is entered.

6. A DMA write operation method of a SATA data DMA transmission system based on FPGA, used to transfer SATA disk data to a CPU, characterized in that: The invention is applied to a SATA data DMA transmission system based on an FPGA. The SATA data DMA transmission system based on the FPGA comprises a register configuration module (10), a first FIFO storage module (20), a second FIFO storage module (30), a DMA state machine module (40), a SATA controller module (50), and an MB bus and AXI bus conversion module (60). The register configuration module (10) is connected to the DMA state machine module (40) and the SATA controller module (50) respectively. The first FIFO storage module (20) is connected to the register configuration module (10). The DMA state machine module (40) is connected to the first FIFO storage module (20). The second FIFO storage module (30) is connected to the DMA state machine module (40). The SATA controller module (50) is connected to the register configuration module (10), the second FIFO storage module (30), and a SATA disk respectively. The MB bus and AXI bus conversion module (60) is connected to the DMA state machine module (40) and a CPU respectively. The DMA write operation method comprises the following steps: The register configuration module (10) receives the DMA write operation instruction sent by the CPU, and writes the base address of the discrete user memory space and the corresponding space size into an N-bit user data into the first FIFO storage module (20) in sequence; When the total memory space of the first FIFO storage module (20) reaches a set storage capacity threshold, the register configuration module (10) sends a start instruction and a write operation instruction to the DMA state machine module (40) and the SATA controller module (50) respectively; When the SATA controller module (50) receives the write operation instruction, it reads the SATA disk data from the SATA disk and writes it into the second FIFO storage module (30); when the DMA state machine module (40) receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module (20), initiates a write busrt operation, reads the SATA disk data from the second FIFO storage module (30), and writes it into the memory space through the MB bus and AXI bus conversion module (60); Retrieving the base address and size of the second user memory space from the first FIFO storage module (20) and initiating a write busrt operation; reading the SATA disk data in the second FIFO storage module (30) and writing the data into the memory space via the MB bus and AXI bus conversion module (60); After all SATA disk data in the first FIFO storage module (20) is retrieved and all write busrt operations are completed, the DMA state machine module (40) returns to the initial state, completing the DMA write operation, and the SATA controller module (50) pulls up the SATA_done signal to indicate that the data transmission is completed.

7. The DMA write operation method of the FPGA-based SATA data DMA transmission system according to claim 6, wherein: When the total memory space of the first FIFO storage module (20) reaches a set storage capacity threshold, the register configuration module (10) sends a start instruction and a write operation instruction to the DMA state machine module (40) and the SATA controller module (50) respectively, wherein the storage capacity threshold is the sum of the sizes of each segment of the user discrete memory space.

8. The DMA write operation method of the SATA data DMA transmission system based on FPGA according to claim 6, wherein: When the SATA controller module (50) receives the write operation instruction, it reads the SATA disk data from the SATA disk and writes it into the second FIFO storage module (30); when the DMA state machine module (40) receives the start instruction, it reads the base address and size of the first user memory space from the first FIFO storage module (20), initiates a write busrt operation, reads the SATA disk data in the second FIFO storage module (30) and writes it into the memory space through the MB bus and AXI bus conversion module (60), and in the step of: when the length of the data transmitted by the write busrt is equal to the size of the first user memory space, proceeds to the next step.

9. The DMA write operation method of the SATA data DMA transmission system based on FPGA according to claim 6, wherein: The base address and size of the second user memory space are retrieved from the first FIFO storage module (20), and a write busrt operation is initiated; the SATA disk data in the second FIFO storage module (30) is read out and written into the memory space via the MB bus and AXI bus conversion module (60); when the length of the data transmitted by the write busrt is equal to the size of the second user memory space, the next step is entered.

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