Pixel circuit and display panel
By introducing a shielding structure into the pixel circuit of the display panel, the interference of the control signal line to the initialization signal line is shielded, thus solving the problem of poor display uniformity and improving the display quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI VISIONOX TECH CO LTD
- Filing Date
- 2024-03-15
- Publication Date
- 2026-06-05
Smart Images
Figure CN118038795B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and a display panel. Background Technology
[0002] With the development of display technology, users have increasingly higher requirements for image display quality. Existing display panels suffer from poor display uniformity, which affects the image display quality. Summary of the Invention
[0003] This invention provides a pixel circuit and a display panel to improve the display uniformity of the display panel and enhance the image display quality.
[0004] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a driving module and an initialization module;
[0005] The driving module includes a driving control terminal, a first terminal, and a second terminal, which are used to generate a driving current between the first terminal and the second terminal according to the voltage of the driving control terminal, and drive the light-emitting module according to the driving current.
[0006] The initialization module is electrically connected to at least one control signal line and at least one initialization signal line, respectively, and is used to initialize at least one of the drive control terminal, the first terminal, the second terminal and the light-emitting module;
[0007] The pixel circuit also includes a shielding structure, which is used to shield the control signal on at least one control signal line from interfering with the initialization signal on at least one initialization signal line.
[0008] Optionally, the pixel circuit is formed on the substrate; the shielding structure is located between the film layer containing at least one initialization signal line and the film layer containing at least one control signal line, and the orthographic projection of the shielding structure on the substrate at least partially overlaps with the orthographic projection of the at least one control signal line on the substrate;
[0009] Optionally, the control signal line includes a main body extending along a first direction, and the orthographic projection of the shielding structure on the substrate covers the orthographic projection of the main body of at least one control signal line on the substrate.
[0010] Optionally, the control signal line also includes a branch connected to the main body, the branch extending along a second direction and intersecting with the first direction; the orthographic projection of the shielding structure on the substrate covers the orthographic projection of the branch of at least one control signal line on the substrate.
[0011] Optionally, the distance between the corresponding edges of the orthographic projection of the shielding structure on the substrate and the orthographic projection of the covered main body on the substrate is greater than or equal to 0.
[0012] Optionally, the distance between the corresponding edges of the orthographic projection of the shielding structure on the substrate and the orthographic projection of the covered main body on the substrate is less than or equal to 3 micrometers;
[0013] Optionally, at least one initialization signal line may have an orthographic projection on the substrate that overlaps with the orthographic projection of the shielding structure on the substrate.
[0014] Optionally, the initialization module includes at least two initialization units, each of which is connected to an initialization signal line and a control signal line respectively. The initialization units are used to reset at least one of the drive control terminal, the first terminal, the second terminal, and the light-emitting module.
[0015] At least one initialization signal line is at least partially multiplexed as a shielded structure.
[0016] Optionally, the initialization unit that connects to the initialization signal line which is multiplexed into a shielded structure has a control signal frequency that is less than or equal to the control signal frequency of the control signal line connected to other initialization units.
[0017] Optionally, the initialization module includes a first initialization unit, which is electrically connected to the first control signal line and the first initialization signal line respectively, and is used to initialize the drive control terminal;
[0018] The initialization module also includes a second initialization unit, which is electrically connected to the second control signal line, the second initialization signal line, and the light-emitting module, respectively, and is used to initialize the light-emitting module.
[0019] And / or, the initialization module includes a third initialization unit, which is electrically connected to the third control signal line, the third initialization signal line, and the first or second terminal of the drive module, respectively, and is used to initialize the first or second terminal of the drive module;
[0020] At least a portion of the first initialization signal line is multiplexed as a shielded structure or at least a portion of the third initialization signal line is multiplexed as a shielded structure;
[0021] Optionally, the frequency of the first control signal on the first control signal line is less than the frequency of the second control signal on the second control signal line, and less than the frequency of the third control signal on the third control signal line.
[0022] Optionally, the frequency of the second control signal is equal to the frequency of the third control signal;
[0023] Optionally, the second control signal line can be multiplexed as the third control signal line.
[0024] Optionally, the driving module and the light-emitting module are connected in series between the first power line and the second power line; wherein, the driving current generated by the driving module is related to the first power supply voltage on the first power line, and the light-emitting module is electrically connected to the second power line.
[0025] At least a portion of the first power line or at least a portion of the second power line is reused as a shielding structure;
[0026] Optionally, the pixel circuit further includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the light-emitting module. The first light-emitting control module and the second light-emitting control module are respectively used to turn on or off according to the light-emitting control signal.
[0027] Optionally, the pixel circuit also includes a data writing module, which is used to write data voltage to the drive control terminal;
[0028] Optionally, the pixel circuit also includes a compensation module, which is connected between the second end of the driving module and the driving control end, and is used to compensate the threshold voltage of the driving module.
[0029] Optionally, the compensation module includes a first oxide transistor;
[0030] Optionally, the initialization module includes a first initialization unit, which is connected to the drive control terminal through the compensation module;
[0031] Optionally, the first initialization unit includes a second oxide transistor;
[0032] Optionally, the frequency of the light emission control signal is higher than the frequency of the data writing voltage written by the data writing module to the drive control terminal.
[0033] Secondly, embodiments of the present invention also provide a display panel, including the pixel circuit of the first aspect.
[0034] Optionally, the display panel also includes initialization signal lines and control signal lines; the pixel circuit includes first-type transistors and second-type transistors;
[0035] The display panel also includes a substrate and a first active layer, a second active layer and a multilayer metal layer stacked on one side of the substrate. The first active layer is an active layer of a first type of transistor, and the second active layer is an active layer of a second type of transistor. The second active layer is located on the side of the first active layer away from the substrate.
[0036] At least one metal layer includes the gate of a first type transistor, at least one metal layer includes the gate of a second type transistor, and at least one metal layer includes the source and drain of the first type transistor and / or the second type transistor; at least a portion of at least one control signal line is on the same layer as the gate of the first type transistor.
[0037] Optionally, the shielding structure is in the same layer as the gate of the second type of transistor or is located in a metal layer on the side of the metal layer where the gate of the second type of transistor is located away from the substrate;
[0038] Optionally, at least a portion of at least one control signal line is on the same layer as the gate of the second type of transistor;
[0039] Optionally, at least a portion of at least one initialization signal line is on the same layer as the source and drain;
[0040] Optionally, the multilayer metal layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked from one side of the substrate; at least one control signal line is located in the first metal layer, the shielding structure is located in the second or third metal layer, and at least a portion of at least one initialization signal line is located in the fourth metal layer.
[0041] Optionally, the gate of the first type of transistor is located in the first metal layer;
[0042] Optionally, the gate of the second type of transistor is located in a second metal layer and / or a third metal layer;
[0043] Optionally, the first active layer, the first metal layer, the second metal layer, the second active layer, the third metal layer, and the fourth metal layer are stacked sequentially from one side of the substrate.
[0044] Optionally, the pixel circuit also includes a storage capacitor, and the second metal layer includes one electrode of the storage capacitor;
[0045] Optionally, the initialization signal lines are arranged in a grid pattern;
[0046] Optionally, the initialization signal line includes a first sub-initialization signal line and a second sub-initialization signal line, the extension directions of the first sub-initialization signal line and the extension directions of the second sub-initialization signal line intersect, and the first sub-initialization signal line and the second sub-initialization signal line are electrically connected.
[0047] Optionally, the display panel further includes a fifth metal layer located on the side of the fourth metal layer away from the substrate, the first sub-initialization signal line being located in at least one of the second, third, and fourth metal layers, and the second sub-initialization signal line being located in the fifth metal layer;
[0048] Optionally, the first type of transistor includes a low-temperature polycrystalline silicon transistor, and the second type of transistor includes an oxide transistor.
[0049] Optionally, the initialization module includes a first initialization unit, which is electrically connected to the first control signal line and the first initialization signal line respectively, and is used to initialize the drive control terminal; the initialization module also includes a second initialization unit and / or a third initialization unit, which is electrically connected to the second control signal line, the second initialization signal line and the light-emitting module respectively, and is used to initialize the light-emitting module; the third initialization unit is electrically connected to the third control signal line, the third initialization signal line and the first or second terminal of the drive module respectively, and is used to initialize the first or second terminal of the drive module;
[0050] The pixel circuit also includes a first light-emitting control module and a second light-emitting control module, and the light-emitting control terminals of the first light-emitting control module and the second light-emitting control module are both connected to the light-emitting control signal line.
[0051] The pixel circuit also includes a data writing module, whose write control terminal is connected to the write control signal line;
[0052] The pixel circuit also includes a compensation module, the control terminal of which is connected to a compensation control signal line; the first initialization unit and the compensation module each include an oxide transistor, and the data writing module, the driving module, the first light emission control module, the second light emission control module, the second initialization unit and the third initialization unit each include a low-temperature polysilicon transistor;
[0053] Optionally, the overall extension direction of the first sub-initialization signal line, the first control signal line, the second control signal line, the third control signal line, the write control signal line, the compensation control signal line, and the light emission control signal line is the first direction; the first control signal line, the write control signal line, the compensation control signal line, the light emission control signal line, and the second control signal line connected to the same pixel circuit are arranged sequentially along the second direction;
[0054] Optionally, the first sub-initialization signal line of the first initialization signal line is multiplexed into a shielding structure, and the orthographic projection of the shielding structure on the substrate overlaps with the orthographic projection of the second control signal line on the substrate; the second control signal line is located in the metal layer of the shielding structure near the substrate, and the first sub-initialization signal line of the second initialization signal line and the first sub-initialization signal line of the third initialization signal line are located in the metal layer of the shielding structure away from the second control signal line.
[0055] Optionally, the second control signal line can be multiplexed as the third control signal line;
[0056] Optionally, the orthographic projection of the first sub-initialization signal line of the second initialization signal line onto the substrate overlaps with the orthographic projection of the shielding structure onto the substrate; along the second direction, the first sub-initialization signal line of the third initialization signal line is located between the compensation control signal line and the first sub-initialization signal line of the first initialization signal line; or, the orthographic projection of the first sub-initialization signal line of the third initialization signal line onto the substrate overlaps with the orthographic projection of the shielding structure onto the substrate; along the second direction, the first sub-initialization signal line of the second initialization signal line is located between the compensation control signal line and the first sub-initialization signal line of the first initialization signal line.
[0057] Optionally, the second control signal line, the third control signal line, the write control signal line, and the light emission control signal line are located in the first metal layer;
[0058] Optionally, the first control signal line and the compensation control signal line are located in the second metal layer and / or the third metal layer;
[0059] The first sub-initialization signal line of the first initialization signal line is located in the second or third metal layer; the first sub-initialization signal line of the second initialization signal line and the first sub-initialization signal line of the third initialization signal line are located in the fourth metal layer.
[0060] This invention provides a pixel circuit and a display panel. The pixel circuit includes a driving module, an initialization module, and a shielding structure. The initialization module is electrically connected to at least one control signal line and at least one initialization signal line, respectively, and is used to initialize at least one of the driving control terminal, the first terminal, the second terminal, and the light-emitting module. The shielding structure is used to shield the control signal on the at least one control signal line from interfering with the initialization signal on the at least one initialization signal line, so that the initialization signal on the initialization signal line can be relatively stable, resulting in better uniformity of initialization of the pixel circuit in the display panel, thereby improving the display uniformity of the display panel and thus improving the display quality. Attached Figure Description
[0061] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;
[0062] Figure 2 This is a cross-sectional view of the film structure of the pixel circuit provided in an embodiment of the present invention;
[0063] Figure 3 This is a schematic diagram of the signal lines connecting the pixel circuit provided in an embodiment of the present invention;
[0064] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;
[0065] Figure 5This is a top view of a display panel provided in an embodiment of the present invention;
[0066] Figure 6 This is a cross-sectional view of a display panel provided in an embodiment of the present invention;
[0067] Figure 7 This is a schematic diagram of the structure of the first active layer in the display panel;
[0068] Figure 8 This is a schematic diagram of the structure of the first metal layer provided in an embodiment of the present invention;
[0069] Figure 9 This is a schematic diagram of the structure of the second metal layer provided in an embodiment of the present invention;
[0070] Figure 10 This is a schematic diagram of the structure of the second active layer provided in an embodiment of the present invention;
[0071] Figure 11 This is a schematic diagram of the structure of the third metal layer provided in an embodiment of the present invention;
[0072] Figure 12 This is a schematic diagram of the structure of the fourth metal layer provided in an embodiment of the present invention;
[0073] Figure 13 This is a schematic diagram of the structure of the fifth metal layer provided in an embodiment of the present invention. Detailed Implementation
[0074] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.
[0075] As described in the background section, existing display panels suffer from poor display uniformity, affecting image quality. The inventors have discovered that this problem arises because existing display panels typically include a driving transistor and an initialization transistor in their pixel circuitry. The initialization transistor transmits an initialization voltage to some internal nodes in the pixel circuitry, thereby initializing these nodes. However, transitions in the control signal connected to the gate of the initialization transistor can disturb the initialization voltage, resulting in poor display uniformity and affecting the image quality of the display panel.
[0076] For the reasons stated above, embodiments of the present invention provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 This is a cross-sectional view of the film structure of the pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 2 The pixel circuit includes a driving module 110 and an initialization module 120. The driving module 110 includes a driving control terminal G1, a first terminal S1, and a second terminal D1, and is used to generate a driving current between the first terminal S1 and the second terminal D1 according to the voltage of the driving control terminal G1, and drive the light-emitting module 200 according to the driving current. The initialization module 120 is electrically connected to at least one control signal line Ctrl and at least one initialization signal line Vref, and is used to initialize at least one of the driving control terminal G1, the first terminal S1, the second terminal D1, and the light-emitting module 200. The pixel circuit also includes a shielding structure 130, which is used to shield the interference of the control signal on the at least one control signal line Ctrl on the initialization signal on the at least one initialization signal line Vref.
[0077] The driving module 110 may include a driving transistor. The initialization module 120 may include at least one initialization transistor. The operation of the pixel circuit may include an initialization phase. During the initialization phase, the initialization module 120 initializes at least one of the driving control terminal G1, the first terminal S1, the second terminal D1 of the driving module 110, and the light-emitting module 200 to clear residual charges from the previous frame. The conduction state of the initialization module 120 is controlled by a control signal on the control signal line Ctrl. The control signal undergoes at least one high-low level transition in each frame. In existing display panels, there is a coupling capacitor between the initialization signal line Vref and the control signal line Ctrl. Therefore, the transition of the control signal can interfere with the initialization signal on the initialization signal line Vref, causing instability in the initialization signal. In this embodiment, the pixel circuit also includes a shielding structure 130. The shielding structure 130 can be connected to a fixed voltage. The shielding structure 130 can be used to shield the control signal on the control signal line Ctrl from interfering with the initialization signal on the initialization signal line Vref, so that the initialization signal on the initialization signal line Vref can be relatively stable, resulting in better uniformity of initialization of the pixel circuit in the display panel, thereby improving the display uniformity of the display panel and enhancing the display quality.
[0078] The pixel circuit of this embodiment includes a driving module, an initialization module, and a shielding structure. The initialization module is electrically connected to at least one control signal line and at least one initialization signal line, respectively, and is used to initialize at least one of the driving control terminal, the first terminal, the second terminal, and the light-emitting module. The shielding structure is used to shield the control signal on the at least one control signal line from interfering with the initialization signal on the at least one initialization signal line, so that the initialization signal on the initialization signal line can be relatively stable, resulting in better uniformity of initialization of the pixel circuit in the display panel, thereby improving the display uniformity of the display panel and thus improving the display quality.
[0079] Continue to refer to Figure 2 Based on the above technical solution, optionally, the pixel circuit is formed on the substrate; the shielding structure 130 is located between the film layer where at least one initialization signal line Vref is located and the film layer where at least one control signal line Ctrl is located, and the orthographic projection of the shielding structure 130 on the substrate at least partially overlaps with the orthographic projection of the at least one control signal line Ctrl on the substrate; in this way, the shielding structure 130 can play a good shielding role against the potential changes on the control signal line Ctrl, reduce the influence of the potential changes on the control signal line Ctrl on the initialization signal on the initialization signal line Vref, improve the initialization uniformity, and thus improve the display quality of the image.
[0080] Figure 3 This is a schematic diagram of the signal lines connecting the pixel circuit provided in an embodiment of the present invention, in conjunction with... Figures 1-3 Based on the above technical solution, optionally, the control signal line Ctrl includes a main body Ctrl1 extending along the first direction x, and the orthographic projection of the shielding structure 130 on the substrate covers the orthographic projection of the main body Ctrl1 of at least one control signal line Ctrl on the substrate.
[0081] In this embodiment, the main body Ctrl1 of the control signal line Ctrl constitutes the main structure of the control signal line Ctrl. Therefore, the potential transitions of the main body Ctrl1 of the control signal line Ctrl can significantly interfere with the initialization signal on the initialization signal line Vref. In this embodiment, the orthographic projection of the shielding structure 130 on the substrate covers the orthographic projection of at least one main body Ctrl1 of the control signal line Ctrl on the substrate, thereby shielding the interference of the potential transitions of the main body Ctrl1 of the control signal line Ctrl on the initialization signal on the initialization signal line Vref, and thus improving the display quality.
[0082] Based on the above technical solution, optionally, the distance between the corresponding edge of the orthographic projection of the shielding structure 130 on the substrate and the orthographic projection of the covered main body Ctrl1 on the substrate is greater than or equal to 0; that is, the orthographic projection of the shielding structure 130 on the substrate completely covers the orthographic projection of the main body Ctrl1 on the substrate, and the edge of the orthographic projection of the shielding structure 130 on the substrate does not overlap with the edge of the main body Ctrl1 on the substrate. This configuration allows the shielding structure 130 to provide better shielding against potential changes in the main body Ctrl1 on the control signal line Ctrl, further improving the image display quality.
[0083] Based on the above technical solution, optionally, the distance between the corresponding edge of the orthographic projection of the shielding structure 130 on the substrate and the orthographic projection of the covered main body Ctrl1 on the substrate is less than or equal to 3 micrometers; in this way, it can be ensured that the shielding structure 130 plays a good shielding role against the potential jump of the main body Ctrl1 on the control signal line Ctrl, while ensuring that the area occupied by the shielding structure 130 is not too large, reducing the wiring difficulty and ensuring pixel density.
[0084] Based on the above technical solutions, optionally, the control signal line Ctrl also includes a branch Ctrl2 connected to the main body Ctrl1. The branch Ctrl2 extends along the second direction y, which intersects with the first direction x. The orthographic projection of the shielding structure 130 on the substrate covers the orthographic projection of at least one branch Ctrl2 of the control signal line Ctrl on the substrate. In this way, the shielding structure 130 can shield the potential jump of the branch Ctrl2 of the control signal line Ctrl from interfering with the initialization signal on the initialization signal line Vref, thereby further improving the display quality.
[0085] Based on the above technical solutions, optionally, at least one initialization signal line's orthographic projection on the substrate overlaps with the orthographic projection of the shielding structure on the substrate. This allows the shielding structure to more effectively shield the initialization signal line from interference caused by potential jumps on the control signal line, further improving the display quality.
[0086] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, combined with... Figure 2 and Figure 4 Optionally, the initialization module 120 includes at least two initialization units ( Figure 4 The diagram illustrates that the initialization module 120 includes three initialization units, namely the first initialization unit 121, the second initialization unit 122, and the third initialization unit 123. Each initialization unit is connected to an initialization signal line and a control signal line. The initialization unit is used to reset at least one of the drive control terminal G1, the first terminal S1, the second terminal D1, and the light-emitting module 200. At least a portion of the at least one initialization signal line is multiplexed as the shielding structure 130.
[0087] In this embodiment, by multiplexing at least a portion of at least one initialization signal line as a shielding structure 130, interference from the control signal on the control signal line to other initialization signal lines is shielded. This improves the initialization uniformity of the pixel circuit by at least some initialization units, thereby enhancing the image display quality. Furthermore, by multiplexing at least a portion of at least one initialization signal line as a shielding structure, it is unnecessary to add an additional shielding structure to the display panel, simplifying the display panel wiring and facilitating increased pixel density.
[0088] Based on the above technical solution, optionally, the control signal frequency on the control signal line connected to the initialization unit which is multiplexed as a shielded structure is less than or equal to the control signal frequency on the control signal line connected to other initialization units.
[0089] Specifically, for any initialization unit, the higher the control frequency of the connected control signal line, the higher the conduction frequency of the initialization unit; conversely, the lower the control frequency of the connected control signal line, the lower the conduction frequency of the initialization unit. A higher conduction frequency of the initialization unit has a greater impact on the display panel's image quality. In this embodiment, by using the initialization signal line connected to the initialization unit with the lower conduction frequency as a shielding structure, interference from control signal changes on the signal on the initialization signal line connected to the initialization unit with the higher conduction frequency is shielded. This makes the initialization signal transmitted by the initialization unit with the higher conduction frequency relatively stable, and improves image display quality without requiring additional shielding.
[0090] Continue to refer to Figure 4 Based on the above technical solution, optionally, the initialization module 120 includes a first initialization unit 121, which is electrically connected to the first control signal line SN1 and the first initialization signal line Vref1, and is used to initialize the drive control terminal G1; the initialization module 120 also includes a second initialization unit 122, which is electrically connected to the second control signal line SP2, the second initialization signal line Vref2, and the light-emitting module 200, and is used to initialize the light-emitting module 200; and / or, the initialization module 120 includes a third initialization unit 123, which is electrically connected to the third control signal line SP3, the third initialization signal line Vref3, and the first terminal S1 or the second terminal D1 of the drive module 110, and is used to initialize the first terminal S1 or the second terminal D1 of the drive module 110.
[0091] The light-emitting module 200 may include a light-emitting device, and the second initialization unit 122 may be electrically connected to the anode of the light-emitting device to initialize the anode of the light-emitting device.
[0092] In some optional embodiments of the present invention, at least a portion of the first initialization signal line Vref1 is multiplexed as a shielding structure 130.
[0093] Specifically, in pixel circuits, the driving transistors, due to being in the same bias state for a long time, suffer from poor low-grayscale display effects. To solve this problem, a multi-pulse driving method can be used to drive the third initialization unit 123 to initialize the first terminal S1 or the second terminal D1 of the driving module 110, thereby changing the bias state of the driving transistors; and a multi-pulse driving method can be used to drive the second initialization unit 122 to initialize the light-emitting module 200, thereby improving the display effect. Therefore, the conduction frequency of the second initialization unit 122 and the third initialization unit 123 is higher than the conduction frequency of the first initialization unit 121. That is, the frequency of the first control signal on the first control signal line SN1 is less than the frequency of the second control signal on the second control signal line SP2, and less than the frequency of the third control signal on the third control signal line SP3. In this case, at least a portion of the first initialization line is reused as a shielding structure 130. This allows the first initialization signal line Vref1 connected to the first initialization unit 121 with a lower conduction frequency to be used as a shielding structure 130. This shields the signals on the initialization signal lines Vref connected to the second initialization unit 122 and the third initialization unit 123 with higher conduction frequencies from being interfered with by changes in the control signal. This makes the initialization signals transmitted by the second initialization unit 122 and the third initialization unit 123 with higher conduction frequencies relatively stable. Without the need to add an additional shielding structure 130, the display quality can be improved.
[0094] In another alternative embodiment of the invention, at least a portion of the third initialization signal line Vref3 is multiplexed as a shielding structure 130.
[0095] Specifically, among the second initialization unit 122 and the third initialization unit 123, the second initialization unit 122, which initializes the light-emitting module 200, has a relatively greater impact on the display effect of the display panel. In this embodiment, by multiplexing at least a portion of the third initialization signal line Vref3 as a shielding structure 130, the interference of the control signal change on the control signal line Ctrl on the initialization signals on the first initialization signal line Vref1 and the second initialization signal line Vref2 is shielded, which is more conducive to improving the display quality of the screen.
[0096] Based on the above technical solution, optionally, the frequency of the second control signal is equal to the frequency of the third control signal. In some optional embodiments of the present invention, the second control signal line SP2 is multiplexed as the third control signal line SP3, which can reduce the number of signal lines in the display panel and help improve pixel density.
[0097] Continue to refer to Figure 2 and Figure 4 In some optional embodiments of the present invention, the driving module 110 and the light-emitting module 200 are connected in series between the first power line VDD and the second power line VSS; wherein, the driving current generated by the driving module 110 is related to the first power supply voltage on the first power line VDD, and the light-emitting module 200 is electrically connected to the second power line VSS; at least a portion of the first power line VDD or at least a portion of the second power line VSS is reused as a shielding structure 130.
[0098] Specifically, the initialization unit includes an initialization transistor. Parasitic capacitance exists between the gate and source of the initialization transistor, and also between its gate and drain. The gate of the initialization transistor is connected to a control signal line, and either its source or drain is connected to the initialization signal line. Due to the coupling effect of the parasitic capacitance, potential changes on the control signal line can interfere with the initialization signal on the initialization signal line. In this embodiment, at least a portion of the first power line VDD and the second power line VSS is multiplexed as a shielding structure 130. Compared to using the structure of the initialization signal line as the shielding structure 130, the potential of the shielding structure 130 itself is more stable, resulting in a better shielding effect of the shielding structure 130 on the control signal on the control signal line, thus further improving the display quality.
[0099] Based on the above technical solution, optionally, the pixel circuit also includes a first light-emitting control module 140 and a second light-emitting control module 150. The first light-emitting control module 140 is connected between the first power line VDD and the first terminal S1 of the driving module 110, and the second light-emitting control module 150 is connected between the second terminal D1 of the driving module 110 and the light-emitting module 200. The first light-emitting control module 140 and the second light-emitting control module 150 are respectively used to turn on or off according to the light-emitting control signal.
[0100] Specifically, the operation of the pixel circuit may include a light-emitting phase. Outside of this phase, the light-emitting control signal is an invalid level signal, and both the first light-emitting control module 140 and the second light-emitting control module 150 are turned off. During the light-emitting phase, the light-emitting control signal may remain at an active level, or it may include multiple active level pulses and multiple invalid level pulses, such that during this phase, both the first light-emitting control module 140 and the second light-emitting control module 150 have on-time periods, and the light-emitting module 200 emits light for display.
[0101] Continue to refer to Figure 4 Based on the above technical solution, optionally, the pixel circuit also includes a data writing module 160, which is used to write data voltage to the drive control terminal G1. The data voltage is transmitted via the data line Data.
[0102] Optionally, the pixel circuit further includes a compensation module 170, which is connected between the second terminal D1 and the drive control terminal G1 of the drive module 110, and is used to compensate the threshold voltage of the drive module 110. In some optional embodiments of the present invention, the compensation module 170 includes a first oxide transistor. The oxide transistor has a small leakage current, which allows the potential of the drive control terminal G1 of the drive module 110 to be well maintained.
[0103] Optionally, the initialization module includes a first initialization unit 121, which is connected to the drive control terminal G1 via a compensation module 170. In some optional embodiments of the present invention, the first initialization unit 121 includes a second oxide transistor, further enabling the potential of the drive control terminal G1 of the drive module 110 to be well maintained.
[0104] Optionally, the frequency of the light emission control signal is higher than the frequency at which the data writing module 160 writes data voltage to the drive control terminal G1. In some optional embodiments of the present invention, the frequency of the light emission control signal is equal to the frequency on the second control signal line SP2 to which the second initialization unit 122 is connected. During at least a portion of the pixel circuit operation, when the control signal on the second control signal line SP2 is at an active level causing the second initialization unit 122 to be turned on, the light emission control signal is at an inactive level causing both the first light emission control module 140 and the second light emission control module 150 to be turned off; when the control signal on the second control signal line SP2 is at an inactive level causing the second initialization unit 122 to be turned off, the light emission control signal is at an active level causing both the first light emission control module 140 and the second light emission control module 150 to be turned on.
[0105] This invention also provides a display panel that includes the pixel circuits of any of the above embodiments of the invention and has the beneficial effects of the display panels of any of the above embodiments of the invention.
[0106] Figure 5 This is a top view of a display panel provided in an embodiment of the present invention, with reference to... Figure 5Optionally, the display panel further includes an initialization signal line Vref and a control signal line Ctrl; the pixel circuit includes a first type transistor and a second type transistor; the display panel further includes a substrate and a first active layer, a second active layer and multiple metal layers stacked on one side of the substrate, wherein the first active layer is the active layer of the first type transistor, the second active layer is the active layer of the second type transistor, and the second active layer is located on the side of the first active layer away from the substrate; at least one metal layer includes the gate of the first type transistor, at least one metal layer includes the gate of the second type transistor, and at least one metal layer includes the source and drain of the first type transistor and / or the second type transistor; at least a portion of at least one control signal line Ctrl is on the same layer as the gate of the first type transistor.
[0107] Specifically, the pixel circuit includes two different types of transistors, and the transistor types included in the module are determined according to the connection relationship and function of different modules in the pixel circuit, which can enable the display panel to achieve better display effects. Optionally, the first type of transistor includes a low-temperature polysilicon transistor, and the second type of transistor includes an oxide transistor. In some optional embodiments of the present invention, the shielding structure 130 is on the same layer as the gate of the second type of transistor. Since the metal layer containing the gate of the second type of transistor includes fewer circuit structures, setting the shielding structure 130 on the same layer as the gate of the second type of transistor can make full use of the film layer space and simplify wiring. Optionally, at least a portion of at least one control signal line is on the same layer as the gate of the second type of transistor, which allows the control signal line and the gate of the second type of transistor to be connected on the same layer, making the connection between the control signal line and the gate of the second type of transistor more convenient and easier to implement.
[0108] In another optional embodiment of the present invention, the shielding structure 130 is located in the metal layer on the side away from the substrate of the metal layer where the gate of the second type transistor is located, thereby ensuring the shielding effect on the control signal on the control signal line located at the gate of the second type transistor.
[0109] Based on the above technical solution, optionally, at least a portion of at least one initialization signal line Vref is on the same layer as the source and drain.
[0110] The metal layer containing the gate of the second type of transistor can be located on the side of the metal layer containing the gate of the first type of transistor that is away from the substrate. The metal layers containing the source and drain can be located on the side of the metal layer containing the gate of the first type of transistor that is away from the substrate, and also on the side of the gate of the second type of transistor that is away from the substrate. Therefore, by setting the shielding structure 130 to be on the same layer as the gate of the second type of transistor, at least a portion of at least one control signal line Ctrl to be on the same layer as the gate of the first type of transistor, and at least a portion of at least one initialization signal line Vref to be on the same layer as the source and drain, it can be ensured that the metal layer containing the shielding structure 130 is located between the metal layer containing at least one control signal line Ctrl and the metal layer containing at least one initialization signal line Vref, thus ensuring that the shielding structure 130 can perform its shielding function.
[0111] Figure 6 This is a cross-sectional view of a display panel provided in an embodiment of the present invention, with reference to... Figure 6 Based on the above technical solution, optionally, the multilayer metal layer includes a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 stacked from one side of the substrate 300. Figure 7 This is a schematic diagram of the structure of the first active layer in the display panel. Figure 8 This is a schematic diagram of the structure of the first metal layer provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of the second metal layer provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of the structure of the second active layer provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of the third metal layer provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of the structure of the fourth metal layer provided in an embodiment of the present invention. (Reference) Figures 6-12 Optionally, at least one control signal line Ctrl is located on the first metal layer M1, the shielding structure 130 is located on the second metal layer M2 or the third metal layer M3, and at least a portion of the initialization signal line Vref is located on the fourth metal layer M4. This configuration allows the shielding structure 130 to block interference from control signals on the control signal lines located at least partially on the first metal layer M1 on the initialization signal line Vref located on the fourth metal layer M4, thereby improving the display effect.
[0112] Based on the above technical solution, in some optional embodiments of the present invention, the gate of the first type of transistor is located in the first metal layer M1.
[0113] Based on the above technical solution, in some optional embodiments of the present invention, the gate of the second type transistor is located in the second metal layer M2 and / or the third metal layer M3. The second type transistor can be a dual-gate structure. Specifically, the second type transistor can include a top gate and a bottom gate, wherein the bottom gate can be located in the second metal layer M2 and the top gate can be located in the third metal layer M3.
[0114] Based on the above technical solution, optionally, the first active layer P1, the first metal layer M1, the second metal layer M2, the second active layer P2, the third metal layer M3 and the fourth metal layer M4 are stacked sequentially from one side of the substrate.
[0115] Optionally, the pixel circuit also includes a storage capacitor, the second metal layer M2 includes one plate of the storage capacitor, and the other plate of the storage capacitor may be located in the first metal layer M1.
[0116] Optionally, the initialization signal line Vref is grid-shaped, which reduces the resistance of the initialization signal line Vref and reduces the voltage drop when transmitting the initialization signal, thus improving the display effect. In some optional embodiments of the present invention, the initialization signal line Vref includes a first sub-initialization signal line and a second sub-initialization signal line, the extension directions of the first sub-initialization signal line and the extension directions of the second sub-initialization signal line intersect, and the first sub-initialization signal line and the second sub-initialization signal line 20 are electrically connected.
[0117] Optionally, the display panel also includes a fifth metal layer M5 located on the side of the third metal layer M3 away from the substrate. Figure 13 This is a schematic diagram of the structure of the fifth metal layer provided in an embodiment of the present invention. The first sub-initialization signal line is located in at least one of the second metal layer M2, the third metal layer M3 and the fourth metal layer M4. The second sub-initialization signal line Vref20 is located in the fifth metal layer M5. The second sub-initialization signal line Vref20 and the first sub-initialization signal line can be connected through a via.
[0118] Combination Figure 4Optionally, the initialization module 120 includes a first initialization unit 121, which is electrically connected to the first control signal line SN1 and the first initialization signal line Vref1, respectively, for initializing the drive control terminal G1; the initialization module 120 also includes a second initialization unit 122 and / or a third initialization unit 123, whereby the second initialization unit 122 is electrically connected to the second control signal line SP2, the second initialization signal line Vref2, and the light-emitting module 200, respectively, for initializing the light-emitting module 200; and the third initialization unit 123 is electrically connected to the third control signal line SP3, the third initialization signal line Vref3, and the first terminal S1 or the second terminal D1 of the drive module 110, for initializing the first terminal S1 or the second terminal D1 of the drive module 110. The pixel circuit is initialized; it also includes a first light-emitting control module 140 and a second light-emitting control module 150, the light-emitting control terminals of the first light-emitting control module 140 and the second light-emitting control module 150 are both connected to the light-emitting control signal line EM; the pixel circuit also includes a data writing module 160, the write control terminal of the data writing module 160 is connected to the write control signal line SP1; the pixel circuit also includes a compensation module 170, the control terminal of the compensation module 170 is connected to the compensation control signal line SN2; the first initialization unit 121 and the compensation module 170 respectively include oxide transistors, and the data writing module 160, the driving module 110, the first light-emitting control module 140, the second light-emitting control module 150, the second initialization unit 122 and the third initialization unit 123 include low-temperature polysilicon transistors.
[0119] Continue to refer to Figures 5-13 Optionally, the overall extension direction of the first sub-initialization signal line, the first control signal line SN1, the second control signal line SP2, the third control signal line SP3, the write control signal line SP1, the compensation control signal line SN2, and the light emission control signal line EM is the first direction x; the first control signal line SN1, the write control signal line SP1, the compensation control signal line SN2, the light emission control signal line EM, and the second control signal line SP2 connected to the same pixel circuit are arranged sequentially along the second direction y.
[0120] Based on the above technical solution, optionally, the first sub-initialization signal line (denoted as Vref11) of the first initialization signal line Vref1 is multiplexed into a shielding structure 130, and the orthographic projection of the shielding structure 130 on the substrate overlaps with the orthographic projection of the second control signal line SP2 on the substrate; the second control signal line SP2 is located in the metal layer of the shielding structure 130 near the substrate, and the first sub-initialization signal line (denoted as Vref21) of the second initialization signal line Vref2 and the first sub-initialization signal line (denoted as Vref31) of the third initialization signal line Vref3 are located in the metal layer of the shielding structure 130 away from the second control signal line SP2; with this configuration, it can be ensured that the shielding structure 130 can shield the interference of the potential change on the second control signal line SP2 on the first sub-initialization signal line of the second initialization signal line Vref2 and the first sub-initialization signal line of the third initialization signal line Vref3.
[0121] In some optional embodiments of the present invention, the orthographic projection of the first sub-initialization signal line Vref21 of the second initialization signal line Vref2 onto the substrate overlaps with the orthographic projection of the shielding structure 130 onto the substrate; along the second direction y, the first sub-initialization signal line Vref31 of the third initialization signal line Vref3 is located between the compensation control signal line SN2 and the first sub-initialization signal line Vref11 of the first initialization signal line Vref1, so that the shielding structure 130 can more effectively shield the signal interference on the second initialization signal line Vref2 caused by the potential change on the second control signal line SP2.
[0122] In other optional embodiments of the present invention, the orthographic projection of the first sub-initialization signal line of the third initialization signal line Vref3 onto the substrate overlaps with the orthographic projection of the shielding structure 130 onto the substrate; along the second direction y, the first sub-initialization signal line of the second initialization signal line Vref2 is located between the first sub-initialization signal line of the compensation control signal line SN2 and the first initialization signal line Vref1, so that the shielding structure 130 can better shield the signal interference on the third initialization signal line Vref3 caused by the potential change on the second control signal line SP2.
[0123] Continue to refer to Figures 6-12 Optionally, the second control signal line SP2, the third control signal line SP3, the write control signal line SP1, and the light emission control signal line are located in the first metal layer M1.
[0124] Continue to refer to Figures 6-12Optionally, the first control signal line SN1 and the compensation control signal line SN2 are located in the second metal layer M2 and / or the third metal layer M3. In this embodiment, it is schematically shown that the first control signal line SN1 and the compensation control signal line SN2 are respectively located in the second metal layer M2 and the third metal layer M3. The first control signal line SN1 in the second metal layer M2 and the third metal layer M3 that transmit the same signal can be connected by vias, and the compensation control signal line SN2 in the second metal layer M2 and the third metal layer M3 that transmit the same signal can be connected by vias to reduce the signal transmission resistance.
[0125] Continue to refer to Figures 6-12 Optionally, the first sub-initialization signal line of the first initialization signal line Vref1 is located in the second metal layer M2 or the third metal layer M3; the first sub-initialization signal line Vref21 of the second initialization signal line Vref2 and the first sub-initialization signal line Vref31 of the third initialization signal line Vref3 are located in the fourth metal layer M4.
[0126] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.
Claims
1. A pixel circuit, characterized in that, include: Driver module and initialization module; The driving module includes a driving control terminal, a first terminal, and a second terminal, and is used to generate a driving current between the first terminal and the second terminal according to the voltage of the driving control terminal, and drive the light-emitting module according to the driving current. The pixel circuit also includes a shielding structure, which is used to shield the control signal on at least one control signal line from interfering with the initialization signal on at least one initialization signal line. The initialization module includes a first initialization unit, which is electrically connected to a first control signal line and a first initialization signal line, and is used to initialize the drive control terminal. The initialization module further includes a second initialization unit, which is electrically connected to the second control signal line, the second initialization signal line, and the light-emitting module, respectively, and is used to initialize the light-emitting module. And / or, the initialization module includes a third initialization unit, which is electrically connected to a third control signal line, a third initialization signal line, and a first or second terminal of the drive module, respectively, for initializing the first or second terminal of the drive module; At least a portion of the first initialization signal line is multiplexed as the shielding structure, or at least a portion of the third initialization signal line is multiplexed as the shielding structure; The frequency of the first control signal on the first control signal line is less than the frequency of the second control signal on the second control signal line, and less than the frequency of the third control signal on the third control signal line.
2. The pixel circuit according to claim 1, characterized in that, The pixel circuit is formed on the substrate; the shielding structure is located between the film layer containing at least one of the initialization signal lines and the film layer containing at least one of the control signal lines, and the orthographic projection of the shielding structure on the substrate at least partially overlaps with the orthographic projection of the at least one of the control signal lines on the substrate.
3. The pixel circuit according to claim 2, characterized in that, The control signal line includes a main body extending along a first direction, and the orthographic projection of the shielding structure on the substrate covers the orthographic projection of the main body of at least one of the control signal lines on the substrate.
4. The pixel circuit according to claim 3, characterized in that, The control signal line also includes a branch connected to the main body, the branch extending along a second direction that intersects with the first direction; the orthographic projection of the shielding structure on the substrate covers the orthographic projection of at least one branch of the control signal line on the substrate.
5. The pixel circuit according to claim 4, characterized in that, The distance between the orthographic projection of the shielding structure on the substrate and the corresponding edge of the orthographic projection of the covered main body on the substrate is greater than or equal to 0.
6. The pixel circuit according to claim 5, characterized in that, The distance between the orthographic projection of the shielding structure on the substrate and the corresponding edge of the orthographic projection of the covered main body on the substrate is less than or equal to 3 micrometers.
7. The pixel circuit according to claim 2, characterized in that, At least one of the initialization signal lines has an orthographic projection on the substrate that overlaps with the orthographic projection of the shielding structure on the substrate.
8. The pixel circuit according to claim 1, characterized in that, The frequency of the second control signal is equal to the frequency of the third control signal.
9. The pixel circuit according to claim 8, characterized in that, The second control signal line is multiplexed into the third control signal line.
10. The pixel circuit according to claim 1, characterized in that, The driving module and the light-emitting module are connected in series between the first power line and the second power line; wherein, the driving current generated by the driving module is related to the first power supply voltage on the first power line, and the light-emitting module is electrically connected to the second power line. At least a portion of the first power line or at least a portion of the second power line is reused as the shielding structure.
11. The pixel circuit according to claim 10, characterized in that, The pixel circuit further includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the light-emitting module. The first light-emitting control module and the second light-emitting control module are respectively used to turn on or off according to the light-emitting control signal.
12. The pixel circuit according to any one of claims 1-11, characterized in that, It also includes a data writing module, which is used to write data voltage to the drive control terminal.
13. The pixel circuit according to claim 12, characterized in that, The pixel circuit also includes a compensation module, which is connected between the second end of the driving module and the driving control end, and is used to compensate the threshold voltage of the driving module.
14. The pixel circuit according to claim 13, characterized in that, The compensation module includes a first oxide transistor.
15. The pixel circuit according to claim 14, characterized in that, The initialization module includes a first initialization unit, which is connected to the drive control terminal through the compensation module.
16. The pixel circuit according to claim 15, characterized in that, The first initialization unit includes a second oxide transistor.
17. The pixel circuit according to claim 12, characterized in that, The frequency of the light emission control signal is higher than the frequency at which the data writing module writes the data voltage to the drive control terminal.
18. A display panel, characterized in that, Includes the pixel circuit according to any one of claims 1-17.
19. The display panel according to claim 18, characterized in that, It also includes the initialization signal line and the control signal line; the pixel circuit includes a first type of transistor and a second type of transistor; The display panel further includes a substrate and a first active layer, a second active layer and a multilayer metal layer stacked on one side of the substrate. The first active layer is an active layer of a first type of transistor, the second active layer is an active layer of a second type of transistor, and the second active layer is located on the side of the first active layer away from the substrate. At least one of the metal layers includes the gate of the first type transistor, at least one of the metal layers includes the gate of the second type transistor, and at least one of the metal layers includes the source and drain of the first type transistor and / or the second type transistor; at least a portion of at least one of the control signal lines is on the same layer as the gate of the first type transistor.
20. The display panel according to claim 19, characterized in that, The shielding structure is either in the same layer as the gate of the second type of transistor or located in the metal layer on the side of the metal layer containing the gate of the second type of transistor that is away from the substrate.
21. The display panel according to claim 19, characterized in that, At least a portion of at least one of the control signal lines is on the same layer as the gate of the second type of transistor.
22. The display panel according to claim 19, characterized in that, At least a portion of at least one of the initialization signal lines is on the same layer as the source and drain.
23. The display panel according to claim 19, characterized in that, The multilayer metal layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked from one side of the substrate; at least one of the control signal lines is located in the first metal layer, the shielding structure is located in the second metal layer or the third metal layer, and at least a portion of at least one of the initialization signal lines is located in the fourth metal layer.
24. The display panel according to claim 23, characterized in that, The gate of the first type of transistor is located in the first metal layer.
25. The display panel according to claim 23, characterized in that, The gate of the second type of transistor is located in the second metal layer and / or the third metal layer.
26. The display panel according to claim 23, characterized in that, The first active layer, the first metal layer, the second metal layer, the second active layer, the third metal layer, and the fourth metal layer are stacked sequentially from one side of the substrate.
27. The display panel according to claim 23, characterized in that, The pixel circuit also includes a storage capacitor, and the second metal layer includes one electrode of the storage capacitor.
28. The display panel according to claim 23, characterized in that, The initialization signal lines are in a grid pattern.
29. The display panel according to claim 28, characterized in that, The initialization signal line includes a first sub-initialization signal line and a second sub-initialization signal line. The extension directions of the first sub-initialization signal line and the second sub-initialization signal line intersect, and the first sub-initialization signal line and the second sub-initialization signal line are electrically connected.
30. The display panel according to claim 29, characterized in that, The display panel further includes a fifth metal layer located on the side of the fourth metal layer away from the substrate, the first sub-initialization signal line being located in at least one of the second metal layer, the third metal layer, and the fourth metal layer, and the second sub-initialization signal line being located in the fifth metal layer.
31. The display panel according to claim 30, characterized in that, The first type of transistor includes a low-temperature polycrystalline silicon transistor, and the second type of transistor includes an oxide transistor.
32. The display panel according to claim 31, characterized in that, The initialization module includes a first initialization unit, which is electrically connected to a first control signal line and a first initialization signal line, respectively, and is used to initialize the drive control terminal; the initialization module further includes a second initialization unit and / or a third initialization unit, wherein the second initialization unit is electrically connected to a second control signal line, a second initialization signal line, and the light-emitting module, respectively, and is used to initialize the light-emitting module; the third initialization unit is electrically connected to a third control signal line, a third initialization signal line, and a first terminal or a second terminal of the drive module, respectively, and is used to initialize the first terminal or the second terminal of the drive module; The pixel circuit also includes a first light-emitting control module and a second light-emitting control module, wherein the light-emitting control terminals of the first light-emitting control module and the second light-emitting control module are both connected to the light-emitting control signal line. The pixel circuit also includes a data writing module, and the write control terminal of the data writing module is connected to the write control signal line; The pixel circuit further includes a compensation module, the control terminal of which is connected to a compensation control signal line; the first initialization unit and the compensation module each include the oxide transistor, and the data writing module, the driving module, the first light emission control module, the second light emission control module, the second initialization unit, and the third initialization unit each include a low-temperature polysilicon transistor.
33. The display panel according to claim 32, characterized in that, The overall extension direction of the first sub-initialization signal line, the first control signal line, the second control signal line, the third control signal line, the write control signal line, the compensation control signal line, and the light emission control signal line is the first direction; the first control signal line, the write control signal line, the compensation control signal line, the light emission control signal line, and the second control signal line connected to the same pixel circuit are arranged sequentially along the second direction.
34. The display panel according to claim 33, characterized in that, The first sub-initialization signal line of the first initialization signal line is multiplexed as the shielding structure, and the orthographic projection of the shielding structure on the substrate overlaps with the orthographic projection of the second control signal line on the substrate; the second control signal line is located in the metal layer of the shielding structure near the substrate, and the first sub-initialization signal line of the second initialization signal line and the first sub-initialization signal line of the third initialization signal line are located in the metal layer of the shielding structure away from the second control signal line.
35. The display panel according to claim 34, characterized in that, The second control signal line is multiplexed into the third control signal line.
36. The display panel according to claim 35, characterized in that, The first sub-initialization signal line of the second initialization signal line overlaps with the orthographic projection of the shielding structure on the substrate in the second initialization signal line; along the second direction, the first sub-initialization signal line of the third initialization signal line is located between the compensation control signal line and the first sub-initialization signal line of the first initialization signal line; or, the first sub-initialization signal line of the third initialization signal line overlaps with the orthographic projection of the shielding structure on the substrate in the second initialization signal line; along the second direction, the first sub-initialization signal line of the second initialization signal line is located between the compensation control signal line and the first sub-initialization signal line of the first initialization signal line.
37. The display panel according to claim 32, characterized in that, The second control signal line, the third control signal line, the write control signal line, and the light emission control signal line are located in the first metal layer.
38. The display panel according to claim 32, characterized in that, The first control signal line and the compensation control signal line are located in the second metal layer and / or the third metal layer; The first sub-initialization signal line of the first initialization signal line is located in the second metal layer or the third metal layer; the first sub-initialization signal line of the second initialization signal line and the first sub-initialization signal line of the third initialization signal line are located in the fourth metal layer.