Driving circuit and display device

Abstract

The application provides a driving circuit and a display device. The driving circuit comprises a plurality of sampling driving units, and each sampling driving unit comprises a trigger control end, a scan input end and a scan output end. In the first K sampling driving units, each sampling driving unit further comprises a trigger input end, the trigger control end is connected with a selection signal, and the trigger input end is connected with a collection start signal, and is used for outputting a collection scan signal of the first K rows when the selection signal is a collection effective level. The other collection driving units are connected with the first K sampling driving units in cascade, and the collection scan signal output by the mth collection driving unit is used as a trigger signal of the (m+K)th collection driving unit. In the pixel voltage collection stage of the display panel, the driving circuit sequentially outputs the collection scan signal row by row, and the selection signal is configured as the collection effective level in the non-display area of each frame of image signal of the display panel. The driving circuit can reduce the number of timing chips and the process cost.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and display device. Background Technology

[0002] With the development of display technology, display devices are being used more and more widely, and the requirements for display devices are becoming increasingly stringent. Among them, liquid crystal displays (LCDs) have the characteristics of small size, low power consumption, no radiation, and relatively low manufacturing cost, and occupy a dominant position in the display market.

[0003] Typically, in liquid crystal display devices, the impedance of the data lines themselves and the coupling capacitance with other traces can easily cause charging delays in the liquid crystal cells, leading to color shift issues on the panel. Therefore, it is necessary to collect pixel voltage data to adjust the voltage of subsequent pixels based on the collected pixel voltage data.

[0004] However, in order to collect pixel voltage, timing chips required for collecting pixel voltage need to be added to the bonding area of ​​the display panel, which increases the number of chips and the process cost. Summary of the Invention

[0005] This application provides a driving circuit and a display device, which aims to solve the problem in the prior art that in order to collect pixel voltage, it is necessary to add timing chips required for collecting pixel voltage, thereby increasing the number of chips and process costs in the bonding area of ​​the display panel.

[0006] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a driving circuit. The driving circuit includes a trigger control terminal, a scan input terminal, and a scan output terminal. The trigger control terminal is connected to a trigger signal, and the scan input terminal is connected to a corresponding scan clock signal. The sampling driving unit is configured to turn on when the trigger signal is at an active level, so as to output the scan clock signal as a corresponding row acquisition scan signal at the scan output terminal.

[0007] In the first K sampling driving units, each sampling driving unit further includes a trigger input terminal. The trigger control terminal is connected to a strobe signal, and the trigger input terminal is connected to a sampling start signal. When the strobe signal is at a valid sampling level, the first K rows of sampling scan signals are output at the scan output terminal respectively; where K is an integer greater than 0.

[0008] The other sampling driving units are cascaded with the first K sampling driving units respectively, and the acquisition scan signal output by the m-th sampling driving unit is used as the trigger signal of the (m+K)-th sampling driving unit, so that the multiple sampling driving units output the acquisition scan signal sequentially row by row; where m is a positive integer less than M, and M is the number of sampling driving units;

[0009] The driving circuit is used for the display panel, which includes a plurality of sub-pixel units, at least some of which include voltage acquisition units. During the pixel voltage acquisition phase of the display panel, the driving circuit outputs the acquisition scanning signal line by line to drive the voltage acquisition module to turn on line by line. The strobe signal is configured to the acquisition effective level in the cancellation area of ​​each frame image signal of the display panel.

[0010] Each of the sampling driving units includes a trigger unit, an output unit, and a pull-down unit; the number of scan clock signals is 2K, and in the first K sampling driving units,

[0011] Each trigger unit includes a first transistor, the gate of which serves as the trigger control terminal and the source of which serves as the trigger input terminal;

[0012] Each output unit includes a second transistor and a bootstrap capacitor. The gate of the second transistor is electrically connected to the drain of the first transistor, the source serves as the scan input terminal, and the drain serves as the scan output terminal. The two ends of the bootstrap capacitor are electrically connected to the gate and drain of the second transistor, respectively.

[0013] Each pull-down unit includes a third transistor and a fourth transistor. The source of the third transistor and the source of the fourth transistor are electrically connected to the gate and drain of the second transistor, respectively. The drain of the third transistor and the drain of the fourth transistor are connected to a low-level signal. The gate of the third transistor and the gate of the fourth transistor are connected to the acquisition scan signal output by the next-level sampling drive unit.

[0014] In each of the sampling driving units after the Kth sampling driving unit, each trigger unit includes a fifth transistor, the gate and source of the fifth transistor are connected and serve as the trigger control terminal, and the drain of the fifth transistor is electrically connected to the scan control terminal of the output unit.

[0015] To address the aforementioned technical problems, the second technical solution provided in this application is: to provide a display device. The display device includes:

[0016] The display panel includes multiple data lines, multiple image scan lines, multiple acquisition scan lines, and multiple sub-pixel units arranged in a matrix. Each sub-pixel unit includes a driving unit and a liquid crystal unit, with a connection node between the driving unit and the liquid crystal unit. At least some of the sub-pixel units also include a voltage acquisition unit. The first connection terminal of the voltage acquisition unit is electrically connected to the connection node, the control terminal of the voltage acquisition unit is electrically connected to the acquisition scan line of the corresponding row, and the second connection terminal of the voltage acquisition unit serves as a pixel voltage acquisition terminal.

[0017] The driving circuit is as described in the above technical solution. Multiple scanning output terminals of the driving circuit are connected to the acquisition scanning lines to sequentially output acquisition scanning signals to multiple acquisition scanning lines in the anonymization area of ​​each frame image signal, so that the voltage acquisition unit is sequentially turned on and outputs the corresponding pixel voltage at the pixel voltage acquisition terminal.

[0018] The driving circuit also serves as a gate driving module, transmitting image scanning signals to multiple sub-pixel units.

[0019] The first K sampling driving units of the driving circuit further include a first gating switch, which includes a first gating control terminal, a first access terminal, a second access terminal, and a first output terminal; the first gating control terminal serves as a trigger control terminal to receive the gating signal, the first access terminal serves as a first trigger input terminal to receive the frame start signal, and the second access terminal serves as a second trigger input terminal to receive the acquisition start signal.

[0020] Each sampling drive unit further includes a second gating switch and a third gating switch; the second gating switch includes a second gating control terminal, a scan receiving terminal, a first scan output terminal, and a second scan output terminal; the second gating control terminal is connected to the gating signal, the scan receiving terminal is connected to the scan output terminal, the first scan output terminal is connected to the corresponding image scan line, the second scan output terminal is connected to the corresponding acquisition scan line, and the first scan output terminal and the second scan output terminal are connected to the trigger control terminal of the next-level sampling drive unit;

[0021] The third gating switch includes a third gating control terminal, a first pull-down terminal, a second pull-down terminal, and a pull-down access terminal. The third gating control terminal is connected to the gating signal, the first pull-down terminal is connected to the image scanning signal output by the next-level driving unit, the second pull-down terminal is connected to the acquisition scanning signal output by the next-level sampling driving unit, and the pull-down access terminal is connected to the pull-down unit.

[0022] The strobe signal is configured to be high in the display area of ​​each frame of image signal and low in the cancellation area;

[0023] When the gating signal is high, the first gating switch connects the first input terminal and the first output terminal, and the second gating switch connects the scan receiving terminal and the first scan output terminal, so that the sampling driving units at each level output the image scan signal sequentially line by line; the third gating switch connects the first pull-down terminal and the pull-down input terminal, so that the image scan signal output by the current sampling driving unit is turned off when the next level sampling driving unit outputs the image scan signal.

[0024] When the strobe signal is low, the first strobe switch connects the second access terminal and the first output terminal, and the second strobe switch connects the scan receiving terminal and the second scan output terminal, so that the sampling driving units at each level output the acquisition scan signal sequentially line by line; the third strobe switch connects the second pull-down terminal and the pull-down access terminal, so that the acquisition scan signal output by the current sampling driving unit is turned off when the next level sampling driving unit outputs the acquisition scan signal.

[0025] The first selection switch includes a sixth transistor and a seventh transistor, wherein the sixth transistor is an N-type transistor and the seventh transistor is a P-type transistor; the gate of the sixth transistor is connected to the first selection control terminal, the source is connected to the first access terminal, and the drain is connected to the first output terminal; the gate of the seventh transistor is connected to the first selection control terminal, the source is connected to the second access terminal, and the drain is connected to the first output terminal.

[0026] The second selection switch includes an eighth transistor and a ninth transistor, wherein the eighth transistor is an N-type transistor and the ninth transistor is a P-type transistor; the gate of the eighth transistor is connected to the second selection control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the first scan output terminal; the gate of the ninth transistor is connected to the second selection control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the second scan output terminal.

[0027] The third gating switch includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is an N-type transistor, and the second pull-down transistor is a P-type transistor. The gate of the first pull-down transistor is connected to the third gating control terminal, the source is connected to the first pull-down terminal, and the drain is connected to the pull-down access terminal. The gate of the second pull-down transistor is connected to the third gating control terminal, the source is connected to the second pull-down terminal, and the drain is connected to the pull-down access terminal.

[0028] When the strobe signal is high, the sixth transistor, the eighth transistor, and the first pull-down transistor are turned on, and the driving circuit serves as the gate driving module, used to sequentially output the image scanning signal to multiple sub-pixel units in the display area of ​​each frame image signal line by line.

[0029] When the strobe signal is low, the seventh transistor, the ninth transistor, and the second pull-down transistor are turned on, and the driving circuit, as a data acquisition driving module, is used to sequentially output the data acquisition scanning signal to multiple sub-pixel units in the annulment region of each frame of image signal, line by line.

[0030] In the driving circuit, K equals 1; the driving circuit is located on one side of the display panel and is used to output the image scanning signal and / or the acquisition scanning signal to the display panel.

[0031] In the driving circuit, K equals 2;

[0032] The first sampling driving unit and the sampling driving units cascaded thereafter are disposed on the first side of the display panel, and the second sampling driving unit and the sampling driving units cascaded thereafter are disposed on the second side of the display panel, with the first side and the second side opposite to each other;

[0033] The first sampling driving unit and the subsequent cascaded sampling driving units are used to output the image scanning signal and / or the acquisition scanning signal for odd-numbered rows, and the second sampling driving unit and the subsequent cascaded sampling driving units are used to output the image scanning signal and / or the acquisition scanning signal for even-numbered rows.

[0034] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a driving circuit, i.e., a display device, comprising multiple sampling driving units. Each of the first K sampling driving units includes a trigger control terminal, a trigger input terminal, a scan input terminal, and a scan output terminal. The trigger control terminal is connected to a strobe signal, the trigger input terminal is connected to a data acquisition start signal, and the scan input terminal is connected to a corresponding scan clock signal. This ensures that when the strobe signal is at a valid acquisition level, the first K sampling driving units output the first K rows of acquisition scan signals at their respective scan output terminals. Simultaneously, by cascading the subsequent K-th sampling driving units with the first K sampling driving units, each subsequent sampling driving unit includes a trigger control terminal, a scan input terminal, and a scan output terminal. The trigger control terminal is connected to a trigger signal, the scan input terminal is connected to a corresponding scan clock signal, and the acquisition scan signal output by the m-th sampling driving unit serves as the trigger signal for the (m+K)-th sampling driving unit. This enables multiple sampling driving units to sequentially output acquisition scan signals line by line, thereby achieving the timing scan signal required for acquiring pixel voltages. Furthermore, by configuring the gating signal to an effective acquisition level in the anonymization zone of each frame of the image signal on the display panel, the driving circuit outputs acquisition scan signals line by line in the anonymization zone of each frame of the image signal. This allows the voltage acquisition module to be turned on line by line during the anonymization zone period, thereby achieving pixel voltage acquisition. By having the driving circuit output acquisition scan signals during the anonymization zone period of each frame of the image signal, the image display on the display panel will not be affected. At the same time, by making the structure of the driving circuit similar to that of the gate driving module, and by ensuring that the timing of its required acquisition start signal is the same as that of the reset signal required by the sub-pixel unit of the display panel, and that the required gating signal and scan clock signal are the same as those of the gate driving module, the driving circuit can be fabricated together with the gate driving module without the need for additional design and fabrication of acquisition timing chips. This effectively reduces the number of chips and the process cost in the bonding area of ​​the display panel. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of the display device provided in the first embodiment of this application;

[0037] Figure 2 yes Figure 1 A schematic diagram of the driving circuit provided in the embodiment;

[0038] Figure 3 yes Figure 2 The timing diagram of the driving circuit provided in the embodiment;

[0039] Figure 4 This is a schematic diagram of the structure of the display device provided in the second embodiment of this application;

[0040] Figure 5 yes Figure 4 A schematic diagram of the driving circuit provided in the embodiment;

[0041] Figure 6 yes Figure 5 The timing diagram of the driving circuit provided in the embodiment;

[0042] Figure 7 This is a schematic diagram of the drive circuit provided in the third embodiment of this application;

[0043] Figure 8 This is a schematic diagram of the structure of the display device provided in the fourth embodiment of this application;

[0044] Figure 9 yes Figure 8 A schematic diagram of one embodiment of the driving circuit;

[0045] Figure 10 yes Figure 8 A schematic diagram of another embodiment of the drive circuit;

[0046] Figure 11 This is a schematic diagram of the structure of the display device provided in the fifth embodiment of this application;

[0047] Figure 12 yes Figure 10 A schematic diagram of the driving circuit provided in the embodiment.

[0048] Figure label:

[0049] 100 - Display device; 10 - Display panel; 11 - Sub-pixel unit; 20 - Data driving module; 30 - Timing control module; 40 - Gate driving module; 41 - First gate driving module; 42 - Second gate driving module; 50 - Driving circuit; 501 - First driving circuit; 502 - Second driving circuit; 51 - Sampling driving unit; 511 - Trigger unit; 512 - Output unit; 513 - Pull-down unit; 514 - First gating switch; 515 - Second gating switch; 516 - Third gating switch;

[0050] Q1 - Drive transistor; M1 - Switch transistor; T1 - First transistor; T2 - Second transistor; T3 - Third transistor; T4 - Fourth transistor; T5 - Fifth transistor; T6 - Sixth transistor; T7 - ​​Seventh transistor; T8 - Eighth transistor; T9 - Ninth transistor; T11 - First pull-down transistor; T12 - Second pull-down transistor; C - Bootstrap capacitor; Q(1)~Q(M) - Scan control signal; S(1)~S(M) - Image scan line; G(1)~G(M) - Image scan signal; Em(1)~Em(M) - Acquisition scan signal; E(1)~E(M) - Acquisition scan signal; ABK - Strobe signal; STV - Frame start signal; RESET - Acquisition start signal; EK, EK(1)~EK(2K) - Scan clock signal; VSS - Low level signal. Detailed Implementation

[0051] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0052] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0054] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0055] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0057] Please see Figure 1 This is a schematic diagram of the structure of the display device provided in the first embodiment of this application. In this embodiment, a display device 100 is provided, which includes a display panel 10, a gate driving module 40, a driving circuit 50, a data driving module 20, and a timing control module 30. The gate driving module 40 and the driving circuit 50 are respectively disposed on opposite sides of the display panel 10.

[0058] The display panel 10 includes multiple image scan lines S(1) to S(M), multiple acquisition scan lines Em(1) to Em(M), multiple data lines, and multiple sub-pixel units 11 arranged in a matrix. The multiple image scan lines S(1) to S(M) extend along a first direction and are spaced apart along a second direction, used to transmit image scan signals G(1) to G(M) to the sub-pixel units 11. The acquisition scan lines Em(1) to Em(M) are spaced apart from and insulated from the image scan lines S(1) to S(M). The multiple acquisition scan lines Em(1) to Em(M) extend along the first direction and are spaced apart along the second direction, used to transmit acquisition scan signals E(1) to E(M) to the sub-pixel units 11. The multiple data lines extend along the second direction and are spaced apart along the first direction. The image scan lines S(1) to S(M) form a grid, defining the area of ​​sub-pixel units 11. Each grid area is provided with one sub-pixel unit 11. Data lines are used to transmit data signals to the sub-pixel units 11. The first direction is perpendicular to the second direction. In this embodiment, the row direction of the matrix formed by the sub-pixel units 11 is defined as the first direction, and the column direction of the matrix is ​​defined as the second direction, in order to illustrate the embodiment of this application. In other embodiments, the first direction and the second direction can also be defined according to the arrangement design of the sub-pixel units 11.

[0059] Each sub-pixel unit 11 includes a driving unit and a liquid crystal unit. The driving unit includes a driving transistor Q1, whose gate is electrically connected to the corresponding image scan line G(i), its source is electrically connected to a data line, and its drain is electrically connected to the liquid crystal unit, specifically to the pixel electrode of the liquid crystal unit. The liquid crystal unit includes a pixel electrode, a common electrode of the liquid crystal layer, and a color filter layer (not shown). The pixel electrode, the liquid crystal layer, and the common electrode form a liquid crystal capacitor, used to drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby controlling the amount of light transmitted. The color filter layer is used to filter the light into colored light of the corresponding color. A connection node N1 is provided between the driving unit and the liquid crystal unit.

[0060] At least some sub-pixel units 11 also include voltage acquisition units. The control terminal of the voltage acquisition unit is electrically connected to the corresponding acquisition scan line Em(i), the first connection terminal is electrically connected to the connection node N1, and the second connection terminal, as a pixel voltage acquisition terminal, is electrically connected to the data driving module 20. This allows the acquisition scan signals E(1) to E(M) to be transmitted through the acquisition scan lines Em(1) to Em(M) to control the voltage acquisition unit to conduct, thereby realizing the acquisition of the pixel voltage at the connection node N1 of the sub-pixel unit 11. Specifically, the voltage acquisition unit includes a switching transistor M1. The gate of the switching transistor M1 is electrically connected to the corresponding acquisition scan line Em(i) as the control terminal, the source is electrically connected to the connection node N1 as the first connection terminal, and the drain is electrically connected to the data driving module 20 as the second connection terminal.

[0061] The gate driving module 40 includes multiple scanning signal terminals (not shown in the figure), which are electrically connected to multiple image scanning lines S(1) to S(M). During the display area stage of each frame of image signal, the gate driving module 40 is used to output image scanning signals G(1) to G(M) sequentially line by line at the multiple scanning signal terminals, so that the driving transistor Q1 of the sub-pixel unit 11 is turned on sequentially line by line, so that the data voltage transmitted by the data line can be applied to the liquid crystal unit, thereby displaying the image.

[0062] The driving circuit 50 includes multiple scanning output terminals (not shown in the figure), which are electrically connected to multiple acquisition scan lines Em(1) to Em(M). During the cancellation phase of each frame of image signal, the driving circuit 50 sequentially outputs acquisition scan signals E(1) to E(M) at the multiple scanning output terminals, so that the voltage acquisition units in the sub-pixel unit 11 are sequentially turned on line by line, so that the pixel voltage of the sub-pixel unit 11 is transmitted to the pixel voltage acquisition terminal through the voltage acquisition unit, thereby realizing the acquisition of pixel voltage. For details, please refer to the following description of the specific structure of the driving circuit 50.

[0063] Please see Figure 2 , Figure 2 yes Figure 1A schematic diagram of the driving circuit provided in the embodiment. In this embodiment, a driving circuit 50 is provided, which is used to transmit acquisition scanning signals E(1) to E(M) to the acquisition scanning lines Em(1) to Em(M) of the display panel 10 to realize the acquisition of pixel voltage.

[0064] Specifically, the driving circuit 50 includes multiple sampling driving units 51. Each sampling driving unit 51 includes a trigger control terminal, a scan input terminal, and a scan output terminal. The trigger control terminal is connected to a trigger signal, and the scan input terminal is connected to the corresponding scan clock signal EK(j). The sampling driving unit 51 is used to turn on when the trigger signal is at an effective level, so as to output the scan clock signal EK(j) as the acquisition scan signal E(i) of the corresponding row at the scan output terminal.

[0065] The first sampling driving unit 51 also includes a trigger input terminal, and the trigger control terminal of the first sampling driving unit is connected to the strobe signal ABK, the trigger input terminal is connected to the acquisition start signal RESET, and the scan input terminal is connected to the corresponding scan clock signal EK(j). The first sampling driving unit 51 is used to output the first row of acquisition scan signal E(1) at the scan output terminal when the strobe signal ABK is at the acquisition valid level.

[0066] Furthermore, the other sampling drive units 51 are cascaded with the first sampling drive unit 51 in sequence, and the acquisition scan signal E(m) output by the m-th sampling drive unit 51 is used as the trigger signal of the (m+1)-th sampling drive unit 51, so that the multiple sampling drive units 51 output acquisition scan signals E(2)~(M) sequentially row by row. Where m is a positive integer less than M, and M is the number of sampling drive units 51.

[0067] Specifically, the strobe signal ABK is used to control the conduction time of the gate driving module 40 and the conduction time of the driving circuit 50. The strobe signal ABK is configured to be a display valid level in the display area of ​​each frame of image signal and a acquisition valid level in the blank area (no-image area) of each frame of image signal. In a specific embodiment, the display valid level can be high and the acquisition valid level can be low; or, the display valid level can be low and the acquisition valid level can be high, which can be set according to the type of trigger device in the gate driving module 40 and the driving circuit 50. In this embodiment, the example of a display valid level being high and an acquisition valid level being low is used for explanation. That is, in this embodiment, the strobe signal ABK is configured to be high in the display area of ​​each frame of image signal and low in the blank area of ​​each frame of image signal, thereby illustrating the embodiment.

[0068] The example is given where the effective level is high and the effective level for acquisition is low. That is, in this embodiment, the strobe signal ABK is configured to be high in the display area of ​​each frame of image signal and low in the cancellation area of ​​each frame of image signal, and the embodiment is described in this way.

[0069] With the above settings, and controlled by the strobe signal ABK, the gate driving module 40 outputs image scanning signals G(1) to G(M) in the display area stage of each frame of image signal, and the driving circuit 50 outputs acquisition scanning signals E(1) to E(M) in the annulment area of ​​each frame of image signal. Each frame of image signal does not require an additional voltage acquisition stage, thus avoiding a reduction in the refresh rate of the display panel 10. Furthermore, by outputting acquisition scanning signals E(1) to E(M) in the annulment area to acquire pixel voltages, the image display of the display panel 10 is not affected. Simultaneously, with the above settings, the structure of the driving circuit 50 is similar to that of the gate driving module 40, and the driving circuit 50 and the gate driving module 40 can share the scan clock signal EK and the acquisition start signal RESET. The reset signal of the display panel 10 can be used as the acquisition start signal RESET. Therefore, the driving circuit 50 can be fabricated together with the gate driving module 40, eliminating the need for additional design and fabrication of acquisition timing chips, thereby effectively reducing the number of chips and process costs in the bonding area of ​​the display panel 10.

[0070] Specifically, each sampling drive unit includes a trigger unit 511, an output unit 512, and a pull-down unit 513; wherein the number of scan clock signals EK is 2. Specifically, in the first sampling drive unit 51:

[0071] The trigger unit 511 is mainly used to control the turn-on time of the output unit 512 to realize the progressive scanning of the display panel 10. Specifically, the trigger unit 511 includes a first transistor T1. The gate of the first transistor T1 is connected to the strobe signal ABK as the trigger control terminal, and the source is connected to the acquisition start signal RESET as the trigger control terminal. When the strobe signal ABK is at the acquisition valid level, the first transistor T1 is turned on to output the first line scan control signal Q(1) at the drain.

[0072] Output unit 512 is mainly used to output the corresponding first scan clock signal EK(1) as the first row acquisition scan signal E(1). Specifically, the output unit 512 includes a second transistor T2 and a bootstrap capacitor C. The gate of the second transistor T2 is electrically connected to the drain of the first transistor T1. The source is connected to the first scan clock signal EK(1) as the scan input terminal. The drain is connected to the first row acquisition scan line Em(1) as the scan output terminal, which is used to generate and output the first row acquisition scan signal E(1). The two ends of the bootstrap capacitor C are electrically connected to the gate and drain of the second transistor T2 respectively. It is used to charge when the first row scan control signal Q(1) is high level, store the voltage of the gate and drain terminals of the second transistor T2, and when the first sampling drive unit 51 outputs the first row acquisition scan signal E(1), the voltage of the gate of the second transistor T2 is raised again. That is, when the first scan clock signal EK(1) is high level, the potential of the first row scan control signal Q(1) is raised by the coupling effect of the bootstrap capacitor C, so as to ensure that the second transistor T2 can be reliably turned on and output the first row acquisition scan signal E(1).

[0073] The pull-down unit 513 is used to immediately pull down the gate and drain potentials of the second transistor T2 to a low level, that is, to turn off the first row's acquisition scan signal E(1). Specifically, the pull-down unit 513 includes a third transistor T3 and a fourth transistor T4. The source of the third transistor T3 and the source of the fourth transistor T4 are electrically connected to the gate and drain of the second transistor T2, respectively. The drains of the third transistor T3 and the fourth transistor T4 are connected to a low-level signal VSS. The gates of the third transistor T3 and the fourth transistor T4 are connected to the acquisition scan signal E(2) output by the next-level sampling drive unit 51. Among them, the third transistor T3 is used to pull down the potential of the first row's scan control signal Q(1) so as to turn off the second transistor T2; the fourth transistor T4 acts on the first row's acquisition scan line Em(1) to pull down the potential of the first row's acquisition scan signal E(1).

[0074] Each sampling driving unit 51 after the first sampling driving unit 51:

[0075] First, it should be noted that the symbol k in the following text is a positive integer greater than 0. Specifically, (k+1) represents the sequence number of the current sampling driving unit 51, k represents the sequence number of the previous sampling driving unit 51, and (k+2) represents the sequence number of the next sampling driving unit 51.

[0076] Each trigger unit 511 includes a fifth transistor T5. The gate and source of the fifth transistor T5 are connected and serve as a trigger control terminal, connected to the scan output terminal of the previous stage sampling drive unit 51. The drain of the fifth transistor T5 is electrically connected to the scan control terminal of the output unit 512. That is, the acquisition scan signal E(k) output by the previous stage sampling drive unit 51 serves as the trigger signal of this stage sampling drive unit 51. When the acquisition scan signal E(k) is high, the fifth transistor T5 is turned on to output the (k+1)th row scan control signal Q(k+1) at the drain, which is used to control the turn-on time of this stage output unit 512.

[0077] Each output unit 512 is mainly used to output the scan clock signal EK(j) corresponding to its current stage as the acquisition scan signal E(k+1) for the corresponding row. Specifically, the structure and function of each output unit 512 are similar to those of the output unit 512 of the first sampling drive unit 51. Each output unit 512 also includes a second transistor T2 and a bootstrap capacitor C. The gate of the second transistor T2 is electrically connected to the drain of the first transistor T1. The source serves as the scan input terminal connected to the scan clock signal EK(j) corresponding to its current stage. The drain serves as the scan output terminal connected to the acquisition scan line Em(k+1) of the corresponding row, used to generate and output the acquisition scan signal E(k+1) for the corresponding row. The two ends of the bootstrap capacitor C are respectively electrically connected to the second transistor T2. The gate and drain of transistor T2 are used to charge when the scan control signal Q(k+1) is high, storing the voltage at the gate and drain of the second transistor T2. When the sampling drive unit 51 outputs the scan signal E(k+1) for the current row, the voltage at the gate of the second transistor T2 is raised again. That is, when the scan clock signal EK(j) corresponding to the current stage is high, the potential of the scan control signal Q(k+1) for the current stage is raised by the coupling effect of the bootstrap capacitor C, so as to ensure that the second transistor T2 can be reliably turned on and output the scan signal E(k+1) for the current row.

[0078] Each pull-down unit 513 is used to immediately pull down the gate and drain potentials of the second transistor T2 in this stage to a low potential, i.e., to turn off the acquisition scan signal E(k+1) of the corresponding row. Specifically, similar to the pull-down unit 513 in the first sampling drive unit 51, the pull-down unit 513 in this stage also includes a third transistor T3 and a fourth transistor T4. The source of the third transistor T3 and the source of the fourth transistor T4 are electrically connected to the gate and drain of the second transistor T2, respectively. The drains of the third transistor T3 and the fourth transistor T4 are connected to a low-level signal VSS. The gates of the third transistor T3 and the fourth transistor T4 are connected to the acquisition scan signal E(k+2) output by the next-stage sampling drive unit 51. Among them, the third transistor T3 is used to pull down the scan control signal Q(k+1) of this row so as to turn off the second transistor T2; the fourth transistor T4 acts on the acquisition scan line Em(k+1) of the corresponding row to pull down the potential of the acquisition scan signal E(k+1) of this row.

[0079] Please see Figure 3 , Figure 3 yes Figure 2 The timing diagram of the driving circuit provided in the embodiment is shown. Specifically, in this embodiment, the number of scan clock signals EK is 2, and the first scan clock signal EK(1) and the second scan clock signal EK(2) are alternately output at high level.

[0080] During the display area stage, the strobe signal ABK is high. In the initial stage of this stage, the frame start signal STV is high to trigger the gate drive module 40, so that the gate drive module 40 outputs the image scan signals G(1) to G(M) sequentially line by line based on the two scan clock signals EK(1) and EK(2).

[0081] During the cancellation phase, the strobe signal ABK is low. At the beginning of this phase, the acquisition start signal RESET is high to trigger the first-level sampling drive unit 51 to output the first scan clock signal EK(1) as the first row acquisition scan signal E(1). After outputting the first row acquisition scan signal E(1), each level of the sampling drive unit 51 sequentially outputs the corresponding row acquisition scan signals E(2) to E(M). Here, M is the number of sampling drive units 51.

[0082] Please see Figure 4 , Figure 4This is a schematic diagram of the structure of the display device provided in the second embodiment of this application. In the display device 100 provided in this embodiment, the gate driving module 40 includes a first gate driving module 41 and a second gate driving module 42, which are respectively disposed on opposite sides of the display panel 10; the driving circuit 50 includes a first driving circuit 501 and a second driving circuit 502, which are respectively disposed on opposite sides of the display panel 10 and are respectively adjacent to the first gate driving module 41 and the second gate driving module 42.

[0083] The first gate driving module 41 includes multiple scan signal terminals, each electrically connected to multiple image scan lines with odd-numbered sequences, for outputting an odd-numbered row image scan signal G(2i-1). The second gate driving module 42 includes multiple scan signal terminals, each electrically connected to multiple image scan lines with even-numbered sequences, for outputting an even-numbered row image scan signal G(2i). Here, i is a positive integer greater than 0.

[0084] Please refer to the following: Figure 5 , Figure 5 yes Figure 4 A schematic diagram of the driving circuit provided in the embodiment. In the driving circuit 50, the structures of the first two sampling driving units 51, namely the first-stage sampling driving unit 51 and the second-stage sampling driving unit 51, are similar to... Figure 2 The structure of the first sampling driving unit 51 in the embodiment is similar, except that the scanning input terminal of the first-level sampling driving unit 51 in this embodiment is connected to the first scanning clock signal EK(1), and the scanning input terminal of the second-level sampling driving unit 51 is connected to the second scanning clock signal EK(2), so that the first-level sampling driving unit 51 outputs the first row acquisition scanning signal E(1), and the second-level sampling driving unit 51 outputs the second row acquisition scanning signal E(2).

[0085] Furthermore, in this embodiment, the sampling driving units 51 with odd-numbered serial numbers are cascaded to form a first driving circuit 501, used to output odd-numbered row acquisition scan signals E(2i-1); the sampling driving units 51 with even-numbered serial numbers are cascaded to form a second driving circuit 502, used to output even-numbered row acquisition scan signals E(2i). The first driving circuit 501 is disposed on the first side of the display panel 10, adjacent to the first gate driving module 41, and the second driving circuit 502 is disposed on the second side of the display panel 10, adjacent to the second gate driving module 42, with the first side and the second side opposite to each other.

[0086] Specifically, the acquisition scan signal E(m) output by the m-th level sampling drive unit 51 is used as the trigger signal of the (m+2)-th level sampling drive unit 51, and the pull-down unit 513 in this level sampling drive unit 51 is connected to the acquisition scan signal E(m+1) output by the next level sampling drive unit 51, so that when the acquisition scan signal E(m+1) output by the next level sampling drive unit 51 is high, the acquisition scan signal E(m) of this level is immediately turned off.

[0087] Please see Figure 6 , Figure 6 yes Figure 5 The timing diagram of the driving circuit provided in the embodiment is shown. Specifically, in this embodiment, the number of scan clock signals EK is 4, and the first scan clock signal EK(1), the second scan clock signal EK(2), the third scan clock signal EK(3) and the fourth clock signal EK(4) are output at high level in sequence.

[0088] During the display area stage, the strobe signal ABK is high. In the initial stage of this stage, the frame start signal STV is high to trigger the gate drive module 40, so that the gate drive module 40 outputs the image scan signals G(1) to G(M) sequentially line by line based on the four scan clock signals EK(1) to EK(4).

[0089] During the cancellation phase, the strobe signal ABK is low. In the initial phase of this phase, the acquisition start signal RESET is high. During the phase when the acquisition start signal RESET is high, the first-level sampling drive unit 51 and the second-level sampling drive unit 51 sequentially output the high level of the first row acquisition scan signal E(1) and the high level of the second row acquisition scan signal E(2). After outputting the first two rows of acquisition scan signals E(1) to E(2), each level of the sampling drive unit 51 sequentially outputs the corresponding row of acquisition scan signals E(3) to E(M).

[0090] Please see Figure 7 , Figure 7 This is a schematic diagram of the driving circuit provided in the third embodiment of this application. In the driving circuit 50 provided in this embodiment, the structure of the first K sampling driving units 51, i.e., the first-level sampling driving unit 51 to the Kth-level sampling driving unit 51, is similar to... Figure 2 The structure of the first sampling driving unit 51 in this embodiment is similar, except that the scanning input terminals of the first-level sampling driving unit 51 to the Kth-level sampling driving unit 51 are respectively connected to the first scanning clock signal EK(1) to the Kth scanning clock signal EK(K), so that the first K-level sampling driving units 51 sequentially output the acquired scanning signals E(1) to (K). Here, K is an integer greater than 0. Furthermore, in this embodiment, the number of scanning clock signals EK corresponds to 2K.

[0091] Furthermore, in this embodiment, the sampling driving units 51 with the sequence number (m+i·K) are cascaded sequentially to output the acquisition scan signal E(m+i·K) of the sequence number (m+i·K). Here, m is a positive integer greater than 0 and less than or equal to K, i is a natural number, and (m+i·K) is less than or equal to M.

[0092] Specifically, the acquisition scan signal E(m) output by the m-th level sampling drive unit 51 is used as the trigger signal of the (m+K)-th level sampling drive unit 51, and the pull-down unit 513 in this level sampling drive unit 51 is connected to the acquisition scan signal E(m+1) output by the next level sampling drive unit 51, so that when the acquisition scan signal E(m+1) output by the next level sampling drive unit 51 is high, the acquisition scan signal E(m) of this level is immediately turned off.

[0093] Please see Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of the structure of the display device provided in the fourth embodiment of this application. Figure 9 yes Figure 8 A schematic diagram of one embodiment of the driving circuit is shown. In this embodiment, the driving circuit 50 also serves as a gate driving module 40, transmitting image scanning signals G(1) to G(M) to the plurality of sub-pixel units 11. Typically, the gate driving module 40 and the driving circuit 50 are mainly composed of opaque materials such as metal and semiconductor. Therefore, a black light-shielding layer is usually provided to shield the gate driving module 40 and the driving circuit 50, which is why the display device 100 has a bezel. In this embodiment, by multiplexing the driving circuit 50 as the gate driving module 40, the area of ​​the bezel region is reduced, thus reducing the bezel width and length of the display device 100.

[0094] Specifically, the first K sampling driving units 51 of the driving circuit 50 further include a first gating switch 514. The first gating switch 514 includes a first gating control terminal, a first access terminal, a second access terminal, and a first output terminal. The first gating control terminal serves as a trigger control terminal and receives the gating signal ABK. The first access terminal serves as a first trigger input terminal and receives the frame start signal STV. The second access terminal serves as a second trigger input terminal and receives the acquisition start signal RESET.

[0095] Each sampling drive unit 51 further includes a second gating switch 515 and a third gating switch 516. The second gating switch 515 includes a second gating control terminal, a scan receiving terminal, a first scan output terminal, and a second scan output terminal. The second gating control terminal is connected to a gating signal ABK, the scan receiving terminal is connected to the scan output terminal, the first scan output terminal is connected to the corresponding image scan line, and the second scan output terminal is connected to the corresponding acquisition scan line. The first and second scan output terminals are also connected to the trigger control terminal of the next-level sampling drive unit 51. The third gating switch 516 includes a third gating control terminal, a first pull-down terminal, a second pull-down terminal, and a pull-down access terminal. The third gating control terminal is connected to the gating signal ABK, the first pull-down terminal is connected to the image scan signal output by the next-level sampling drive unit 51, the second pull-down terminal is connected to the acquisition scan signal output by the next-level sampling drive unit 51, and the pull-down access terminal is connected to a pull-down unit 513.

[0096] The strobe signal ABK is configured to be high in the display area of ​​each frame of image signal and low in the cancellation area.

[0097] When the strobe signal ABK is high, the first strobe switch 514 connects the first input terminal and the first output terminal, and the second strobe switch 515 connects the scan receiving terminal and the first scan output terminal, so that each stage of the sampling drive unit 51 outputs the image scan signal line by line sequentially. At the same time, the third strobe switch 516 connects the first pull-down terminal and the pull-down input terminal, so as to turn off the image scan signal output by the current stage sampling drive unit 51 when the next stage sampling drive unit 51 outputs the image scan signal.

[0098] When the strobe signal ABK is low, the first strobe switch 514 connects the second input terminal and the first output terminal, and the second strobe switch 515 connects the scan receiving terminal and the second scan output terminal, so that each level of the sampling drive unit 51 outputs the acquisition scan signals G(1) to G(M) sequentially line by line. At the same time, the third strobe switch 516 connects the second pull-down terminal and the pull-down input terminal, so as to turn off the acquisition scan signals E(1) to E(M) output by the current level sampling drive unit 51 when the next level sampling drive unit 51 outputs the acquisition scan signal.

[0099] In this embodiment, taking K=1 as an example, the driving circuit 50 is disposed on one side of the display panel 10 and is used to output image scanning signals G(1) to G(M) to the display panel 10 in the display area of ​​each frame image signal and to output acquisition scanning signals E(1) to E(M) to the display panel 10 in the cancellation area of ​​each frame image signal.

[0100] In this embodiment, the operating timing of the driving circuit 50 is consistent with... Figure 3 Same as above, please refer to the details. Figure 3The number of scan clock signals EK is 2, and the first scan clock signal EK(1) and the second scan clock signal EK(2) are alternately output at high level.

[0101] During the display area stage, the strobe signal ABK is high to control the drive circuit 50 to turn on the first access terminal and the first output terminal of the first strobe switch 514, and to turn on the scan receiving terminal and the first scan output terminal of the second strobe switch 515, so that the drive circuit 50 is connected to the image scan lines S(1) to S(M) as a gate drive unit; in the initial stage of this stage, the frame start signal STV is high to trigger the drive circuit 50 to output the image scan signals G(1) to G(M) sequentially line by line.

[0102] During the cancellation phase, the gating signal ABK is low to control the drive circuit 50 to connect the second access terminal and the first output terminal, as well as the scanning receiver terminal and the second scanning output terminal of the second gating switch 515, thereby connecting the drive circuit 50 to the acquisition scan lines Em(1) to Em(M). In the initial stage of this phase, the acquisition start signal RESET is high to trigger the sampling drive units 51 at each level to sequentially output the acquisition scan signals E(1) to E(M) for the corresponding rows. Here, M is the number of sampling drive units 51.

[0103] Please see Figure 10 , Figure 10 yes Figure 8 A schematic diagram of another embodiment of the driving circuit is shown. In this embodiment, the first selection switch 514 includes a sixth transistor T6 and a seventh transistor T7. The sixth transistor T6 is an N-type transistor, and the seventh transistor T7 is a P-type transistor. The gate of the sixth transistor T6 is connected to the first selection control terminal, the source is connected to the first access terminal, and the drain is connected to the first output terminal. The gate of the seventh transistor T7 is connected to the first selection control terminal, the source is connected to the second access terminal, and the drain is connected to the first output terminal.

[0104] The second gating switch 515 includes an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 is an N-type transistor, and the ninth transistor T9 is a P-type transistor. The gate of the eighth transistor T8 is connected to the second gating control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the first scan output terminal. The gate of the ninth transistor T9 is connected to the second gating control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the second scan output terminal.

[0105] The third selection switch 516 includes a first pull-down transistor T11 and a second pull-down transistor T12. The first pull-down transistor T11 is an N-type transistor, and the second pull-down transistor T12 is a P-type transistor. The gate of the first pull-down transistor T11 is connected to the third selection control terminal, the source is connected to the first pull-down terminal, and the drain is connected to the pull-down access terminal. The gate of the second pull-down transistor T12 is connected to the third selection control terminal, the source is connected to the second pull-down terminal, and the drain is connected to the pull-down access terminal.

[0106] Specifically, when the strobe signal ABK is high, the sixth transistor T6, the eighth transistor T8 and the first pull-down transistor T11 are turned on, and the driving circuit 50 acts as the gate driving module 40 to sequentially output image scanning signals G(1) to G(M) to multiple sub-pixel units 11 in the display area of ​​each frame image signal.

[0107] When the strobe signal ABK is low, the seventh transistor T7, the ninth transistor T9, and the second pull-down transistor T12 are turned on. The driving circuit 50 serves as the acquisition driving module, which is used to sequentially output the acquisition scanning signals E(1) to E(M) to multiple sub-pixel units 11 in the anonymization area of ​​each frame image signal.

[0108] Please see Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of the structure of the display device provided in the fifth embodiment of this application. Figure 12 yes Figure 11 A schematic diagram of the driving circuit provided in this embodiment. In this embodiment, K = 2, and... Figure 4 and Figure 5 Similarly, the driving circuit 50 includes a first driving circuit 501 and a second driving circuit 502. The difference is that in this embodiment, the first driving circuit 501 also serves as a first gate driving module 41, which is used to transmit odd-numbered row image scanning signals G(2i-1) to the display panel 10 during the display area stage of each frame image signal. The second driving circuit 502 also serves as a second gate driving module 42, which is used to transmit even-numbered row image scanning signals G(2i) to the display panel 10 during the display area stage of each frame image signal; where i is a natural number.

[0109] and Figure 8 Similarly, in the embodiment, the first two sampling driving units 51 of the driving circuit 50 also include a first gating switch 514. The first gating switch 514 includes a first gating control terminal, a first access terminal, a second access terminal, and a first output terminal. The first gating control terminal serves as a trigger control terminal and receives the gating signal ABK. The first access terminal serves as a first trigger input terminal and receives the frame start signal STV. The second access terminal serves as a second trigger input terminal and receives the acquisition start signal RESET.

[0110] Each sampling drive unit 51 further includes a second gating switch 515 and a third gating switch 516. The second gating switch 515 includes a second gating control terminal, a scan receiving terminal, a first scan output terminal, and a second scan output terminal. The second gating control terminal is connected to the gating signal ABK, the scan receiving terminal is connected to the scan output terminal, the first scan output terminal is connected to the corresponding image scan line S(m), and the second scan output terminal is connected to the corresponding acquisition scan line Em(m). The first scan output terminal and the second scan output terminal are connected to the trigger control terminal of the next-level sampling drive unit 51 to transmit the trigger signal to the next-level sampling drive unit 51 so that the drive circuit 50 outputs the image scan signals G(1)~G(M) and E(1)~E(M) line by line.

[0111] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A driving circuit comprising multiple sampling driving units, each sampling driving unit comprising a trigger control terminal, a scan input terminal, and a scan output terminal, wherein the trigger control terminal is connected to a trigger signal, and the scan input terminal is connected to a corresponding scan clock signal; the sampling driving unit is configured to turn on when the trigger signal is at an active level, so as to output the scan clock signal as a sampling scan signal for the corresponding row at the scan output terminal; Its features are, In the first K sampling driving units, each sampling driving unit further includes a trigger input terminal. The trigger control terminal is connected to a strobe signal, and the trigger input terminal is connected to a sampling start signal. When the strobe signal is at a valid sampling level, the first K rows of sampling scan signals are output at the scan output terminal respectively; where K is an integer greater than 0. The other sampling driving units are cascaded with the first K sampling driving units respectively, and the acquisition scan signal output by the m-th sampling driving unit is used as the trigger signal of the (m+K)-th sampling driving unit, so that the multiple sampling driving units output the acquisition scan signal sequentially row by row; where m is a positive integer less than M, and M is the number of sampling driving units; The driving circuit is used for the display panel, which includes a plurality of sub-pixel units, at least some of which include voltage acquisition units. During the pixel voltage acquisition phase of the display panel, the driving circuit outputs the acquisition scanning signal line by line to drive the voltage acquisition module to turn on line by line. The strobe signal is configured to the acquisition effective level in the cancellation area of ​​each frame image signal of the display panel.

2. The driving circuit according to claim 1, characterized in that, Each of the sampling driving units includes a trigger unit, an output unit, and a pull-down unit; wherein, the number of scan clock signals is 2K, and in the first K sampling driving units, Each trigger unit includes a first transistor, the gate of which serves as the trigger control terminal and the source of which serves as the trigger input terminal; Each output unit includes a second transistor and a bootstrap capacitor. The gate of the second transistor is electrically connected to the drain of the first transistor, the source serves as the scan input terminal, and the drain serves as the scan output terminal. The two ends of the bootstrap capacitor are electrically connected to the gate and drain of the second transistor, respectively. Each pull-down unit includes a third transistor and a fourth transistor. The source of the third transistor and the source of the fourth transistor are electrically connected to the gate and drain of the second transistor, respectively. The drain of the third transistor and the drain of the fourth transistor are connected to a low-level signal. The gate of the third transistor and the gate of the fourth transistor are connected to the acquisition scan signal output by the next-level sampling drive unit.

3. The driving circuit according to claim 2, characterized in that, In each of the sampling driving units following the Kth sampling driving unit Each trigger unit includes a fifth transistor, the gate and source of which are connected and serve as the trigger control terminal, and the drain of which is electrically connected to the scan control terminal of the output unit.

4. A display device, characterized in that, include: The display panel includes multiple data lines, multiple image scan lines, multiple acquisition scan lines, and multiple sub-pixel units arranged in a matrix. Each sub-pixel unit includes a driving unit and a liquid crystal unit, with a connection node between the driving unit and the liquid crystal unit. At least some of the sub-pixel units also include a voltage acquisition unit. The first connection terminal of the voltage acquisition unit is electrically connected to the connection node, the control terminal of the voltage acquisition unit is electrically connected to the acquisition scan line of the corresponding row, and the second connection terminal of the voltage acquisition unit serves as a pixel voltage acquisition terminal. The driving circuit is the driving circuit as described in any one of claims 1-3, wherein multiple scanning output terminals of the driving circuit are connected to the acquisition scanning lines respectively, so as to sequentially output acquisition scanning signals to multiple acquisition scanning lines in the anonymization area of ​​each frame image signal, so as to sequentially turn on the voltage acquisition units and output the corresponding pixel voltage at the pixel voltage acquisition terminal.

5. The display device according to claim 4, characterized in that, The driving circuit also serves as a gate driving module, transmitting image scanning signals to multiple sub-pixel units; The first K sampling driving units of the driving circuit further include a first gating switch, which includes a first gating control terminal, a first access terminal, a second access terminal, and a first output terminal; the first gating control terminal serves as a trigger control terminal to receive the gating signal, the first access terminal serves as a first trigger input terminal to receive the frame start signal, and the second access terminal serves as a second trigger input terminal to receive the acquisition start signal. Each sampling drive unit further includes a second gating switch and a third gating switch; the second gating switch includes a second gating control terminal, a scan receiving terminal, a first scan output terminal, and a second scan output terminal; the second gating control terminal is connected to the gating signal, the scan receiving terminal is connected to the scan output terminal, the first scan output terminal is connected to the corresponding image scan line, the second scan output terminal is connected to the corresponding acquisition scan line, and the first scan output terminal and the second scan output terminal are connected to the trigger control terminal of the next-level sampling drive unit; The third gating switch includes a third gating control terminal, a first pull-down terminal, a second pull-down terminal, and a pull-down access terminal. The third gating control terminal is connected to the gating signal, the first pull-down terminal is connected to the image scanning signal output by the next-level sampling driving unit, the second pull-down terminal is connected to the acquisition scanning signal output by the next-level sampling driving unit, and the pull-down access terminal is connected to the pull-down unit.

6. The display device according to claim 5, characterized in that, The strobe signal is configured to be high in the display area of ​​each frame of image signal and low in the ablation area; When the gating signal is high, the first gating switch connects the first input terminal and the first output terminal, and the second gating switch connects the scan receiving terminal and the first scan output terminal, so that the sampling driving units at each level output the image scan signal sequentially line by line; the third gating switch connects the first pull-down terminal and the pull-down input terminal, so that the image scan signal output by the current sampling driving unit is turned off when the next level sampling driving unit outputs the image scan signal. When the strobe signal is low, the first strobe switch connects the second access terminal and the first output terminal, and the second strobe switch connects the scan receiving terminal and the second scan output terminal, so that the sampling driving units at each level output the acquisition scan signal sequentially line by line; the third strobe switch connects the second pull-down terminal and the pull-down access terminal, so that the acquisition scan signal output by the current sampling driving unit is turned off when the next level sampling driving unit outputs the acquisition scan signal.

7. The display device according to claim 6, characterized in that, The first selection switch includes a sixth transistor and a seventh transistor. The sixth transistor is an N-type transistor, and the seventh transistor is a P-type transistor. The gate of the sixth transistor is connected to the first selection control terminal, the source is connected to the first access terminal, and the drain is connected to the first output terminal. The gate of the seventh transistor is connected to the first selection control terminal, the source is connected to the second access terminal, and the drain is connected to the first output terminal. The second selection switch includes an eighth transistor and a ninth transistor, wherein the eighth transistor is an N-type transistor and the ninth transistor is a P-type transistor; the gate of the eighth transistor is connected to the second selection control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the first scan output terminal; the gate of the ninth transistor is connected to the second selection control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the second scan output terminal. The third selection switch includes a first pull-down transistor and a second pull-down transistor, wherein the first pull-down transistor is an N-type transistor and the second pull-down transistor is a P-type transistor; The gate of the first pull-down transistor is connected to the third gating control terminal, the source is connected to the first pull-down terminal, and the drain is connected to the pull-down access terminal; the gate of the second pull-down transistor is connected to the third gating control terminal, the source is connected to the second pull-down terminal, and the drain is connected to the pull-down access terminal.

8. The display device according to claim 7, characterized in that, When the strobe signal is high, the sixth transistor, the eighth transistor and the first pull-down transistor are turned on, and the driving circuit, as the gate driving module, is used to sequentially output the image scanning signal to multiple sub-pixel units in the display area of ​​each frame image signal line by line. When the strobe signal is low, the seventh transistor, the ninth transistor, and the second pull-down transistor are turned on, and the driving circuit, as a data acquisition driving module, is used to sequentially output the data acquisition scanning signal to multiple sub-pixel units in the annulment region of each frame of image signal, line by line.

9. The display device according to claim 4 or 6, characterized in that, In the driving circuit, K equals 1; the driving circuit is located on one side of the display panel and is used to output the image scanning signal and / or the acquisition scanning signal to the display panel.

10. The display device according to claim 4 or 6, characterized in that, In the driving circuit, K equals 2; The first sampling driving unit and the sampling driving units cascaded thereafter are disposed on the first side of the display panel, and the second sampling driving unit and the sampling driving units cascaded thereafter are disposed on the second side of the display panel, with the first side and the second side opposite to each other; The first sampling driving unit and the subsequent cascaded sampling driving units are used to output the image scanning signal and / or the acquisition scanning signal for odd-numbered rows, and the second sampling driving unit and the subsequent cascaded sampling driving units are used to output the image scanning signal and / or the acquisition scanning signal for even-numbered rows.

Images