Silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure and manufacturing method thereof

Abstract

The present invention specifically relates to a silicon control unit and a wide bandgap semiconductor unit composite device structure and a manufacturing method thereof. The device structure includes a substrate; an epitaxial layer, the epitaxial layer is made on the substrate and the epitaxial layer is a wide bandgap semiconductor material, an electron tunneling layer is made on the upper surface of the epitaxial layer, and the epitaxial layer is divided into a voltage-resistant layer structural region and an electric field shielding structural region; a silicon material layer, the silicon material layer is made on the electron tunneling layer; a switch control unit, the switch control unit is made in the silicon material layer; a shielding region, the shielding region is made in the electric field shielding structural region of the electron tunneling layer and / or the epitaxial layer; a drain electrode, the drain electrode is made on the second surface of the substrate. The present invention provides a silicon control unit and a wide bandgap semiconductor voltage-resistant unit composite device structure, which solves the difficulties in the design, process manufacturing and special equipment requirements of wide bandgap semiconductor devices and obtains a more excellent device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor structure and manufacturing technology, and in particular to a silicon control unit and wide bandgap semiconductor unit composite device structure and a manufacturing method thereof. Background Art

[0002] Wide bandgap semiconductor materials (such as silicon carbide, gallium nitride, gallium oxide, diamond, aluminum nitride, etc.) can provide much higher pressure resistance per unit thickness than silicon, but they have various problems in the basic structure and process manufacturing of power devices. For example, silicon carbide MOSFET devices have always had gate oxide interface states and various reliability issues related to them, while it is difficult to achieve P doping through ion implantation of materials such as gallium nitride, gallium oxide, diamond, and aluminum nitride.

[0003] In order to make power devices of wide bandgap semiconductors, it is often necessary to re-explore various Schottky contacts and shielding on wide bandgap semiconductor materials, gate oxidation structures and various gate oxide post-treatments and interface state reduction experiments. The exploration and experiments of these new process methods have improved the devices, but there are still many problems. For example, the low channel mobility and threshold voltage reliability caused by the gate oxide problem of SiC MOSFET have always been a major problem restricting the production and yield of silicon carbide devices. At the same time, silicon power devices and processes are very mature, and the design, manufacture and equipment of devices are very mature. Through some new device structures and process manufacturing methods, the switch control unit in the traditional silicon power device structure is still made of silicon material, and the wide bandgap semiconductor drift region is integrated as a voltage-resistant unit to form a composite device, which is expected to solve the difficulties in the design, process manufacturing and special equipment requirements of wide bandgap semiconductor devices. Summary of the invention

[0004] Based on the above description, the present invention provides a silicon control unit and a wide bandgap semiconductor voltage-resistant unit composite device structure, which solves the difficulties in wide bandgap semiconductor device design, process manufacturing and special equipment requirements and obtains a more excellent device performance.

[0005] The technical solution of the present invention to solve the above technical problems is as follows:

[0006] The present invention provides a silicon control unit and a wide bandgap semiconductor withstand voltage unit composite device structure, the device structure comprises a substrate, the substrate comprises a first surface and a second surface opposite to each other, the direction of the second surface pointing to the first surface is a first direction;

[0007] An epitaxial layer, wherein the epitaxial layer is formed on the first surface of the substrate and is a wide bandgap semiconductor material, an electron tunneling layer is formed on the upper surface of the epitaxial layer, and the epitaxial layer is divided into a voltage-resistant layer structural region and an electric field shielding structural region along a first direction;

[0008] A silicon material layer, wherein the silicon material layer is formed on the electron tunneling layer;

[0009] A switch control unit, wherein the switch control unit is made in a silicon material layer;

[0010] A shielding region, wherein the shielding region is formed in an electric field shielding structural region of the electron tunneling layer and / or the epitaxial layer and has a doping type opposite to that of the epitaxial layer;

[0011] A drain electrode is formed on the second surface of the substrate.

[0012] Based on the above technical solution, the present invention can also be improved as follows.

[0013] Furthermore, the shielding area is manufactured in multiple layers along the first direction, and each layer is provided with multiple layers.

[0014] Furthermore, the shielding area is connected to a source electrode in the switch control unit to achieve grounding.

[0015] Furthermore, the switch control unit includes a P-well region formed on a silicon material layer, a source N+ region formed on the P-well region, a gate trench formed at least through the P-well region and the source N+ region, and a source P+ region formed between two adjacent gate trenches.

[0016] Specifically, the source P+ region penetrates the source N+ region, the P-well region, the silicon material layer and is connected to the shielding region. Alternatively, a connection layer is formed at the bottom corner of the gate trench, the connection layer is discontinuously arranged and connected to the shielding region, and the connection layer is also connected to the source N+ region through the P-well region.

[0017] Furthermore, the connecting layer is a half-wrapped structure made at one of the groove corners or a fully wrapped structure made at both groove corners at the same time; when the connecting layer is a half-wrapped structure, it can be arranged at the same groove corner, or it can be distributed alternately on the left and right.

[0018] Furthermore, the shielding region contacts the bottom of the gate trench.

[0019] Furthermore, the electron tunneling layer is distributed in sections above the shielding region, and its width does not exceed the width of the shielding region.

[0020] Furthermore, the shielding area has a wavy structure or a long strip structure.

[0021] The present invention also provides a method for manufacturing the above device structure, comprising the following steps:

[0022] An epitaxial layer is formed on a substrate, a shielding region is formed in the epitaxial layer, and an electron tunneling layer is formed on the upper surface of the epitaxial layer by ion implantation;

[0023] H is implanted on the upper surface of the epitaxial layer and one surface of the single crystal silicon wafer, and then they are bonded and annealed to complete the preparation of the silicon material layer on the epitaxial layer;

[0024] Then, a switch control unit is made in the silicon material layer, and a drain electrode is made on the back side of the substrate.

[0025] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0026] (1) The device structure combines the high withstand voltage characteristics of wide bandgap semiconductors with the mature device technology and mechanism of traditional silicon-based devices. Through some new device structures and process manufacturing methods, the switch control unit components in the traditional silicon power device structure are still made of silicon materials, while the wide bandgap semiconductor drift region is integrated as a withstand voltage unit to form a composite device. This can solve the difficulties in wide bandgap semiconductor device design, process manufacturing and special equipment requirements, and the resulting device performance is even better;

[0027] (2) Avoiding the special process and construction difficulties in the manufacture of traditional wide bandgap semiconductor devices. For example, the difficulties of the gate oxidation process in existing silicon carbide power MOSFET devices, the channel mobility problems and reliability problems caused by gate oxide interface defects, avoiding the special high-temperature equipment process requirements such as high-temperature gate oxide and post-processing in the manufacture of traditional silicon carbide devices; or the difficulties in the construction of device structures that are difficult to activate by ion implantation, such as the difficulties in the construction of P-type ion implantation activation in GaN and Ga2O3, or the difficulties in the construction of N-type ion implantation activation in diamond devices;

[0028] (3) In the preparation method, the method of H injection followed by bonding annealing can improve the bonding strength and ensure the quality of the final device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 10 Structural schematic diagrams of several different silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structures provided by embodiments of the present invention;

[0030] Fig.11 The manufacturing process flow of the silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure described in the specific case 1;

[0031] Fig.12 It is the simulation structure of the device structure obtained in the specific case 1;

[0032] Fig.13 This is the conduction characteristic curve obtained by simulating the device in specific case 1;

[0033] Fig.14The mobility result of the channel obtained by device simulation in specific case 1;

[0034] Fig.15 The conduction band energy level at the Si / SiC interface obtained by device simulation in specific case 1;

[0035] Fig.16 The electric field distribution diagram (left) and blocking characteristic curve (right) obtained by simulating the breakdown of the device in specific case 1.

[0036] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0037] 1 substrate, 2 epitaxial layer, 3 electron tunneling layer, 4 silicon material layer, 5 switch control unit, 6 shielding area, 7 drain electrode, 8 connection layer;

[0038] 51 P well region, 52 source N+ region, 53 gate trench, 54 source P+ region. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be noted that in the description of the present application, the drawings and the description of the embodiments are illustrative rather than restrictive, and the same drawings throughout the embodiments of the specification mark the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0042] The present invention Figure 3 , 4 Figures 6, 9, and 10 are longitudinal cross-sectional views of the relevant device structure and top-view structures at the interface between the silicon material layer and the electron tunneling layer, respectively. Figure 7 Two different layouts for multi-layer shielding areas; Fig.16 The left side is the electric field distribution diagram during breakdown, and the right side is the blocking characteristic curve.

[0043] like Figure 1 As shown, a silicon control unit and a wide bandgap semiconductor voltage-resistant unit composite device structure includes a substrate 1, and the substrate 1 includes a first surface and a second surface relative to each other. For the convenience of description, the direction from the second surface to the first surface is defined as a first direction.

[0044] Epitaxial layer 2, epitaxial layer 2 is made on the first surface of substrate 1 and is a wide bandgap semiconductor material, an electron tunneling layer 3 is made on the upper surface of epitaxial layer 2, and epitaxial layer 2 is divided into an electric field shielding structural area and a voltage-resistant layer structural area along a first direction (that is, the side close to substrate 1 is the voltage-resistant structural area, and the upper side of the voltage-resistant structural area is the electric field shielding area).

[0045] The silicon material layer 4 is manufactured on the electron tunneling layer 3 .

[0046] The switch control unit 5 is manufactured in the silicon material layer 4 .

[0047] The shielding region 6 is formed in the electric field shielding structural region of the electron tunneling layer 3 and / or the epitaxial layer 2 and its doping type is opposite to that of the epitaxial layer 2. For example, the shielding region 6 is formed in both the electron tunneling layer and the electric field shielding structural region by ion implantation, or the shielding region 6 is formed only in the electric field shielding structural region by ion implantation. For details, see Figure 1 , Figure 7 and Figure 8 It can also be understood that, because it is difficult to implement P-doping in some wide bandgap semiconductors, the epitaxial layer is usually N-doped and the shielding region 6 is P-doped.

[0048] The drain electrode 7 is formed on the second surface of the substrate 1 .

[0049] The present invention solves the difficulties in design, process manufacturing and special equipment requirements of wide bandgap semiconductor devices by using silicon materials to make the switch control unit components in traditional silicon power devices and using wide bandgap semiconductor drift regions as voltage-resistant units. The prepared device has better performance. Taking wide bandgap semiconductor material SiC as an example, simulation results show that the mobility at the channel is 60cm 2 / V·s, while the channel mobility of common pure SiC MOSFET devices is 20cm 2 / V·s, the on-state characteristics of the device are effectively improved.

[0050] In the present invention, the shielding area 6 can be made into only one layer or multiple layers along the first direction, and each layer can be arranged with multiple layers. For details, see Figure 1 and Figure 7When multiple layers are produced, the shielding areas 6 between different layers can be distributed in exactly the same manner or in a staggered manner.

[0051] Furthermore, the shielding area 6 can also be connected to the source electrode in the switch control unit 5 to achieve grounding. The grounding of the shielding area 6 can effectively improve the dynamic characteristics of the device.

[0052] The switch control unit 5 includes a P-well region 51 formed on the silicon material layer 4, a source N+ region 52 formed on the P-well region 51, a gate trench 53 formed at least through the P-well region 51 and the source N+ region 52, and a source P+ region 54 formed between two adjacent gate trenches 53.

[0053] In the present invention, the shielding area 6 can be connected to the source in the switch control unit 5 in the following manner to achieve grounding. For example, the source P+ area 54 penetrates the source N+ area 52, the P well area 51, the silicon material layer 4 and the shielding area 6 in direct contact. For details, see Figure 2 Alternatively, a connection layer 8 is formed at the bottom corner of the gate trench 53, the connection layer 8 is discontinuously arranged and connected to the shielding area 6, and the connection layer 8 is also connected to the source N+ area 52 through the P well area 51. For details, see Figure 3 and Figure 4 .in, Figure 3 The middle connection layer 8 is a half-wrapped P-type connection layer made at the corner of one of the grooves. Figure 4 The middle connection layer 8 is a structure made at the bottom of the two grooves to completely wrap the grooves.

[0054] When grounding is achieved through the connection layer 8 at the bottom of the gate trench 53, the connection layer 8 can also provide a better effect on the trench gate oxide layer, but it is required that the connection layer 8 is not completely continuous, but is periodically distributed. It can also be understood that when the connection layer 8 is only formed at one of the groove corners, it can be arranged alternately at the two groove corners at the bottom of the gate trench, or it can be arranged only at one groove corner.

[0055] Furthermore, the shielding area 6 can also be directly connected to the gate groove 53. This can be achieved by controlling the thickness of the silicon control unit structure layer or the depth of the gate groove 53. In this case, a better electric field shielding effect can be achieved, and the shielding area 6 can be ungrounded (see Figure 5 ), grounding can also be achieved by providing a connection layer 8 (see Figure 6 ).

[0056] Furthermore, the electron tunneling layer 3 is distributed in sections above the shielding area 6, and its width does not exceed the width of the shielding area 6. For details, see Figure 8 , which can effectively improve the problem of decreased blocking ability caused by excessive concentration at the interface.

[0057] Furthermore, the shielding area 6 may be a wavy structure or a strip structure or other irregular shaped structures. For example, multiple incompletely staggered strip structures may be used. Such structures and wavy structures may make the current distribution of the device more uniform and optimize the thermal management of the device. The shielding area 6 may not be grounded or may be grounded through the connecting layer 8, and the connecting layer 8 is preferably distributed alternately on both sides of the electric field shielding layer instead of one side, see Fig.10 .

[0058] The present invention also provides a method for manufacturing the above device structure, comprising the following steps:

[0059] An epitaxial layer 2 is formed on a substrate 1, a shielding region 6 is formed in the epitaxial layer 2, and an electron tunneling layer 3 is formed on the upper surface of the epitaxial layer 2 by ion implantation;

[0060] H is implanted into the upper surface of the epitaxial layer 2 and the first surface of the single crystal silicon wafer, and then they are bonded and annealed to complete the preparation of the silicon material layer 4 on the epitaxial layer 2;

[0061] Then, a switch control unit 5 is manufactured in the silicon material layer 4 , and a drain electrode 7 is manufactured on the back side of the substrate 1 .

[0062] Specific case 1

[0063] The present invention is further described in detail below by taking the wide bandgap semiconductor material SiC as an example. Fig.11 , the device structure is made as follows:

[0064] (1) epitaxially grow an N-type wide bandgap semiconductor SiC epitaxial layer on the substrate, form an N+ auxiliary electron tunneling layer by ion implantation, form a P+ masking region by ion implantation and anneal to activate;

[0065] (2) Through intelligent peeling or laser peeling and other technical processes, a 1~2μm single crystal silicon wafer thin layer is peeled off and bonded to the surface of a wide bandgap semiconductor voltage-resistant epitaxial wafer that already has a surface structural electric field masking structural area under room temperature and vacuum. The bonding equipment and process can use SAB technology wafer bonding process equipment to avoid defects, oxide layers or amorphous layers at the bonding interface. Through annealing and other treatment methods, the bonding interface is further repaired and enhanced. Specifically, the surface of the wide bandgap semiconductor epitaxial and the single crystal silicon wafer thin layer to be bonded are cleaned, and then H is injected, the single crystal silicon wafer thin layer is flipped and bonded to the wide bandgap semiconductor epitaxial, and annealed;

[0066] (3) On the composite wafer of the bonded silicon material layer, conventional silicon-based CMOS process is used to construct the switch control unit components and form the back electrode. In this step, it is important to avoid long-term high-temperature processes as much as possible during the process, and to use advanced laser annealing process equipment to avoid the bonding interface layer from being subjected to large temperature gradients and thermal stresses, which may cause interface defects and bubbles and affect the yield. Taking the following switch control unit as an example, its preparation process is as follows: P-well region, source N+ region, source P+ region are formed by ion implantation or diffusion process, gate trench is formed by etching, gate dielectric is grown, gate polysilicon is grown and etched, and back electrode is deposited.

[0067] The prepared structure is as Figure 1 As shown, the device is used as an example for simulation, and the simulation structure is as follows Fig.12 As shown, the conduction characteristics of the device are obtained as Fig.13 As shown, the mobility of the device channel and the conduction band energy level at the Si / SiC interface are extracted, such as Fig.14 and Fig.15 The blocking characteristics of the device are shown in Fig.16 shown.

[0068] from Fig.14 It can be seen that the mobility at the channel is 60cm 2 / V·s, while the channel mobility of common pure SiC MOSFET is 20cm 2 / V·s, the increase in channel mobility is beneficial to improving the conduction characteristics of the device. Fig.15 It can be seen that due to the high doping concentration of SiC at the interface, the conduction band energy level drops rapidly near the interface, which is conducive to the tunneling of electrons from Si to SiC, thereby improving the conduction characteristics of the device. Fig.16 It can be seen that the breakdown voltage of the device is 1226V, and the gate oxide peak electric field at breakdown is only 1.97MV / cm.

[0069] Specific case 2

[0070] The present invention is further described in detail below by taking a multi-layer shielding region structure as an example. The device structure is manufactured as follows:

[0071] (1) epitaxially grow an N-type wide bandgap semiconductor epitaxial layer on the substrate, form the first P+ masking region by ion implantation, then epitaxially grow an N-type wide bandgap semiconductor epitaxial layer for a second time, and then form an N+ auxiliary electron tunneling layer and a second P-type masking region by ion implantation and annealing activation;

[0072] (2) Through intelligent peeling or laser peeling and other technical processes, a 1~2μm single crystal silicon wafer thin layer is peeled off and bonded to the surface of a wide bandgap semiconductor voltage-resistant epitaxial wafer that already has a surface structural electric field masking structural area under room temperature and vacuum. The bonding equipment and process can use SAB technology wafer bonding process equipment to avoid defects, oxide layers or amorphous layers at the bonding interface. Through annealing and other treatment methods, the bonding interface is further repaired and enhanced. Specifically, the surface of the wide bandgap semiconductor epitaxial and the single crystal silicon wafer thin layer to be bonded are cleaned, and then H is injected, the single crystal silicon wafer thin layer is flipped and bonded to the wide bandgap semiconductor epitaxial, and annealed;

[0073] (3) On the composite wafer of the bonded silicon material layer, conventional silicon-based CMOS process is used to construct the switch control unit components and form the back electrode. In this step, it is important to avoid long-term high-temperature processes as much as possible during the process, and to use advanced laser annealing process equipment to avoid the bonding interface layer from being subjected to large temperature gradients and thermal stresses, which may cause interface defects and bubbles and affect the yield. Taking the following switch control unit as an example, its preparation process is as follows: P-well region, source N+ region, source P+ region are formed by ion implantation or diffusion process, gate trench is formed by etching, gate dielectric is grown, gate polysilicon is grown and etched, and back electrode is deposited.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A composite device structure of a silicon control unit and a wide bandgap semiconductor withstand voltage unit, characterized in that: The device structure includes A substrate (1), the substrate (1) comprising a first surface and a second surface opposite to each other, wherein the direction in which the second surface points to the first surface is a first direction; An epitaxial layer (2), the epitaxial layer (2) being manufactured on a first surface of a substrate (1) and being made of a wide bandgap semiconductor material, an electron tunneling layer (3) being manufactured on the upper surface of the epitaxial layer (2), and the epitaxial layer (2) being divided into a voltage-resistant layer structural region and an electric field shielding structural region along a first direction; A silicon material layer (4), wherein the silicon material layer (4) is manufactured on the electron tunneling layer (3); A switch control unit (5), wherein the switch control unit (5) is manufactured in the silicon material layer (4); A shielding region (6), the shielding region (6) being fabricated in an electric field shielding structural region of the electron tunneling layer and / or the epitaxial layer (2) and having a doping type opposite to that of the epitaxial layer (2); the shielding region (6) being fabricated in multiple layers along a first direction, and each layer being provided with multiple layers; the shielding region (6) being connected to a source electrode in the switch control unit (5) to achieve grounding; A drain electrode (7), wherein the drain electrode (7) is manufactured on the second surface of the substrate (1).

2. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 1, characterized in that: The switch control unit (5) comprises a P-well region (51) formed on a silicon material layer (4), a source N+ region (52) formed on the P-well region (51), a gate trench (53) formed at least through the P-well region (51) and the source N+ region (52), and a source P+ region (54) formed between two adjacent gate trenches (53).

3. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 2, characterized in that: The source P+ region (54) penetrates the source N+ region (52), the P-well region (51), the silicon material layer (4), and is connected to the shielding region (6).

4. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 2, characterized in that: A connection layer (8) is formed at the bottom corner of the gate trench (53); the connection layer (8) is arranged discontinuously and is connected to the shielding area (6); the connection layer (8) is also connected to the source N+ area (52) through the P well area (51).

5. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 4, characterized in that: The connecting layer (8) is a half-wrapped structure made at one of the groove corners or a full-wrapped structure made at both groove corners; When the connecting layer (8) is a half-wrapped structure, it is arranged at the same groove corner or alternately distributed on the left and right sides.

6. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 2, characterized in that: The shielding region (6) is in contact with the bottom of the gate trench (53).

7. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 1, characterized in that: The electron tunneling layer (3) is distributed in sections above the shielding area (6), and its width does not exceed the width of the shielding area (6).

8. The silicon control unit and wide bandgap semiconductor withstand voltage unit composite device structure according to claim 1, characterized in that: The shielding area (6) has a wavy structure or a long strip structure.

9. The method for manufacturing the device structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: An epitaxial layer (2) is fabricated on a substrate (1), a shielding region (6) is fabricated in the epitaxial layer (2), and an electron tunneling layer (3) is fabricated on the upper surface of the epitaxial layer (2) by ion implantation; H is implanted into the upper surface of the epitaxial layer (2) and one surface of the single crystal silicon wafer, and then they are bonded and annealed to complete the preparation of the silicon material layer (4) on the epitaxial layer (2); Then, a switch control unit (5) is manufactured in the silicon material layer (4), and a drain electrode (7) is manufactured on the back side of the substrate (1).

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