A dual DC input three-level energy storage converter and common mode voltage suppression method and device thereof

Abstract

The present invention discloses a dual DC input three-level energy storage converter and a common mode voltage suppression method and device thereof, the method comprising: calculating the common mode voltage value of each basic space vector; using the basic space vector of small common mode voltage to redefine a new virtual space vector; calculating the position of the basic space vector of small common mode voltage used; deriving a virtual space vector diagram according to the position of the basic space vector of small common mode voltage used; deriving a switch sequence according to the virtual space vector diagram, thereby achieving common mode voltage suppression. The present invention proposes constructing a virtual space vector that neither charges nor discharges the neutral point through a combination of simplified basic space vectors, thereby achieving suppression of the common mode voltage and balance of the neutral point voltage. In addition, on the basis of suppressing the common mode voltage, the control of the asymmetric DC bus is achieved by optimizing the duty cycle and the switch sequence.

Description

Technical Field

[0001] The present invention belongs to the field of energy storage control, and in particular relates to a dual DC input three-level energy storage converter and a common mode voltage suppression method and device thereof. Background Art

[0002] As the interface between renewable energy power generation devices and the power grid, the converter is the core equipment for energy conversion and plays an irreplaceable role. Among them, the three-level converter has obvious advantages in du / dt, semiconductor loss, output harmonics, filter volume and life cycle cost, making it widely used in solar photovoltaic grid-connected inverters and energy storage devices.

[0003] Dual DC input three-level energy storage converters are used in many real-world applications. For example, in the field of photovoltaic power generation, the upper and lower capacitors on the DC side of the three-level converter are connected to two independent photovoltaic arrays, and the independent maximum power tracking control of the two photovoltaic arrays can be realized in an independent manner to obtain the maximum power from different sources for the energy storage device. In addition, in some high-power occasions, two groups of uncontrolled rectifier bridges are usually connected to the upper and lower capacitors on the DC side to increase power. However, due to the actual operating conditions, the voltages of the upper and lower capacitors are inconsistent. At this time, for the three-level converter, the traditional modulation method based on neutral point voltage balance will cause the output current to be distorted, affecting the waveform quality of the output current. Moreover, in some specific fields, the voltages of the upper and lower DC bus capacitors need to be adjusted asymmetrically. Therefore, for the advanced pulse width modulation strategy of the three-level converter, it must not only be able to balance the neutral point voltage, but also be able to work effectively under an unbalanced DC bus.

[0004] The asymmetry of the DC bus makes its space vector diagram asymmetric and complex, which makes it very time-consuming to implement space vector PWM (SVPWM) by calculating the duration of the three nearest vectors. For the control under unbalanced DC bus, the traditional hybrid PWM that combines SVPWM and carrier-based modulation can simplify the calculation, but it may also cause low-frequency oscillation and fail to maintain high control accuracy. The traditional virtual space vector PWM (VSVPWM) improves the control accuracy of the imbalance by constructing a virtual space vector that neither charges nor discharges the neutral point, but does not consider the negative impact of the common mode voltage (CMV). Excessive CMV can cause common mode interference, increase the risk of resonance, and damage the insulation of lines and electrical equipment. In recent years, the improved virtual space vector PWM proposed by defining a set of virtual voltage vectors (basic space vectors with low CMV) and the carrier-based dual modulation wave virtual space vector PWM have taken into account the reduction of common mode voltage, but because they only focus on the balance of neutral point voltage and the reduction of common mode voltage, they ignore the control accuracy of the unbalanced DC link.

[0005] Most of the proposed modulation strategies often only consider a single optimization goal. For some special occasions, it is necessary not only to overcome the problems of high common-mode voltage and neutral point voltage oscillation, but also to solve the problem of unbalanced control accuracy under unbalanced DC bus. Summary of the invention

[0006] The purpose of the present invention is to provide a dual DC input three-level energy storage converter and a common mode voltage suppression method and device thereof, which constructs a virtual space vector that neither charges nor discharges the neutral point by combining simplified basic space vectors, thereby achieving suppression of the common mode voltage and balance of the neutral point voltage. In addition, on the basis of suppressing the common mode voltage, the control of the asymmetric DC bus is achieved by optimizing the duty cycle and the switching sequence.

[0007] The present invention is implemented according to the following technical solutions:

[0008] In the first aspect, the present invention provides a dual DC input three-level energy storage converter, including upper and lower DC power supplies E1 and E2, upper and lower DC bus capacitors C1 and C2, an A-phase bridge arm composed of power switching devices S1-S4 and freewheeling diodes D1-D4, a B-phase bridge arm composed of power switching devices S5-S8 and freewheeling diodes D5-D8, a C-phase bridge arm composed of power switching devices S9-S12 and freewheeling diodes D9-D12, and a three-phase AC filter and a three-phase AC power grid; point O is the midpoint of the DC bus capacitor, a, b, c are the output ends of the A, B, C three-phase bridge arms; the DC power supplies E1 and E2 are formed by battery packs connected in series, and the upper and lower battery packs E1 and E2 are respectively connected in parallel with the upper and lower bus capacitors C1 and C2 to form a dual DC input T-type three-level structure.

[0009] In a second aspect, a method for suppressing common mode voltage of a dual DC input three-level energy storage converter is provided, the method comprising:

[0010] The method adopts the method of eliminating the low-frequency oscillation of the unbalance ξ by defining a set of virtual space vectors that do not charge or discharge the neutral point, where ξ=(V c1 -V c2 ) / V dc , V c1 is the upper capacitor voltage, V c2 is the lower capacitor voltage, V dc The DC bus voltage is half of the DC bus voltage. The specific steps include:

[0011] Calculate the common mode voltage value of each basic space vector;

[0012] Redefine the virtual space vector using the basic space vector with small common mode voltage;

[0013] Calculate the position of the fundamental space vector of the adopted small common mode voltage;

[0014] A virtual space vector diagram is derived from the position of the basic space vector of the adopted small common mode voltage;

[0015] The switching sequence is derived from the virtual space vector diagram to achieve common-mode voltage rejection.

[0016] In one implementation, the switching sequence of the b-phase in the conventional VSVPWM is modified from “PONOP” to “NOPON” to avoid using a fundamental space vector with a large common mode voltage.

[0017] In one implementation, the virtual space vector is redefined, taking the case where the angle between the reference space vector and the real axis is in the range of 0 to 60 degrees as an example, and is expressed as:

[0018]

[0019] in, is the redefined virtual zero vector, and is a redefined virtual large vector. and is a redefined virtual small vector, is the redefined virtual center vector;

[0020] The redefined virtual vector is half of the vector sum of the N-type small basic space vector "OON" and the medium basic space vector "PNO"; the redefined virtual small vector is half of the vector sum of the P-type small basic space vector "POO" and the medium basic space vector "OPN"; the redefined virtual medium vector It is one third of the vector sum of three adjacent medium-sized basic space vectors "PON", "OPN" and "PNO".

[0021] In one embodiment, the method further includes performing asymmetric control on the dual DC input three-level energy storage converter, and the specific steps include:

[0022] Carrier-based PWM with zero-sequence voltage injection is used to achieve DC bus asymmetry control;

[0023] The volt-second balance equation and the neutral point current are calculated based on the switching sequence obtained from the virtual space vector diagram of VSVPWM;

[0024] By introducing a new control degree of freedom to change the duty cycle to adjust the neutral point current, asymmetric control of the DC bus can be achieved;

[0025] The duty cycle and the injected zero-sequence voltage are calculated to obtain the driving pulse of the power switch tube.

[0026] In one embodiment, the volt-second balance equation is:

[0027]

[0028]

[0029] where d jK (j=a, b and c, K=N, O and P) is the duty cycle of the 'K' state of the 'j' phase, and Represents the three-phase sinusoidal command voltage, v z is the injected zero-sequence voltage.

[0030] In one embodiment, the asymmetric control of the DC bus is achieved by changing the duty cycle through introducing a new control degree of freedom, and the calculation process is as follows:

[0031]

[0032] Among them, △d is the newly introduced control degree of freedom, and it is combined with the duty cycle d of the b-phase O state. bO Add together to get the new duty cycle d bO ′; In order to ensure volt-second balance and achieve asymmetric control, the unbalance degree ξ is introduced into the duty cycle calculation of the P state and N state of the b phase to obtain the new duty cycle d of the P state and N state of the b phase bP ′ and d bN ′.

[0033] In one embodiment, after the asymmetric control of the DC bus is achieved by adjusting the neutral point current by changing the duty cycle through the introduction of a new control degree of freedom, the maximum and minimum values ​​of the introduced new control degree of freedom Δd are restricted, and the calculation process is as follows:

[0034]

[0035] Among them, τ 1 and τ 2 The minimum and maximum values ​​are d bO and 1-d bO ;

[0036] The average midpoint current is calculated by adjusting the duty cycle, and the min To △d max Within the range, calculate △d, and the calculation process is as follows:

[0037]

[0038]

[0039] in, It is the reference value of the average value of the midpoint current.

[0040] In one implementation, the common mode voltage suppression effect of the dual DC input three-level energy storage converter is verified by obtaining the common mode voltage CMV peak-to-peak value under different modulation degrees; the common mode voltage CMV peak-to-peak value under different modulation degrees is obtained as follows:

[0041]

[0042] m is the modulation index. When m is less than 2 / 3, the reference voltage vector is located at I 1 and I 2region, only zero, small and medium virtual space vectors are selected to synthesize the reference voltage vector; I 1 Area and I 2 The maximum and minimum CMV values ​​in the region are V c1 / 3 and -V c2 / 3, the peak-to-peak value of CMV in the entire basic cycle of VSVPWM is 2 / 3V dc ; When m is greater than 2 / 3, the reference voltage vector can be located in region I 3 ,I 4 or I 5 , select a large virtual space vector to synthesize the reference voltage vector; the maximum and minimum values ​​of CMV are max(V c1 / 3,2V c1 / 3-V c2 / 3) and min(-V c2 / 3,V c1 / 3-2V c2 / 3), the peak-to-peak value of CMV in the entire basic cycle of VSVPWM is max(2V c1 / 3,2V c2 / 3).

[0043] In a third aspect, the present invention provides a common mode voltage suppression device for a dual DC input three-level energy storage converter, the device comprising:

[0044] A common mode voltage value calculation module, used for calculating the common mode voltage value of each basic space vector;

[0045] A virtual space vector synthesis module for redefining a virtual space vector using a basic space vector with a small common mode voltage;

[0046] A position calculation module, used to calculate the position of a basic space vector of the adopted small common mode voltage;

[0047] A virtual space vector diagram module, used for obtaining a virtual space vector diagram according to the position of a basic space vector of a small common mode voltage adopted;

[0048] The switch sequence generation module is used to obtain the switch sequence according to the virtual space vector diagram, so as to achieve common mode voltage suppression.

[0049] In one embodiment, the device further includes an asymmetric control module for performing asymmetric control on a dual DC input three-level energy storage converter; the asymmetric control module includes:

[0050] A PWM implementation module for implementing asymmetric control of the DC bus using carrier-based PWM with zero-sequence voltage injection;

[0051] A calculation module, used for calculating the volt-second balance equation and the neutral point current according to the switching sequence obtained from the virtual space vector diagram of the VSVPWM;

[0052] Asymmetric control of the DC bus, which is used to adjust the neutral point current by changing the duty cycle through the introduction of a new control freedom to achieve asymmetric control of the DC bus;

[0053] The drive pulse generation module is used to calculate the duty cycle and the injected zero-sequence voltage to obtain the drive pulse of the power switch tube.

[0054] Beneficial effects of the present invention:

[0055] 1. Based on the original T-type three-level topology, the present invention forms a dual DC input T-type three-level structure by connecting the upper and lower bus capacitors in parallel with the upper and lower battery groups respectively. By utilizing the large equivalent capacitance of the battery group, the capacitance of the bus capacitor can be reduced, which is beneficial to reducing cost and volume.

[0056] 2. By simplifying the combination of basic space vectors, a virtual space vector is constructed that neither charges nor discharges the neutral point, thereby achieving suppression of the common-mode voltage and control of the neutral-point voltage.

[0057] 3. In addition, the asymmetric DC bus is controlled by optimizing the duty cycle and switching sequence on the basis of suppressing the common mode voltage.

[0058] 4. The dual-input three-level energy storage converter and its asymmetric control method proposed in the present invention can expand the application scenarios of traditional three-level converters, and can also improve the output power and energy utilization efficiency of the DC side in special occasions such as photovoltaic power generation and energy storage; the present invention can suppress common-mode voltage, reduce common-mode interference caused by excessive common-mode voltage, resonance risk and insulation damage to the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings are part of the present invention and are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but do not constitute an improper limitation of the present invention. Obviously, the accompanying drawings described below are only some embodiments. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0060] Figure 1 It is a dual-input three-level energy storage converter circuit topology;

[0061] Figure 2 A flow chart of a dual DC input three-level energy storage converter and a common mode voltage suppression method thereof provided in one embodiment of the present invention;

[0062] Figure 3A basic space vector diagram provided by an embodiment of the present invention;

[0063] Figure 4 A virtual space vector diagram provided by an embodiment of the present invention;

[0064] Figure 5 An embodiment of the present invention provides a region I 1 Take the output state diagram of each phase as an example according to the proposed switching sequence; Figure 5 (a) is the output state diagram of each phase obtained according to the switching sequence of traditional VSVPWM Figure 5 (b) is the output state diagram of each phase obtained according to the proposed VSVPWM switching sequence;

[0065] Figure 6 The output state diagram of each phase obtained after adjusting the duty ratio of the b-phase O, P, N states provided by an embodiment of the present invention;

[0066] Figure 7 A comparison diagram of CMV peak-to-peak values ​​of three methods provided in one embodiment of the present invention, wherein Figure 7 In (a), the unbalance degree ξ is ±0.1, Figure 7 (b) The unbalance ξ is ±0.5;

[0067] Figure 8 A comparison diagram of the Δd range of the VSVPWM proposed by the present invention and the calculation method of the traditional VSVPWM is provided in one embodiment of the present invention, wherein Figure 8 (a) is the △d range of the proposed VSVPWM, Figure 8 (b) △d range of traditional VSVPWM;

[0068] Fig. 9 A diagram of zero-sequence components injected under different ξ provided in one embodiment of the present invention, wherein the modulation index m is 0.8;

[0069] Fig.10 The following is a comparison chart of experimental results of three methods provided in one embodiment of the present invention under different modulation degrees and different balance degrees, wherein Fig.10 (a) m is 0.4, the unbalance reference value ξ * is 0.5, Fig.10 In (b), m is 1.0, and the unbalance reference value ξ * is -0.6;

[0070] Fig.11 The three methods provided in one embodiment of the present invention are as follows: ξ *The CMV peak-to-peak comparison chart for different m when set to 0.5 and -0.6; Fig.11 (a) is the reference value of imbalance ξ * This is a CMV peak-to-peak comparison chart of 0.5. Fig.11 (b) is the unbalance reference value ξ * The CMV peak-to-peak comparison chart at -0.6;

[0071] Fig.12 The three methods provided in one embodiment of the present invention are as follows: when m is between 0.1 and 1.15, the unbalance reference value is ξ * Comparison of CMV root mean square (RMS) values ​​when set to 0.5 and -0.6; Fig.12 (a) Unbalance reference value ξ * is 0.5, Fig.12 (b) Unbalance reference value ξ * is -0.6;

[0072] Fig.13 A comparison chart of the unbalanced control accuracy between the VSVPWM proposed by the present invention and method ③ provided in one embodiment of the present invention;

[0073] Fig.14 This is a diagram showing the effectiveness of an experimental study on the asymmetry control of a DC bus provided by an embodiment of the present invention.

[0074] It should be noted that these drawings and textual descriptions are not intended to limit the conceptual scope of the present invention in any way, but are intended to illustrate the concept of the present invention for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0076] In order to deepen the recognition and understanding of the present invention, the technical solution of the present invention is further introduced below in conjunction with the accompanying drawings and specific implementation methods.

[0077] The specific embodiments of the present invention are further described in detail below:

[0078] like Figure 1As shown, a dual-input three-level energy storage converter circuit topology structure includes upper and lower DC power supplies E1 and E2 (formed by battery groups connected in series), upper and lower DC bus capacitors C1 and C2, an A-phase bridge arm composed of power switch devices S1-S4 and freewheeling diodes D1-D4, a B-phase bridge arm composed of power switch devices S5-S8 and freewheeling diodes D5-D8, a C-phase bridge arm composed of power switch devices S9-S12 and freewheeling diodes D9-D12, as well as a three-phase AC filter and a three-phase AC power grid, point O is the midpoint of the DC bus capacitor, a, b, and c are the output ends of the A, B, and C three-phase bridge arms, the upper and lower battery groups E1 and E2 are respectively connected in parallel with the upper and lower bus capacitors C1 and C2 to form a dual DC input T-type three-level structure.

[0079] The traditional VSVPWM under the unbalanced DC bus can eliminate the low-frequency oscillation of the imbalance degree ξ by defining a set of virtual space vectors that do not charge or discharge the neutral point. Taking the case where the angle between the reference space vector and the real axis ranges from 0 to 60 degrees as an example, the defined virtual space vectors are as follows:

[0080]

[0081] in is the virtual zero vector, and is a virtual small vector, and is a virtual large vector, is the virtual mean vector.

[0082] In order to solve the problem of too high common mode voltage of dual-input three-level converter and ensure that it always works in a safe, efficient and stable operating state, the present invention provides a common mode voltage suppression method for dual DC input three-level energy storage converter, such as Figure 2 As shown, the method eliminates the low-frequency oscillation of the unbalance ξ by defining a set of virtual space vectors that do not charge or discharge the neutral point, where ξ=(V c1 -V c2 ) / V dc , V c1 is the upper capacitor voltage, V c2 is the lower capacitor voltage, V dc The voltage of the DC bus is half of the voltage of the DC bus. Specifically, the following steps are included:

[0083] Step S100: Calculate the common mode voltage value of each basic space vector.

[0084] The common mode voltage value of each basic space vector is found as shown in Table I:

[0085] Table I

[0086]

[0087] Step S200: synthesizing a new virtual space vector using a basic space vector with a small common mode voltage.

[0088] In order to reduce the common mode voltage, avoid using basic space vectors with large common mode voltage when synthesizing virtual space vectors. Use basic space vectors with small common mode voltage to synthesize virtual space vectors. The number of basic space vectors used is reduced from 27 to 19, such as Figure 3 shown.

[0089] Furthermore, the virtual space vector is redefined, taking the case where the angle between the reference space vector and the real axis is in the range of 0 to 60 degrees as an example, as follows:

[0090]

[0091] in, is the redefined virtual zero vector, and is a redefined virtual large vector. and is a redefined virtual small vector, is the redefined virtual center vector;

[0092] The redefined virtual vector is half of the vector sum of the N-type small basic space vector "OON" and the medium basic space vector "PNO"; the redefined virtual small vector is half of the vector sum of the P-type small basic space vector "POO" and the medium basic space vector "OPN"; the redefined virtual medium vector It is one third of the vector sum of three adjacent medium-sized basic space vectors "PON", "OPN" and "PNO".

[0093] Step S300: Calculate the position of the basic space vector of the adopted small common mode voltage.

[0094] In the embodiment of the present application, the position of the basic space vector used is calculated as follows:

[0095]

[0096] Step S400: derive a virtual space vector diagram according to the position of the basic space vector of the small common mode voltage used. Figure 4 shown.

[0097] By comparing the virtual space vector diagram of VSVPWM proposed in step S400 with the VSVPWM when the DC bus is balanced, it is found that the duration of the latest three virtual space vectors can be calculated using the traditional VSVPWM method when the DC bus is balanced.

[0098] Step S500: deriving a switch sequence according to the virtual space vector diagram, thereby achieving common mode voltage suppression.

[0099] In the embodiment of the present application, a new switching sequence is proposed according to the proposed virtual space vector diagram of VSVPWM, as shown in Table II:

[0100] Table II

[0101]

[0102] Specifically, in area I 1 As an example, according to the proposed switching sequence, the output state of each phase can be obtained as follows Figure 5 As shown, the analysis shows that the common mode voltage peak-to-peak value of the VSVPWM proposed by the present invention is from 4V dc / 3 down to 2V dc / 3. From area I 1 It can be extended to other regions, and the peak-to-peak values ​​of the common-mode voltage in each region are as follows:

[0103] Table III

[0104]

[0105] In a possible implementation, the dual DC input three-level energy storage converter and the common mode voltage suppression method thereof further include step S600.

[0106] Step S600: performing asymmetric control on a dual DC input three-level energy storage converter.

[0107] In order to solve the problem of low unbalanced control accuracy of the asymmetric DC bus and ensure that it always works in a safe, efficient and stable operating state, the present invention proposes an asymmetric control method for a dual DC input three-level energy storage converter. The asymmetric control includes an improved volt-second balance equation, calculation of injected zero-sequence voltage and optimization of duty cycle.

[0108] In an embodiment of the present application, asymmetric control is performed on a dual DC input three-level energy storage converter, and the specific steps include:

[0109] Step S610: using carrier-based PWM with zero-sequence voltage injection to implement asymmetric control of the DC bus.

[0110] Step S620: Calculate the volt-second balance equation and the neutral point current according to the switching sequence obtained from the virtual space vector diagram.

[0111] For simplicity and to achieve asymmetric control of the DC bus, the proposed VSVPWM is implemented using a carrier-based PWM with zero-sequence voltage injection. For the proposed switching sequence, the volt-second balance equation can be calculated, and the calculation process is as follows:

[0112]

[0113]

[0114] where d jK (j=a, b and c, K=N, O and P) is the duty cycle of the 'K' state of the 'j' phase, and Represents the three-phase sinusoidal command voltage, v z To inject zero-sequence voltage. The calculation method of duty ratio is the same when the reference space vector is located in other areas. After determining the duty ratio, the driving pulse of the power switch tube can be obtained according to the output state of each phase.

[0115] Step S630: The duty cycle is changed by introducing a new control degree of freedom to adjust the neutral point current to achieve asymmetric control of the DC bus.

[0116] The average midpoint current is calculated based on the volt-second balance equation and duty cycle Since the defined virtual space vector neither charges nor discharges the neutral point, the average value is 0. The calculation process is as follows:

[0117]

[0118] Among them, i a ,i b and i c Represents three-phase sinusoidal current;

[0119] Furthermore, the asymmetric control of the DC bus is realized by changing the duty cycle through introducing a new control degree of freedom. The calculation process is as follows:

[0120] The calculation process is as follows:

[0121]

[0122] Where △d is the newly introduced control degree of freedom, and it is combined with d bO Add, d bO Modified to d bO In order to ensure volt-second balance and realize asymmetric control, the unbalance degree ξ is introduced into the duty cycle calculation of the P state and N state of the b phase to obtain the new duty cycle d of the P state and N state of the b phase. bP ′ and dbN According to the modified duty cycle, the output state of each phase can be obtained as follows: Figure 6 shown.

[0123] In a possible implementation, in order to ensure that the duration is between 0 and 1, the maximum and minimum values ​​of the newly introduced control freedom Δd are limited, and the calculation process is as follows:

[0124]

[0125] Among them, τ 1 and τ 2 The minimum and maximum values ​​are d bO and 1-d bO .

[0126] The average midpoint current can be calculated by adjusting the duty cycle, and the average midpoint current can be calculated by adjusting the duty cycle. min To △d max Within the range, △d can be calculated. The calculation process is as follows:

[0127]

[0128]

[0129] in, It is the reference value of the average value of the midpoint current.

[0130] Step S640: Calculate the duty cycle and the injected zero-sequence voltage to obtain a driving pulse for the power switch tube.

[0131] Since the VSVPWM proposed in the present invention modifies the switching order of phase b from "PONOP" to "NOPON" to avoid a basic space vector with a large CMV, the common-mode voltage suppression effect of the dual DC input three-level energy storage converter can be verified by obtaining the common-mode voltage CMV peak-to-peak value under different modulation indices. The CMV peak-to-peak value of the VSVPWM proposed under different modulation indices is calculated as follows:

[0132]

[0133] Where m is the modulation degree.

[0134] When m is less than 2 / 3, the reference voltage vector is located at Figure 3 I 1 and I 2 region, only zero, small and medium virtual space vectors are selected to synthesize the reference voltage vector. 1 Area and I 2 The maximum and minimum CMV values ​​in the region are V c1 / 3 and -Vc2 / 3. Therefore, the peak-to-peak value of CMV in the entire basic cycle of the VSVPWM proposed by the present invention is 2 / 3V dc , where m is less than 2 / 3. When m is greater than 2 / 3, the reference voltage vector can be located in region I 3 ,I 4 or I 5 , where a large virtual space vector is selected to synthesize the reference voltage vector. In this case, the maximum and minimum values ​​of CMV are max(V c1 / 3,2V c1 / 3-V c2 / 3) and min(-V c2 / 3,V c1 / 3-2V c2 / 3). Therefore, the peak-to-peak value of CMV in the entire basic cycle of the VSVPWM proposed by the present invention is max(2V c1 / 3,2V c2 / 3), where m is greater than 2 / 3.

[0135] In the prior art, the PWM method for reducing CMV under unbalanced DC link adopts the method of using zero, small, medium and large basic space vectors to synthesize any reference voltage vector m, and the peak-to-peak value of CMV is max(2V) in the whole basic cycle. c1 / 3,2V c2 / 3).

[0136] By comparing the traditional VSVPWM, the prior art and the VSVPWM proposed in the present invention, it is found that the CMV peak-to-peak value of the VSVPWM proposed in the present invention in the entire cycle at different m is smaller than that of the traditional VSVPWM and the PWM with reduced CMV.

[0137] Since the control target of the VSVPWM proposed in the present invention is different from that of the traditional VSVPWM, the calculation method of △d is also different. In addition, since the volt-second balance equation of the unbalanced DC bus of the proposed VSVPWM is changed compared with the VSVPWM under the traditional balanced DC bus, the injected zero-sequence component should also change accordingly.

[0138] Figure 7 is the CMV peak-to-peak comparison of the above three methods, where Figure 7 In (a), ξ is ±0.1, Figure 7 In (b), ξ is ±0.5. It can be clearly seen that the proposed VSVPWM has obvious advantages over the other two methods in the entire cycle of different m and under different ξ.

[0139] Figure 8The △d range of the VSVPWM proposed in the present invention is compared with the calculation method of the traditional VSVPWM. It can be seen that the △d is different due to the different calculation methods. min Something has changed.

[0140] Fig. 9 Figure 2 is the injected zero-sequence component diagram under different ξ, where m is 0.8. It is found that the injected zero-sequence component changes with the change of ξ, which is different from the traditional zero-sequence injection method.

[0141] Methods ①, ② and ③ are respectively traditional VSVPWM, VSVPWM proposed by the present invention and methods in the prior art. Fig.10 The experimental results of three methods under different modulation degrees and different balance degrees are given. Fig.10 In (a), m is 0.4, and the unbalance reference value (ξ * ) is 0.5. It can be seen from the figure that the CMV peak-to-peak values ​​of methods ①, ② and ③ are approximately 364.1V, 181.9V and 225.3V respectively. Compared with the traditional VSVPWM, the CMV peak-to-peak value of the VSVPWM proposed in the present invention is reduced by about 50%. Compared with the method in the prior art, the CMV peak-to-peak value of the VSVPWM proposed in the present invention is also reduced by 19.3%. Fig.10 In (b), m is 1.0, and the unbalance reference value (ξ * ) is -0.6, the peak-to-peak values ​​of the CMV curves of methods ①, ② and ③ are approximately 363.8 V, 225.1 V and 225.1 V respectively. Compared with the traditional VSVPWM, the CMV peak-to-peak value of the VSVPWM proposed in the present invention is reduced by about 35.4%.

[0142] Fig.11 For * The CMV peak-to-peak values ​​of different m when set to 0.5 and -0.6. Both the VSVPWM method and method ③ proposed in the present invention can achieve CMV reduction, and when the CMV peak-to-peak value is less than 2 / 3, the CMV peak-to-peak value of the VSVPWM proposed in the present invention is also reduced compared with method ③.

[0143] Fig.12 For the three methods, when m ranges between 0.1 and 1.15, ξ * The CMV root mean square (RMS) values ​​when set to 0.5 and -0.6. The RMS value of the VSVPWM proposed in this paper is also lower than that of the traditional VSVPWM.

[0144] Fig.13 The comparison results of the proposed VSVPWM and method ③ in terms of unbalanced control accuracy, where m is 1.1, ξ * is -0.6. Fig.13As shown on the left, the ξ of method ③ * The error between ξ and ξ fluctuates greatly, with the maximum fluctuation being about 0.045. Fig.13 As shown on the right, the control error of ξ of the VSVPWM proposed in the present invention is greatly reduced, and the control accuracy is significantly improved compared with method ③.

[0145] Fig.14 This is the effectiveness experiment of the asymmetry control of the DC bus. * First change from 0 to 0.7, then change from 0.7 to -0.4, and m remains at 0.9. c1 and V c2 The curves show the effectiveness of the proposed DC bus asymmetry control. Fig.14 The current magnification curve at the bottom shows that the phase current waveform is highly sinusoidal during the process of adjusting the imbalance. * The THD of the phase current during the change from 0 to 0.7 and from 0.7 to -0.4 is 2.59% and 2.64% respectively.

[0146] The above experimental results show that the dual-DC input three-level energy storage converter and the common-mode voltage suppression method thereof provided by the embodiments of the present invention can realize asymmetric control and common-mode voltage suppression for the dual-input three-level converter.

[0147] In one embodiment, a dual DC input three-level energy storage converter and a common mode voltage suppression device thereof are proposed. The device comprises:

[0148] A virtual space vector definition module, used to define a set of virtual space vectors that do not charge or discharge the neutral point;

[0149] A virtual space vector synthesis module, used to synthesize a new virtual space vector using a basic space vector with a small common mode voltage;

[0150] A position calculation module, used to calculate the position of a basic space vector of the adopted small common mode voltage;

[0151] A virtual space vector diagram module, used for obtaining a virtual space vector diagram according to the position of a basic space vector of a small common mode voltage adopted;

[0152] The switch sequence generation module is used to obtain the switch sequence according to the virtual space vector diagram, so as to achieve common mode voltage suppression.

[0153] Furthermore, the device also includes an asymmetric control module for asymmetric control of the dual DC input three-level energy storage converter; the asymmetric control module includes:

[0154] A PWM implementation module for implementing asymmetric control of the DC bus using carrier-based PWM with zero-sequence voltage injection;

[0155] A calculation module, used for calculating the volt-second balance equation and the neutral point current according to the switching sequence obtained from the virtual space vector diagram;

[0156] Asymmetric control of the DC bus, used to adjust the neutral point current by changing the duty cycle to achieve asymmetric control of the DC bus;

[0157] The drive pulse generation module is used to calculate the duty cycle and the injected zero-sequence voltage to obtain the drive pulse of the power switch tube.

[0158] It should be noted that the dual DC input three-level energy storage converter and its common-mode voltage suppression device provided in the above embodiment only use the division of the above-mentioned functional modules as an example when executing the dual DC input three-level energy storage converter and its common-mode voltage suppression method. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the dual DC input three-level energy storage converter and its common-mode voltage suppression device provided in the above embodiment belong to the same concept as the dual DC input three-level energy storage converter and its common-mode voltage suppression method embodiment. The embodiment and implementation process thereof are detailed in the dual DC input three-level energy storage converter and its common-mode voltage suppression method embodiment, which will not be repeated here.

[0159] The various functional modules in the embodiments of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0160] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this patent can make some changes or modify the technical contents suggested above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the invention without departing from the content of the technical solution of the present invention still fall within the scope of the solution of the present invention.

Claims

1. A method for suppressing common mode voltage of a dual DC input three-level energy storage converter, characterized in that: The method adopts the method of eliminating the low-frequency oscillation of the unbalance ξ by defining a set of virtual space vectors that do not charge or discharge the neutral point, where ξ=(V c1 -V c2 ) / V dc , V c1 is the upper capacitor voltage, V c2 is the lower capacitor voltage, V dc The DC bus voltage is half of the DC bus voltage. The specific steps include: Calculate the common mode voltage value of each basic space vector; Redefine the virtual space vector using the basic space vector with small common mode voltage; Calculate the position of the fundamental space vector of the adopted small common mode voltage; A virtual space vector diagram is derived from the position of the basic space vector of the adopted small common mode voltage; The switching sequence is derived from the virtual space vector diagram to achieve common mode voltage suppression; The method further includes asymmetric control of the dual DC input three-level energy storage converter, and the specific steps include: A carrier-based PWM with zero-sequence voltage injection is used to achieve DC bus asymmetry control; Calculate the volt-second balance equation and the neutral point current based on the switching sequence obtained from the virtual space vector diagram; By introducing the duty cycle time control freedom to change the duty cycle to adjust the neutral point current to achieve asymmetric control of the DC bus; the calculation process is as follows: Among them, △d is the duty cycle time control freedom, and it is compared with the duty cycle d of the b phase O state bO Add together to get the new duty cycle d bO ′; In order to ensure volt-second balance and achieve asymmetric control, the unbalance degree ξ is introduced into the duty ratio d of the P state and N state of phase b bp ,d bN Calculate the new duty cycle d of the P state and N state of phase b bP ′ and d bN ′; The duty cycle and the injected zero-sequence voltage are calculated to obtain the driving pulse of the power switch tube.

2. The common mode voltage suppression method of a dual DC input three-level energy storage converter according to claim 1, characterized in that: The switching sequence of the b-phase in the conventional VSVPWM is modified from "PONOP" to "NOPON" to avoid using the basic space vector with a large common-mode voltage.

3. The common mode voltage suppression method of a dual DC input three-level energy storage converter according to claim 1, characterized in that: The redefinition of the virtual space vector, when the angle between the reference space vector and the real axis is in the range of 0 to 60 degrees, is expressed as: in, is the redefined virtual zero vector, is an N-type small basic space vector, are three adjacent medium-sized basic space vectors, is a P-type small basic space vector, V dc , and is a redefined virtual large vector. and is a redefined virtual small vector, is the redefined virtual center vector; The redefined virtual vector is half of the vector sum of the N-type small basic space vector "OON" and the medium-sized basic space vector "PNO"; the redefined virtual small vector is half of the vector sum of the P-type small basic space vector "POO" and the medium basic space vector "OPN"; the redefined virtual medium vector It is one third of the vector sum of three adjacent medium-sized basic space vectors "PON", "OPN" and "PNO".

4. The common mode voltage suppression method of a dual DC input three-level energy storage converter according to claim 1, characterized in that: The volt-second balance equation is: where d jK is the duty cycle of the K state of phase j, j represents phases a, b and c, K represents the N, O and P switching states, and Represents the three-phase sinusoidal command voltage, v z is the injected zero-sequence voltage and ξ is the degree of unbalance.

5. The common mode voltage suppression method of a dual DC input three-level energy storage converter according to claim 1 or 4, characterized in that: After the asymmetric control of the DC bus is realized by adjusting the neutral point current by changing the duty cycle through the duty cycle time control freedom, the maximum and minimum values ​​of the introduced duty cycle time control freedom Δd are restricted, and the calculation process is as follows: Among them, τ1 and τ2 are the minimum and maximum values ​​​​of d bo and 1-d bo , d bO , d bP , d bN are the duty cycles of the N, O and P switching states of phase b respectively; The average midpoint current is calculated by adjusting the duty cycle, and the min To △d max Within the range, calculate △d, and the calculation process is as follows: in, is the average value of the midpoint current, i b is the b-phase sinusoidal current, It is the reference value of the average value of the midpoint current.

6. The common mode voltage suppression method of a dual DC input three-level energy storage converter according to claim 5, characterized in that: The common mode voltage suppression effect of the dual DC input three-level energy storage converter is verified by obtaining the common mode voltage CMV peak-to-peak value under different modulation indices; the common mode voltage CMV peak-to-peak value under different modulation indices is obtained as follows: m is the modulation index. When m is less than 2 / 3, the reference voltage vector is located in the I1 and I2 regions. Only zero, small and medium virtual space vectors are selected to synthesize the reference voltage vector. The maximum and minimum CMV values ​​in the I1 and I2 regions are V c1 / 3 and -V c2 / 3, the peak-to-peak value of CMV in the entire basic cycle of VSVPWM is 2 / 3V dc ; When m is greater than 2 / 3, the reference voltage vector can be located in region I3, I4 or I5, and a large virtual space vector is selected to synthesize the reference voltage vector; the maximum and minimum values ​​of CMV are max(V c1 / 3,2V c1 / 3-V c2 / 3) and min(-V c2 / 3,V c1 / 3-2V c2 / 3), the peak-to-peak value of CMV in the entire basic cycle of VSVPWM is max(2V c1 / 3,2V c2 / 3).

7. A common mode voltage suppression device for a dual DC input three-level energy storage converter, characterized in that: The device comprises: A common mode voltage value calculation module, used for calculating the common mode voltage value of each basic space vector; A virtual space vector synthesis module, used to redefine a virtual space vector using a basic space vector with a small common mode voltage; A position calculation module, used to calculate the position of a basic space vector of the adopted small common mode voltage; A virtual space vector diagram module, used for obtaining a virtual space vector diagram according to the position of a basic space vector of a small common mode voltage adopted; The device also includes an asymmetric control module, which is used for asymmetric control of the dual DC input three-level energy storage converter; the asymmetric control module includes: A PWM implementation module for implementing asymmetric control of the DC bus using carrier-based PWM with zero-sequence voltage injection; A calculation module, used for calculating the volt-second balance equation and the neutral point current according to the switching sequence obtained from the virtual space vector diagram; Asymmetric control of the DC bus, which is used to adjust the neutral point current by introducing the duty cycle time control freedom to achieve asymmetric control of the DC bus; A driving pulse generation module is used to calculate the duty cycle and the injected zero-sequence voltage to obtain the driving pulse of the power switch tube; The asymmetric control of the DC bus is achieved by changing the duty cycle by introducing the duty cycle time control freedom, and the calculation process is as follows: Among them, △d is the duty cycle time control freedom, and it is compared with the duty cycle d of the b phase O state bO Add together to get the new duty cycle d bO ′; In order to ensure volt-second balance and achieve asymmetric control, the unbalance degree ξ is introduced into the duty ratio d of the P state and N state of phase b bp ,d bN Calculate the new duty cycle d of the P state and N state of phase b bP ′ and d bN ′; The switch sequence generation module is used to obtain the switch sequence according to the virtual space vector diagram, so as to achieve common mode voltage suppression.

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