Variable modulus adder based on constant add / subtract, method of operation and related apparatus

Abstract

The application discloses a variable modulus addition operation device based on constant addition and subtraction, an operation method and related devices, and provides a variable modulus addition operation device based on constant addition and subtraction. The variable modulus addition operation device comprises a first adder, a constant subtractor, a first CNOT gate and a controlled constant adder which are connected in sequence. The constant in the constant subtractor and the controlled constant adder is a modulus. The variable modulus addition operation device is used for calculating the modulus addition operation result of two input data to be added and the modulus. For any two input data to be added, the modulus addition operation result of the data and the modulus preset in the variable modulus addition operation device can be calculated.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum computing, and particularly relates to a variable modulus addition operator based on constant addition and subtraction, a calculation method and a related device. BACKGROUND

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. The quantum computer has the ability to process mathematical problems more efficiently than ordinary computers, for example, it can accelerate the time for cracking RSA keys from hundreds of years to a few hours, so it is a key technology under research.

[0003] Modular operation has a wide range of applications in number theory and cryptography, from parity to prime number discrimination, from Sunzi theorem to Caesar cipher, from finite field to implementation of block cipher domain tower, from elliptic curve on finite field to elliptic curve public key cryptography, all of which are filled with the figure of modular operation. Therefore, modular operation is the most commonly used function in the operation component, and the same is true for quantum computing. How to implement variable modulus addition operation is a technical problem that needs to be solved in quantum computing. SUMMARY

[0004] The purpose of the application is to provide a variable modulus addition operator based on constant addition and subtraction, a calculation method and a related device, which aims to realize the modulus addition operation of any two numbers in quantum computing.

[0005] One embodiment of the application provides a variable modulus addition operator based on constant addition and subtraction, which comprises a first adder, a constant subtractor, a first CNOT gate and a controlled constant adder connected in sequence, the constant in the constant subtractor and the controlled constant adder is a modulus, and the variable modulus addition operator is used to calculate the modulus addition result of two input data to be added and the modulus.

[0006] Optionally, the four input ends of the variable modulus addition operator are connected with the three input ends of the first adder and one of the input ends of the first CNOT gate, and the four input ends of the variable modulus addition operator are used to input the quantum states corresponding to the two data to be added, the initial calculation auxiliary data and the initial comparison auxiliary data.

[0007] Optionally, one of the output ends of the first adder is connected with the input end of the constant subtractor, the output end of the constant subtractor is connected with the other input end of the first CNOT gate, and the two output ends of the first CNOT gate are connected with the two input ends of the controlled constant adder.

[0008] Optionally, the output end of the constant subtractor comprises a data output end and a symbol output end, one input end of the controlled constant adder comprises a data input end and a symbol input end, the symbol output end of the constant subtractor is connected with the other input end of the first CNOT gate, and one output end of the first CNOT gate is connected with the symbol input end of the controlled constant adder.

[0009] Optionally, the two output ends of the controlled constant adder are respectively used for outputting quantum states corresponding to the modulo addition operation result and the intermediate comparison auxiliary data, and the other two output ends of the first adder are used for outputting quantum states corresponding to one of the data to be added and the intermediate calculation auxiliary data.

[0010] Optionally, the four output ends of the variable modulo addition operator are connected with the two output ends of the controlled constant adder and the other two output ends of the first adder.

[0011] Optionally, the first adder, the constant subtractor, the first CNOT gate and the controlled constant adder are a modulo addition operation module, and the variable modulo addition operator further comprises an auxiliary data reset module connected with the modulo addition operation module, and the auxiliary data reset module is used for resetting the intermediate comparison auxiliary data to the initial comparison auxiliary data.

[0012] Optionally, the auxiliary data reset module comprises a subtractor, a first NOT gate, a second CNOT gate, a second NOT gate and a second adder which are sequentially connected in cascade, four input ends of the auxiliary data reset module are respectively connected with three input ends of the subtractor and one input end of the second CNOT gate, four output ends of the auxiliary data reset module are respectively connected with three output ends of the second adder and one output end of the second CNOT gate, three output ends of the second adder are used for outputting quantum states corresponding to the modulo addition operation result, one of the data to be added and the initial calculation auxiliary data, and one output end of the second CNOT gate is used for outputting a quantum state corresponding to the initial comparison auxiliary data.

[0013] Optionally, the other three output ends of the subtractor are respectively connected with an input end of the first NOT gate and two input ends of the second adder, an output end of the first NOT gate is connected with the other input end of the second CNOT gate, the other output end of the second CNOT gate is connected with an input end of the second NOT gate, and an output end of the second NOT gate is connected with the other input end of the second adder.

[0014] Optionally, one output end of the subtracter comprises a data output end and a sign output end, another input end of the second adder comprises a data input end and a sign input end, the sign output end of the subtracter is connected with the input end of the first NOT gate, and the output end of the second NOT gate is connected with the sign input end of the second adder.

[0015] Yet another embodiment of the present application provides a variable modulus addition operation method based on constant addition and subtraction, which comprises:

[0016] obtaining the variable modulus addition operation device and two data to be added as described in the above embodiments;

[0017] inputting the two data to be added into the variable modulus addition operation device, and running the variable modulus addition operation device to obtain a quantum state corresponding to a modulus addition operation result of the two data to be added and the modulus number;

[0018] determining the modulus addition operation result based on the quantum state corresponding to the modulus addition operation result.

[0019] Yet another embodiment of the present application provides a variable modulus addition operation device based on constant addition and subtraction, which comprises:

[0020] an obtaining unit configured to obtain the variable modulus addition operation device and two data to be added as described in the above embodiments;

[0021] a calculating unit configured to input the two data to be added into the variable modulus addition operation device, and run the variable modulus addition operation device to obtain a quantum state corresponding to a modulus addition operation result of the two data to be added and the modulus number;

[0022] a determining unit configured to determine the modulus addition operation result based on the quantum state corresponding to the modulus addition operation result.

[0023] Yet another embodiment of the present application provides a storage medium, wherein a computer program is stored in the storage medium, and the computer program is configured to execute the method described in the above embodiments when running.

[0024] Yet another embodiment of the present application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to execute the method described in the above embodiments.

[0025] Compared with the prior art, the variable modulus addition operator based on constant addition and subtraction provided by the application comprises a first adder, a constant subtractor, a first CNOT gate and a controlled constant adder connected in sequence, the constant in the constant subtractor and the controlled constant adder is a modulus, and the variable modulus addition operator is used for calculating the modulus addition result of two input data to be added and the modulus, and for any two input data to be added, the modulus addition result of the data and the modulus preset in the variable modulus addition operator can be calculated. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A hardware structure block diagram of a computer terminal for a variable modulus addition operation method based on constant addition and subtraction provided by the embodiment of the application is provided.

[0027] Figure 2 A structure schematic diagram of a variable modulus addition operator based on constant addition and subtraction provided by the embodiment of the application is provided.

[0028] Figure 3 A structure schematic diagram of another variable modulus addition operator based on constant addition and subtraction provided by the embodiment of the application is provided.

[0029] Figure 4 A structure schematic diagram of an auxiliary data reset module provided by the embodiment of the application is provided.

[0030] Figure 5 A flowchart of a variable modulus addition operation method based on constant addition and subtraction provided by the embodiment of the application is provided.

[0031] Figure 6 A structure schematic diagram of a variable modulus addition operation device based on constant addition and subtraction provided by the embodiment of the application is provided. DETAILED DESCRIPTION

[0032] The embodiments described below with reference to the drawings are exemplary and are only used to explain the application, and cannot be explained as a limitation of the application.

[0033] The embodiment of the application first provides a variable modulus addition operation method based on constant addition and subtraction, which can be applied to electronic equipment, such as a computer terminal, specifically, a common computer, a quantum computer and the like.

[0034] The following will be described in detail by taking a computer terminal as an example. Figure 1 A hardware structure block diagram of a computer terminal for a variable modulus addition operation method based on constant addition and subtraction provided by the embodiment of the application is provided. As shown in Figure 1 illustrated, the computer terminal can include one or more ( Figure 1The computer terminal shown in the figure only includes one processor 102 (the processor 102 can include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing the variable modulus addition operation method based on constant addition and subtraction. Optionally, the computer terminal can also include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that, Figure 1 The structure shown in the figure is only schematic and does not limit the structure of the computer terminal described above. For example, the computer terminal can include more or fewer components than those shown in the figure, or have a different configuration than that shown in the figure. Figure 1 Figure 1 The structure shown in the figure is only schematic and does not limit the structure of the computer terminal described above. For example, the computer terminal can include more or fewer components than those shown in the figure, or have a different configuration than that shown in the figure.

[0035] The memory 104 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the variable modulus addition operation method based on constant addition and subtraction in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the method described above. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, and these remote memories can be connected to the computer terminal through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0036] The transmission device 106 is used to receive or send data via a network. Specific examples of the network can include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module which is used to communicate with the Internet in a wireless manner.

[0037] It should be noted that a real quantum computer is a hybrid structure, which includes two parts: one part is a classical computer responsible for performing classical computation and control; the other part is a quantum device responsible for running a quantum program to implement quantum computation. The quantum program is a sequence of instructions written in a quantum language such as QRunes language that can run on a quantum computer, which supports quantum logic gate operations and finally realizes quantum computation. Specifically, the quantum program is a sequence of instructions for operating quantum logic gates in a certain time sequence.

[0038] ​In practical applications, due to the limitation of the development of quantum device hardware, quantum computing simulation is usually needed to verify quantum algorithms, quantum applications, etc. Quantum computing simulation is a process of simulating the running of a quantum program corresponding to a specific problem by means of the resources of an ordinary computer (i.e. a quantum virtual machine). Generally, a quantum program corresponding to a specific problem needs to be constructed. The quantum program referred to in the embodiments of the present application is a program written in a classical language representing quantum bits and their evolution, in which quantum bits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.

[0039] As an embodiment of a quantum program, a quantum circuit, also known as a quantum logic circuit, is the most commonly used general quantum computing model, representing a circuit for operating on quantum bits in an abstract concept, which consists of quantum bits, a circuit (time line), and various quantum logic gates, and finally the result needs to be read out by a quantum measurement operation.

[0040] Unlike a traditional circuit which is connected by metal wires to transmit voltage signals or current signals, in a quantum circuit, the circuit can be regarded as being connected by time, that is, the state of a quantum bit naturally evolves over time, and in this process, it is operated according to the instructions of a Hamiltonian operator until it encounters a logic gate.

[0041] A quantum program as a whole corresponds to a total quantum circuit, and the quantum program described in the present application refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: a quantum program can be composed of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register for storing the measurement results, and a control flow node (jump instruction), and a quantum circuit can contain tens, hundreds or even thousands of quantum logic gate operations. The execution process of a quantum program is a process of executing all quantum logic gates in a certain time sequence. It should be noted that the time sequence is the time sequence in which a single quantum logic gate is executed.

[0042] It should also be noted that the present application relates to a quantum computer, in an ordinary computing device based on a silicon chip, the unit of the processing chip is a CMOS tube, and such a computing unit is not limited by time and environmental conditions, that is, such a computing unit is not limited by the length of use and is available at any time. In addition, at present, the number of such computing units in a silicon chip is sufficient, that is, the number of computing units in a chip is tens of thousands. The number of computing units is sufficient and the computing logic of the CMOS tube is fixed, for example: AND logic. When operating with CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the effect of operation.

[0043] Unlike the logic units in ordinary computing devices, the basic computing unit in current quantum computers is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its usage time and is not always available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is a crucial challenge. The number of qubits is also one of the representative indicators of a quantum computer's performance. Each qubit performs computational functions through on-demand configured logic functions. Given the limited number of qubits and the diverse logic functions in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum logic gates are generally represented using unitary matrices. A unitary matrix is ​​not only a matrix form but also a type of operation and transformation. In general, the action of a quantum logic gate on a quantum state is calculated by left-multiplying a unitary matrix by the matrix corresponding to the right vector of the quantum state. In quantum computing, a finite number of qubits combined with diverse logical functions achieves computational effects.

[0044] Given these differences in quantum computers, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to address. Therefore, this invention proposes a variable modular addition arithmetic unit, method, and related apparatus based on constant addition and subtraction to achieve modular addition of any two input data with a preset modulus in quantum computing.

[0045] See Figure 2 , Figure 2 This is a schematic diagram of a variable modular adder based on constant addition and subtraction provided in an embodiment of the present invention. The variable modular adder 200 includes a first adder (QAdder) 210 and a constant subtractor cascaded together. 220, the first CNOT gate 230, and the controlled constant adder ( )240, the constants in the constant subtractor 220 and the controlled constant adder 240 are both modulo numbers, and the variable modulo adder 200 is used to calculate the modulo addition result of the two input data to be added with the modulo number.

[0046] If N represents a modulus, x and y represent two data to be added, the value of x and y is an integer between [0, N-1], then the modular addition operation is x+y mod N. The quantum state corresponding to the data to be added is encoded by n quantum bits, and the number of quantum bits required by the quantum circuit corresponding to the embodiment of the present application is 2n+2, wherein .

[0047] Optionally, the four input ends 200a1, 200a2, 200a3 and 200a4 of the variable modular addition operator 200 are connected with the three input ends 210a1, 210a2 and 210a3 of the first adder 210 and one of the input ends 230a1 of the first CNOT gate 230, respectively, and the four input ends 200a1, 200a2, 200a3 and 200a4 of the variable modular addition operator 200 are used for inputting the quantum states corresponding to the two data to be added x and y, the initial calculation auxiliary data and the initial comparison auxiliary data.

[0048] Among them, the quantum bit corresponding to the encoded initial calculation auxiliary data is used to assist in the calculation of addition or subtraction, and the quantum bit corresponding to the initial comparison auxiliary data is used to assist in the calculation of comparison.

[0049] It should be noted that the input items and output items corresponding to the input ends and output ends can be quantum bits, and the data is encoded on the quantum state of the quantum bits, and each quantum logic gate acts on the quantum bits, so that the quantum state of the quantum bits evolves.

[0050] As shown in Figure 2 , x and y are both encoded by n quantum bits, to obtain the quantum state corresponding to the data to be added x and the quantum state corresponding to the data to be added y, then is input as the input item of the input end 200a1, and is input as the input item of the input end 200a2.

[0051] Among them, the initial calculation auxiliary data and the initial comparison auxiliary data can be 0 or other values, which are not limited herein. In the embodiment of the present application, the initial calculation auxiliary data and the initial comparison auxiliary data are both set to 0, and are encoded by one quantum bit, and the encoded is input as the input items of the input ends 200a3 and 200a4.

[0052] Optionally, one of the outputs 210b1 of the first adder 210 is connected with the input 220a of the constant subtractor 220, and the output 220b of the constant subtractor 220 is connected with the other input 230a2 of the first CNOT gate 230, and the two outputs 230b1 and 230b2 of the first CNOT gate 230 are connected with the two inputs 240a1 and 240a2 of the controlled constant adder 240.

[0053] Optionally, the output 220b of the constant subtractor 220 includes a data output 220bm and a sign output 220bn, and one of the inputs 240a2 of the controlled constant adder 240 includes a data input 240a2m and a sign input 240a2n, and the sign output 220bn of the constant subtractor 220 is connected with the other input 230a2 of the first CNOT gate 230, and one of the outputs 230b2 of the first CNOT gate 230 is connected with the sign input 240a2n of the controlled constant adder 240.

[0054] Optionally, the two outputs 240b1 and 240b2 of the controlled constant adder 240 are used to output the quantum states corresponding to the result of the modulo addition operation and the intermediate comparison auxiliary data respectively, and the other two outputs 210b2 and 210b3 of the first adder 210 are used to output the quantum states corresponding to one of the data to be added and the intermediate calculation auxiliary data.

[0055] In an embodiment of the present application, the four outputs 200b1, 200b2, 200b3 and 200b4 of the variable modulo addition operator 200 are connected with the two outputs 240b1 and 240b2 of the controlled constant adder 240 and the other outputs 210b2 and 210b3 of the first adder 210 respectively.

[0056] The specific principle is as follows:

[0057] Quantum state After the first adder 210, it evolves into , wherein the quantum bit corresponding to the initial calculation auxiliary data is reset to after the addition calculation of the auxiliary first adder.

[0058] Quantum state After the constant subtractor 220, it evolves into .

[0059] If , the quantum bit corresponding to the sign bit is , the first CNOT gate 230 will not be executed, and the quantum state of the comparison qubit for encoding the initial comparison auxiliary data 0 is still , the constant adder 240 will not be executed, and the modular addition operation result output by the output end 200b1 is , the quantum state corresponding to the to-be-added data y output by the output end 200b2 is , the quantum state corresponding to the intermediate calculation auxiliary data output by the output end 200b3 is , the quantum state corresponding to the intermediate comparison auxiliary data output by the output end 200b4 is ;

[0060] If , the quantum bit corresponding to the sign bit is , the first CNOT gate 230 is executed, and the quantum state of the comparison qubit for encoding the initial comparison auxiliary data 0 evolves into , the constant adder 240 is also executed, and the modular addition operation result output by the output end 200b1 is , the quantum state corresponding to the to-be-added data y output by the output end 200b2 is , the quantum state corresponding to the intermediate calculation auxiliary data output by the output end 200b3 is , the quantum state corresponding to the intermediate comparison auxiliary data output by the output end 200b4 is .

[0061] It can be seen that, for , the quantum bit corresponding to the initial comparison auxiliary data does not need to be reset and can be reused; for , the quantum bit corresponding to the initial comparison auxiliary data needs to be reset before being reused. However, both and can calculate x+ymod N.

[0062] Referring to Figure 3 , Figure 3 is another structure schematic diagram of a variable modular addition operation device based on constant addition and subtraction provided by the embodiment of the application. The variable modular addition operation device 200 comprises a modular addition operation module 200A and an auxiliary data reset module 200B which are cascaded in sequence, the modular addition operation module 200A comprises the first adder 210, the constant subtractor 220, the first CNOT gate 230 and the controlled constant adder 240, and the auxiliary data reset module 200B is used for resetting the intermediate comparison auxiliary data to the initial comparison auxiliary data.

[0063] Optionally, referring to Figure 4 , Figure 4A structural schematic diagram of an auxiliary data reset module is provided for an embodiment of the present application. The auxiliary data reset module 200B includes a subtractor 250 (QSubtractor), a first NOT gate 260, a second CNOT gate 270, a second NOT gate 280 and a second adder 290 connected in cascade, four input ends 200c1, 200c2, 200c3, 200c4 of the auxiliary data reset module 200B are connected with three input ends 250a1, 250a2, 250a3 of the subtractor 250 and one input end 270a1 of the second CNOT gate 270 respectively.

[0064] Optionally, four output ends 200d1, 200d2, 200d3, 200d4 of the auxiliary data reset module 200B are connected with three output ends 290b1, 290b2, 290b3 of the second adder 290 and one output end 270b2 of the second CNOT gate 270 respectively, the three output ends 290b1, 290b2, 290b3 of the second adder 290 are used for outputting the modulo addition operation result, one of the to-be-added data and the quantum state corresponding to the initial calculation auxiliary data, and the one output end 270b2 of the second CNOT gate 270 is used for outputting the quantum state corresponding to the initial comparison auxiliary data.

[0065] Optionally, three output ends 250b1, 250b2, 250b3 of the subtractor 250 are connected with an input end 260a of the first NOT gate 260 and two input ends 290a2, 290a3 of the second adder 290 respectively, an output end 260b of the first NOT gate 260 is connected with another input end 270a2 of the second CNOT gate 270, another output end 270b1 of the second CNOT gate 270 is connected with an input end 280a of the second NOT gate 280, and an output end 280b of the second NOT gate 280 is connected with another input end 290a1 of the second adder 290.

[0066] Optionally, one of the output ends 250b1 of the subtractor 250 includes a data output end 250b1m and a sign output end 250b1n, another input end 290a1 of the second adder 290 includes a data input end 290a1m and a sign input end 290a1n, the sign output end 250b1n of the subtractor 250 is connected with the input end 260a of the first NOT gate 260, and the output end 280b of the second NOT gate 280 is connected with the sign input end 290a1 of the second adder 290.

[0067] The specific principle is as follows:

[0068] If , the quantum state evolves to after the first NOT gate 260, the quantum state evolves to ; , the control bit of the second CNOT gate 270 is , the second CNOT gate 270 will not be executed; after the second NOT gate 280, the quantum state evolves to ; finally, after the second adder 290, the quantum state evolves to , that is, the output end 200d1 outputs , while the rest of the quantum states remain unchanged, and the output ends 200d2, 200d3 and 200d4 respectively output , ;

[0069] If , the quantum state evolves to after the subtracter 250; after the first NOT gate 260, the quantum state evolves to ; , the control bit of the second CNOT gate 270 is , the second CNOT gate 270 will be executed, and after the second CNOT gate 270, the quantum states corresponding to the intermediate comparison auxiliary data and respectively evolve to and , where the quantum state corresponding to the intermediate comparison auxiliary data is reset to ; after the second NOT gate 280, the quantum state evolves to ; finally, after the second adder 290, the quantum state evolves to , that is, the output end 200d1 outputs , while the rest of the quantum states remain unchanged, and the output ends 200d2, 200d3 and 200d4 respectively output , .

[0070] It can be seen that, compared with the previous embodiment, the auxiliary comparison bit is reset in the embodiment, so that the reset auxiliary comparison bit can be used for other calculations, saving calculation resources; meanwhile, after the auxiliary comparison bit is reset in the embodiment, it can be used for inverse calculation, realizing variable subtraction and addition operation.

[0071] It should be noted that the subtracter in the embodiment of the present application can be obtained by taking inverse of the quantum circuit corresponding to the adder, specifically, the first adder and the second adder can be realized by the adder interface QAdderIgnorecarry() in QPanda, and the subtracter can be realized by QAdderIgnorecarry().dagger().

[0072] Wherein, the adder and the subtracter can realize addition and subtraction of any two input data, while the constant adder and the constant subtracter can only realize addition and subtraction of any one input data and the constant coded in the constant adder and the constant subtracter.

[0073] Of course, the adder, the subtracter, the constant adder and the constant subtracter in the embodiment of the present application can have other implementation manners besides the specific implementation methods provided above, which are not limited herein.

[0074] Compared with the prior art, the variable modulus addition operation device provided by the present application can realize modulus addition operation of any two input data and the modulus, and can realize modulus addition operation of any two input data and the modulus preset in the variable modulus addition operation device.

[0075] Referring to Figure 5 , Figure 5 The flowchart of the variable modulus addition operation method based on constant addition and subtraction provided by the embodiment of the present application is shown. The method comprises:

[0076] Step 501: obtaining the variable modulus addition operation device and two data to be added as described in the above embodiment;

[0077] Step 502: inputting the two data to be added into the variable modulus addition operation device, and running the variable modulus addition operation device to obtain the quantum state corresponding to the modulus addition operation result of the two data to be added and the modulus;

[0078] Step 503: determining the modulus addition operation result based on the quantum state corresponding to the modulus addition operation result.

[0079] Referring to Figure 6 , Figure 6 The structure diagram of the variable modulus addition operation device based on constant addition and subtraction provided by the embodiment of the present application is shown. The device comprises:

[0080] The acquisition unit 601 is configured to acquire the variable modulus adder and two pieces of data to be added as described in the above embodiments.

[0081] The calculation unit 602 is configured to input the two pieces of data to be added into the variable modulus adder, and run the variable modulus adder to obtain a quantum state corresponding to a modulus addition result of the two pieces of data to be added and the modulus.

[0082] The determination unit 603 is configured to determine the modulus addition result based on the quantum state corresponding to the modulus addition result.

[0083] Another embodiment of the present application provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in the method embodiments of any of the above embodiments when running.

[0084] Specifically, in the present embodiment, the above storage medium can be configured to store a computer program for executing the following steps:

[0085] The acquisition unit 601 is configured to acquire the variable modulus adder and two pieces of data to be added as described in the above embodiments.

[0086] The calculation unit 602 is configured to input the two pieces of data to be added into the variable modulus adder, and run the variable modulus adder to obtain a quantum state corresponding to a modulus addition result of the two pieces of data to be added and the modulus.

[0087] The determination unit 603 is configured to determine the modulus addition result based on the quantum state corresponding to the modulus addition result.

[0088] Specifically, in the present embodiment, the above storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0089] Another embodiment of the present application also provides an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in the method embodiments of any of the above embodiments.

[0090] Specifically, the above electronic device can further include a transmission device connected with the processor and an input and output device connected with the processor.

[0091] Specifically, in the present embodiment, the above processor can be configured to execute the following steps through the computer program:

[0092] Obtain the variable modulus adder and two data to be added as described in the above embodiment;

[0093] Input the two data to be added into the variable modulus adder, and run the variable modulus adder to obtain a quantum state corresponding to the modulus addition result of the two data to be added and the modulus;

[0094] Determine the modulus addition result based on the quantum state corresponding to the modulus addition result.

[0095] The above embodiments according to the drawings illustrate the structure, features and effects of the present application. The above description is only the preferred embodiment of the present application, but the present application is not limited by the drawings. Any changes or modifications made in accordance with the concept of the present application, or equivalent embodiments with equivalent changes, are still within the scope of the present application.

Claims

1. A constant add-subtract based variable modular adder, comprising: The variable modulo addition operator comprises a first adder, a constant subtractor, a first CNOT gate, a controlled constant adder and an auxiliary data reset module connected in sequence; the constant in the constant subtractor and the controlled constant adder is a modulus, the variable modulo addition operator is used for calculating a modulo addition result of two input data to be added and the modulus, four input ends of the variable modulo addition operator are used for inputting quantum states corresponding to the two data to be added, initial calculation auxiliary data and initial comparison auxiliary data; the auxiliary data reset module comprises a subtractor, a first NOT gate, a second CNOT gate, a second NOT gate and a second adder connected in sequence, three output ends of the second adder are used for outputting the modulo addition result, quantum states corresponding to one of the data to be added and the initial calculation auxiliary data, one output end of the second CNOT gate is used for outputting a quantum state corresponding to the initial comparison auxiliary data.

2. The variable modulus modular operator of claim 1, wherein, The four input ends of the variable modulo addition operator are connected with three input ends of the first adder and one input end of the first CNOT gate.

3. The variable modulus adder of claim 2, wherein, One output end of the first adder is connected with an input end of the constant subtractor, an output end of the constant subtractor is connected with another input end of the first CNOT gate, two output ends of the first CNOT gate are connected with two input ends of the controlled constant adder.

4. The variable modulus modular adder of claim 3, wherein, The output end of the constant subtractor comprises a data output end and a sign output end, one input end of the controlled constant adder comprises a data input end and a sign input end, the sign output end of the constant subtractor is connected with another input end of the first CNOT gate, one output end of the first CNOT gate is connected with the sign input end of the controlled constant adder.

5. The variable modulus modular adder of claim 4, wherein, Two output ends of the controlled constant adder are used for outputting quantum states corresponding to the modulo addition result and intermediate comparison auxiliary data respectively, the other two output ends of the first adder are used for outputting quantum states corresponding to one of the data to be added and intermediate calculation auxiliary data.

6. The variable modulus modular adder of claim 5, wherein, Four output ends of the variable modulo addition operator are connected with two output ends of the controlled constant adder and the other two output ends of the first adder.

7. The variable modulus adder of any one of claims 1-5, wherein, The first adder, the constant subtractor, the first CNOT gate and the controlled constant adder are a modulo addition module, the auxiliary data reset module is connected with the modulo addition module and is used for resetting the intermediate comparison auxiliary data to the initial comparison auxiliary data.

8. The variable modulus modular adder of claim 7, wherein, Four input ends of the auxiliary data reset module are connected with three input ends of the subtractor and one input end of the second CNOT gate respectively, four output ends of the auxiliary data reset module are connected with three output ends of the second adder and one output end of the second CNOT gate respectively.

9. The variable modulus adder of claim 8, wherein, The three outputs of the subtractor are connected with the input of the first NOT gate and two inputs of the second adder respectively, the output of the first NOT gate is connected with another input of the second CNOT gate, another output of the second CNOT gate is connected with the input of the second NOT gate, and the output of the second NOT gate is connected with another input of the second adder.

10. The variable modulus adder of claim 9, wherein, One of the outputs of the subtractor comprises a data output and a sign output, and another input of the second adder comprises a data input and a sign input, the sign output of the subtractor is connected with the input of the first NOT gate, and the output of the second NOT gate is connected with the sign input of the second adder.

11. A method of constant add-subtract based variable modular addition operation, characterized by, The method comprises: obtaining the variable modulus adder and two data to be added according to any one of claims 1-10; inputting the two data to be added into the variable modulus adder, and running the variable modulus adder to obtain a quantum state corresponding to a modulus addition result of the two data to be added and the modulus number; determining the modulus addition result based on the quantum state corresponding to the modulus addition result.

12. A constant adder / subtracter based variable modulus adder device, characterized by The device comprises: an obtaining unit configured to obtain the variable modulus adder and two data to be added according to any one of claims 1-10; a calculating unit configured to input the two data to be added into the variable modulus adder, and run the variable modulus adder to obtain a quantum state corresponding to a modulus addition result of the two data to be added and the modulus number; a determining unit configured to determine the modulus addition result based on the quantum state corresponding to the modulus addition result.

13. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the method in claim 11 when running. 14.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to execute the method in claim 11.

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