Circuit and method for mitigating gradient effects in an image sensor

Abstract

The present disclosure relates to circuits and methods for mitigating gradient effects in image sensors. An image sensor can include a pixel array and an associated delay calibration circuit for determining an amount of delay for a row control signal. The delay calibration circuit can include circuitry for generating a calibration row control signal, circuitry for propagating the calibration row control signal along a row of dummy pixels, and one or more sampling circuits coupled to one or more tap points in the row of dummy pixels for monitoring when the calibration row control signal reaches the one or more tap points. The pixel array can output signals during normal operation. The image sensor can include column readout circuitry for reading out the signals from the pixel array. The column readout circuitry can be controlled using a progressively delayed sampling signal based on a count value output from the one or more sampling circuits.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to imaging systems, and more particularly to image sensors with large pixel arrays. BACKGROUND

[0002] Image sensors can include large pixel arrays with thousands of rows and thousands of columns. Image sensors can include row control circuitry to provide row control signals to different rows of pixels in the array via corresponding row control lines.

[0003] Designing image sensors with large pixel arrays is challenging. When the pixel array is very large, the row control lines can exhibit large RC (resistance-capacitance) time constants across the array, which can introduce considerable delays during readout or integration. These time delays can cause performance variations, such as visible gradient effects across the horizontal (row-wise) dimension of the array, or can cause loss of full well charge. Embodiments herein arise in this context. SUMMARY

[0004] According to one aspect of embodiments of the present disclosure, an image sensor is provided. The image sensor includes a pixel array and a delay calibration circuit. The delay calibration circuit includes a dummy row of pixels, a calibration row driver configured to output a row control signal to the dummy row of pixels via a row line, and a plurality of sampling circuits coupled to tap points along the row line and configured to measure a propagation delay of the row control signal along the row line.

[0005] According to another aspect of embodiments of the present disclosure, an imaging circuit is provided. The imaging circuit includes a pixel array and a delay calibration circuit. The delay calibration circuit includes a dummy row of pixels, a calibration row driver configured to output a row control signal to the dummy row of pixels via a row line, and at least one sampling circuit coupled to one or more dummy pixels in the dummy row of pixels and configured to measure a propagation delay of the row control signal along the row line.

[0006] According to yet another aspect of embodiments of the present disclosure, a method of operating an image sensor is provided. The method includes generating a calibration row control signal, propagating the calibration row control signal along a dummy row of pixels, monitoring, using one or more sampling circuits coupled to one or more tap points in the dummy row of pixels, when the calibration row control signal reaches the one or more tap points as the calibration row control signal propagates along the dummy row of pixels, outputting a signal from a pixel array separate from the dummy row of pixels, and controlling a column readout circuit to receive the signal from the pixel array using a progressively delayed sampling signal based on a count value output from the one or more sampling circuits. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a diagram of an exemplary system with an image sensor, in accordance with some embodiments.

[0008] Figure 2 is a diagram of an exemplary pixel array for reading out signals from a pixel array, and associated row and column control circuitry, in accordance with some embodiments.

[0009] Figure 3 is a timing diagram showing a scenario with mismatched column sampling errors, in accordance with some embodiments.

[0010] Figure 4 is a diagram showing exemplary delay calibration circuitry configured to calibrate control line delays across a pixel array, in accordance with some embodiments.

[0011] Figure 5 is a circuit diagram of an exemplary dummy pixel, in accordance with some embodiments.

[0012] Figure 6 is a timing diagram showing a scenario with matched column sampling errors, in accordance with some embodiments.

[0013] Figure 7 is a diagram showing exemplary bilateral delay calibration circuitry, in accordance with some embodiments.

[0014] Figure 8 is a diagram showing exemplary bilateral delay calibration circuitry with a single sampling circuit, in accordance with some embodiments. DETAILED DESCRIPTION

[0015] Embodiments of the present technology relate to image sensors. Those skilled in the art will understand that the exemplary embodiments of the present technology can be practiced with modification and alteration without one or more of the specific details described herein. In other instances, well-known operations have not been described in detail in order to avoid unnecessarily obscuring the embodiments of the present technology.

[0016] Electronic devices, such as digital cameras, computers, cellular telephones, and other electronic devices, can include image sensors that collect incoming light to capture images. Image sensors can include an array of pixels, sometimes referred to as image sensor pixels or imaging pixels. Image sensor pixels include light-sensitive elements, such as photodiodes, that convert incoming light into image signals. Image sensors can include hundreds, thousands, or millions of imaging pixels. Image sensors can include control circuitry, such as driver circuitry for selectively accessing the pixels, and readout circuitry for reading out image signals corresponding to the charge generated by the light-sensitive elements.

[0017] Figure 1is a diagram of an illustrative imaging and response system that includes an imaging system that captures images using image sensors. Figure 1 System 100 can be an electronic device such as a camera, a cellular telephone, a video camera, or other electronic device that captures digital image data, can be a vehicle safety system (e.g., an active braking system or other vehicle safety system), or can be a surveillance system.

[0018] As shown in Figure 1 System 100 can include an imaging system such as imaging system 10 and a host subsystem such as host subsystem 20. Imaging system 10 can include a camera such as camera module 12. Camera module 12 can include one or more image sensors 14 such as in an image sensor array integrated circuit and one or more lenses. Each lens can focus light onto an associated image sensor 14 during an image capture operation. Image sensor 14 can include light sensitive elements such as image sensor pixels that convert incoming light into digital data. Image sensor 14 can include hundreds of pixels, thousands of pixels, millions of pixels, or any desired number of pixels.

[0019] Each image sensor in camera module 12 can be the same, or there can be different types of image sensors in a given image sensor array integrated circuit. In some examples, image sensor 14 can also include bias circuitry, sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog to digital converter circuitry, data output circuitry, memory, buffer circuitry, and / or addressing circuitry.

[0020] Still and video image data from image sensor 14 can be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 can be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, or face detection. Image processing and data formatting circuitry 16 can additionally or alternatively be used to compress raw camera image files if desired (e.g., to Joint Photographic Experts Group or JPEG format).

[0021] In one example arrangement such as a system on a chip (SoC) arrangement, sensor 14 and image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, sensor 14 and image processing circuitry 16 can be formed on separate semiconductor substrates. For example, sensor 14 and image processing circuitry 16 can be formed on separate substrates that are vertically stacked relative to one another.

[0022] Imaging system 10 can transmit acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include input-output device 22 and storage and processing circuitry 24. Host subsystem 20 may include processing software for detecting objects in the image, detecting motion of objects between image frames, determining distances to objects in the image, or filtering or otherwise processing the image provided by imaging system 10. For example, image processing and data formatting circuitry 16 of imaging system 10 can transmit acquired image data to storage and processing circuitry 24 of host subsystem 20.

[0023] If needed, system 100 can provide users with many advanced functions. For example, in a computer or mobile phone, it can provide users with the ability to run user applications. For these functions, the input-output devices 22 of the host subsystem 20 may include a keyboard, input-output ports, buttons, a display, and storage and processing circuitry 24. The storage and processing circuitry 24 of the host subsystem 20 may include volatile memory and / or non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, etc.). The storage and processing circuitry 24 may additionally or alternatively include a microprocessor, microcontroller, digital signal processor, and / or application-specific integrated circuit.

[0024] Figure 2 It shows Figure 1 An example of the arrangement of the image sensor 14. For example... Figure 2 As shown, the image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44, sometimes referred to as control and processing logic, can provide... Figure 1 The image processing and data formatting circuitry 16 may be part of, or separate from, the image sensor 14. The image sensor 14 may include a pixel array, such as an array 32 of pixels 34. Pixel 34 is sometimes referred to herein as an image sensor pixel, imaging pixel, or image pixel. The control and processing circuitry 44 may be coupled to the row control circuitry 40 via control path 27 and to the column control and readout circuitry 42 via data path 26.

[0025] The line control circuit 40 can receive a line address from the control and processing circuit 44 and can provide the corresponding line control signal to the image pixel 34 through one or more control paths 36. The line control signal may include a pixel reset control signal, a charge transfer control signal, an overflow control signal, a line selection control signal, a double conversion gain control signal, or any other desired pixel control signal.

[0026] Column control and readout circuitry 42 can be coupled to one or more columns of pixel array 32 via one or more conductive lines, such as column lines 38. A given column line 38 can be coupled to a column of image pixels 34 in image pixel array 32 and can be used to read out image signals from image pixels 34 as well as to provide bias signals (e.g., bias currents or bias voltages) to image pixels 34. In some examples, each pixel column can be coupled to a corresponding column line 38.

[0027] For image pixel readout operations, a row of pixels in image pixel array 32 can be selected using row driver circuitry 40, and image data associated with image pixels 34 of the row of pixels can be read out on column lines 38 by column readout circuitry 42. Column readout circuitry 42 can include column circuitry such as column amplifiers for amplifying signals read out from array 32, sample and hold circuitry for sampling and storing signals read out from array 32, analog-to-digital converter circuitry for converting read out analog signals to corresponding digital signals, and / or column memory for storing readout signals and any other desired data. Column control and readout circuitry 42 can output digital pixel readout values to control and processing logic 44 over line 26.

[0028] Pixel array 32 can have any number of rows and columns. In general, the size of image pixel array 32 and the number of rows and columns in array 32 will depend on the particular implementation of image sensor 14. While “rows” and “columns” are generally described herein as horizontal and vertical, respectively, the terms row and column can be used interchangeably and can refer to any grid-like structure. Features described herein as “rows” can be arranged vertically and features described herein as “columns” can be arranged horizontally. In other embodiments, pixel array 32 can be grouped into patches or sub-regions of equal or unequal size. For example, a pixel array can be divided into four regions of equal size and area. In general, a pixel array can be divided into more than four sub-regions, four to ten sub-regions, 10 to 20 sub-regions, 20 to 50 sub-regions, or 50 to 100 sub-regions, which are independently controlled, addressed, and read out.

[0029] The pixel array 32 can have a color filter array with a plurality of color filter elements that allow a single image sensor to sample different colors of light. For example, an image sensor pixel, such as an image pixel in the array 32, can have a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels. For example, the red, green, and blue image sensor pixels can be arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of a repeating cell of 2x2 image pixels with two green image pixels opposite each other along diagonals and adjacent to a red image pixel opposite a blue image pixel along diagonals. As another example, wideband image pixels with wideband color filter elements (e.g., clear color filter elements, yellow color filter elements, etc.) can be used in place of the green pixels in the Bayer pattern. These examples are merely illustrative, and in general, color filter elements of any desired colors and in any desired pattern can be formed over any desired number of image pixels 34.

[0030] Image sensors can sometimes include very large pixel arrays. For example, a large pixel array can include thousands of columns and / or thousands of rows. As described above in connection with Figure 2 The row control circuit 40 can be used to provide row control signals to corresponding rows of pixels in the pixel array 32 via respective row control lines 36. In scenarios where each row of pixels includes thousands or tens of thousands of pixels (columns), the row control lines 36 can exhibit large RC (resistance-capacitance) time constants, which result in progressively larger time delays across the width of the pixel array 32. If not carefully managed, this time delay caused by the large RC time constants can result in a variation in the sampling error across the pixel array.

[0031] Figure 3 is a timing diagram illustrating a scenario with mismatched column sampling errors. Waveform 50 represents an output voltage waveform read out from a first column in the pixel array. Waveform 51 represents an output voltage waveform read out from a last (Nth) column in the pixel array. Due to large RC time constants on the row control signals used for readout, such as delays in the row select signal, charge transfer signal, reset signal, and / or other row control signals, the waveform 51 can experience a time lag or can be delayed relative to the waveform 50. If the column readout circuit is to sample all columns at the same time, such as at time tl as shown, Figure 3 it is clear that the sampling error for the first column will be different from the sampling error for the Nth column due to the time delay. As shown in Figure 3 the sampling error of the output signal can be defined as the voltage difference between the final steady voltage level and the sampled voltage level.

[0032] According to one embodiment, the image sensor 14 can be provided with a delay calibration circuit configured to calibrate control line delays across the large pixel array to help mitigate RC time constants on the control lines. Figure 4 is a block diagram illustrating an image sensor pixel array coupled to an illustrative calibration circuit, such as a delay calibration circuit 52. As Figure 4 shown, the pixel array 32 can be a portion of an active imaging area or region that includes pixels for capturing images, and can receive row control signals from row driver circuitry, such as row drivers 41. The row drivers 41 can be formed as Figure 2 part of the row control circuitry 40 shown. Each row of pixels in the array 32 can receive one or more row control signals from one or more row drivers 41 via a row line 36.

[0033] The delay calibration circuit 52 can include a delay calibration row 54 driven using a calibration row driver 41’. The calibration row driver 41’ is configured to generate one or more calibration row control signals. The calibration row driver 41’ can be the same as or substantially similar to the active row drivers 41 that drive the pixel array 32. The delay calibration row 54 can include a row of dummy pixels 34’. The delay calibration row 54 can be considered separate from the active imaging pixel array 32. The dummy pixels 34’ can have a pixel structure similar to or substantially the same as the image sensor pixels 34 in the active imaging pixel array 32.

[0034] Figure 5 is a circuit diagram of an illustrative dummy pixel 34’. As Figure 5 shown, the dummy pixel 34’ can include a photosensitive element, such as a photodiode PD, and a charge transfer transistor, such as a charge transfer transistor T1, having a first source-drain terminal coupled to the photodiode PD, a second source-drain terminal coupled to a floating diffusion node FD, and a gate terminal configured to receive a charge transfer control signal TX. The p-type (anode) terminal of the photodiode PD is coupled to a ground power line, sometimes also referred to as a ground line or ground. Unlike the pixels 34 in the active array portion, the photodiode PD in the dummy pixel 34’ can have its n-type (cathode) terminal shorted to a positive power line (e.g., a power terminal on which a positive power voltage VDD is provided) via a connection path 62. By shorting the cathode to VDD, any charge generated in the floating diffusion node can automatically flow into the positive power, rather than being stored within the photodiode. In other embodiments, the cathode terminal of the photodiode PD can alternatively be shorted to ground. A dummy pixel 34’ configured in this manner can be referred to and defined herein as a dark pixel, a black pixel, a replica dark pixel, or a replica black pixel. The charge transfer transistor T1 is sometimes referred to as a charge transfer gate. The floating diffusion node FD is sometimes referred to as a floating diffusion region.

[0035] Pixel 34' may also include a reset transistor T2 having a drain terminal coupled to a positive power supply line provided thereto with VDD, a source terminal coupled to a floating diffusion node FD, and a gate terminal configured to receive a reset control signal RST. When referring to the current-conducting terminals of a metal-oxide-semiconductor transistor, the terms "source" terminal and "drain" terminal are used interchangeably and are sometimes referred to as "source-drain" terminals. For example, the drain terminal of reset transistor T2 may be referred to as its first source-drain terminal, and the source terminal of reset transistor T2 may be referred to as its second source-drain terminal, or vice versa.

[0036] The dummy pixel 34' may also include a source follower transistor T3, which has a drain terminal coupled to a positive power supply line, a gate terminal coupled to a floating diffusion node FD, and a source terminal. The source follower transistor T3 is sometimes simply referred to as a "source follower". The dummy pixel 34' may also include a row select transistor T4, which has a drain terminal coupled to the source terminal of the source follower T3, a gate terminal configured to receive a row select control signal RS, and a source terminal coupled to a corresponding column line 38. The column line 38 may be coupled to more than 10 pixels in a pixel column, 10 to 100 pixels in a column, hundreds of pixels in a column, or thousands of pixels in a column. The column line 38 is sometimes referred to as a pixel output line or pixel output column line. In scenarios where the photodiode in the dummy pixel 34' is shorted to VDD, the column line 38 can be pre-charged to a low voltage, and the low-to-high voltage can be read. In a scenario where the photodiode in dummy pixel 34' is short-circuited to ground, column line 38 can be pre-charged to a high voltage, and the high-to-low voltage can be read. In the latter scenario where the high-to-low voltage is read, a very low noise (VLN) current source can be connected to column line 38 to pull down the voltage on line 38 during readout operations.

[0037] exist Figure 5 In the example, transistors T1-T4 may all be n-type metal-oxide-semiconductor (NMOS) transistors. In other embodiments, at least some of transistors T1-T4 may optionally be implemented as p-type metal-oxide-semiconductor (PMOS) transistors. In other embodiments, dummy pixel 34' may optionally include four or more n-channel and / or p-channel transistors.

[0038] exist Figure 5In the example, dummy pixel 34' includes four transistors T1-T4, which is merely illustrative. Generally, dummy pixel 34' may include the same number of components as imaging pixel 34 in array 32. In other embodiments, imaging pixel 34 and dummy pixel 34' may each include multiple photodiodes coupled to a shared floating diffusion node, fewer than four transistors, more than four transistors, five or more transistors, six or more transistors, one or more storage capacitors, one or more storage nodes, one or more mode switching transistors, multiple conversion gain components, Bloom control components, and / or other pixel structures. Imaging pixel 34 and dummy pixel 34' may be rolling shutter type pixels or global shutter type pixels, such as pixels including additional storage nodes coupled between photodiodes and the floating diffusion region.

[0039] Return to reference Figure 4 The delay calibration circuit 52 may also include sampling circuits such as sampling circuits 56-1, 56-2, and 56-3, interpolation blocks such as interpolation circuit 58, and delay generators such as column sampling signal (delay) generator 60. For example, each of the sampling circuits 56-1, 56-2, and 56-3 may be implemented as a time-to-digital converter (TDC) including an analog-to-digital converter (ADC) and a counter circuit coupled in series. Other types of time-to-digital converters may be implemented if desired. The ADC in each time-to-digital converter 56 may receive a reference voltage Vref, which is set to simulate the expected voltage level at each dummy pixel 34'. Each time-to-digital converter 56 may also receive a reference clock signal CLKref, which may include a start pulse for synchronization with the calibration row driver 41' to simultaneously begin conversion across calibration rows 54.

[0040] The calibration line driver 41' can output one or more line signals to the calibration line 54 via line line 36'. The calibration line driver 41' can be configured to output a line selection signal to the line selection transistor T4 in each dummy pixel 34' (see...). Figure 5 The charge transfer signal is output to the charge transfer gate T1 in each dummy pixel 34', the reset signal is output to the reset transistor T2 in each dummy pixel 34', and / or can be configured to output other row control signals through row line 36'. The same voltage value can be read from each dummy pixel 34' in row 54. Since the photodiode in each dummy pixel 34' is shorted to VDD, the same high value can be read from each dummy pixel 34' as the row control signal propagates along row line 36'.

[0041] The sampling circuit 56 can be coupled to each tap point in the calibration row 54. Figure 4In the example of FIG. 4, the first TDC 56-1 is coupled to the first (leading) dummy pixel 34' in the calibration row 54; the second TDC 56-1 is coupled to the center (middle) dummy pixel 34' in the calibration row 54; and the third TDC 56-3 is coupled to the last (trailing) dummy pixel 34' in the calibration row 54. Configured in this way, the counter circuit in each TDC 56 can be used to measure the amount of time that has elapsed between the start pulse in the signal CLKref and the arrival of the row control signal output from the row driver 41' at each respective tap (sampling) point. As the row control signal propagates along the length of the row line 36', the count value or delay should increase from left to right. The count values output by the counters of each TDC 56 can optionally be stored for post-processing to determine the amount of propagation delay across the calibration row 54.

[0042] In certain embodiments, the interpolation circuit 58 can be configured to receive the stored count values from each sampling circuit 56. In the example of FIG. 4, in which three sampling circuits 56 are used, the interpolation circuit 58 can be configured to perform a first linear interpolation between the count values output from circuits 56-1 and 56-2, and a second linear interpolation between the count values output from circuits 56-2 and 56-3. This example, in which the delay calibration circuit 52 includes three sampling circuits 56, is merely illustrative. Figure 4

[0043] In another embodiment, the delay calibration circuit 52 can include only two sampling circuits 56. In this embodiment, a first TDC can be coupled to a first tap point at a first (leading) dummy pixel 34' in the calibration row, while a second TDC can be coupled to a second tap point at a last (trailing) dummy pixel 34' in the calibration row. In this example, in which two sampling circuits 56 are used, the interpolation circuit 58 can be configured to perform only one linear interpolation between the count values output from the first and second TDCs. This example, in which the delay calibration circuit 52 includes two sampling circuits 56, is merely illustrative.

[0044] ​In another embodiment, the delay calibration circuit 52 can include four sampling circuits 56. In this embodiment, a first TDC can be coupled to a first tap point at a first (leading) dummy pixel 34' in the calibration row, a second TDC can be coupled to a second tap point at a dummy pixel 34' located three-quarters of the way along the row line 36', a third TDC can be coupled to a third tap point at a dummy pixel 34' located two-thirds of the way along the row line 36', and a fourth TDC can be coupled to a fourth tap point at a last (trailing) dummy pixel 34' in the calibration row. In this example where four sampling circuits 56 are used, the interpolation circuit 58 can be configured to perform a first linear interpolation between count values output from the first and second TDC circuits, a second linear interpolation between count values output from the second and third TDC circuits, and a third linear interpolation between count values output from the third and fourth TDC circuits.

[0045] This example of the delay calibration circuit 52 including four sampling circuits 56 is merely illustrative. A greater number of sampling circuits 56 can help provide improved delay calibration accuracy. In general, the delay calibration circuit 52 can include two or more sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', three or more sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', four or more sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', four to ten sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', or more than ten sampling circuits 56 distributed evenly or unevenly along the calibration row line 36'.

[0046] The interpolated values output from the interpolation circuit 58 can be fed to a column sampling signal generator 60. The column sampling signal generator 60 can generate corresponding sampling signals by progressively delaying the sampling signals fed to each column readout circuit in the circuit 42 based on the interpolated values. For example, the generator 60 can output a first sampling signal S1 for controlling the column readout circuit to read out signals from a first column of pixels of the array 32, a second sampling signal S2 for controlling the column readout circuit to read out signals from a second column of pixels of the array 32, a third sampling signal S3 for controlling the column readout circuit to read out signals from a third column of pixels of the array 32, and so on, and an Nth sampling signal SN for controlling the column readout circuit to read out signals from a last (Nth) column of pixels in the array 32 based on the interpolated values. The column readout circuit receiving the sampling signals S1 : SN can include column amplifiers, column analog-to-digital converters, column memory circuits, and / or other column readout components. In other words, the sampling signals S1 : SN can be progressively delayed by an amount similar to the amount detected or observed by the delay calibration circuit 52.

[0047] Progressively delaying the column sampling signals in this way can help equalize column sampling errors between different columns of pixels in the image sensor. Figure 6This is a timing diagram illustrating a scenario with matched column sampling error. Waveform 51 represents the output voltage waveform read from the first column of the pixel array. Waveform 53 represents the output voltage waveform read from the last (Nth) column of the pixel array. Due to the large RC time constant on the row control signals used for reading, such as delays in the row selection signal, charge transfer signal, reset signal, and / or other row control signals, waveform 53 may experience a time lag or may be delayed relative to waveform 51.

[0048] like Figure 6 As shown, the first column can be sampled using sampling signal S1 at time t1, and the last (Nth) column can be sampled using sampling signal SN at time t2. The delay between time t1 and t2 can be calculated using the method described above. Figure 4 The described delay calibration circuit 52 determines this. Operating in this manner, the sampling error of the first column can be substantially equal to or match the sampling error of the last column and every other column in the pixel array. Therefore, this technique is technically advantageous by improving image uniformity across the pixel array, reducing unwanted gradient artifacts in readout, and can help assist various types of fault analysis algorithms.

[0049] The delay calibration circuit 52 can perform such calibration operations every frame, every N frames (where N equals 2, 3, 4, 5, 2-10, or greater than 10), or as needed. The delay calibration circuit 52 includes a calibration line 54 driven by a calibration line driver 41' for dummy pixels 34'. Figure 4 The examples are also illustrative. Generally, the delay calibration circuit 52 may include one or more calibration rows 54 driven by one or more line drivers 41'. In another embodiment, the delay calibration circuit 52 may include two calibration rows of dummy pixels 34' driven by two line drivers 41'. In another embodiment, the delay calibration circuit 52 may include three calibration rows of dummy pixels 34' driven by three line drivers 41'. In yet another embodiment, the delay calibration circuit 52 may include more than three calibration rows of dummy pixels 34' driven by more than three line drivers 41'. In this case, random or similar averaging methods may be applied.

[0050] The pixel array 32 is driven by a row driver 41 from one side of the array, and the calibration row 54 is driven by a calibration row driver 41' from one side of the array. Figure 4 The embodiments described are exemplary and are not intended to limit the scope of the embodiments of the invention. Figure 7 Another embodiment is shown, in which the image pixel array 32 is driven by a row driver from the opposite side (edge). For example... Figure 7As shown, the pixel array 32 is controlled in part by row signals generated by row drivers 41-1 disposed on a first (left) side of the array, and in part by row signals generated by row drivers 41-2 disposed on a second (right) side of the array. Driving row control signals from both sides of the pixel array 32 can help to halve the worst-case RC time constant across the array.

[0051] The delay calibration circuit 52 can include a calibration row 54 that is driven using a first calibration row driver 41'-1 disposed on a first (left) side of the calibration row 54, and a second calibration row driver 41'-2 disposed on a second (right) side of the calibration row 54. The calibration row drivers 41'-1 and 41'-2 can be the same as or substantially similar to the active row drivers 41-1 and 41-2 that drive the pixel array 32. The delay calibration row 54 can include a row of dummy pixels 34' of the type shown, or other types of dummy or black pixels having a structure similar to the active imaging pixels in the array 32. Figure 5 The delay calibration row 54 can include a row of dummy pixels 34' of the type shown, or other types of dummy or black pixels having a structure similar to the active imaging pixels in the array 32.

[0052] Figure 7 The delay calibration circuit 52 can also include sampling circuits such as sampling circuits 56-1, 56-2, and 56-3, an interpolation circuit 58, and a column sample signal (delay) generator 60. For example, each of the sampling circuits 56-1, 56-2, and 56-3 can be implemented as a time-to-digital converter (TDC) including an analog-to-digital converter (ADC) and a counter circuit coupled together in series. In some examples, the analog-to-digital converter can be a 1-bit ADC or a comparator. Other types of time-to-digital converters can be implemented if desired. The ADC in each time-to-digital converter 56 can receive a reference voltage Vref that is set to analog the expected voltage level at each dummy pixel 34'. Each time-to-digital converter 56 can also receive a reference clock signal CLKref that can include a start pulse for synchronization with the calibration row drivers 41' to start conversions simultaneously across the calibration row 54.

[0053] The calibration row drivers 41'-1 and 41'-2 can output one or more row signals to the calibration row 54 via the row lines 36'. The calibration row drivers 41'-1 and 41'-2 can be configured to output a row select signal to a row select transistor T4 (see FIG. 2) in each dummy pixel 34' to enable the dummy pixel 34' to receive a voltage from the row line 36' to which the row select transistor T4 is coupled. The calibration row drivers 41'-1 and 41'-2 can also be configured to output a reset signal to a reset transistor T3 (see FIG. 2) in each dummy pixel 34' to reset the voltage on the row line 36' to which the reset transistor T3 is coupled. Figure 5The calibration line driver 41'-1 outputs a charge transfer signal to the charge transfer gate T1 in each dummy pixel 34', outputs a reset signal to the transistor T2 in each dummy pixel 34', and / or can be configured to output other line control signals via line 36'. The same voltage value can be read from each dummy pixel 34' in line 54. Since the photodiode in each dummy pixel 34' is shorted to VDD or ground depending on the presence of a VLN current source, the same high or low value can be read from each dummy pixel 34' as the line control signal propagates along line 36'. The line control signal output from calibration line driver 41'-1 propagates along line 36' from left to right, while the line control signal output from calibration line driver 41'-2 propagates along line 36' from right to left. Calibration line drivers 41'-1 and 41'-2 can be enabled and / or disabled simultaneously, independently at different times, or in an interleaved manner.

[0054] The sampling circuit 56 can be coupled to each tap point in the calibration row 54. Figure 7 In the example, the first TDC 56-1 is coupled to the first (leading) dummy pixel 34' in calibration row 54; the second TDC 56-1 is coupled to the center (middle) dummy pixel 34' in calibration row 54; and the third TDC 56-3 is coupled to the last (tailing) dummy pixel 34' in calibration row 54. Configured in this way, TDCs 56-1 and 56-2, or other sampling circuitry associated with the left half of the calibration row, can be used to measure the amount of time it takes for the row control signal to propagate from the left edge of the array to the center point from the row driver 41'-1. Similarly, TDCs 56-2 and 56-3, or other sampling circuitry associated with the right half of the calibration row, can be used to measure the amount of time it takes for the row control signal to propagate from the right edge of the array to the center point from the row driver 41'-2. In other words, the count value or delay should increase from left to center, and the count value or delay should increase from right to center. The count values ​​output by the counters of each TDC 56 may optionally be stored for post-processing to determine the amount of propagation delay across the delay calibration line 54.

[0055] In some implementations, the interpolation circuit 58 may be configured to receive a stored count value from each sampling circuit 56. Three sampling circuits 56 are shown in the illustration. Figure 7The example of five sampling circuits 56 distributed evenly along the calibration row line 36' is merely illustrative. In other implementations, the delay calibration circuit 52 can include five sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', seven sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', nine sampling circuits 56 distributed evenly or unevenly along the calibration row line 36', eleven sampling circuits distributed evenly or unevenly along the calibration row line 36', eleven sampling circuits to one hundred and one sampling circuits distributed evenly or unevenly along the calibration row line 36', or other odd number of sampling circuits. A greater number of sampling circuits 56 can help provide improved delay calibration accuracy. If desired, the delay calibration circuit 52 can also include an even number of sampling circuits. The interpolation circuit 58 can be configured to perform one or more interpolation operations using the count values obtained from the sampling circuits 56 associated with the left half of the calibration row 54. The interpolation circuit 58 can be configured to perform one or more interpolation operations using the count values obtained from the sampling circuits 56 associated with the right half of the calibration row 54.

[0056] The interpolated values output from the interpolation circuit 58 can be fed to the column sample signal generator 60. The column sample signal generator 60 can generate corresponding sample signals by progressively delaying the sample signals fed to each column readout circuit in the circuit 42 based on the interpolated values. The sample signals output by the generator 60 can be progressively delayed from left to center and right to center by an amount similar to that detected or observed by the delay calibration circuit 52. Progressively delaying the column sample signals in this manner can help equalize column sample errors between different pixel columns in the image sensor. Thus, by improving image uniformity across the pixel array, this technique is technically advantageous by reducing unwanted gradient artifacts in the readout, and can help assist various types of fault analysis algorithms. The delay calibration circuit 52 can perform such calibration operations once per frame, once every N frames (where N equals 2, 3, 4, 5, 2-10, or greater than 10), or as desired.

[0057] where the delay calibration circuit 52 includes one calibration row 54 of dummy pixels 34' driven using the calibration row drivers 41'-1 and 41'-2 Figure 7The examples are illustrative. Generally, the delay calibration circuit 52 may include one or more calibration rows 54 driven by one or more row drivers 41' on both sides of the array. In another embodiment, the delay calibration circuit 52 may include two calibration rows of dummy pixels 34' driven by two row drivers 41'-1 located at the left edge of the array and two row drivers 41'-2 located at the right edge of the array. In another embodiment, the delay calibration circuit 52 may include three calibration rows of dummy pixels 34' driven by three row drivers 41'-1 located at the left edge of the array and three row drivers 41'-2 located at the right edge of the array. In another embodiment, the delay calibration circuit 52 may include more than three calibration rows of dummy pixels 34' driven by more than three row drivers 41'-1 located at the left edge of the array and more than three row drivers 41'-2 located at the right edge of the array.

[0058] The delay calibration circuit 52 includes multiple sampling circuits 56. Figure 7 The embodiments described are exemplary and are not intended to limit the scope of the embodiments of the invention. Figure 8 Another implementation is shown in which the delay calibration circuit 52 is driven from the opposite end, but only a single sampling circuit 56' is used.

[0059] like Figure 8 As shown, the pixel array 32 can be partially controlled by row signals generated by row drivers 41-1 located on the first (left) periphery of the array, and partially controlled by row signals generated by row drivers 41-2 located on the second (right) periphery edge of the array. Driving the row control signals from the two edges of the pixel array 32 helps to halve the worst-case RC time constant across the array.

[0060] The delay calibration circuit 52 may include a calibration row 54 driven by a first calibration row driver 41'-1 disposed on a first (left) outer peripheral edge of the calibration row 54 and a second calibration row driver 41'-2 disposed on a second (right) outer peripheral edge of the calibration row 54. The delay calibration row 54 may include a combination of... Figure 5 A row of dummy pixels 34' of the type shown, or other types of dummy pixels or dark pixels with a structure similar to the active imaging pixels in array 32.

[0061] Figure 8The delay calibration circuit 52 may also include only a sampling circuit, such as a sampling circuit 56', an interpolation circuit 58, and a column sampling signal (delay) generator 60. For example, the sampling circuit 56' may be implemented as a time-to-digital converter (TDC) that includes an analog-to-digital converter (ADC) and a counter circuit coupled in series. Other types of time-to-digital converters may be implemented if desired. The ADC in the time-to-digital converter 56' may receive a reference voltage Vref, which is set to simulate the expected voltage level at each dummy pixel 34'. The time-to-digital converter 56' may also receive a reference clock signal CLKref, which may include a start pulse for synchronization with the calibration row drivers 41'-1 and 41'-2 to simultaneously begin conversion across calibration rows 54.

[0062] Calibration line drivers 41'-1 and 41'-2 can output one or more line signals to calibration line 54 via line line 36'. Calibration line drivers 41'-1 and 41'-2 can be configured to output line selection signals to line selection transistor T4 in each dummy pixel 34' (see [link to documentation]). Figure 5 The calibration row driver 41'-1 outputs a charge transfer signal to the charge transfer gate T1 in each dummy pixel 34', outputs a reset signal to the transistor T2 in each dummy pixel 34', and / or can be configured to output other row control signals via row line 36'. The same voltage value can be read from each dummy pixel 34' in the calibration row 54. Since the photodiode in each dummy pixel 34' is shorted to VDD or ground, the same low-to-high or high-to-low value can be read from each dummy pixel 34' as the row control signal propagates along row line 36'. The row control signal output from calibration row driver 41'-1 propagates along row line 36' from left to right, while the row control signal output from calibration row driver 41'-2 propagates along row line 36' from right to left.

[0063] exist Figure 8 In this configuration, sampling circuit 56' is positioned at a center location equidistant from row drivers 41'-1 and 41'-2, coupled to the left calibration row driver 41'-1 via a first direct connection path 62-1, and coupled to the right calibration row driver 41'-2 via a second direct connection path 62-2. Because sampling circuit 56' is formed at the midpoint between the two calibration row drivers, the propagation delay of line 62-1 will be substantially equal to the propagation delay of line 62-2. Lines 62-1 and 62-2 may have equal lengths. In other words, lines 62-1 and 62-2 can be considered balanced routing paths with the same propagation delay.

[0064] During the first calibration phase, left column driver 41'-1 can be activated while right column driver 41'-2 is disabled. During this first calibration phase, the column control signal output from column driver 41'-1 can propagate through path 62-1 and reach TDC 56' to record a first count value. The column control signal can also propagate from left to right along column line 36', and then from right to left through path 62-2 to reach TDC 56' to record a second count value during the first calibration phase. Assuming equal propagation of paths 62-1 and 62-2, the difference between the first and second count values can be calculated to determine the amount of propagation delay across delay calibration column 54.

[0065] During the second calibration phase, left column driver 41'-1 can be disabled while right column driver 41'-2 is activated. During this second calibration phase, the column control signal output from driver 41'-2 can propagate through path 62-2 and reach TDC 56' to record a third count value. The column control signal can also propagate from right to left along column line 36', and then from left to right through path 62-1 to reach TDC 56' to record a fourth count value during the second calibration phase. Assuming matching propagation of paths 62-1 and 62-2, the difference between the third and fourth count values can be calculated to determine the amount of propagation delay across delay calibration column 54. The propagation delays calculated from the first and second calibration phases can optionally be averaged to obtain a final delay value. This example in which calibration column drivers 41'-1 and 41'-2 are activated at different times is illustrative. In other embodiments, calibration column drivers 41'-1 and 41'-2 can be enabled and / or disabled simultaneously or in an interleaved manner. The count values output by the counters of each TDC 56 can optionally be stored for post-processing to determine the amount of propagation delay across delay calibration column 54.

[0066] In certain embodiments, the delay calculation and arithmetic circuit 59 can be configured to receive the stored count values from the sampling circuit 56'. The delay calculation and arithmetic circuit 59 can be configured to calculate a difference value based on the count values acquired during the first calibration phase or the second calibration phase. The resulting difference value or delay value can be fed to the column sampling signal generator 60. The column sampling signal generator 60 can generate corresponding sampling signals by gradually delaying the sampling signals fed to each column readout circuit in the circuit 42 based on the calculated difference value. If desired, the amount of delay can also be generated by interpolating the difference value. The sampling signals output by the generator 60 can be gradually delayed from left to middle and right to middle by an amount similar to that detected or observed by the delay calibration circuit 52. Gradually delaying the column sampling signals in this manner can help to equalize the column sampling error between different pixel columns in the image sensor. Thus, by improving the image uniformity across the pixel array, this technique is technically advantageous by reducing unwanted gradient artifacts in the readout, and can help to assist various types of fault analysis algorithms. The delay calibration circuit 52 can perform such calibration operations once per frame, once every N frames (where N equals 2, 3, 4, 5, 2-10, or greater than 10), or as desired.

[0067] where the delay calibration circuit 52 includes one calibration row 54 of dummy pixels 34' driven using calibration row drivers 41'-1 and 41'-2 Figure 8 Examples of the above are illustrative. In general, the delay calibration circuit 52 can include one or more calibration rows 54 of dummy pixels 34' driven using one or more row drivers 41' disposed on either side of the array. In another embodiment, the delay calibration circuit 52 can include two calibration rows of dummy pixels 34' driven by two row drivers 41'-1 disposed on the left edge of the array and two row drivers 41'-2 disposed on the right edge of the array. In another embodiment, the delay calibration circuit 52 can include three calibration rows of dummy pixels 34' driven by three row drivers 41'-1 disposed on the left edge of the array and three row drivers 41'-2 disposed on the right edge of the array. In another embodiment, the delay calibration circuit 52 can include more than three calibration rows of dummy pixels 34' driven by more than three row drivers 41'-1 disposed on the left edge of the array and more than three row drivers 41'-2 disposed on the right edge of the array. In this case, a random or similar averaging method can be applied.

[0068] According to one embodiment, an image sensor including a pixel array and a delay calibration circuit is provided. The delay calibration circuit can include a row of dummy pixels, a calibration row driver configured to output a row control signal to the row of dummy pixels via a row line, and a plurality of sampling circuits coupled to tap points along the row line and to measure a propagation delay of the row control signal along the row line.

[0069] According to another embodiment, the plurality of sampling circuits can optionally include a plurality of time-to-digital converters.

[0070] According to another embodiment, at least one of the plurality of time-to-digital converters can optionally include an analog-to-digital converter and a counter.

[0071] According to another embodiment, at least one dummy pixel can optionally include a photodiode having an anode coupled to a ground power line and a cathode coupled to a positive power line or the ground power line.

[0072] According to another embodiment, the plurality of sampling circuits can optionally include a first sampling circuit coupled to a leading dummy pixel in a row of dummy pixels, a second sampling circuit coupled to a middle dummy pixel in the row of dummy pixels, and a third sampling circuit coupled to a last dummy pixel in the row of dummy pixels.

[0073] According to another embodiment, the plurality of sampling circuits can optionally include a plurality of sampling circuits coupled to tap points evenly distributed along a row line.

[0074] According to another embodiment, the delay calibration circuit can further include an interpolation circuit configured to receive count values from the plurality of sampling circuits.

[0075] According to another embodiment, the delay calibration circuit can further optionally include a column sampling signal delay generator configured to receive interpolated values from the interpolation circuit and generate sampling signals progressively delayed relative to one another based on the interpolated values.

[0076] According to another embodiment, the image sensor can further optionally include a column readout circuit configured to receive signals from the array of pixels and controlled by the sampling signals generated by the column sampling signal delay generator.

[0077] According to another embodiment, the delay calibration circuit can further optionally include an additional calibration row driver configured to output an additional row control signal to a row of dummy pixels via a row line.

[0078] According to another embodiment, the calibration row driver is optionally disposed at a first end of the row of dummy pixels and the additional calibration row driver is optionally disposed at a second end opposite the first end of the row of dummy pixels.

[0079] According to another embodiment, the delay calibration circuit can further optionally include an additional row of dummy pixels and an additional calibration row driver configured to output an additional row control signal to the additional row of dummy pixels via an additional row line.

[0080] According to one embodiment, there is provided an imaging circuit comprising a pixel array and a delay calibration circuit having a row of dummy pixels, a calibration row driver configured to output a row control signal to the row of dummy pixels via a row line, and at least one sampling circuit coupled to one or more dummy pixels in the row of dummy pixels and for measuring a propagation delay of the row control signal along the row line.

[0081] According to another embodiment, the delay calibration circuit can optionally further comprise an additional row of dummy pixels and an additional calibration row driver configured to output an additional row control signal to the additional row of dummy pixels via an additional row line.

[0082] According to another embodiment, the at least one dummy pixel can optionally comprise a photodiode having an anode coupled to a first power supply line and a cathode coupled to a second power supply line different from the first power supply line.

[0083] According to another embodiment, the at least one sampling circuit can be a time-to-digital converter comprising an analog-to-digital converter and a counter.

[0084] According to another embodiment, the at least one sampling circuit is optionally coupled to a leading dummy pixel in the row of dummy pixels via a first path and to a last dummy pixel in the row of dummy pixels via a second path. The first path and the second path are optionally of equal length.

[0085] According to another embodiment, the delay calibration circuit can optionally comprise a delay computation and arithmetic circuit configured to receive count values from the at least one sampling circuit and configured to compute difference values based on the received count values, and a column sample signal delay generator configured to generate sample signals progressively delayed relative to each other based on the computed difference values.

[0086] According to another embodiment, the imaging circuit can optionally further comprise a column readout circuit configured to receive signals from the pixel array and controlled by the sample signals generated by the column sample signal delay generator.

[0087] According to one embodiment, there is provided a method of operating an image sensor, the method comprising generating a calibration row control signal; propagating the calibration row control signal along a row of dummy pixels; using one or more sampling circuits coupled to one or more tap points in the row of dummy pixels, monitoring when the calibration row control signal reaches the one or more tap points as the calibration row control signal propagates along the row of dummy pixels; outputting signals from a pixel array separate from the row of dummy pixels; and controlling a column readout circuit to receive signals from the pixel array using progressively delayed sample signals based on count values output from the one or more sampling circuits.

[0088] The foregoing is merely illustrative, and various modifications can be made to the embodiments described. The embodiments described can be implemented individually or in any combination.

Claims

1. An image sensor, comprising: a pixel array; and a delay calibration circuit, comprising a dummy pixel row, a calibration row driver configured to output a row control signal to the dummy pixel row via a row line, and a plurality of sampling circuits coupled to tap points along the row line and to measure a propagation delay of the row control signal along the row line.

2. The image sensor of claim 1, wherein the plurality of sampling circuits comprises a plurality of time-to-digital converters.

3. The image sensor of claim 2, wherein at least one of the plurality of time-to-digital converters comprises an analog-to-digital converter and a counter.

4. The image sensor of claim 1, wherein at least one dummy pixel comprises a photodiode having an anode coupled to a ground power line and a cathode coupled to a positive power line or the ground power line.

5. The image sensor of claim 1, wherein the plurality of sampling circuits comprises only: a first sampling circuit coupled to a leading dummy pixel in the dummy pixel row; a second sampling circuit coupled to a middle dummy pixel in the dummy pixel row; and a third sampling circuit coupled to a last dummy pixel in the dummy pixel row.

6. The image sensor of claim 1, wherein the plurality of sampling circuits comprises a plurality of sampling circuits coupled to a subset of dummy pixels in the dummy pixel row.

7. The image sensor of claim 1, wherein the delay calibration circuit further comprises: an interpolation circuit configured to receive count values from the plurality of sampling circuits.

8. The image sensor of claim 7, wherein the delay calibration circuit further comprises: a column sample signal delay generator configured to receive interpolation values from the interpolation circuit and generate sample signals progressively delayed relative to one another based on the interpolation values.

9. The image sensor of claim 8, further comprising: a column readout circuit configured to receive signals from the pixel array and controlled by the sample signals generated by the column sample signal delay generator.

10. The image sensor of claim 1, wherein the delay calibration circuit further comprises: an additional calibration row driver configured to output an additional row control signal to the dummy pixel row via the row line.

11. The image sensor of claim 10, wherein the calibration row driver is disposed at a first end of the dummy pixel row, and wherein the additional calibration row driver is disposed at a second end of the dummy pixel row opposite the first end.

12. The image sensor of claim 1, wherein the delay calibration circuit further comprises: an additional dummy pixel row; and an additional calibration row driver configured to output an additional row control signal to the additional dummy pixel row via an additional row line.

13. An imaging circuit, comprising: a pixel array; and a delay calibration circuit, comprising a dummy pixel row, a calibration row driver configured to output a row control signal to the dummy pixel row via a row line, and a plurality of sampling circuits coupled to tap points along the row line and to measure a propagation delay of the row control signal along the row line. a delay calibration circuit, the delay calibration circuit comprising a dummy pixel row, a calibration row driver configured to output a row control signal to the dummy pixel row via a row line, and at least one sampling circuit coupled to one or more dummy pixels in the dummy pixel row and to measure a propagation delay of the row control signal along the row line.

14. The imaging circuit of claim 13, wherein the delay calibration circuit further comprises: an additional dummy pixel row; and an additional calibration row driver configured to output an additional row control signal to the additional dummy pixel row via an additional row line.

15. The imaging circuit of claim 13, wherein at least one dummy pixel comprises a photodiode having an anode coupled to a first power supply line and a cathode coupled to a second power supply line different from the first power supply line.

16. The imaging circuit of claim 13, wherein the at least one sampling circuit comprises a time-to-digital converter comprising an analog-to-digital converter and a counter.

17. The imaging circuit of claim 13, wherein the at least one sampling circuit is coupled to a leading dummy pixel in the dummy pixel row via a first path and to a last dummy pixel in the dummy pixel row via a second path, and wherein the first path and the second path have equal lengths.

18. The imaging circuit of claim 17, wherein the delay calibration circuit further comprises: a delay calculation and arithmetic circuit configured to receive count values from the at least one sampling circuit and configured to calculate a difference value based on the received count values; and a column sampling signal delay generator configured to generate sampling signals progressively delayed relative to each other based on the calculated difference value.

19. The imaging circuit of claim 18, further comprising: a column readout circuit configured to receive signals from the pixel array and controlled by the sampling signals generated by the column sampling signal delay generator.

20. A method of operating an image sensor, the method comprising: generating a calibration row control signal; propagating the calibration row control signal along a dummy pixel row; monitoring, using one or more sampling circuits coupled to one or more tap points in the dummy pixel row, when the calibration row control signal reaches the one or more tap points as the calibration row control signal propagates along the dummy pixel row; outputting signals from a pixel array separate from the dummy pixel row; and controlling a column readout circuit to receive the signals from the pixel array using progressively delayed sampling signals based on count values output from the one or more sampling circuits. ​

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