Multi-channel synchronous analysis system and signal processing method for analyzing global navigation satellite system signals

Abstract

A device includes: an antenna, an RF path, an analog-to-digital converter (ADC), a filter, and a navigation channel that processes received GNSS signals based on a navigation clock. A communication modem is configured to receive signals via a first antenna, a first RF path, and a first ADC and process the received signals based on a modem clock to generate signals. The communication modem is also configured to transmit signals via an (R + 1)th RF path and a digital-to-analog converter (DAC) using an (R + 1)th antenna based on the modem clock. A multi-channel synchronous signal analysis system (MSSAS) receives the output of the ADC and processes the output signal of the ADC using a plurality of decimators and a plurality of data receivers. Each of the decimators in the decimators is configured to process the output of the ADC and output data to one of the plurality of data receivers. A CPU is configured to control all devices.

Description

Technical Field

[0001] The present disclosure generally relates to multi-channel systems and signal processing methods for signal analysis, and more particularly, to systems that perform signal spectrum analysis, interference search, verification of input digital-to-analog paths, and processing of digitized input signals. Background Art

[0002] Acquiring, identifying, and reducing interference in GNSS satellite signals at a GNSS receiver can take a significant amount of time. Various techniques for performing time-domain and frequency-domain signal processing in the time domain and frequency domain to reduce the required time are known. In one method, a spectrum analyzer can act as a fast Fourier transform (FFT), and the spectrum analyzer can be used to reduce interference in the positioning mode. Other methods use an interference suppressor consisting of an FFT module, an interference detection and nulling processor module, an IFFT module, a correlator module, filters, delay modules, decimators, and correlators. There is a need for a method for reducing the time required to acquire and identify GNSS signals that requires fewer and less expensive hardware components than is typically required. Summary of the Invention

[0003] In one embodiment, the input of a first receiving antenna receives a signal from a communication modem. The received signal is transmitted through a first RF path and digitized in a first analog-to-digital converter (“ADC”). The digitized signal output of the first ADC is input to a multiplexer. The output of the first ADC is also input to the communication modem, where the output of the first ADC is processed. The signal from the output of the communication modem is input to a digital-to-analog converter (“DAC”), and then input to an RF path connected to the DAC. The signal from the output of the RF path connected to the DAC is sent to a transmitting antenna. In one embodiment, the receiving antenna and the transmitting antenna can be replaced by a single transceiver antenna.

[0004] The input of a second receiving antenna receives a Global Navigation Satellite System (“GNSS”) signal, which is then transmitted through a second RF path and digitized in a second ADC connected to the second RF path. The digitized signal from the output of the second ADC enters the multiplexer. The output of the second ADC also enters a filter, and then is input to a navigation channel, where the signal input to the navigation channel is processed. In one embodiment, the signal from the RF path can be transmitted from a single antenna.

[0005] In one embodiment, multiple filters may be used at the input of one or more ADCs, such as a second ADC being connected to one of the multiple filters. The outputs of the multiple filters are provided to the input of the navigation channel. In one embodiment, the multiple filters are controlled by the CPU.

[0006] Depending on the implemented device, the antenna, RF path, and ADC may be used to receive various signals, such as corrections for GNSS and / or modem corrections. In one embodiment, the signal is received at the input of the receiving antenna, transmitted through the RF path, and digitized in the ADC. Then the output of the ADC is input to the multiplexer.

[0007] In one embodiment, a multi-channel synchronous signal analysis system ("MSSAS") is also part of the device, and the multi-channel synchronous signal analysis system ("MSSAS") is configured to receive the outputs of the ADC and process these outputs using multiple decimators, each decimator being configured to output data to one of the corresponding multiple data receivers.

[0008] In one embodiment, the CPU initializes and controls the following components: the communication modem, filters, navigation channel, multiplexer, and MSSAS.

[0009] In one embodiment, the apparatus includes: a first antenna configured to receive a signal; a first RF path for receiving the signal from the first antenna and processing the signal received from the first antenna; a first ADC for receiving the processed signal from the first RF path and digitizing the processed signal; a communication modem configured to receive the digitized signal from the first ADC and process the digitized signal based on a modem clock to generate a first processed signal, the communication modem further configured to transmit the first processed signal, and the communication modem further configured to transmit the first processed signal to a DAC to cause the DAC to convert the first processed signal from a digital signal to an analog signal and transmit the first processed analog signal via the R+1 RF path to the R+1 antenna. A second antenna is configured to receive a GNSS signal, and a second RF path is configured to receive the GNSS signal from the second antenna and process the GNSS signal. A second ADC is configured to receive the processed GNSS signal from the second RF path and digitize the processed GNSS signal, and a filter is configured to receive the digitized GNSS signal from the second ADC and filter the digitized GNSS signal. A navigation channel is configured to receive the filtered GNSS signal from the filter and process the filtered GNSS signal. The R-th antenna is for receiving a signal, and the R-th RF path is configured to receive the signal from the R-th antenna and process the signal from the R-th antenna based on the R-th clock (where the R-th clock may be a system clock or other clock) to generate a second processed signal. The R-th ADC is configured to receive the second processed signal from the R-th RF path and digitize the second processed signal. The MSSAS is configured to receive the outputs of the first ADC, the second ADC, and the R-th ADC, and the MSSAS is configured to process the outputs of the first ADC, the second ADC, and the R-th ADC using a plurality of decimators, each decimator being configured to output data to one of a corresponding plurality of data receivers. The CPU is configured to control: the first RF path, the second RF path, the R-th RF path, and the R+1 RF path; the first ADC, the second ADC, and the R-th ADC; the DAC; the communication modem; the filter; the navigation channel; and the MSSAS. Description of the Drawings

[0010] Figure 1 Shows a receiver according to an embodiment;

[0011] Figure 2 Shows according to an embodiment Figure 1 Detailed diagram of the multi-channel synchronous signal analysis system shown in

[0012] Figure 3 shows a detailed diagram of a converter module (referred to as A2A) as shown in Figure 2 ; a timing diagram according to an embodiment; and

[0013] Figure 4 a detailed diagram of a preparation unit according to an embodiment.

[0014] Figure 5 DETAILED DESCRIPTION

[0015] Figure 1 shows a schematic diagram of a Global Navigation Satellite System (GNSS) receiver 1 according to an embodiment. In one embodiment, the receiver 1 includes a plurality of antennas 100(1), 100(2), …, 100(R), 100(R + 1) (collectively referred to as antennas 100). Each antenna 100 communicates with a corresponding one of the RF paths 101(1), 101(2), 101(R), … 101(R + 1). The RF paths 100(1), 100(2), … 100(R) each communicate with a corresponding one of the analog-to-digital converters (ADCs) 103(1), 103(2), …, 103(R). The RF path 101(R + 1) communicates with a digital-to-analog converter (DAC) 102. The DAC 102 communicates with a communication modem 104, and the communication modem 104 communicates with a CPU 109. The ADC 103(1) communicates with the communication modem 104 and a multiplexer 111. The ADC 103(2) communicates with the multiplexer 111 and a filter 105, and the filter 105 communicates with a navigation channel 106 and the CPU 109. The navigation channel 106 also communicates with the CPU 109. The ADC 103(R) communicates with the multiplexer 111. The R ADCs are similarly connected to the multiplexer 111. The multiplexer 111 communicates with the CPU 109 and a multi-channel synchronization signal analysis system (MSSAS) 107, and the multi-channel synchronization signal analysis system (MSSAS) 107 also communicates with the CPU 109. The multiplexer 111 transmits signals S100(1)…S100(N) including an ADC data bus and signals S112(1)…S112(N) including an ADC clock signal to the MSSAS 107.

[0016] In one embodiment, the receiver 1 operates as follows. The GNSS signal from the satellite arrives at the antenna 100(2), and reaches the ADC 103(2) through the RF path 101(2). The digitized signal is input to the filter 105 and the multiplexer 111. The signal passes through the filter 105 and is input to the navigation channel 106, where the signal is processed.

[0017] The signal is received by the antenna 100(1) and input to the ADC 103(1) via the RF path 101(1). The digitized signal output from the ADC 103(1) is then input to the communication modem 104 and the digitized signal is processed. In one embodiment, the communication modem 104 acts as a receiver and transmitter of data. The communication modem 104 generates a signal that is transmitted to the DAC 102, and the DAC 102 transmits the signal to the antenna 100(R+1) through the RF path 101(R+1). The digitized signal output from the ADC103(1) is also input to the multiplexer 111.

[0018] The signal is also received by the antenna 100(R) and reaches the ADC 103(R) through the RF path 101(R). The digitized signal output from the ADC 103(R) is input to the multiplexer 111.

[0019] The digitized signals and the ADC clock from the ADC 103(1)…103(R) are input and manipulated by the multiplexer 111. In the multiplexer 111, the output data and clock of each of the ADC(1)…ADC(R) are processed, and are respectively output as signals S100(1)…S100(N) and signals S112(1)…S112(N). The signals S100(1)…S100(N) and the signals S112(1)…S100(N) from the multiplexer 111 are input to the multi-channel synchronous analysis system (MSSAS) 107. In the MSSAS107, the signals from the ADC 103(1)…ADC 103(R) are further processed as described below.

[0020] In one embodiment, the CPU 109 controls the operations of the communication modem 104, the filter 105, the navigation channel 106, the multiplexer 111, and the MSSAS107. In one embodiment, the user can achieve data exchange with the CPU 109 via the communication module 110.

[0021] In one embodiment, components of the receiver operate at different frequencies (e.g., clock speeds generated by one or more crystal oscillators): the ADC 103(1), communication modem 104, and DAC 102 operate at the communication clock CLKcom; the ADC 103(2), filter 105, and navigation channel 106 operate at the navigation clock CLKnav; the ADC 103(R) operates at the system clock CLKsys or another clock CLKother.

[0022] In one embodiment, when receiving data streams from the ADC 103(1)…ADC 103(R), a portion of the MSSAS107 operates at the ADC clock (CLKadc), and another portion of the MSSAS 107 operates at CLKsys. After the data and the ADC 103(1)…ADC 103(R) clocks have passed through the multiplexer 111, CLKcom, CLKnav, CLKother, and CLKsys can be sources of the clock CLKadc. The data received by the MSSAS107 is resynchronized from the clock CLKadc to the clock CLKsys, and the signal is processed at the clock CLKsys.

[0023] For example, if GNSS signal processing is required, the data from the filter 105, navigation channel 106, and ADC 103(2) is input to the MSSAS107, and the clock CLKnav serves as the clock CLKadc. The size of the ADC 103 data bus is equal to A bits, where A is a positive integer. The signals S100(1)…S100(N) have an A-bit capacity.

[0024] In one embodiment, the MSSAS107 can partially perform the functions of the communication modem 104. For example, the hardware for the MSSAS107 can include additional processing capabilities to also perform operations related to the communication modem 104. When the MSSAS107 includes additional processing capabilities, the communication modem 104 can include weaker processing capabilities, and when the MSSAS107 does not include additional processing capabilities, the communication modem 104 can include stronger processing capabilities.

[0025] Figure 2 A detailed diagram of the multi-channel synchronous signal analysis system (MSSAS) 107 shown in Figure 1 the embodiment is shown. The MSSAS107 is configured to analyze input signals during the operation of the communication modem 104 and during the processing of GNSS signals for, e.g., interference suppression.

[0026] In one embodiment, MSSAS 107 includes primary ADC data processors / processors (A2A) 200(1)…200(N), and the primary ADC data processors / processors (A2A) 200(1)…200(N) communicate with each other, with A2A 200, CPU 109, bus 204, and multiplexer 111. Each of A2A 200(1)…200(N) also communicates with a corresponding one of decimators 201(1), 201(2), …, 201(N). Each of decimators 201(1), 201(2), …, 201(N) also communicates with CPU 109 and bus 204. Bus 204 communicates with CPU 109, memory 202, and mixed-radix discrete Fourier transforms (MRD) 203(1), 203(2), … 203(M). Priority signals S200(1), S200(2), …, S200(N) are transmitted and received among A2A 200(1)…200(N). Enable signals S201(1), S201(2), …, S201(N) from each of A2A 200(1), A2A 200(2), …, A2A 200(N) are transmitted to their respective corresponding decimators 201(1), 201(2), …, 201(N).

[0027] For the following description, CPU 109, memory 202, and MRD 203 will be referred to as "data receivers", meaning that these devices receive data. A2A 200(1), A2A 200(2), …, A2A 200(N) (collectively referred to as "A2A 200") are preliminary processors of data from ADCs 103(1)…ADCs 103(R) (collectively referred to as "ADC 103"). A2A 200 converts the data from ADC 103 into the format required by the data receivers. In one embodiment, packet data is the output data stream from A2A 200, and packet data is defined as a set of data received from the ADC and transmitted via one of A2A 200(1), A2A 200(2), …, A2A 200(N) to any data receiver. The minimum packet data size of X-bit data is equal to the width of bus 204. If necessary, some service information can be added to the packet data from A2A 200 (e.g., at least X bits). CPU 109 can change the configuration of the packet data and the data receivers during the operation of A2A 200. Note that in one embodiment, the new settings of A2A 200 are considered valid after the packet data is sent. When operating with memory 202, A2A 200 allocates a starting address and an ending address. The recording of the packet data starts from the starting address, and when the ending address is reached, the next recording is made according to the starting address, i.e., circular recording of the address space of memory 202.

[0028] Decimators 201(1), 201(2), …, 201(N) (collectively referred to as "decimator 201") use different decimation factors from 1 to 64 to decimate signals and transmit the signals to any data receiver via bus 204. The data processing in the decimator 201 can be synchronized with the A2A 200. In one embodiment, the data output from the decimator 201 is referred to as decimated packet data having a minimum size of X bits.

[0029] The decimator 201 processes the data from the ADC 103 in a mode independent of the A2A 200, where the size of the decimated packet data is determined by the CPU 109 and does not depend on the synchronization signal S201. In the case of operating synchronously with the A2A 200, the decimator 201 receives the data from the ADC 103 and processes the data from the ADC 103 if the synchronization signal S201 is available.

[0030] The CPU 109 can change the configuration of the decimated packet data and the data receiver during operation with the decimator 201. The new settings of the decimator 201 are effective after the decimated packet data is completed.

[0031] MRDs 203(1), 203(2), … 203(N) (collectively referred to as "MRD 203") are blocks with forward and reverse complex FFT / DFT support. The MRD 203 places the result of the data processing in a location based on the indicated address. The MRD 203 is capable of placing the result of the data processing into the CPU 109 or the memory 202. The first data in the received packet data is service data that sets the operating mode of the MRD.

[0032] In one embodiment, the AXI interconnect architecture is used for the bus 204. This architecture ensures a high data transfer rate and fast access to data.

[0033] In one embodiment, the MSSAS107 operates as follows. The CPU 109 starts and controls the following components: A2A200, decimator 201, and MRD 203.

[0034] Signals S100(1), S100(2), …, S100(N) (collectively referred to as signal S100) are each input to the corresponding A2A200 and decimator 201. In the A2A 200 and the decimator 201, the data is processed and then transmitted via the bus 204 to other locations and / or devices.

[0035] The enabling signals S201(1), S201(2), …, S201(N) (collectively referred to as the enabling signal S201) from the A2A 200 are input to the extractor 201. The enabling signal S201 provides the possibility of synchronous data processing in the A2A 200 and the extractor 201. The priority signals S200 from each A2A 200 are input to each A2A 200. During initialization, the A2A 200 selects one of the signals S200, which defines the priority and works with the A2A 200. If the thus selected signals S200(1), S200(2), …, S200(N) (collectively referred to as the priority signal S200) are available, the A2A 200 transmits the packet data and generates the selection signal S200 based on the current number of A2As. The priority signal S200 is used for multiple A2A200s working together. When using the priority signal S200, the first unit A2A200 is started by the CPU 109, and then the A2A 200s are started according to the priority signal S200. When not using the priority signal S200, the A2A 200s are run by the CPU 109.

[0036] The MRD 203 receives data from each A2A 200 and the extractor 201 via the bus 204 and processes the data. The CPU 109 receives data from each A2A 200, the extractor 201, the MRD 203, and the memory 202 via the bus 204 and processes the data. The memory 202 receives data from any of the A2A 200, the extractor 200, and the MRD 203 via the bus 204. The A2A 200 and the extractor 201 resynchronize the data from the ADC 103 from the clock CLKadc to the clock CLKsys.

[0037] In one embodiment, the size of the bus 204 is equal to X bits. Data of size A bits from the ADC 103 is fed to the inputs of the A2A 200 and the extractor 201. X-bit data is output from the A2A 200 and the extractor 201 (the data width of the bus 204 is X bits).

[0038] If the CPU 109 shuts down the A2A 200, the A2A200 will only shut down after the packet data has been completely transmitted. If the CPU 109 shuts down the extractor 201, the extractor 201 will only shut down after the extracted packet data has been completely transmitted.

[0039] In one embodiment, the operating mode of each in the unit A2A 200 is as follows.

[0040] 1) The A2A 200 operates individually / separately with a specified number of packet data.

[0041] Before operation, the CPU 109 activates the A2A 200. Then, the A2A sends a preset number of packet data to any data receiver, and then the A2A is turned off.

[0042] 2) The A2A 200 operates individually with an unlimited number of packet data.

[0043] Before operation, the CPU 109 activates the A2A 200. Then, the A2A sends an unlimited number of packet data to any data receiver. If necessary, the CPU 109 turns off the A2A 200.

[0044] 3) The A2A 200 operates jointly with a specified number of packet data.

[0045] The CPU 109 is programmed as follows:

[0046] A) The number of units 200 required to operate in the joint mode;

[0047] B) Determine the priority order of the units 200 by means of the signal S200; and

[0048] C) The pattern of the specified number of packet data.

[0049] The A2A 200 alternately sends single packet data. After sending the packet data, a signal S200 is generated in the A2A 200. The A2A 200 waits for the priority signal S200 to send the next packet data. If the A2A 200 has sent the specified number of single packet data, the A2A 200 is turned off.

[0050] 4) The A2A 200 operates jointly with an unlimited number of packet data.

[0051] The CPU 109 is programmed as follows:

[0052] A) The number of units 200 required to operate in the joint mode;

[0053] B) Determine the priority order of the units 200 by means of the signal S200; and

[0054] C) The pattern of the unlimited number of packet data.

[0055] The A2A 200 alternately sends single packet data. After sending the packet data, a signal S200 is generated in the A2A 200. The A2A 200 waits for the priority signal S200 to send the next single packet data. If necessary, the CPU 109 turns off the A2A 200.

[0056] In one embodiment, the operating mode of the extractor 201 is as follows.

[0057] 1) The extractor 201 operates independently of the A2A 200 and generates a specified number of extracted packet data. Before the operation, the CPU 109 starts the extractor 201. The extractor 201 then sends the specified number of extracted packet data to any data receiver, and then shuts down the extractor 201.

[0058] 2) The extractor 201 operates independently of the A2A 200 and generates an unlimited number of extracted packet data. Before the operation, the CPU 109 starts the extractor 201. The extractor 201 then sends the unlimited number of extracted packet data to any data receiver, and if necessary, the CPU 109 shuts it down.

[0059] 3) The extractor 201 operates synchronously with the A2A 200 and generates a specified number of extracted packet data. Before the operation, the CPU 109 starts the extractor 201 and the A2A 200. If the synchronization signal S201 is available, the extractor 201 sends the specified number of extracted packet data to any data receiver, and then shuts down the extractor 201. The A2A 200 sends the specified number of packet data to any data receiver, and then the A2A 200 shuts down. In one embodiment, when operating in the MRD working mode, the packet data may only include service data for the MRD, and the service data is sent before the data from the extractor.

[0060] 4) The extractor 201 operates synchronously with the A2A 200 and generates an unlimited number of extracted packet data. Before the operation, the CPU 109 starts the extractor 201 and the A2A 200. If the synchronization signal S201 is available, the extractor 201 sends the unlimited number of extracted packet data to any data receiver. If necessary, the CPU 109 shuts it down. The A2A 200 sends the unlimited number of packet data to any data receiver, and then the CPU 109 shuts it down. In one embodiment, when operating in the MRD working mode, the packet data may only include service data for the MRD, and the service data is sent before the data from the extractor.

[0061] Figure 3 Shows Figure 2 A detailed diagram of the A2A 200 shown in. In one embodiment, the A2A 200 includes a preformatting unit 300 communicating with an asynchronous dual-clock first-in first-out (FIFO) unit 301, and the asynchronous dual-clock first-in first-out (FIFO) unit 301 communicates with a preparation unit 302.

[0062] The pre-formatting unit 300 pre-prepares data. In one embodiment, the pre-formatting unit 300 can transform / convert the input A-bit data from the ADC 103 into W-bit output data in any of the following ways: zero-extend the most significant bit; extend the most significant bit one by one; sign-bit extension; big-endian / little-endian; or byte permutation / byte swap.

[0063] The FIFO unit 301 realizes the resynchronization of the data from the ADC 103 from the clock CLKadc to the clock CLKsys. The FIFO unit 301 generates an X-bit word from Nword input W-bit words. The following formula is used: X = W * Nword, where: Nword is any non-fractional number, provided that the result X is a multiple of 2n.

[0064] The size of the FIFO unit 301 is selected such that the A2A 200 generates packet data one by one, and there is enough time for these packet data to be processed by the data receiver and for the CPU 109 to process the results obtained in the memory 202 and the MRD 203, so that the FIFO unit 301 does not overflow. The size of the FIFO unit 301 is selected such that data is not lost. The pre-formatting unit 300 and the FIFO unit 301 are also installed in the extractor 201.

[0065] The preparation unit 302 processes the data output from the FIFO unit 301 and generates packet data. In addition, the preparation unit 302 generates X-bit data for the bus 204. The input parts of the pre-formatting unit 300 and the FIFO unit 301 operate with the clock CLKadc. The output parts of the preparation unit 302 and the FIFO unit 301 operate with the clock CLKsys.

[0066] In one embodiment, the A2A 200 operates as follows. The CPU 109 controls the following components: the pre-formatting unit 300, the FIFO unit 301, and the preparation unit 302. During the initialization of the preparation unit 302, the FIFO unit 301 is turned off. After running the preparation unit 302, the FIFO unit 301 is turned on to generate packet data. The data from the ADC 103 passes through the multiplexer 111 and is input to the pre-formatting unit 300. The pre-formatting unit 300 pre-prepares the data. The data from the pre-formatting unit 300 is input to the FIFO unit 301, and the data from the FIFO unit 301 is input to the preparation unit 302, where the data is processed.

[0067] If the A2A 200 operates synchronously with the extractor 201, the preparation unit 302 generates a synchronization signal S201. The signal S201 output from the preparation unit 302 is input to the extractor 201. The data output from the preparation unit 302 is transmitted to the data receiver via the bus 204.

[0068] If there are some combined operations of the A2A 200, the preparation unit 302 generates a signal S200. The preparation unit 302 waits for the priority signal S200 and then generates packet data.

[0069] Figure 4 A timing diagram showing the synchronous operation of the A2A 200 and the extractor 201 is shown.

[0070] In one embodiment, in the synchronous mode, the data from the ADC 103 is simultaneously input to the A2A 200 and the extractor 201. The digitized symbols output from the ADC 103 are input to the A2A 200 and the extractor 201, and the digitized symbols output from the ADC 103 are processed in the A2A 200 and the extractor 201 and then sent to the data receiver. The A2A 200 is allocated as follows: packet data = Q slots, slot = F packet data, and packet data = 1 symbol.

[0071] The size of the packet data is set by the packet data counter 401. The packet data counter 401 counts the number of X-bit words equal to the symbol. The size of the slot is set by the slot counter. The slot counter counts the number of packet data. The size of the packet data is set by the packet data counter. The packet data counter counts the number of slots.

[0072] In the data stream from the FIFO unit 301, there are symbols for the input packet data including time stamps. The packet data generated by the A2A 200 is called reference packet data. When S201 is invalid and the extractor 201 ignores the input data, the prefix is a programmable part of the input packet data. The transmission data is a part of the input packet data, and when S201 is valid, the input packet data is processed in the extractor 201. The time stamp allows the input packet data and the reference packet data to be synchronized

[0073] When processing the input packet data (one symbol), the A2A 200 generates a data stream that can be supplemented by service data. For example, the service data can set the packet data quantity value for the data receiver, and the service data can set the address where the MRD 203 can place the result. In one embodiment, the packet data consists of a prefix and a transmission enable signal.

[0074] In one embodiment, the following operations are performed. The size parameters of the packet data, slots, and packet data in A2A 200 are set before the operation of CPU 109. A2A 200 processes the data and adds the data to the memory (or CPU). CPU 109 processes the data from A2A 200 and determines the boundary offset of the reference packet data and the input packet data relative to each other. In order to align / adjust the reference packet data and the input packet data, there is service data in the packet data from A2A 200. In order to adjust the reference packet data and the input packet data in extractor 201, an estimated delay can be used, which delays the generation of signal S201. During the time of the estimated delay, the data arriving at extractor 201 is ignored. The estimated delay is used once in the process of synchronizing the reference packet data and the input packet data.

[0075] CPU 109 adjusts extractor 201. CPU 109 also adjusts the estimated delay in A2A 200, the prefix delay, the size of the transmission data, and the data receiver in preparation unit 302. Then, A2A 200 and extractor 201 implement the processing of the data from ADC 103. If necessary, CPU 109 can reconfigure the operation of A2A 200 to synchronize it with extractor 201. The new settings of A2A 200 are applied after the end of the packet data transmission.

[0076] Figure 5 The details of preparation unit 302 are shown. Preparation unit 302 includes packet data generator 400, packet data counter 401, slot counter 402, packet data counter 403, and transmission data counter 404. In one embodiment, CPU 109 controls packet data generator 400, packet data counter 401 via packet data generator 400 (i.e., CPU 109 programs packet data counter 401 via packet data generator 400), slot counter 402 via packet data generator 400, packet data counter 403 via packet data generator 400, and transmission data counter 404.

[0077] In one embodiment, the initialization of preparation unit 302 occurs as follows. During initialization, CPU 109 adjusts the operation mode of packet data generator 400 (corresponding to the operation mode of A2A 200), packet data counter 401 via packet data generator 400, slot counter 402 via packet data generator 400, packet data counter 403 via packet data generator 400, FIFO unit 301, and preformatting unit 300. According to the operation mode of packet data generator 400, extractor 201, the data receiver, and A2A 200 can also be initialized.

[0078] Once the packet data generator 400 starts generating packet data / wrapped data, the FIFO unit 301 is turned on. The data from the ADC 103 is transmitted through the multiplexer 111 and fed to the pre-formatting unit 300. The pre-formatting unit 300 preliminarily prepares the data. The data from the pre-formatting unit 300 is input to the FIFO unit 301. The data from the FIFO unit 301 is input to the packet data generator 400, where the data is processed. During the operation of the packet data generator 400 for generating packet data, the following counters are used: the wrapped data counter 401, the slot counter 402, and the packet data counter 403.

[0079] If the packet data generator 400 operates synchronously with the extractor 201, the packet data generator 400 generates the synchronization signal S201. The signal S201 from the output of the packet data generator 400 is fed to the input of the extractor 201. The data from the output of the packet data generator 400 is fed to the data receiver via the bus 204.

[0080] If multiple A2A 200 modules operate jointly, the packet data generator 400 generates the signal S200. When using the priority signal S200, the CPU 109 starts the first unit packet data generator 400 and then starts the packet data generator 400 according to the priority signal S200. The packet data generator 400 waits for the priority signal S200 and then generates packet data. When not using the priority signal S200, the packet data generator 400 is run by the CPU 109. The transmission data counter 404 counts the number of X-bit words transmitted to the memory 202 of the packet data generator 400. The CPU 109 reads the data counter 404 during its operation, obtains a portion of the data from the memory 202 and processes it. Thereafter, the CPU 109 subtracts the number of the processed data from the memory 202 from the number in the transmission data counter 404.

[0081] The foregoing detailed description should be understood to be illustrative and exemplary in every respect and not restrictive, and the scope of the inventive concept disclosed herein is not determined by the detailed description but by the claims as interpreted in accordance with the full scope permitted by patent law. It should be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concept, and those skilled in the art can implement various modifications without departing from the scope and spirit of the inventive concept. Without departing from the scope and spirit of the inventive concept, those skilled in the art can achieve various other combinations of features.

Claims

1. An apparatus for analyzing global navigation satellite signals, the apparatus comprising: a first antenna configured to receive signals; a first RF path configured to receive signals from the first antenna and process the signals received from the first antenna; a first ADC configured to receive the processed signals from the first RF path and digitize the processed signals; a communication modem configured to receive the digitized signals from the first ADC, and the communication modem is configured to process the digitized signals based on a modem clock to generate a first processed signal, the communication modem is further configured to transmit the first processed signal, and the communication modem is further configured to transmit the first processed signal to a DAC such that the DAC converts the first processed signal from a digital signal into an analog signal and transmits the first processed analog signal via an R+1 RF path to an R+1 antenna; a second antenna configured to receive GNSS signals; a second RF path configured to receive the GNSS signals from the second antenna and process the GNSS signals; a second ADC configured to receive the processed GNSS signals from the second RF path and digitize the processed GNSS signals; a filter configured to receive the digitized GNSS signals from the second ADC and filter the digitized GNSS signals; a navigation channel configured to receive the filtered GNSS signals from the filter and process the filtered GNSS signals; an Rth antenna for receiving signals; an Rth RF path configured to receive signals from the Rth antenna, and the Rth RF path is configured to process the signals received from the Rth antenna based on an Rth clock to generate a second processed signal; an Rth ADC configured to receive the second processed signal from the Rth RF path and digitize the second processed signal; a multi-channel synchronous signal analysis system configured to receive the outputs of the first ADC, the second ADC, and the Rth ADC, and the multi-channel synchronous signal analysis system is configured to process the outputs of the first ADC, the second ADC, and the Rth ADC using a plurality of decimators, each decimator being configured to output data to one of a corresponding plurality of data receivers; and A CPU, which is configured to control the following: the first RF path, the second RF path, the Rth RF path, and the (R + 1)th RF path; the first ADC, the second ADC, and the Rth ADC; the DAC; the communication modem; the filter; the navigation channel; and the multi-channel synchronization signal analysis system.

2. The device according to claim 1, wherein The multi-channel synchronization signal analysis system is further configured to process the output of the ADC, and the multi-channel synchronization signal analysis system is further configured to resynchronize the output of the ADC to the system clock using an asynchronous FIFO unit.

3. The device according to claim 1, wherein, In the multi-channel synchronization signal analysis system, the data and clock signals received from any ADC are first transformed and then the received data and clock signals are processed.

4. The device according to claim 1, wherein The multi-channel synchronization signal analysis system is configured to decimate the signals from the ADC and further process the decimated signals.

5. The device according to claim 1, wherein The multi-channel synchronization signal analysis system is further configured to synchronize the decimated and undecimated signals from the ADC.

6. The apparatus according to claim 2, wherein The asynchronous FIFO unit is configured to process the entire data stream.

7. The device according to claim 1, wherein, The received data is controlled by service data.

8. The device according to claim 1, wherein The portions of the digitized signals generated by each of the ADCs are deleted after decimation.

9. The device according to claim 1, wherein The multi-channel synchronization signal analysis system processes the digitized signals from multiple ADCs simultaneously.

10. The device according to claim 1, wherein The multi-channel synchronization signal analysis system is further configured to process the undecimated signals from the ADC.

11. A method for analyzing global navigation satellite signals, the method comprising: generating a signal at a communication modem based on a modem clock using a signal received via a first RF path and a first ADC from a first antenna; transmitting the signal generated by the communication modem based on the modem clock to a (R + 1)th antenna via a DAC and a (R + 1)th RF path; generating a processed signal at a navigation channel by processing a filtered signal received from a filter, the filter receiving a digitized GNSS signal from a second ADC communicating with a second RF path and filtering the received digitized GNSS signal, the second RF path processing a GNSS signal based on a navigation clock, the GNSS signal being received from a second antenna that receives GNSS signals; digitizing a signal received at an Rth ADC via an Rth RF path from an Rth antenna, the Rth RF path being configured to process a signal based on an Rth clock; Receive the output of the first ADC, the output of the second ADC, and the output of the Rth ADC at a multi-channel synchronous signal analysis system, the multi-channel synchronous signal analysis system being configured to process the output of the first ADC, the output of the second ADC, and the output of the Rth ADC using a plurality of decimators, each decimator being configured to output data to one of a corresponding plurality of data receivers; And Control the following by the CPU: the first RF path, the second RF path, the Rth RF path, and the (R + 1)th RF path; the first ADC, the second ADC, and the Rth ADC; the DAC; the communication modem; the filter; the navigation channel; And the multi-channel synchronous signal analysis system.

12. The method according to claim 11, wherein, The output of the ADC is input to the multi-channel synchronous signal analysis system, the multi-channel synchronous signal analysis system further being configured to process the output of the ADC and resynchronize the output of the ADC to the system clock using an asynchronous FIFO unit.

13. The method according to claim 11, wherein In the multi-channel synchronous signal analysis system, the data and clock signals received from any ADC are first transformed and then the received data and clock signals are processed.

14. The method according to claim 11, wherein, The multi-channel synchronous signal analysis system is configured to decimate the signals from the ADC and further process the decimated signals.

15. The method according to claim 11, wherein, The multi-channel synchronous signal analysis system is further configured to synchronously process the decimated and undecimated signals from the ADC.

16. The method according to claim 12, wherein The asynchronous FIFO unit is configured to process the entire data stream.

17. The method according to claim 11, wherein Control is performed on the data received by the service data interface.

18. The method according to claim 11, wherein, After decimation, the portions of the digitized signals generated by each of the ADCs are deleted.

19. The method according to claim 11, wherein, The multi-channel synchronous signal analysis system simultaneously processes the digitized signals from multiple ADCs.

20. The method according to claim 11, wherein, The multi-channel synchronous signal analysis system is further configured to process the undecimated signals from the ADC.

21. An apparatus for analyzing global navigation satellite signals, the apparatus comprising: A communication modem configured to receive digitized signals from a first ADC, the first ADC communicating with a first RF path and a first antenna for receiving signals, the communication modem being configured to process the digitized signals based on a modem clock to generate a first processed signal, the communication modem further being configured to transmit the first processed signal to a DAC communicating with an (R + 1)th RF path and an (R + 1)th antenna; A navigation channel configured to process the filtered GNSS signals received from a filter, the filter being configured to receive the digitized GNSS signals from a second ADC and filter the received digitized GNSS signals, the second ADC being configured to receive GNSS signals from a second RF path and digitize the received GNSS signals, the second RF path communicating with a second antenna for receiving the GNSS signals; An R-th antenna configured to receive signals and transmit the signals via an R-th RF path, the R-th RF path being configured to process the signals based on an R-th clock and transmit a second processed signal to an R-th ADC, the R-th ADC being configured to digitize the second processed signal; A multi-channel synchronous signal analysis system configured to receive the outputs of the first ADC, the second ADC, and the R-th ADC, and the multi-channel synchronous signal analysis system being configured to process the outputs of the first ADC, the second ADC, and the R-th ADC using a plurality of decimators, each decimator being configured to output data to one of a corresponding plurality of data receivers; And A CPU configured to control: the first RF path, the second RF path, the R-th RF path, and the (R + 1)-th RF path; the first ADC, the second ADC, and the R-th ADC; the DAC; the communication modem; the filter; the navigation channel; And the multi-channel synchronous signal analysis system.

22. The device according to claim 21, wherein, The output of the ADC is input to the multi-channel synchronous signal analysis system, and the multi-channel synchronous signal analysis system is further configured to process the output of the ADC and resynchronize the output of the ADC to the system clock using an asynchronous FIFO unit.

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