Array substrate, manufacturing method thereof, mask plate and display device

Abstract

The embodiment of the present disclosure provides a mask, an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a substrate and a via hole arranged on one side of the substrate, wherein: the via hole comprises a first structure and a second structure surrounding the first structure, and the first structure and the second structure have different light transmittances; the first structure has a substantially rectangular orthographic projection on the substrate and has a plurality of straight sides; the second structure has a substantially octagonal orthographic projection on the substrate, the second structure comprises a plurality of first sub-structures and a plurality of second sub-structures, the first sub-structure has a strip-shaped orthographic projection on the substrate, the first sub-structure is arranged in parallel with the straight sides of the first structure one by one, and the second sub-structure has a tile-shaped orthographic projection on the substrate; the second sub-structure is located between two adjacent first sub-structures and connects the adjacent first sub-structures.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to an array substrate and its fabrication method, a photomask, and a display device. Background Technology

[0002] An array substrate includes a substrate and multiple conductive elements disposed on the substrate, such as signal lines, pixel electrodes, etc. These conductive elements are disposed in multiple layers, and when conductive elements in different layers need to be electrically connected, vias are used to achieve this connection. Summary of the Invention

[0003] This disclosure provides an array substrate, a method for fabricating the same, a photomask, and a display device.

[0004] This disclosure provides an array substrate, including a substrate and a via disposed on one side of the substrate, wherein: the via includes a first structure and a second structure surrounding the first structure, and the first structure and the second structure have different light transmittance;

[0005] The first structure has a roughly rectangular orthographic projection onto the substrate and has multiple straight sides;

[0006] The second structure has an orthographic projection on the substrate that is approximately octagonal. The second structure includes multiple first substructures and multiple second substructures. The orthographic projection of the first substructure on the substrate is strip-shaped. The first substructure is arranged parallel to the straight edges of the first structure in a one-to-one correspondence. The orthographic projection of the second substructure on the substrate is tile-shaped. The second substructure is located between two adjacent first substructures and connects the adjacent first substructures.

[0007] In some embodiments, the orthographic projection of the first structure onto the substrate is a right-angled rectangle or a rounded rectangle.

[0008] In some embodiments, the orthographic projection of the first structure onto the substrate is a rounded rectangle, and includes a plurality of straight sides and an arcuate side connecting adjacent straight sides;

[0009] The two ends of the arc-shaped side have a first included angle between the line connecting the center of the rounded rectangle and the line connecting the two ends of the arc-shaped side. The first included angle is between 5° and 45°.

[0010] The plurality of straight edges include: two opposing first straight edges and two opposing second straight edges, wherein the ratio of the length of the first straight edge to the distance between the two second straight edges is in the range of [0.5, 1); and the ratio of the length of the second straight edge to the distance between the two first straight edges is in the range of [0.4, 1).

[0011] In some embodiments, the width of the first substructure is greater than the width of the second substructure.

[0012] In some embodiments, the first substructure has the same light transmittance;

[0013] Alternatively, the transmittance of the first substructure is greater than that of the second substructure.

[0014] The array substrate further includes:

[0015] A conductive element is disposed on the substrate;

[0016] A connector is located on the side of the conductive element away from the substrate, and an insulating layer is provided between the connector and the conductive element; a via is provided on the insulating layer, and the connector is connected to the conductive element through the via;

[0017] The connector includes a connecting portion and an overlapping portion. The connecting portion is located within the via, and the overlapping portion is located on the surface of the insulating layer away from the substrate. The portion of the insulating layer away from the substrate opposite to the overlapping portion is approximately flat.

[0018] In some embodiments, the slope angle of the longitudinal section of the via is less than 30°.

[0019] In some embodiments, the slope angle of the longitudinal section of the via is 10° to 29°.

[0020] This disclosure also provides a photomask for use in a method for fabricating an array substrate, wherein the array substrate is the array substrate described in the above embodiments, and the photomask includes:

[0021] A fully transparent area is provided opposite to the area where the first structure of the via is located; the fully transparent area has multiple sides.

[0022] A graphic area is provided opposite to the area where the second structure of the via is located. The graphic area surrounds the fully transparent area and includes multiple partially transparent areas and multiple corner areas spaced apart from each other. Each partially transparent area is provided opposite to one side of the fully transparent area. The light transmittance of the partially transparent area is less than that of the fully transparent area. The corner area is located at the corner of the fully transparent area and is a light-blocking area.

[0023] In some embodiments, the partially light-transmitting area includes at least one light-transmitting slit and at least one light-blocking slit, the light-blocking slit and the light-transmitting slit being alternately arranged in a direction away from the fully light-transmitting area, wherein one of the light-blocking slits contacts the fully light-transmitting area, and the light-transmitting slit extends along the extension direction of the side opposite to it.

[0024] In some embodiments, in the partially light-transmitting area, the ratio of the width of the light-blocking slit to the width of the light-transmitting slit is between 0.5:1 and 2:1.

[0025] In some embodiments, the width of the light-transmitting slit is smaller than the exposure limit width.

[0026] In some embodiments, the width of the light-transmitting slit is between 1 μm and 1.5 μm.

[0027] In some embodiments, the partially light-transmitting area includes a plurality of light-transmitting slits and a plurality of light-blocking slits. For any two light-transmitting slits in the same partially light-transmitting area, the length of the light-transmitting slit farther from the fully light-transmitting area is greater than the length of the light-transmitting slit closer to the fully light-transmitting area.

[0028] In some embodiments, the plurality of light-transmitting slits in the graphic area are divided into at least one slit group, each slit group including a plurality of the light-transmitting slits, the plurality of light-transmitting slits in the same slit group surrounding the fully light-transmitting area, and different light-transmitting slits in the same slit group located on different sides of the fully light-transmitting area.

[0029] For any two adjacent light-transmitting slits in the same slit group, the extension lines of the two adjacent light-transmitting slits near the edge of the fully light-transmitting area converge at a first intersection point, and the distance from each of the two adjacent light-transmitting slits to the first intersection point is less than or equal to a preset etching offset.

[0030] In some embodiments, the photomask includes a transparent substrate and a light-shielding layer disposed on the transparent substrate. The light-shielding layer has a first cutout portion corresponding to the fully transparent area and a second cutout portion corresponding to the partially transparent area. An optical film is disposed in the second cutout portion. The light transmittance of the optical film is less than that of the transparent substrate and greater than that of the light-shielding layer.

[0031] This disclosure also provides a method for fabricating an array substrate, including:

[0032] A via is formed on one side of a substrate using photolithography. The via includes a first structure and a second structure surrounding the first structure. The first structure and the second structure have different light transmittances. The orthographic projection of the first structure on the substrate is approximately rectangular and has multiple straight edges. The orthographic projection of the second structure on the substrate is approximately octagonal. The second structure includes multiple first substructures and multiple second substructures. The orthographic projection of the first substructure on the substrate is strip-shaped. The first substructures are arranged parallel to the straight edges of the first structure, corresponding one-to-one. The orthographic projection of the second substructure on the substrate is tile-shaped. The second substructure is located between two adjacent first substructures and connects adjacent first substructures.

[0033] The photolithography patterning process includes an exposure process, and the mask used in the exposure process is the aforementioned mask.

[0034] In some embodiments, before forming a via on one side of the substrate using photolithography, the fabrication method further includes:

[0035] Conductive components are formed on the substrate;

[0036] An insulating layer is formed on the side of the conductive element away from the substrate; wherein the via is formed on the insulating layer and exposes the conductive element;

[0037] After forming a via on one side of the substrate using photolithography, the fabrication method further includes:

[0038] A connector is provided on the side of the insulating layer away from the substrate, and the connector is connected to the conductive element through the via; the connector includes a connecting portion and an overlapping portion, the connecting portion is located in the via, the overlapping portion is located on the surface of the insulating layer away from the substrate, and the portion of the surface of the insulating layer away from the substrate opposite to the overlapping portion is substantially flat.

[0039] In some embodiments, the insulating layer includes: a first insulator layer and a second insulator layer located between the first insulator layer and the conductive element, wherein the first insulator layer is made of a photosensitive material;

[0040] The method of forming vias exposing the conductive components on the insulating layer using photolithography includes:

[0041] The first insulator layer is exposed using the photomask;

[0042] The exposed first insulator layer is developed to form an intermediate via in the first insulator layer at the position corresponding to the via;

[0043] Using the developed first insulator layer as a mask layer, the second insulator layer between the first insulator layer and the conductive element is etched to form the via.

[0044] This disclosure also provides a display device including the array substrate described above. Attached Figure Description

[0045] The accompanying drawings are provided to further understand the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof.

[0046] In the attached diagram:

[0047] Figure 1 This is a plan view of the array substrate provided in some embodiments.

[0048] Figure 2 A cross-sectional schematic diagram illustrating the connection of conductive elements in different layers provided in some embodiments.

[0049] Figure 3 This is a partial schematic diagram of a mask provided in some embodiments.

[0050] Figure 4 To utilize Figure 3 A schematic diagram of the vias formed by the mask in the image.

[0051] Figure 5A This is a partial plan view of a mask provided in some embodiments of this disclosure.

[0052] Figure 5B for Figure 5A A schematic diagram showing the dimensions of the light-transmitting slit.

[0053] Figure 6 For along Figure 5A A cross-sectional view of line A-A' in the middle.

[0054] Figure 7 This is a partial plan view of the mask provided in some other embodiments of this disclosure.

[0055] Figure 8A This is a partial plan view of the mask provided in some other embodiments of this disclosure.

[0056] Figure 8B for Figure 8A A schematic diagram showing the dimensions of the light-transmitting slit.

[0057] Figure 9 A schematic diagram showing the dimensions for etching offset.

[0058] Figure 10This is a partial plan view of a mask provided in some other embodiments of this disclosure.

[0059] Figure 11 along Figure 10 A cross-sectional view of line B-B' in the middle.

[0060] Figure 12A This is a flowchart illustrating a method for fabricating an array substrate according to some embodiments of this disclosure.

[0061] Figure 12B This is a flowchart illustrating a method for fabricating an array substrate provided in some other embodiments of this disclosure.

[0062] Figures 13 to 15 This is a schematic diagram of the process of forming vias provided in some embodiments of this disclosure.

[0063] Figure 16 This is a plan view of a via provided in some embodiments of this disclosure.

[0064] Figure 17 This is a schematic diagram of a first conductive element and a second conductive element, and their respective vias, provided in some embodiments of this disclosure.

[0065] Figure 18 Scanning electron microscope (SEM) images of the first and second vias provided in some embodiments of this disclosure, viewed in a direction perpendicular to the substrate.

[0066] Figure 19 Scanning electron microscope (SEM) images of longitudinal sections of the vias provided in different embodiments.

[0067] Figure 20 This is a schematic diagram of an array substrate provided in some embodiments of this disclosure.

[0068] Figure 21 This is a plan view of a first conductive element, a second conductive element, and a connector provided in some embodiments of this disclosure. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0070] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0071] The array substrate includes a substrate and multiple conductive elements disposed on the substrate, such as gate lines, data lines and other signal lines, and pixel electrodes. These conductive elements are disposed in multiple layers, and when conductive elements in different layers need to be electrically connected, vias are used to achieve this connection.

[0072] Figure 1 Here is a plan view of the array substrate provided in some embodiments, such as Figure 1 As shown, the array substrate includes a substrate 10, which includes a display area AA and a peripheral area WA. Multiple gate lines GL and multiple data lines DL are disposed on the substrate 10, and these lines are interleaved to define multiple pixel areas P within the display area AA. Thin-film transistors, pixel electrodes, and other structures are disposed in the pixel areas P. A gate driving circuit 20 and a source driving circuit 30 may also be disposed on the substrate 10, both located in the peripheral area WA. The gate driving circuit 20 is connected to the gate lines GL and provides scan signals to them. The gate driving circuit 20 may have multiple scan signal output terminals, which may be disposed on the same layer as the data lines; each gate line GL is connected to one scan signal output terminal. The source driving circuit 30 is connected to the data lines DL and provides data signals to them.

[0073] Figure 2 This is a cross-sectional schematic diagram showing the connection of conductive elements in different layers provided in some embodiments, such as... Figure 2As shown, a first conductive element 11 is disposed on a substrate 10. A gate insulating layer GI is disposed on the side of the first conductive element 11 away from the substrate 10. A second conductive element 12 is disposed on the side of the gate insulating layer GI away from the substrate 10. A passivation layer PVX is disposed on the side of the second conductive element 12 away from the substrate 10. A planarization layer PLN is disposed on the side of the passivation layer PVX away from the substrate 10. A connector 13 is disposed on the side of the planarization layer PLN away from the substrate 10. The connector 13 is connected to the first conductive element 11 through a via Va penetrating the planarization layer PLN, the passivation layer PVX, and the gate insulating layer GI, and is connected to the second conductive element 12 through a via Vb penetrating the planarization layer PLN and the passivation layer PVX. In one example, the first conductive element 11 is the aforementioned scan signal output terminal (which is disposed on the same layer as the data line), and the second conductive element 12 is the aforementioned gate line GL. Of course, the first conductive element 11 and the second conductive element 12 can also have other structures. For example, the first conductive element 11 can be a data line DL, and the second conductive element 12 can be a fan-out line BL connected to the data driving circuit.

[0074] like Figure 2 As shown, the connector 13 is connected to the first conductive element 11 and the second conductive element 12 through a through hole. In order to prevent the connector 13 from breaking, the side of the through hole can be set as a gentle slope. Figure 3 This is a partial schematic diagram of the mask provided in some embodiments. Figure 3 The mask M0 shown is used in the via fabrication process. Figure 3 The diagram only shows the area of ​​mask M0 corresponding to one of the vias (e.g., via Va). Figure 3 The area includes: a first light-transmitting area M01, a first light-blocking area M02 surrounding the first light-transmitting area M01, a second light-transmitting area M03 surrounding the first light-blocking area M02, and a second light-blocking area M04 surrounding the second light-transmitting area M03.

[0075] Taking via Va as an example, the fabrication process of via Va includes: exposing and developing the planarization layer PLN using a mask M0 to form a sub-via on the planarization layer PLN; then, using the planarization layer PLN as a mask layer to etch the passivation layer PVX to form via Va. During exposure, the first light-transmitting area M01 of the mask M0 corresponds to the bottom of via Va, and the second light-blocking area M04 and the second light-transmitting area M03 of the mask correspond to the sides of via Va. The width of the second light-transmitting area M03 is very small; therefore, when light passes through the second light-transmitting area M03, it is insufficient to fully expose the planarization layer PLN. In other words, the first light-blocking area M02 and the second light-transmitting area M03 together can act as a semi-transparent area, thus partially exposing the corresponding position of the planarization layer PLN, thereby forming a slope on the side of via Va.

[0076] Among them, in utilizing Figure 3 When the mask M0 is exposed, because the width L1 at the corner of the second light-transmitting area M03 is greater than the width L2 at other locations, the light flux at the corner of the second light-transmitting area M03 is greater than the light flux at other locations. As a result, the planarization layer at the corner is easily fully exposed. After the passivation layer is etched subsequently, anomalies will also occur at the position corresponding to the corner of the second light-transmitting area M03. Figure 4 To utilize Figure 3 A schematic diagram of the vias formed by the mask in the image, as shown below. Figure 4 As shown, in addition to the via Va formed on the array substrate, an additional small hole Vc will appear near the corner of the via Va (which corresponds to the corner of the second light-transmitting area M03). In this case, when the connector 13 is formed later, the connector 13 is likely to break at the position of the small hole Vc, which will cause the impedance of the connector 13 to increase and may lead to risks such as open circuit and burn.

[0077] This disclosure provides a photomask for forming vias on one side of a substrate. Each via includes a first structure and a second structure surrounding the first structure, the first and second structures having different transmittances. The vias can be formed using a photolithography process, which includes an exposure process.

[0078] Figure 5A This is a partial plan view of the mask provided in some embodiments of this disclosure. Figure 7 This is a partial plan view of the mask provided in some other embodiments of this disclosure. Figure 8A For example, partial plan views of the mask provided in other embodiments of this disclosure, such as Figure 5A As shown, the photomask includes a fully transparent area M10 and a patterned area. During exposure, the fully transparent area M10 is positioned relative to the location where a first structure is to be formed. The patterned area is positioned relative to the location where a second structure is to be formed. The fully transparent area M10 can be a polygonal area with multiple sides. The term "fully transparent area M10" refers to an area where light irradiating it can pass through completely or substantially completely; for example, the transmittance of the fully transparent area M10 is 85% or higher, or 90% or higher, or 95% or higher, or equal to 100%.

[0079] In some examples, the fully transparent area M10 can be a rectangle, a square, a hexagon, an octagon, or other polygons. The angles of the polygons can be angles defined by straight lines or rounded corners.

[0080] The graphic area surrounds the fully transparent area M10 and includes multiple partially transparent areas HT spaced apart from each other, and multiple corner areas CA. Each partially transparent area HT is positioned opposite one side of the fully transparent area M10. A partially transparent area HT is one where a portion of the light incident on it passes through, while the remaining light fails to pass through. The transmittance of the partially transparent area HT is less than that of the fully transparent area M10; for example, the transmittance of the partially transparent area HT is between 40% and 70%, or between 50% and 55%, or between 55% and 60%.

[0081] The corner area CA is located at the corner of the fully transparent area M10. The corner area CA is a light-blocking area, meaning that all or almost all light rays hitting the corner area CA are blocked. For example, the light transmittance of the corner area CA is less than 5%, less than 8%, or equal to 0%. The corner of the fully transparent area M10 refers to the position where two adjacent sides of the fully transparent area M10 are connected.

[0082] It should be noted that the above-mentioned graphic area and the fully transparent area M10 can form a mask area, and the area around the mask area can be a light-blocking area. Figure 5A The image shows only one mask area used in the photolithography patterning process for a single via on the array substrate. In practical applications, the mask M1 can include multiple mask areas, allowing exposure of multiple locations on the photosensitive material to form multiple vias.

[0083] In the photomask provided in this embodiment, a patterned area surrounds a fully transparent area M10. The area in the patterned area opposite the side of the fully transparent area M10 is a partially transparent area HT, and the area corresponding to the corner of the fully transparent area M10 is a light-blocking area. When the photosensitive material is exposed using the photomask M1 in this embodiment, the photosensitive material corresponding to the fully transparent area M10 is fully exposed and thus completely removed after development; the photosensitive material corresponding to the partially transparent area HT is partially exposed and thus partially removed after development, forming a gentle slope; the photosensitive material corresponding to the corner area CA is not exposed and thus retained after development. In this case, when the developed photosensitive material is used as a mask layer to etch the underlying film layer, a via with a slope can be formed. Furthermore, since the photosensitive material corresponding to the corner area CA of the photomask M1 is not removed, no sloping vias will appear after etching. Figure 4 The small holes shown can improve the yield of subsequent connectors.

[0084] like Figure 5A and Figure 7As shown, the partially transparent area HT includes at least one light-transmitting slit TSL and at least one light-blocking slit SSL. The light-blocking slit SSL and the light-transmitting slit TSL are alternately arranged in a direction away from the fully transparent area M10. One of the light-blocking slits SSL is in contact with the fully transparent area M10, and the light-transmitting slit TSL extends along the extension direction of its opposite side. The extension direction of the light-blocking slit SSL is the same as that of the light-transmitting slit TSL. Through the alternating arrangement of the light-blocking slit SSL and the light-transmitting slit TSL, the area where the light-blocking slit SSL and the light-transmitting slit TSL are located has a partially transparent effect.

[0085] In some embodiments, in the partially transparent area HT, the width ratio of the shading slit SSL to the light-transmitting slit TSL is between 0.5:1 and 2:1, thereby allowing the photosensitive material to form a gentle slope after being exposed and developed in the partially transparent area HT. For example, the width ratio of the shading slit SSL to the light-transmitting slit TSL is 0.5:1, 1:1, 1.5:1, or 2:1. Preferably, the widths of the shading slit SSL and the light-transmitting slit TSL are equal to make the slope formed on the photosensitive material even gentler.

[0086] In some embodiments, the width of the light-transmitting slit TSL is less than the exposure limit width, wherein the exposure limit width is a parameter inherent to the photolithography equipment, which indicates that when the width of a certain light-transmitting area or the light-transmitting slit TSL on the photomask M1 exceeds the exposure limit width, the photosensitive material can be fully exposed; when the width of a certain light-transmitting area or the light-transmitting slit TSL on the photomask M1 is less than the exposure limit parameter, the photosensitive material cannot be fully exposed.

[0087] In some embodiments, the width of the light-transmitting slit TSL is between 1 μm and 1.5 μm. For example, the width of the light-transmitting slit TSL is 1 μm, or 1.2 μm, or 1.4 μm or 1.5 μm.

[0088] In some embodiments, the length of the light-transmitting slit TSL closest to the fully transparent area M10 can be equal to the length of its opposite side, for example, as shown below. Figure 5A As shown, the fully transparent area M10 is rectangular, with the lengths of two adjacent sides being L1 and L1', respectively. The length of the light-transmitting slit TSL opposite the side with length L1 is L3, and the length of the light-transmitting slit TSL opposite the side with length L1' is L3', where L1 = L3 and L1' = L3'. Of course, L1 and L3 can be unequal, and L1' and L3' can also be unequal.

[0089] In some embodiments, when the partial light-transmitting area HT includes multiple light-transmitting slits TSL, such as Figure 7 As shown, the length of the light-transmitting slit TSL in the same light-transmitting area HT can be the same.

[0090] In other embodiments, when a portion of the light-transmitting area HT includes multiple light-transmitting slits TSL, such as Figure 8A As shown, for any two light-transmitting slits TSL in the same light-transmitting area HT, the length of the light-transmitting slit TSL farther from the full light-transmitting area M10 is greater than the length of the light-transmitting slit TSL closer to the full light-transmitting area M10.

[0091] In some embodiments, the plurality of light-transmitting slits TSL in the pattern area are divided into at least one slit group, and each slit group includes a plurality of light-transmitting slits TSL. The plurality of light-transmitting slits TSL in the same slit group surround the fully light-transmitting area M10, and different light-transmitting slits TSL in the same slit group are located on different sides of the fully light-transmitting area M10. For any two adjacent light-transmitting slits TSL in the same slit group, the extension lines of the two adjacent light-transmitting slits TSL near the edge of the fully light-transmitting area M10 converge at a first intersection point, and the distance from each of the two adjacent light-transmitting slits TSL to the first intersection point is less than or equal to a preset etching offset.

[0092] Figure 5B for Figure 5A A schematic diagram showing the dimensions of the light-transmitting slit, for example, in... Figure 5A In the process, four light-transmitting slits TSL are arranged around the fully light-transmitting area M10. The four light-transmitting slits TSL form a slit group. The extension lines of two adjacent light-transmitting slits TSL near the edge of the fully light-transmitting area M10 converge at the first intersection point x0. In these two adjacent light-transmitting slits TSL, the distance from each light-transmitting slit TSL to the first intersection point x0 is d0, and d0 is less than the preset etching offset.

[0093] For example, Figure 8B for Figure 8A A schematic diagram showing the dimensions of the light-transmitting slit, as shown below. Figure 8A and Figure 8BAs shown, each side of the fully transparent area M10 has two light-transmitting slits TSL, for a total of eight light-transmitting slits TSL. These eight slits TSL are divided into two groups. The multiple light-transmitting slits TSL within the dashed frame B1 form the first group, and the multiple light-transmitting slits TSL between dashed frames B1 and B2 form the second group. The four light-transmitting slits TSL in the first group are closer to the fully transparent area M10 than the four light-transmitting slits TSL in the second group. In the first group, the extensions of the two adjacent light-transmitting slits TSL near the edge of the fully transparent area M10 converge at a first intersection point x1. The distance from each of these two adjacent light-transmitting slits TSL to the first intersection point is d1, and d1 is less than a preset etching offset. In the second slit group, the extension lines of two adjacent light-transmitting slits TSL near the edge of the fully light-transmitting area M10 converge at the first intersection point x2. In these two adjacent light-transmitting slits TSL, the distance from each light-transmitting slit TSL to the first intersection point x2 is d2, and d2 is less than the preset etching offset.

[0094] The preset etching offset is determined based on the etching process, and can be half the deviation between the target etching area and the actual etching area. Figure 9 A schematic diagram showing the dimension markings for the etching offset, such as... Figure 9 As shown, a mask layer M4 is disposed on the film layer 50 to be etched. The mask layer M4 has an opening with a width of W (W is the width of the target etching area). When etching the film layer 50, and the etching gas can etch both the film layer 50 and the mask layer M4, in addition to longitudinal etching (where the mask layer M4 is not completely etched away longitudinally), a certain amount of transverse etching will also occur. This results in a portion of both the mask layer M4 and the film layer 50 to be etched being etched away laterally. The width of the area etched on the film layer 50 is W1 (W1 is the width of the actual etched area). W1-W is the bilateral etching offset, and (W1-W) / 2 is the unilateral etching offset, which is the preset etching offset mentioned above. It should be noted that... Figure 11 It is only used to indicate the etching offset and does not represent the actual shape after etching.

[0095] In this embodiment, for any two adjacent light-transmitting slits TSL in the same slit group, the extended lines of the two adjacent light-transmitting slits TSL near the edge of the fully transparent area M10 converge at a first intersection point x1, and the distance from each of the two adjacent light-transmitting slits TSL to the first intersection point x1 is less than or equal to a preset etching offset. In this case, after exposing the photosensitive material using the mask M1 and using the developed photosensitive material as a mask layer to etch the underlying film layer, a via with a sloping side will be formed, and the side of the via will still be sloping at the corner position of the via.

[0096] Figure 9 For along Figure 5A A cross-sectional view of line A-A', as shown Figure 9 As shown, in some embodiments, the photomask may include a transparent substrate M11 and a light-shielding layer M12 disposed on the transparent substrate M11. The transparent substrate M11 may be a glass substrate or a substrate of other transparent materials; the light-shielding layer M12 may be made of a metallic material, such as chromium. The light-shielding layer M12 has a first cutout h1 corresponding to the fully transparent area M10, and a third cutout h3 corresponding to the area of ​​the light-transmitting slit TSL.

[0097] Figure 10 This is a partial plan view of the mask provided in some other embodiments of this disclosure. Figure 11 along Figure 10 The sectional view of line B-B' in the middle, and Figure 5A The same as the mask in, in Figure 10 The mask shown includes a fully transparent area M10 and a patterned area surrounding the fully transparent area M10. The patterned area includes multiple partially transparent areas HT and multiple corner areas CA. Figure 5A The difference between the mask M1 shown is that, in Figure 10 In some light-transmitting areas, the HT no longer sets the light-transmitting slits TSL and shading slits SSL, but instead sets the transmittance at all locations to be the same. For example... Figure 11 As shown, the photomask M1 includes a transparent substrate M11 and a light-shielding layer M12 disposed on the transparent substrate M11. The light-shielding layer M12 has a first cutout corresponding to the fully transparent area M10, and a second cutout corresponding to the partially transparent area HT is disposed on the light-shielding layer M12. An optical film HTL is disposed in the second cutout. The transmittance of the optical film HTL is less than the transmittance of the fully transparent area M10. For example, the transmittance of the optical film HTL is between 40% and 70%, or between 50% and 55%, or between 55% and 60%, thereby ensuring that the transmittance of the partially transparent area HT is between 40% and 70%, or between 50% and 55%, or between 55% and 60%.

[0098] Figure 12A This is a flowchart illustrating a method for fabricating an array substrate as provided in some embodiments of this disclosure, such as... Figure 12A As shown, the method for fabricating the array substrate includes:

[0099] S0. A via is formed on one side of the substrate using a photolithography patterning process; the via includes a first structure and a second structure surrounding the first structure, the first structure and the second structure having different light transmittances; the orthographic projection of the first structure on the substrate is approximately rectangular and has multiple straight edges; the orthographic projection of the second structure on the substrate is approximately octagonal, the second structure includes multiple first substructures and multiple second substructures, the orthographic projection of the first substructure on the substrate is strip-shaped, the first substructure is parallel to the straight edges of the first structure in a one-to-one correspondence, the orthographic projection of the second substructure on the substrate is tile-shaped; the second substructure is located between two adjacent first substructures and connects adjacent first substructures.

[0100] The photolithography patterning process includes an exposure process, and the mask used in the exposure process is the mask described in the above embodiments.

[0101] Figure 12B This is a flowchart illustrating a method for fabricating an array substrate provided in some other embodiments of this disclosure, such as... Figure 12B As shown, the manufacturing method includes:

[0102] S1. Forming conductive elements on a substrate.

[0103] S2. An insulating layer is formed on the side of the conductive component away from the substrate, and a via is formed on the insulating layer to expose the conductive component using a photolithography patterning process.

[0104] S3. A connector is provided on the side of the insulating layer away from the substrate. The connector is connected to the conductive component through a via. The connector includes a connecting portion and an overlapping portion. The connecting portion is located inside the via, and the overlapping portion is located on the surface of the insulating layer away from the substrate.

[0105] In the exposure process for forming vias, the photomask of the above embodiment is used for exposure. Since the corner areas of the photomask are light-blocking areas, no light will appear. Figure 4 The phenomenon shown is that small holes are generated near the corner of the via, that is, the part of the insulating layer away from the substrate that is opposite to the overlap is roughly flat.

[0106] It should be noted that "roughly flat" means that there are no pits or bumps on the surface. For example, the flatness of the surface is less than 0.25 times, 0.5 times, or 1 times the thickness of the connector.

[0107] In some embodiments, the insulating layer may be made of a photosensitive material. When forming a via, a mask is used to expose the area to be formed of the via, followed by development, thereby forming the via.

[0108] In other embodiments, the insulating layer may include a first insulator layer and a second insulator layer located between the first insulator layer and the conductive element, wherein the first insulator layer is made of a photosensitive material. Figures 13 to 15 This is a schematic diagram of the via formation process provided in some embodiments of this disclosure, such as... Figures 13 to 15 As shown, the process of forming a via includes:

[0109] S21, such as Figure 13 As shown, the first sub-insulating layer 15 is exposed using the mask M1 in the above embodiment. During exposure, the fully transparent area M10 and the patterned area correspond to the areas where vias are to be formed, thereby ensuring that the area on the first sub-insulating layer 15 corresponding to the fully transparent area M10 is fully exposed, while the area corresponding to the patterned area is partially exposed. Due to light diffraction, the area on the first sub-insulating layer 15 corresponding to the corner area CA also receives a small amount of light, resulting in partial exposure.

[0110] S22. Develop the first sub-insulating layer 15 after exposure. After development, a central via Vm is formed on the first sub-insulating layer 15. The side of the central via Vm is a slope, as shown below. Figure 14 As shown.

[0111] S23. Using the developed first sub-insulating layer 15 as a mask layer, the second sub-insulating layer 16 is etched to form a via V, as shown. Figure 15 As shown. The second sub-insulating layer 16 can be etched using a dry etching method. It should be understood that the etching gas used during the etching process will not affect the conductive components.

[0112] Figure 16 Plan view of the vias provided in some embodiments of this disclosure, such as Figure 16 As shown, the via includes a first structure VO1 and a second structure VO2 surrounding the first structure VO1. The first structure VO1 and the second structure VO2 have different transmittances. It should be noted that, in this embodiment, the transmittance of the first structure VO1 / second structure VO2 refers to the brightness of the first structure VO1 / second structure VO2 as seen through a light microscope along a direction perpendicular to the substrate. Specifically, the transmittance of the first structure VO1 is greater than that of the second structure VO2; that is, the first structure VO1 appears brighter than the second structure VO2 when viewed through a light microscope.

[0113] The orthographic projection of the first structure V01 onto the substrate is approximately rectangular and has multiple straight sides. "Approximately rectangular" means that the orthographic projection can be either a right-angled rectangle or a rounded rectangle. When the orthographic projection is a right-angled rectangle, the multiple straight sides are connected sequentially. When the orthographic projection is a rounded rectangle, the rounded rectangle includes not only multiple straight sides but also curved sides located between adjacent straight sides.

[0114] The orthographic projection of the second structure VO2 onto the substrate is approximately octagonal. The second structure VO2 includes multiple first substructures VO2a and multiple second substructures VO2b. The orthographic projection of the first substructure VO2a onto the substrate is a strip-shaped pattern. The first substructure VO2a is arranged parallel to the straight edges of the first structure VO1 in a one-to-one correspondence. The strip-shaped pattern is a rectangle, and the parallel arrangement of the first substructure VO2a with the straight edges of the first structure VO1 means that the long side of the first substructure VO2a is parallel to the straight edge of the first structure VO1.

[0115] The second substructure V02b, projected onto the substrate, is tile-shaped. It is located between and connected to two adjacent first substructures V02a. The tile shape refers to a pattern with two straight connecting edges and two non-straight edges. One straight connecting edge connects the first ends of the two non-straight connecting edges, and the other connects the second ends of the two non-straight connecting edges. The two straight connecting edges are also the shorter sides of the two strip-shaped patterns. The non-straight edges can be curved or broken lines.

[0116] Specifically, for a via, it has a first opening away from the substrate and a second opening towards the substrate, as well as a side connecting the first opening and the second opening. The orthographic projection of the first structure V01 on the substrate is also the orthographic projection of the first opening on the substrate; the orthographic projection of the second structure V02 on the substrate is also the orthographic projection of the second opening on the substrate.

[0117] Since the first sub-insulating layer 15 is partially exposed in the area corresponding to the corner region CA and the area corresponding to the partially transparent region HT, and during the etching process, the etching gas will not only etch the second sub-insulating layer 16, but also cause a certain amount of etching to the first sub-insulating layer 15, the side of the via formed after etching is a continuous and gentle slope.

[0118] Furthermore, since the area corresponding to corner region CA of the first sub-insulator layer 15 receives a small amount of light during exposure, and since both the first and second insulator layers undergo longitudinal and transverse etching during etching, the resulting via will exhibit... Figure 16The morphology shown includes the first structure V01 and the second structure V02 described above. The second structure V02 includes a first substructure V02a and a second substructure V02b. The first substructure V02a is strip-shaped, and the second substructure V02b is tile-shaped. The width d4 of the first substructure V02a is greater than the width d3 of the second substructure V02b. It should be noted that the width of the first substructure V02a is the width of the strip-shaped shape (i.e., the rectangle); the width of the second substructure V02b refers to the shortest distance between the two non-linear sides of the tile-shaped shape.

[0119] In some embodiments, the first substructure V21 and the second substructure V22 in the via V formed by the mask have the same transmittance; that is, the brightness of the first substructure V21 and the second substructure V22 is the same when viewed through a light mirror along a direction perpendicular to the substrate. In other embodiments, the transmittance of the first substructure V21 is greater than that of the second substructure V22; that is, the brightness of the first substructure V21 is greater than that of the second substructure V22 when viewed through a light mirror along a direction perpendicular to the substrate.

[0120] In practical applications, multiple conductive elements can be formed simultaneously. Additionally, multiple vias can be formed simultaneously on the array substrate, with each conductive element corresponding to at least one via. For example, the multiple conductive elements may include multiple first conductive elements and multiple second conductive elements, and the multiple vias may include first vias corresponding to the first conductive elements and second vias corresponding to the second conductive elements.

[0121] Figure 17 This is a schematic diagram of a first conductive element and a second conductive element, and their corresponding vias, provided in some embodiments of this disclosure. For example... Figure 17 As shown, a gate insulating layer GI is disposed on the side of the first conductive element 11 away from the substrate 10, and a second conductive element 12 is disposed on the side of the gate insulating layer GI away from the substrate 10. A passivation layer PVX and a planarization layer PLN are disposed on the side of the second conductive element 12 away from the substrate 10.

[0122] In this case, for the first via V1, the insulating layer on the side away from the substrate 10 is the planarization layer PLN, the passivation layer PVX, and the gate insulating layer GI; the first sub-insulating layer corresponding to the first via V1 is the planarization layer PLN, and the second sub-insulating layer corresponding to the first via V1 includes the passivation layer PVX and the gate insulating layer GI; the first sub-insulating layer corresponding to the second via V2 is the planarization layer PLN, and the second sub-insulating layer corresponding to the second via V2 is the passivation layer PVX.

[0123] When forming the first via V1 and the second via V2, the planarization layer PLN can be exposed and developed using the aforementioned mask, thereby forming intermediate via Va at the positions where the first via V1 is to be formed and the second via V2 is to be formed; then, the passivation layer PVX and the gate insulating layer GI are etched to form the first via V1 and the second via V2.

[0124] Figure 18 These are scanning electron microscope (SEM) images of the first and second vias provided in some embodiments of this disclosure, viewed along a direction perpendicular to the substrate, wherein the morphology of the mask regions on the mask corresponding to the first via V1 and the second via V2 is as follows: Figure 5A As shown. Figure 18 As shown, the first via V1 and the second via V2 have basically the same morphology. Both the first via V1 and the second via V2 include a first structure V01 and a second structure V02. The orthographic projection of the first structure V01 on the substrate is a rounded rectangle.

[0125] The orthographic projection of the second structure VO2 onto the substrate is approximately octagonal. The second structure VO2 includes multiple first substructures VO2a and multiple second substructures VO2b. The orthographic projection of the first substructures VO2a onto the substrate is a stripe-like pattern, and the orthographic projection of the second substructures VO2b onto the substrate is a tile-like pattern. Figure 18 In the first via V1 and the second via V2, the tile-shaped pattern of the second substructure V02b has two straight connecting edges and two non-straight edges. The non-straight edge closer to the first structure V01 is the arc edge between two adjacent straight edges in the rounded rectangle, and the non-straight edge farther from the first structure V01 is the arc edge.

[0126] In some embodiments, such as Figure 18 As shown, the orthographic projection of the first structure V01 onto the substrate is a rounded rectangle, which includes multiple straight sides and an arc-shaped edge VL2 connecting two adjacent straight sides. The multiple straight sides include two opposing first straight sides VL11 and two opposing second straight sides VL12. The ratio of the length L1 of the first straight side VL11 to the distance D2 between the two second straight sides VL12 is in the range [0.5, 1), and the ratio of the length L2 of the second straight side VL12 to the distance D1 between the two first straight sides VL11 is in the range [0.4, 1). For example, the ratio of the length L1 of the first straight side VL11 to the distance D2 between the two second straight sides VL12 is 0.5, or 0.6, or 0.75, or 0.8, or 0.9; the ratio of the length L2 of the second straight side VL12 to the distance D1 between the two first straight sides VL11 is 0.4, or 0.5, or 0.6, or 0.7, or 0.8.

[0127] It should be noted that, in Figure 18 In the diagram, only the first straight edge VL11, the second straight edge VL12, and the curved edge VL2 of the first through hole V1 are marked. The second through hole V2 also has the same first straight edge VL11, second straight edge VL12, and curved edge VL2, and also meets the above dimensional requirements, so it will not be described again here.

[0128] Furthermore, in the first via V1, the two ends of the arc-shaped edge VL2 of the orthographic projection of the first structure V01 form a first included angle c1 with the line connecting the center of the rounded rectangle; in the second via V2, the two ends of the arc-shaped edge VL2 of the orthographic projection of the first structure V01 form a first included angle c2 with the line connecting the center of the rounded rectangle, and both the first included angles c1 and c2 are between 5° and 45°. For example, both the first included angles c1 and c2 are between 10° and 35°. For example, the first included angle c1 is 5°, or 10°, or 15°, or 20°, or 25°; the first included angle c1 is 10°, or 15°, or 20°, or 25°, or 30°.

[0129] Figure 19 The images shown are scanning electron microscope (SEM) images of longitudinal sections of the vias provided in different embodiments. Figure 19 Figure (a) in the figure is a scanning electron microscope (SEM) image of the longitudinal section of the via provided in the comparative example. Figure 19 Figure (b) is a scanning electron microscope (SEM) image of a longitudinal section of the via provided in this embodiment of the present disclosure. Wherein, when forming the via in this embodiment of the present disclosure, the morphology of the mask region corresponding to the via on the mask plate is as follows: Figure 5A As shown; when forming the vias in the comparative example, the mask area on the mask corresponding to the vias only includes Figure 5A The fully transparent area M10 is surrounded by a light-blocking area, and no light-transmitting slit TSL is provided. For example... Figure 19 As shown, the slope angle α of the longitudinal section of the through hole in this embodiment is 12°, while the slope angle β of the side of the through hole in the comparative example is 33°. It can be seen that by setting the light-transmitting gap in the fully transparent M10 area, the side of the through hole can be made smoother, thereby preventing breakage of the subsequently formed connector. It is understood that, for the through hole in this embodiment, the slope angle of the longitudinal section of the through hole is also the slope angle of the longitudinal section of the second structure V02.

[0130] Figure 20 This is a schematic diagram of an array substrate provided in some embodiments of this disclosure. This array substrate can be fabricated using the methods described in the above embodiments. Figure 20 As shown, the array substrate includes a substrate 10 and a via V located on one side of the substrate 10. In some embodiments, the plan view of the via is as follows. Figure 16As shown, the via V includes a first structure V01 and a second structure V02 surrounding the first structure V01, regarding Figure 16 The descriptions of the first structure V01 and the second structure V02 are as above and will not be repeated here. In some other embodiments, a plurality of vias V are provided on one side of the substrate 10. The plurality of vias V includes, for example, a first via V1 and a second via V2. Scanning electron microscope images of the longitudinal sections of the first via V1 and the second via V2 are shown below. Figure 18 As shown, the first via V1 and the second via V2 also include the first structure V01 and the second structure V02, as described above, and will not be repeated here.

[0131] like Figure 20 As shown, the array substrate further includes a conductive element 11a and a connector 13 disposed on the substrate 10. The connector 13 is located on the side of the conductive element 11a away from the substrate 10. An insulating layer 14 is disposed between the connector 13 and the conductive element 11a. A via V is disposed on the insulating layer 14, and the connector 13 is connected to the conductive element 11a through the via V on the insulating layer 14. The method for fabricating the via V is described in the above embodiments.

[0132] The connector 13 includes a connecting portion 13a and an overlapping portion 13b. The connecting portion 13a is located inside the via V, and the overlapping portion 13b is located on the surface of the insulating layer 14 away from the substrate 10. The portion of the insulating layer 14 away from the substrate 10 that is opposite to the overlapping portion 13b is generally flat.

[0133] like Figure 20 As shown, the via V has a first opening away from the substrate 10 and a second opening close to the substrate 10, as well as a side surface connecting the first opening and the second opening. The side surface of the via V is a sloped surface. The projection of the first opening onto the substrate 10 is the first projection, and the orthographic projection of the second opening onto the substrate 10 is the second projection. The second projection is approximately rectangular. The first projection has multiple first edges and multiple second edges. The first edges are opposite to the sides of the rectangle, and the second edges are opposite to the corners of the rectangle. The distance from the second edge to the first projection is less than the distance from the first edge to the first projection.

[0134] In some embodiments, the longitudinal section slope angle of the through hole V is less than 30°. Optionally, the longitudinal section slope angle of the through hole V is 10° to 29°. For example, the longitudinal section slope angle of the through hole V is less than 25°, or less than 20°, or less than 15°. For example, the slope angle is 12°.

[0135] In some embodiments, the insulating layer 14 includes a first insulator layer and a second insulator layer located between the first insulator layer and the conductive element. The first insulator layer is made of a photosensitive material. Of course, in other embodiments, the first insulator layer may also be a non-photosensitive material. In this case, during the photolithography patterning process, a photoresist layer is first formed on the insulating layer. In this case, during the etching step of the photolithography patterning process, a gas capable of etching the photoresist layer can be incorporated into the etching gas. However, it should be understood that during the etching step, the etching gas should not completely etch away the photoresist layer in the vertical direction.

[0136] In some embodiments, the number of conductive elements 11a and vias in the array substrate are both multiple, and the multiple conductive elements 11a include: multiple first conductive elements 11 and multiple second conductive elements 12. Figure 21 Plan views of the first conductive element, the second conductive element, and the connector provided in some embodiments of this disclosure, such as... Figure 21 As shown, the first conductive element 11 is located between the layer containing the second conductive element 12 and the substrate 10. A gate insulating layer GI is disposed between the first conductive element 11 and the second conductive element 12. A passivation layer PVX and a planarization layer PLN are disposed on the side of the second conductive element 12 away from the substrate 10. The planarization layer PLN is located on the side of the passivation layer PVX away from the substrate 10 and is made of a photosensitive material.

[0137] The insulating layer between the connector 13 and the first conductive element 11 includes a planarization layer PLN, a passivation layer PVX, and a gate insulating layer GI. The insulating layer between the connector and the second conductive element 12 includes a planarization layer PLN and a passivation layer PVX.

[0138] Each connector 13 is connected to a first conductive element 11 through at least one first via V1 and to a second conductive element 12 through at least one second via V2. For example, the connector 13 can be connected to the first conductive element 11 through multiple first vias V1 and to the second conductive element 12 through multiple second vias V2.

[0139] This disclosure also provides a display device, including the array substrate described in the above embodiments. The display device can be any product or component with display functionality, such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0140] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A photomask for fabricating vias in an array substrate; wherein, The mask includes: A fully transparent area, wherein the fully transparent area has multiple sides; The graphic area surrounds the fully transparent area and includes multiple partially transparent areas and multiple corner areas spaced apart from each other. Each partially transparent area is arranged opposite to one side of the fully transparent area. The light transmittance of the partially transparent area is less than that of the fully transparent area. The corner area is located at the corner of the fully transparent area and is a light-blocking area. The partially light-transmitting area includes multiple light-transmitting slits and multiple light-blocking slits. For any two light-transmitting slits in the same partially light-transmitting area, the length of the light-transmitting slit farther from the fully light-transmitting area is greater than the length of the light-transmitting slit closer to the fully light-transmitting area.

2. The photomask according to claim 1, wherein, The partially light-transmitting area includes at least one light-transmitting slit and at least one light-blocking slit, the light-blocking slit and the light-transmitting slit being alternately arranged in a direction away from the fully light-transmitting area, one of the light-blocking slits being in contact with the fully light-transmitting area, the light-transmitting slit extending along the extension direction of the side opposite to it.

3. The photomask according to claim 2, wherein, In the partially transparent area, the ratio of the width of the light-blocking slit to the width of the light-transmitting slit is between 0.5:1 and 2:

1.

4. The photomask according to claim 2, wherein, The width of the light-transmitting slit is less than the exposure limit width.

5. The photomask according to any one of claims 2 to 4, wherein, The width of the light-transmitting slit is between 1 μm and 1.5 μm.

6. The photomask according to any one of claims 2 to 4, wherein, The multiple light-transmitting slits in the graphic area are divided into at least one slit group, and each slit group includes multiple light-transmitting slits. The multiple light-transmitting slits in the same slit group surround the fully light-transmitting area, and different light-transmitting slits in the same slit group are located on different sides of the fully light-transmitting area. For any two adjacent light-transmitting slits in the same slit group, the extension lines of the two adjacent light-transmitting slits near the edge of the fully light-transmitting area converge at a first intersection point, and the distance from each of the two adjacent light-transmitting slits to the first intersection point is less than or equal to a preset etching offset.

7. A photomask for fabricating vias in an array substrate; wherein, The mask includes: A fully transparent area, wherein the fully transparent area has multiple sides; The graphic area surrounds the fully transparent area and includes multiple partially transparent areas and multiple corner areas spaced apart from each other. Each partially transparent area is arranged opposite to one side of the fully transparent area. The light transmittance of the partially transparent area is less than that of the fully transparent area. The corner area is located at the corner of the fully transparent area and is a light-blocking area. The photomask includes a transparent substrate and a light-shielding layer disposed on the transparent substrate. The light-shielding layer has a first cutout corresponding to the fully transparent area and a second cutout corresponding to the partially transparent area. An optical film is disposed in the second cutout. The light transmittance of the optical film is less than that of the transparent substrate and greater than that of the light-shielding layer. The partially translucent area is directly adjacent to the side of the fully translucent area. The multiple sides of the fully translucent area include an adjacent first side and a second side. The length of the first side is a first length, and the length of the second side is a second length. The length of the partially translucent area adjacent to the first side in the direction of extension of the first side is equal to the first length. The length of the partially translucent area adjacent to the second side in the direction of extension of the second side is equal to the second length.

8. A method for fabricating an array substrate, comprising: A via is formed on one side of the substrate using photolithography patterning. The via includes a first structure and a second structure surrounding the first structure, wherein the first structure and the second structure have different light transmittances; The first structure has a roughly rectangular orthographic projection on the substrate and has multiple straight sides; the second structure has a roughly octagonal orthographic projection on the substrate and includes multiple first substructures and multiple second substructures. The first substructure has a strip-shaped orthographic projection on the substrate and is arranged parallel to the straight sides of the first structure in a one-to-one correspondence. The second substructure has a tile-shaped orthographic projection on the substrate. The second substructure is located between two adjacent first substructures and connects adjacent first substructures. The photolithography patterning process includes an exposure process, wherein the photomask used in the exposure process is the photomask according to any one of claims 1 to 7; the area where the first structure of the via is located is opposite to the fully transparent area of ​​the photomask, and the area where the second structure of the via is located is opposite to the pattern area of ​​the photomask.

9. The manufacturing method according to claim 8, wherein, Before forming a via on one side of the substrate using photolithography, the fabrication method further includes: Conductive components are formed on the substrate; An insulating layer is formed on the side of the conductive element away from the substrate; wherein the via is formed on the insulating layer and exposes the conductive element; After forming a via on one side of the substrate using photolithography, the fabrication method further includes: A connector is provided on the side of the insulating layer away from the substrate, and the connector is connected to the conductive element through the via; the connector includes a connecting portion and an overlapping portion, the connecting portion is located in the via, the overlapping portion is located on the surface of the insulating layer away from the substrate, and the portion of the surface of the insulating layer away from the substrate opposite to the overlapping portion is substantially flat.

10. The manufacturing method according to claim 9, wherein, The insulating layer includes: a first insulator layer and a second insulator layer located between the first insulator layer and the conductive element, wherein the first insulator layer is made of a photosensitive material; The method of forming vias exposing the conductive components on the insulating layer using photolithography includes: The first insulator layer is exposed using the photomask; The exposed first insulator layer is developed to form an intermediate via in the first insulator layer at the position corresponding to the via; Using the developed first insulator layer as a mask layer, the second insulator layer between the first insulator layer and the conductive element is etched to form the via.

11. An array substrate, manufactured using the method of any one of claims 8 to 10, the array substrate comprising a substrate and vias disposed on one side of the substrate, wherein: The via includes a first structure and a second structure surrounding the first structure, wherein the first structure and the second structure have different light transmittances; The first structure has a roughly rectangular orthographic projection onto the substrate and has multiple straight sides; The second structure has an orthographic projection on the substrate that is approximately octagonal. The second structure includes multiple first substructures and multiple second substructures. The orthographic projection of the first substructure on the substrate is strip-shaped. The first substructure is arranged parallel to the straight edges of the first structure in a one-to-one correspondence. The orthographic projection of the second substructure on the substrate is tile-shaped. The second substructure is located between two adjacent first substructures and connects the adjacent first substructures.

12. The array substrate according to claim 11, wherein, The orthographic projection of the first structure onto the substrate is a right-angled rectangle or a rounded rectangle.

13. The array substrate according to claim 11, wherein, The first structure has a rounded rectangle as its orthographic projection onto the substrate, and includes multiple straight sides and an arc-shaped side connecting adjacent straight sides. The two ends of the arc-shaped side have a first included angle between the line connecting the center of the rounded rectangle and the line connecting the two ends of the arc-shaped side. The first included angle is between 5° and 45°. The plurality of straight edges include: two opposing first straight edges and two opposing second straight edges, wherein the ratio of the length of the first straight edge to the distance between the two second straight edges is in the range [0.5, 1); and the ratio of the length of the second straight edge to the distance between the two first straight edges is in the range [0.4, 1).

14. The array substrate according to any one of claims 11 to 13, wherein, The width of the first substructure is greater than the width of the second substructure.

15. The array substrate according to any one of claims 11 to 13, wherein, The first substructure has the same light transmittance; Alternatively, the transmittance of the first substructure is greater than that of the second substructure.

16. The array substrate according to any one of claims 11 to 13, wherein, The array substrate further includes: A conductive element is disposed on the substrate; A connector is located on the side of the conductive element away from the substrate, and an insulating layer is provided between the connector and the conductive element; a via is provided on the insulating layer, and the connector is connected to the conductive element through the via; The connector includes a connecting portion and an overlapping portion. The connecting portion is located within the via, and the overlapping portion is located on the surface of the insulating layer away from the substrate. The portion of the insulating layer away from the substrate opposite to the overlapping portion is approximately flat.

17. The array substrate according to any one of claims 11 to 13, wherein, The slope angle of the longitudinal section of the through hole is less than 30°.

18. The array substrate according to claim 17, wherein, The slope angle of the longitudinal section of the through hole is 10°~29°.

19. A display device comprising an array substrate according to any one of claims 11 to 18.

Images