Digital synchronization system, data transmission method and medium adopting digital synchronization interface

Abstract

The application provides a digital synchronization system, a data transmission method and a medium adopting a digital synchronization interface, comprising a sending end and a receiving end; the sending end and the receiving end are connected through a plurality of digital synchronization interfaces; wherein each digital synchronization interface is used for synchronizing data of the sending end based on a preset synchronization indication signal and sending data synchronized with the rest of the digital synchronization interfaces to the receiving end. The application combines a frame header indication signal and a clock synchronization reference signal in an input signal into a new preset synchronization indication signal, only one pin is needed, the pins between data transmission are reduced, and hardware resources can be saved; the application can dynamically synchronize read and write pointers in a data buffer based on the preset synchronization indication signal, and the implementation mode is relatively efficient and simple; the digital synchronization interface constructed by the application is stable, efficient and reliable, and can meet the needs of data transmission and synchronization in various application scenarios.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to digital synchronization systems, data transmission methods and media employing digital synchronization interfaces. Background Technology

[0002] Currently, digital synchronization interfaces, as a crucial component of digital systems, are used to achieve data transmission and synchronization between different parts. Their design is based on digital signal processing, serial communication protocols, and clock and synchronization technologies. However, in terms of digital signal processing, digital synchronization interfaces need to consider the processing and characteristics of digital signals to avoid excessive hardware resource consumption. Simultaneously, in selecting a suitable serial communication protocol, system requirements and data transmission efficiency must be fully considered to make the data transmission method relatively efficient and simple. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the present invention provides a digital synchronization system, data transmission method and medium using a digital synchronization interface, which solves the problems of hardware resource consumption and inefficient and simple data transmission methods in the prior art.

[0004] To achieve the above and other related objectives, a first aspect of this application provides a digital synchronization system employing a digital synchronization interface, comprising: a transmitter and a receiver; the transmitter and the receiver are connected via a plurality of digital synchronization interfaces; wherein each digital synchronization interface is used to synchronize the data of the transmitter based on a preset synchronization indication signal, and to send the data synchronized with the other digital synchronization interfaces to the receiver.

[0005] In some embodiments of the first aspect of this application, the preset synchronization indication signal combines clock synchronization function and frame header indication function; the digital synchronization interface introduces the preset synchronization indication signal through a pin.

[0006] In some embodiments of the first aspect of this application, the digital synchronization interface includes a transmitting module; the transmitting module is connected to the receiving end via a transmitting channel and is used to synchronize the data of the transmitting end and transmit it to the receiving end.

[0007] In some embodiments of the first aspect of this application, the sending module includes a deserialization unit and a data buffer; wherein, the deserialization unit is used to deserialize the data and transmit the deserialized data to the data buffer; the data buffer is used to synchronize the deserialized data across clock domains based on a preset synchronization indication signal.

[0008] In some embodiments of the first aspect of this application, the digital synchronization interface further includes a receiving module, a configuration module, and a self-verification module; the configuration module is connected to the sending module, the receiving module, and the self-verification module respectively; the self-verification module is connected to the sending module and the receiving module respectively.

[0009] In some embodiments of the first aspect of this application, the receiving module is connected to the receiving end via a receiving channel, and is used to synchronize the data of the receiving end and send it to the sending end.

[0010] In some embodiments of the first aspect of this application, the configuration module is used to store configuration information and send corresponding configuration information to the sending module, the receiving module and the self-verification module respectively.

[0011] In some embodiments of the first aspect of this application, the self-verification module is used to perform self-verification to obtain a verification result.

[0012] To achieve the above and other related objectives, a second aspect of this application provides a data transmission method for a digital synchronization system employing a digital synchronization interface, applied to the digital synchronization system employing a digital synchronization interface as described above; the method includes: a transmitting end sending data to each of the digital synchronization interfaces, each of the digital synchronization interfaces synchronizing the data of the transmitting end based on a preset synchronization indication signal, and sending the synchronized data to the receiving end.

[0013] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data transmission method of the digital synchronization system employing a digital synchronization interface.

[0014] As described above, the digital synchronization system, data transmission method, and medium employing a digital synchronization interface of this application have the following beneficial effects:

[0015] (1) The present invention combines the frame header indication signal and the clock synchronization reference signal in the input signal into a new preset synchronization indication signal Tx_frame. The preset synchronization indication signal Tx_frame retains both synchronization and indication functions. By using only one pin, the number of pins required for data transmission is reduced, so as to achieve less hardware resource consumption under synchronization efficiency and save hardware resources.

[0016] (2) Based on the preset synchronization indicator signal Tx_frame, the present invention can dynamically synchronize the read and write pointers in the data buffer FIFO. At the same time, a counter is used inside the system to generate the traditional frame header indicator signal tx_frame. This implementation method is relatively efficient and simple.

[0017] (3) The digital synchronization interface constructed by the present invention is stable, efficient and reliable, and can meet the data transmission and synchronization needs of various application scenarios. Attached Figure Description

[0018] Figure 1 The diagram shown is a schematic representation of a digital synchronization system employing a digital synchronization interface according to an embodiment of this application.

[0019] Figure 2 The diagram shown is a structural schematic of a digital synchronization interface in one embodiment of this application.

[0020] Figure 3 The diagram shown is a structural schematic of the sending module in a digital synchronization interface according to an embodiment of this application.

[0021] Figure 4 The diagram shown is a structural schematic of a data buffer in a sending module according to an embodiment of this application.

[0022] Figure 5 The figure shown is a specific embodiment of a digital synchronization interface based on a preset synchronization indication signal to realize the indication function in data synchronization according to an embodiment of this application.

[0023] Figure 6 The figure shown is a specific embodiment of a digital synchronization interface based on a preset synchronization indication signal to realize the synchronization function in data synchronization according to an embodiment of this application.

[0024] Figure 7 The figure shown is a specific embodiment of a digital synchronization system employing a digital synchronization interface, as described in one embodiment of this application. Detailed Implementation

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0026] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of this application. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of this application. The following detailed description should not be considered limiting, and the scope of the embodiments of this application is defined only by the claims of the published patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0027] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0028] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0029] This invention provides a digital synchronization system, data transmission method, and medium employing a digital synchronization interface. The invention combines the frame header indication signal and the clock synchronization reference signal in the input signal into a new preset synchronization indication signal Tx_frame. This preset synchronization indication signal Tx_frame retains both synchronization and indication functions. By using only one pin, the number of pins required for data transmission is reduced, achieving lower hardware resource consumption while maintaining synchronization efficiency, thus saving hardware resources. Based on the preset synchronization indication signal Tx_frame, this invention can dynamically synchronize the read and write pointers in the data buffer FIFO. Simultaneously, a counter is used internally within the system to generate the traditional frame header indication signal tx_frame, making this implementation relatively efficient and simple. The digital synchronization interface constructed by this invention is stable, efficient, and reliable, meeting the data transmission and synchronization requirements of various application scenarios.

[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the invention.

[0031] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0032] <1> FIFO (First-In, First-Out) data buffer: This is a first-in, first-out (FIFO) data buffer where the first data to enter is read from the FIFO data buffer first. Specifically, existing FIFO data buffers contain multiple storage units, each with an equal data bit width and being the smallest unit in the FIFO data buffer. Therefore, when writing and reading data, existing FIFO data buffers implement a read / write method of M (where M is the data bit width that each storage unit can store) in which M is written and M is read. That is, existing FIFO data buffers can write data with a bit width equal to the data bit width M that its storage unit can store into a storage unit at a time, and can also read data with a bit width of M from a storage unit at a time.

[0033] <2> SPI (Serial Peripheral Interface) is a serial peripheral interface protocol used for communication between digital systems. It is widely used in embedded systems and electronic devices to connect peripherals such as microcontrollers, sensors, memory, and displays.

[0034] This invention provides a digital synchronization system employing a digital synchronization interface, a data transmission method for the digital synchronization system employing a digital synchronization interface, and a storage medium storing an executable program for implementing the data transmission method of the digital synchronization system employing a digital synchronization interface. Regarding the implementation of the digital synchronization system employing a digital synchronization interface, this invention will describe exemplary implementation scenarios of the digital synchronization system employing a digital synchronization interface.

[0035] like Figure 1 The diagram shown illustrates the structure of a digital synchronization system employing a digital synchronization interface according to an embodiment of this application.

[0036] The digital synchronization system includes a transmitter and a receiver; the transmitter and the receiver are connected through several digital synchronization interfaces dig_int_top; wherein each digital synchronization interface dig_int_top is used to synchronize the data of the transmitter based on a preset synchronization indication signal Tx_frame, and to send the data synchronized with the other digital synchronization interfaces dig_int_top to the receiver.

[0037] In some examples, the preset synchronization indicator signal Tx_frame combines clock synchronization and frame header indication functions; the digital synchronization interface dig_int_top introduces the preset synchronization indicator signal Tx_frame through a pin.

[0038] It's important to note that clock and synchronization techniques are crucial in the design process between the transmitter and receiver, ensuring data is transmitted and processed at the correct time. However, using conventional data synchronization methods requires inputting a clock synchronization signal `sys_ref` and a frame header indicator signal `tx_frame` separately as input signals. This means the digital synchronization interface `dig_int_top` needs two pins to connect to both the clock synchronization signal `sys_ref` and the frame header indicator signal `tx_frame`.

[0039] In this invention, the preset synchronization indicator signal Tx_frame combines the functions of the clock synchronization signal sys_ref and the frame header indicator signal tx_frame. Specifically, upon input, the clock synchronization signal sys_ref and the frame header indicator signal tx_frame are merged into a new preset synchronization indicator signal Tx_frame, which retains both synchronization and indicator functions. Therefore, the digital synchronization interface dig_int_top eliminates the need for a separate pin for the clock synchronization signal sys_ref, eliminating the need for a separate interface or pin for synchronization. This implementation is relatively efficient and simple, and achieves lower hardware resource consumption while maintaining high synchronization efficiency.

[0040] Specifically, data synchronization between the sending and receiving ends refers to the synchronized transmission of data between different chips at the sending end to the receiving end, thereby achieving data transmission and synchronization. Combined with... Figure 1 The transmitting end includes multiple chips, each configured with a corresponding digital synchronization interface (dig_int_top), namely digital synchronization interfaces dig_int_top_1, dig_int_top_2, and so on, to dig_int_top_n. Each digital synchronization interface dig_int_top is connected to the receiving end. Each chip in the transmitting end sends data to its respective digital synchronization interface dig_int_top while simultaneously inputting a preset synchronization indicator signal Tx_frame. Upon receiving the same preset synchronization indicator signal Tx_frame, each digital synchronization interface dig_int_top synchronizes the data of each chip using a clock, and then sends it to the receiving end, achieving cross-clock synchronization of data sent from each chip to the receiving end.

[0041] like Figure 2 The diagram shown illustrates the structure of the digital synchronization interface dig_int_top in a digital synchronization system employing a digital synchronization interface according to an embodiment of this application.

[0042] The digital synchronization interface dig_int_top includes a sending module tx_int; the sending module tx_int is connected to the receiving end through a sending channel tx_ch, and is used to synchronize the data of the sending end and send it to the receiving end.

[0043] In some examples, such as Figure 3 The diagram shown illustrates the specific structure of a sending module tx_int in one embodiment of this application. The sending module tx_int includes a deserializing unit tx_serial and a data buffer fifo. The deserializing unit tx_serial is used to deserialize the data and transmit the deserialized data to the data buffer fifo. The data buffer fifo is used to synchronize the deserialized data across clock domains based on a preset synchronization indication signal Tx_frame.

[0044] For example, the transmitting module tx_int receives 4-bit data Tx_in0 and Tx_in1 from the transmitting end. The deserial unit tx_serial deserializes Tx_in0 and Tx_in1 to obtain 16-bit data Tx_data0 and Tx_data1, equivalent to four channels of 4-bit parallel data. The deserialized 16-bit data Tx_data0 and Tx_data1 enter the data buffer FIFO. The FIFO performs cross-clock domain synchronization processing on Tx_data0 and Tx_data1 based on a preset synchronization indicator signal Tx_frame to obtain data Tx_data_I and Tx_data_Q.

[0045] It should be noted that each chip's digital synchronization interface, dig_int_top, includes multiple transmission channels, tx_ch. For example, any chip's digital synchronization interface, dig_int_top, sends out synchronized data Tx_data_I and Tx_data_Q through its two corresponding transmission channels, tx_ch. That is, data Tx_data_I and Tx_data_Q are sent to the receiving end through the transmission channels, tx_ch.

[0046] Specifically, combined Figure 4 The data buffer FIFO includes a synchronization unit (fifo_sync), a write module (fifo_write), a read module (fifo_read), and a storage unit (fifo_ram). When the preset synchronization indicator signal Tx_frame arrives in the data buffer FIFO, two rising edges are generated in the read and write clock domains respectively. These edges are assigned to the write synchronization control signal sync_w and the read synchronization control signal sync_r, thereby resetting the data buffer FIFO's read and write pointers. Afterward, the data buffer FIFO will simultaneously read and write data, ensuring its output data alignment. The specific synchronization process of each module or unit in the data buffer FIFO is as follows:

[0047] The synchronization unit fifo_sync is responsible for synchronization operations across clock domains. The synchronization unit fifo_sync is connected to the write module fifo_write and the read module fifo_read. The synchronization unit fifo_sync receives a preset synchronization indication signal Tx_frame. Based on the preset synchronization indication signal Tx_frame, two rising edge pulses are generated in the read and write clock domains respectively. The rising edge pulses generate corresponding synchronization control signals (such as the write synchronization control signal sync_w and the read synchronization control signal sync_r). The write synchronization control signal sync_w is sent to the write module fifo_write, and the read synchronization control signal sync_r is sent to the read module fifo_read. They are used to control the reset of the write pointer waddr and the read pointer raddr in the data buffer fifo, respectively.

[0048] The storage unit fifo_ram is the actual storage unit of the data buffer fifo, used to store and manage data. The storage unit fifo_ram is usually a dual-port RAM (Random Access Memory), which means that it has two independent ports, one for writing data and the other for reading data. The storage unit fifo_ram controls the read and write pointers through the fifo_write and fifo_read modules, and the storage unit fifo_ram is connected to the write module fifo_write and the read module fifo_read, respectively.

[0049] In the Sys_clk clock domain, the serial data data is deserialized to obtain wdata. The data wdata is then written to the storage unit fifo_ram by the write module fifo_write under the control of the Sys_clk clock domain and based on the write pointer waddr.

[0050] The read module fifo_read is responsible for reading data from the storage unit fifo_ram. Under the control of the Fclk clock domain, it retrieves data from fifo_ram. fifo_read maintains a read pointer raddr, which indicates the location of the next data to be read from fifo_ram. That is, the read module fifo_read reads data rdata from the storage unit fifo_ram through the read pointer raddr and sends the data rdata out through the transmit channel tx_ch.

[0051] For example, the preset synchronization indicator signal Tx_frame will generate two rising edge pulses in the read and write clock domains, namely the write synchronization control signal sync_w and the read synchronization control signal sync_r. The write synchronization control signal sync_w resets the write pointer waddr to the default value of 3, and the read synchronization control signal sync_r resets the read pointer raddr to the default value of 0. When the read pointer raddr and the write pointer waddr of the two chips are the same, it means that the written data and the read data are consistent, and the output data is consistent, thus the data synchronization is completed.

[0052] like Figure 2 As shown, the digital synchronization interface dig_int_top further includes a receiving module rx_int, a configuration module config, and a self-verification module bit_out; the configuration module config is connected to the sending module tx_int, the receiving module rx_int, and the self-verification module bit_out respectively; the self-verification module bit_out is connected to the sending module tx_int and the receiving module rx_int.

[0053] In some examples, the receiving module rx_int is connected to the receiving end via the receiving channel rx_ch, and is used to synchronize the data from the receiving end and send it to the sending end. The receiving module rx_int serializes the received synchronized data according to a certain algorithm. The serialization function of the receiving module rx_int converts the received parallel data stream into a serial data format, ensuring the synchronization, integrity, and accuracy of the data, thereby providing a reliable data foundation for subsequent system operations. Note that in this example, serialization or deserialization is essentially framing and deframing performed to adapt the data to the interface. The number of data bits and the choice between serialization and deserialization should be determined according to the actual application; this example does not impose any limitations.

[0054] In some examples, the configuration module `config` stores configuration information and sends corresponding configuration information to the sending module `tx_int`, the receiving module `rx_int`, and the self-verification module `bist_out`, respectively. The configuration information includes, but is not limited to: transmission enable signal `tx_en`, transmission reset signal `tx_rstn`, receive enable signal `rx_en`, receive reset signal `rx_rstn`, test enable signal `bist_en`, and test mode signal `bist_mode`, etc.

[0055] The configuration module (config) can also be used to configure the SPI bus. It stores the configuration information of each module in the digital synchronization interface (dig_int_top) in registers via the SPI bus and can assign specific pins to different functional modules. This facilitates pin allocation while avoiding redundant pins, enabling flexible and efficient management and control of each module. This flexible pin allocation method not only simplifies hardware design but also improves system scalability and maintainability.

[0056] In some examples, the self-verification module `bist_out` performs self-verification to obtain a verification result, which is then sent to the sending module `tx_int` or the receiving module `rx_int`. The self-verification module `bist_out` is an important component of the Built-In Self-Test (BIST) mechanism, a self-testing mechanism performed internally in the hardware to verify the functionality and performance of hardware components. After performing self-verification, `bist_out` outputs a verification result, which includes test data `bist_out_data`. This test data `bist_out_data` will be used to replace the actual data received by the sending module `tx_int` or the receiving module `rx_int`, depending on the test enable signal `bist_en`.

[0057] It should be noted that the transmission enable signal tx_en is used to control the transmission of data. When the tx_en signal is activated, the tx_int module starts transmitting data. If the tx_en signal is disabled (usually at a low level), the transmission operation will stop.

[0058] The transmit reset signal tx_rstn is used to reset the transmit module tx_int to its initial state. When the tx_rstn signal is activated (usually low), the transmit module tx_int stops its current operation and clears any internal states or registers. This is typically used during system initialization or fault recovery.

[0059] The receive enable signal rx_en is used to control the data reception of the receive module rx_int. When the rx_en signal is activated, the receive module rx_int starts receiving data.

[0060] The receive reset signal rx_rstn is used to reset the receive module rx_int to its initial state. When the rx_rstn signal is activated, the receive module rx_int will stop receiving operations and clear any internal states or registers.

[0061] The test enable signal bist_en is used to control the self-verification module bist_out to start executing the built-in self-test. When the bist_en signal is activated (usually high level), the self-verification module bist_out starts executing the built-in self-test. At this time, the self-verification module bist_out generates test data bist_out_data, which will replace the actual received data.

[0062] The test mode signal bit_mode is used to indicate which type of self-test the self-verification module bit_out should perform. Different bit_mode values ​​may represent different test modes, which may cover different parts of the hardware or perform different types of tests.

[0063] To facilitate the demonstration of the method for implementing the indication function in data synchronization based on the preset synchronization indication signal Tx_frame in this application, the following specific embodiments are provided, and in conjunction with... Figure 5 Explanation:

[0064] At this time, the clock signal FCLK, the preset synchronization indicator signal Tx_frame, and the frame header indicator signal tx_frame are all active high. When the preset synchronization indicator signal Tx_frame enters the transmission module tx_int, a frame header indicator signal tx_frame is generated as an indicator signal. This frame header indicator signal tx_frame functions identically to the traditional frame header indicator signal. The frame header indicator signal tx_frame is generated internally by a counter cnt. Specifically, when a rising edge of Tx_frame is detected, the internal counter cnt increments by 1, and tx_frame is generated and pulled high once. A rising edge of tx_frame indicates a data point (e.g., DATA1, DATA2, ..., DATA2). n The arrival of ), in which the counter cnt accumulates to 2 n Clear to zero. At this point, there are 2 [unclear] cycles within each Tx_frame period. n This data can be changed depending on the specific framing method. The preset synchronization indicator signal TX_frame of this invention replaces the traditional frame header indicator signal sys_ref. At the same time, the preset synchronization indicator signal TX_frame can generate the traditional frame header indicator signal tx_frame. Therefore, the functions of both can be achieved with a single preset synchronization indicator signal TX_frame.

[0065] To facilitate the demonstration of the method for implementing the synchronization function in data synchronization based on the preset synchronization indicator signal Tx_frame in this application, the following specific embodiments are provided, and in conjunction with... Figure 6 Explanation:

[0066] Taking two digital synchronization interfaces as an example, U1_Tx_data1 and U1_Tx_data2 are the data sent by the two channels of the first chip, and U2_Tx_data1 and U2_Tx_data2 are the data sent by the two channels of the second chip. The data content sent by the two chips is strictly identical.

[0067] Because there is always a transmission delay in actual data transmission, the arrival times of the two chips at the digital synchronization interface dig_int_top differ, requiring resynchronization via dig_int_top. After the Tx_frame signal arrives, two rising edges are generated in the read / write clock domain, respectively, and assigned to the sync_w and sync_r signals, thus resetting the FIFO. This takes some time. Afterward, the FIFO will read and write data simultaneously, and its output data will be aligned.

[0068] After a period of time following the arrival of the Tx_frame signal, such as Figure 6 As shown by the second dashed line from the left in the middle, after synchronization through the digital synchronization interface, the data of U1_Tx_data_I is I, and the data of U2_Tx_data_I is also I. That is, U1_Tx_data_I and U2_Tx_data_I achieve data synchronization. U1_Tx_data_Q and U2_Tx_data_Q also achieve data synchronization (both are 8), which ultimately achieves data synchronization alignment.

[0069] To facilitate the demonstration of the digital synchronization system employing a digital synchronization interface in this application, the following specific embodiments are provided, and in conjunction with... Figure 7 Explanation:

[0070] Two chips, U1 and U2, each have a corresponding digital synchronization interface, U1_dig_int_top and U2_dig_int_top. Both interfaces are connected to the same preset synchronization indicator signal, TX_frame. This preset synchronization indicator signal, TX_frame, is input to the data buffer FIFO in the transmitting module tx_int to synchronize its read and write pointers, thereby achieving data synchronization between the two chips U1 and U2. Specifically, the tx_data_in_i output by chip U1 is consistent with the tx_data_in_i output by chip U2, and the tx_data_in_q output by chip U1 is consistent with the tx_data_in_q output by chip U2. Both are then transmitted through their respective transmitting channels, tx_ch.

[0071] It should be understood that the division of the various modules or units in the above system is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules or units can be implemented entirely in software through processing element calls; they can be implemented entirely in hardware; or some modules or units can be implemented by processing element calls to software, while others are implemented in hardware.

[0072] For example, the transmitting module can be a separate processing element, or it can be integrated into a chip in the aforementioned device. Alternatively, it can be stored as program code in the memory of the aforementioned device, and its functions can be called and executed by a processing element of the device. The implementation of other modules is similar. Furthermore, all or part of these modules can be integrated together, or they can be implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0073] For example, these modules or units can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to form a system-on-a-chip (SOC).

[0074] The present invention also provides a data transmission method in a digital synchronization system employing a digital synchronization interface; applied to the digital synchronization system employing a digital synchronization interface as described above; the data transmission method includes: a transmitting end sending data to each of the digital synchronization interfaces, each of the digital synchronization interfaces synchronizing the data of the transmitting end based on a preset synchronization indication signal, and sending the synchronized data to the receiving end.

[0075] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data transmission method in the digital synchronization system employing a digital synchronization interface.

[0076] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using hardware related to a computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned computer-readable storage medium may include, but is not limited to: floppy disks, optical disks, CD-ROMs (Read-Only Optical Disk Memory), magneto-optical disks, ROMs (Read-Only Memory), RAMs (Random Access Memory), EPROMs (Erasable Programmable Read-Only Memory), EEPROMs (Electrically Erasable Programmable Read-Only Memory), magnetic cards or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions. The computer-readable storage medium can be a product not connected to a computer device or a component used in a computer device.

[0077] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0078] In summary, this application provides a digital synchronization system, data transmission method, and medium employing a digital synchronization interface, including a transmitter and a receiver. The transmitter and receiver are connected through several digital synchronization interfaces. Each digital synchronization interface is used to synchronize the data at the transmitter based on a preset synchronization indication signal and to send the data synchronized with the other digital synchronization interfaces to the receiver. This invention combines the frame header indication signal and the clock synchronization reference signal in the input signal into a new preset synchronization indication signal Tx_frame. The preset synchronization indication signal Tx_frame retains both synchronization and indication functions. By using only one pin, it reduces the number of pins required for data transmission, achieving lower hardware resource consumption while maintaining synchronization efficiency, thus saving hardware resources. Based on the preset synchronization indication signal Tx_frame, this invention can dynamically synchronize the read and write pointers in the data buffer FIFO. Simultaneously, it uses a counter internally within the system to generate the traditional frame header indication signal tx_frame, a relatively efficient and simple implementation. The digital synchronization interface constructed by this invention is stable, efficient, and reliable, meeting the data transmission and synchronization needs of various application scenarios. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0079] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A digital synchronization system employing a digital synchronization interface, characterized in that, include: A transmitter and a receiver; the transmitter and the receiver are connected via several digital synchronization interfaces; wherein, Each digital synchronization interface is used to synchronize the data of the transmitting end based on a preset synchronization indication signal, and to send the data synchronized with the other digital synchronization interfaces to the receiving end; The digital synchronization interface includes a sending module; the sending module includes a deserialization unit and a data buffer; wherein, the deserialization unit is used to deserialize the data and transmit the deserialized data to the data buffer; the data buffer is used to synchronize the deserialized data across clock domains based on a preset synchronization indication signal; The data buffer includes a synchronization unit, a write module, a read module, and a storage unit. The synchronization unit is connected to both the write and read modules. The synchronization unit receives a preset synchronization indication signal and generates two rising edge pulses in the read / write clock domain based on the preset synchronization indication signal. These two rising edge pulses generate corresponding synchronization control signals, including a write synchronization control signal and a read synchronization control signal. The write synchronization control signal is sent to the write module, and the read synchronization control signal is sent to the read module. The storage unit is connected to both the write and read modules and is used to store and manage data. The digital synchronization interface further includes a receiving module, a configuration module, and a self-verification module; the configuration module is connected to the sending module, the receiving module, and the self-verification module respectively; the self-verification module is connected to the sending module and the receiving module respectively. The receiving module is connected to the receiving end via a receiving channel and is used to synchronize the data from the receiving end and send it to the sending end. The configuration module is used to store configuration information and send corresponding configuration information to the sending module, receiving module, and self-verification module respectively. The configuration information includes: transmission enable signal tx_en, transmission reset signal tx_rstn, receive enable signal rx_en, receive reset signal rx_rstn, test enable signal bist_en, and test mode signal bist_mode. The configuration module is also used to set up the SPI bus and store the configuration information of each module in the digital synchronization interface in a register through the SPI bus. The self-verification module is used to perform self-verification to obtain verification results and send the verification results to the sending module or receiving module. The preset synchronization indication signal combines clock synchronization and frame header indication functions; after entering the transmission module, the preset synchronization indication signal generates a frame header indication signal through a counter. Specifically, within each preset synchronization indication signal period, there are 2... n When a rising edge of a preset synchronization indicator signal is detected, the counter increments by 1, and the counter accumulates to 2. n The system is then cleared to zero, ultimately generating a frame header indicator signal.

2. The digital synchronization system employing a digital synchronization interface according to claim 1, characterized in that, The preset synchronization indication signal combines clock synchronization function and frame header indication function; the digital synchronization interface introduces the preset synchronization indication signal through a pin.

3. The digital synchronization system employing a digital synchronization interface according to claim 1, characterized in that, The digital synchronization interface includes a sending module; the sending module is connected to the receiving end through a sending channel and is used to synchronize the data of the sending end and send it to the receiving end.

4. A data transmission method for a digital synchronization system employing a digital synchronization interface, characterized in that, Applied to a digital synchronization system employing a digital synchronization interface as described in any one of claims 1 to 3; the method comprises: The transmitting end sends data to each of the digital synchronization interfaces, and each of the digital synchronization interfaces synchronizes the data of the transmitting end based on a preset synchronization indication signal, and sends the synchronized data to the receiving end; The digital synchronization interface includes a sending module; the sending module includes a deserialization unit and a data buffer; wherein, the deserialization unit is used to deserialize the data and transmit the deserialized data to the data buffer; the data buffer is used to synchronize the deserialized data across clock domains based on a preset synchronization indication signal; The data buffer includes a synchronization unit, a write module, a read module, and a storage unit. The synchronization unit is connected to both the write and read modules. The synchronization unit receives a preset synchronization indication signal and generates two rising edge pulses in the read / write clock domain based on the preset synchronization indication signal. These two rising edge pulses generate corresponding synchronization control signals, including a write synchronization control signal and a read synchronization control signal. The write synchronization control signal is sent to the write module, and the read synchronization control signal is sent to the read module. The storage unit is connected to both the write and read modules and is used to store and manage data. The digital synchronization interface further includes a receiving module, a configuration module, and a self-verification module; the configuration module is connected to the sending module, the receiving module, and the self-verification module respectively; the self-verification module is connected to the sending module and the receiving module respectively. The receiving module is connected to the receiving end via a receiving channel and is used to synchronize the data from the receiving end and send it to the sending end. The configuration module is used to store configuration information and send corresponding configuration information to the sending module, receiving module, and self-verification module respectively. The configuration information includes: transmission enable signal tx_en, transmission reset signal tx_rstn, receive enable signal rx_en, receive reset signal rx_rstn, test enable signal bist_en, and test mode signal bist_mode. The configuration module is also used to set up the SPI bus and store the configuration information of each module in the digital synchronization interface in a register through the SPI bus. The self-verification module is used to perform self-verification to obtain verification results and send the verification results to the sending module or receiving module. The preset synchronization indication signal combines clock synchronization and frame header indication functions; after entering the transmission module, the preset synchronization indication signal generates a frame header indication signal through a counter. Specifically, within each preset synchronization indication signal period, there are 2... n When a rising edge of a preset synchronization indicator signal is detected, the counter increments by 1, and the counter accumulates to 2. n The system is then cleared to zero, ultimately generating a frame header indicator signal.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data transmission method of the digital synchronization system using a digital synchronization interface as described in claim 4.

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