Implementing a direct shared memory circuit between a central processing unit and an accelerator cluster

Abstract

The application provides a storage circuit for realizing direct sharing of a central processor and an accelerator cluster, comprising a first circuit, a second circuit and a third circuit connected in series; the first circuit comprises a central processor-external request arbitration module, a memory bank request chip select module and a central processor-accelerator request arbitration module connected in series, and an accelerator request crossbar module connected with the central processor-accelerator request arbitration module; the second circuit is a multi-memory bank storage module; the third circuit comprises a central processor-accelerator response arbitration module, a memory bank response chip select module and a central processor-external response arbitration module connected in series, and an accelerator response crossbar module connected with the central processor-accelerator response arbitration module; the application is based on multi-memory bank, single-port storage, fixed priority arbitration, butterfly topology crossbar interconnection and signal multiplexing, reduces CPU and accelerator access delay, and improves maximum access parallelism.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit design, in particular to a storage circuit for realizing direct sharing of a central processor and an accelerator cluster. BACKGROUND

[0002] In recent years, devices with AIoT (Artificial Intelligence & Internet of Things) chips as the core have gradually been popularized in various industries. The most important circuits in the chip include a CPU (Central Processing Unit) and an accelerator cluster for accelerating AI (Artificial Intelligence) tasks. A direct sharing mechanism of a storage circuit is a mechanism for allowing the accelerator cluster and the CPU to directly access the same storage area to exchange data.

[0003] The current common storage circuit integrates multiple SRAMs (Static Random-Access Memories) as a memory bank using a bus mode, and selects multiple accesses through polling and other fair arbitration modes. The disadvantage of the bus interconnection mode is that the parallelism of data transmission provided is low, which cannot meet the demand of high parallelism of the accelerator cluster for memory access, resulting in that the average efficiency of the acceleration cluster is slowed down. The disadvantage of the fair arbitration is that it does not consider the need for the CPU to have priority in access, so that the delay of the CPU in accessing the storage is lengthened, reducing the execution performance of the CPU. Therefore, when the CPU and the accelerator cluster directly share the storage using such a storage circuit, serious port contention will occur in their access, which will ultimately affect the running effect of the AIoT chip and the device. SUMMARY

[0004] In view of the defects in the prior art, the purpose of the present application is to provide a storage circuit for realizing direct sharing of a central processor and an accelerator cluster.

[0005] According to one aspect of the present application, a storage circuit for realizing direct sharing of a central processor and an accelerator cluster is provided, which comprises a first circuit, a second circuit and a third circuit connected in sequence.

[0006] The first circuit comprises a central processor-external request arbitration module, a memory bank request chip selection module and a central processor-accelerator request arbitration module connected in sequence, and an accelerator request crossbar module connected with the central processor-accelerator request arbitration module;

[0007] The second circuit comprises a plurality of memory bank memory modules.

[0008] The third circuit comprises a central processor-accelerator response arbitration module, a memory bank response chip select module and a central processor-external response arbitration module connected in sequence, and an accelerator response crossbar module connected with the central processor-accelerator response arbitration module;

[0009] The arbitration result of the first circuit is connected to the third circuit to realize multiplexing;

[0010] The first circuit, the second circuit and the third circuit are based on multi-memory bank technology, single-port storage technology, fixed priority arbitration technology, butterfly topology crossbar interconnection technology and signal multiplexing technology, and are used to reduce CPU and accelerator access delay and improve maximum access parallelism.

[0011] Preferably, in the first circuit, the external access request and the CPU access request are connected to a central processor-external request arbitration module; and the N accelerator cluster access requests are connected to an accelerator request crossbar module.

[0012] The central processor-external request arbitration module is connected to a memory bank request chip select module; and the memory bank request chip select module output is simultaneously connected to N central processor-accelerator request arbitration modules.

[0013] The N outputs of the accelerator request crossbar module are connected to N central processor-accelerator request arbitration modules; and the outputs of the N central processor-accelerator request arbitration modules are connected to the second circuit.

[0014] In the third circuit, the N groups of outputs of the second circuit are respectively connected to N central processor-accelerator response arbitration modules.

[0015] Each of the central processor-accelerator response arbitration modules has two outputs, one of which is connected to a memory bank response chip select module, and the other of which is connected to an accelerator response crossbar module.

[0016] The output of the memory bank response chip select module is connected to a central processor-external response arbitration module.

[0017] The N groups of outputs of the accelerator response crossbar module are connected to N access responses of the accelerator cluster.

[0018] The central processor-external response arbitration module has two groups of outputs, one of which is connected to a CPU access response, and the other of which is connected to an external access response.

[0019] Preferably, the central processor-external request arbitration module and the central processor-accelerator request arbitration module use CPU-priority fixed priority arbitration to achieve CPU access without waiting and reduce average delay, including: the central processor-external request arbitration module and the central processor-accelerator request arbitration module achieve fixed priority arbitration based on a 2-to-1 multiplexer, and the valid signal of the CPU access request is selected as long as it is valid;

[0020] The central processor-external response arbitration module achieves fixed priority arbitration based on a 2-to-1 demultiplexer, and the CPU access request is responded to by the CPU access, and the external access request is responded to by the external access based on the signal multiplexing technology of the central processor-external request arbitration module.

[0021] Preferably, the memory bank request chip select module is based on an N-way demultiplexer, and the CPU or external access address is selected to input to the corresponding address of the central processor-accelerator request arbitration module;

[0022] The memory bank response chip select module is based on an N-way multiplexer, and shares arbitration with the memory bank request chip select module based on signal multiplexing technology to ensure that the response data comes from the correct access request.

[0023] Preferably, the accelerator request crossbar module uses a butterfly topology crossbar interconnection technology to allow multiple accelerators to access multiple arbitrary memory banks at the same time, to improve the parallelism of accelerator access and suppress port contention, including:

[0024] The accelerator request crossbar module uses a butterfly topology crossbar interconnection architecture on paths containing addresses, data, and valid signals;

[0025] Each crossbar can change the connection between two inputs and two outputs to parallel connection or cross connection, so that two input and output paths are connected at the same time, improving parallelism;

[0026] Multiple crossbars achieve parallel interconnection of multiple groups of inputs and outputs based on different geometric topologies.

[0027] Preferably, each of the crossbars includes a crossbar control matrix;

[0028] The crossbar control matrix receives valid signals and address high bits, and controls according to the output of a 2-to-1 arbitrator;

[0029] The control process of the 2-to-1 arbitrator is that each arbitrator in the control matrix polls arbitration according to each bit of the input valid signal and address.

[0030] Preferably, the accelerator response crossbar module only contains the crossbar interconnection architecture of butterfly topology, and the arbitration result required by the accelerator response crossbar module is shared based on signal multiplexing technology with the accelerator request crossbar module.

[0031] Preferably, the plurality of central processor-accelerator request arbitration modules are identical in structure with the central processor-external request arbitration module, chip selection input is realized through a CPU valid signal, the lowest priority of accelerator access is realized, and low delay of address and data is realized.

[0032] The plurality of central processor-accelerator response arbitration modules are identical in structure with the central processor-external response arbitration module, and share arbitration with the central processor-accelerator request arbitration module based on signal multiplexing technology.

[0033] Preferably, the multi-bank memory module adopts multi-bank technology and single-port storage technology, and is used for suppressing port contention, reducing CPU and accelerator access delay, and improving maximum access parallelism, and comprises:

[0034] The multi-bank memory module comprises N single-port SRAM banks, and the multi-bank memory module constitutes a complete address space, each SRAM bank corresponds to 1 / N segment of addresses in the complete address space, and the chip selection address of the memory bank request chip selection module corresponds to the 1 / N segment of addresses; the multi-bank memory module allows different SRAM banks to be accessed in parallel, and provides N times of access parallelism.

[0035] Preferably, a first-stage flip-flop is added on all arbitration sharing and data paths connected with the multi-bank memory module, and is used for meeting circuit delay requirements and synchronizing timing alignment.

[0036] Compared with the prior art, the application has at least one of the following beneficial effects:

[0037] The storage circuit for directly sharing the central processor and the accelerator cluster in the embodiment of the application uses CPU-priority fixed-priority arbitration technology on the data path containing CPU access, so that CPU access is always in the first response state, and execution of instructions is not delayed by waiting for accelerator-priority access.

[0038] The storage circuit for directly sharing the central processor and the accelerator cluster in the embodiment of the application uses butterfly topology crossbar interconnection technology and multi-bank technology to connect the accelerator cluster and SRAM, compared with a bus or a multiplexer that only allows one accelerator to access at a time, the maximum access parallelism of the accelerator cluster to the SRAM is improved to N, and the probability of random access port contention between the CPU and a single memory bank in the cluster is reduced to 1 / N, and the average efficiency of accelerator access to storage is improved.

[0039] The storage circuit directly shared by the central processor and the accelerator cluster in the embodiment of the application reduces the delay of the accelerator and the CPU in accessing the SRAM by using single-port storage technology.

[0040] The storage circuit directly shared by the central processor and the accelerator cluster in the embodiment of the application reduces the delay of the accelerator and the CPU in accessing the SRAM by using single-port storage technology. BRIEF DESCRIPTION OF DRAWINGS

[0041] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings:

[0042] Figure 1 The overall circuit architecture of the storage circuit directly shared by the central processor and the accelerator cluster in an embodiment of the application is shown in the figure.

[0043] Figure 2 The overall circuit design schematic of a preferred embodiment of the application is shown in the figure.

[0044] Figure 3 The internal design of the accelerator request crossbar module and the accelerator response crossbar module in a preferred embodiment of the application is shown in the figure, in which (a) is the control matrix of the crossbar in the interconnection architecture, and (b) is the crossbar interconnection architecture of the butterfly topology.

[0045] Figure 4 The AIoT chip system architecture of the storage directly shared by the central processor and the accelerator cluster in a preferred embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0046] The application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that, for those skilled in the art, without departing from the concept of the application, a number of modifications and improvements can be made. These all belong to the protection scope of the application.

[0047] In an embodiment of the application, a storage circuit directly shared by a central processor and an accelerator cluster is provided, and the overall structure thereof is shown in the figure. Figure 1 The storage circuit directly shared by the central processor and the accelerator cluster in the embodiment of the application reduces the delay of the accelerator and the CPU in accessing the SRAM by using single-port storage technology.

[0048] The first circuit includes a central processor-external request arbitration module, a memory bank request chip select module, and a central processor-accelerator request arbitration module connected in sequence, and an accelerator request crossbar module connected with the central processor-accelerator request arbitration module.

[0049] The second circuit includes a multi-bank memory module;

[0050] The third circuit includes a central processor-accelerator response arbitration module, a memory bank response chip select module and a central processor-external response arbitration module connected in sequence, and an accelerator response crossbar module connected with the central processor-accelerator response arbitration module;

[0051] The arbitration result of the first circuit is connected to the third circuit to realize multiplexing;

[0052] The first circuit, the second circuit and the third circuit are based on multi-bank memory technology, single-port memory technology, fixed priority arbitration technology, butterfly topology crossbar interconnection technology and signal multiplexing technology to realize reduction of CPU and accelerator access delay and improvement of maximum access parallelism.

[0053] Based on the overall structure of the above-mentioned circuit, the connection sequence of the overall circuit is the first circuit, the second circuit, the third circuit, and the unmarked connection is the main data path, including data, valid signals, and the main data path in the first circuit also includes address.

[0054] The multiplexing technology concept in the above-mentioned embodiment is that multiplexing combines and separates signals and improves the utilization efficiency of communication resources, so that multiple independent signals can share the same communication channel, thereby realizing more efficient data transmission in networks and communication systems.

[0055] It should be noted that the number of all circuit modules must strictly follow the principle of any positive integer power of 2, and the number of accelerator accesses is not limited by this. When the number of accelerator accesses is not a power of 2, the number of circuit modules required for the application of the circuit modules must exceed the number of accelerator accesses. For example, if the number of accelerator accesses is 7, the number of circuit modules required should be at least 2 to the power of 3, i.e. 8. Similarly, if the number of accelerator accesses is 19, the number of circuit modules required should be at least 2 to the power of 5, i.e. 32. After completing the connection of the accelerator accesses according to the number, all remaining input port signals should be connected to logic 0, and all output ports should be kept in the state of empty connection. In the present application, the number N of selected circuit modules is set to 16. 4

[0056] Based on the above-mentioned embodiment, in a preferred embodiment of the present application, the circuit connection sequence of the first circuit is:

[0057] The external access request and the CPU access request are connected to the central processor-external request arbitration module; at the same time, the 16 access requests of the accelerator cluster are connected to the accelerator request crossbar module; ​

[0058] The central processor-external request arbitration module is connected with the memory bank request chip select module; the memory bank request chip select module outputs and is connected with 16 central processor-accelerator request arbitration modules simultaneously;

[0059] The 16 accelerator request crossbar module outputs are connected with 16 central processor-accelerator request arbitration modules;

[0060] The 16 central processor-accelerator request arbitration module outputs are connected with the second circuit;

[0061] In another preferred embodiment, the circuit connection sequence of the third circuit is as follows:

[0062] The 16 second circuit outputs are respectively connected with 16 central processor-accelerator response arbitration modules;

[0063] Each of the central processor-accelerator response arbitration modules has two outputs, one of which is connected with 16 memory bank response chip select modules, and the other of which is connected with 16 accelerator response crossbar modules;

[0064] The memory bank response chip select module outputs are connected with the central processor-external response arbitration module; and the 16 accelerator response crossbar module outputs are connected with 16 accelerator cluster access responses;

[0065] The two central processor-external response arbitration module outputs are connected with CPU access responses and external access responses respectively.

[0066] The arbitration results of the first circuit are connected with the third circuit to realize multiplexing, as shown in the following figure: Figure 1 Each response module takes the arbitration results of the request module with the corresponding name as the module input, without the need to recalculate the arbitration, thereby reducing the circuit complexity on the data path and further reducing the access delay of the CPU and the accelerator cluster. In some specific embodiments, the central processor-accelerator response arbitration module corresponds to the central processor-external request arbitration module, and the arbitration result of the former is taken as the input of the latter; the memory bank request chip select module corresponds to the memory bank corresponding chip select module, and the arbitration result of the former is taken as the input of the latter; and the like.

[0067] In order to realize CPU access without waiting and reduce the average delay, in a preferred embodiment of the present application, the central processor-external request arbitration module and the central processor-accelerator request arbitration module use CPU priority fixed priority arbitration, specifically: the central processor-external request arbitration module and the accelerator request arbitration module realize fixed priority arbitration based on a 2-to-1 multiplexer, and once the valid signal of the CPU access request is valid, the CPU side is enabled, so that the CPU access is prioritized, and the CPU access delay is reduced;

[0068] Because the CPU request, response has the special circuit line connection on the circuit, in order to prevent the arbitration of corresponding module to go astray, central processing unit-external response arbitration module is based on 2 selects 1 multiplexer implementation, with central processing unit-external request arbitration module is based on signal multicast sharing arbitration, guarantee CPU access request then response CPU access, external access request then response external access, let response return to corresponding response channel.

[0069] In order to further reduce CPU, accelerator access delay, and improve maximum access parallelism, in a preferred embodiment of the application, memory bank request chip select module is based on 16-way multiplexer, according to the address of CPU or external access strobe input to the corresponding address central processing unit-accelerator request arbitration module;

[0070] Memory bank response chip select module is based on 16-way multiplexer, based on signal multicast and memory bank request chip select module sharing arbitration, ensure that the response data comes from the correct access request.

[0071] In order to further improve the accelerator access parallelism, inhibit port contention, in a preferred embodiment of the application, accelerator request crossbar module adopts crossbar interconnection technology of butterfly topology, allows multiple accelerators to access multiple arbitrary different memory banks at the same time, specifically:

[0072] Accelerator request crossbar module adopts crossbar interconnection architecture of butterfly topology on the main path containing address, data, valid signal. The crossbar interconnection architecture is generally matrix, the specific number of crossbars is: if the accelerator is 2^n, n is any positive integer, then (2^n)*n crossbars are needed; If the accelerator is in the interval of 2^(n-1)~2^n, n is any positive integer, then (2^n)*n crossbars are also needed, the redundant crossbar input and output ports are not connected to the accelerator, the input is connected to logic 0, and the output is empty.

[0073] Further, as shown in Figure 3 (b), the input of valid signal and address high 4 bits is connected to Figure 3 (a) shown in crossbar control matrix. Figure 3 Each input of (b) is connected to the same number of accelerator access requests. Figure 3 Each crossbar in the architecture shown in (b) is controlled by Figure 3 (a) control matrix 1 2 select 1 arbiter output. Figure 3 Each arbiter in (a) control matrix is polled according to one bit of input valid signal and address. Figure 3(a) The first column arbiter in (a) arbitrates based on the input valid signal and the highest address bit, the second column arbitrates based on the valid signal and the second highest address bit, and so on. The crossbar can change the connection between two inputs and two outputs from parallel to cross, thus enabling two input-output paths to be connected at the same time, increasing parallelism. By combining different topologies, multiple crossbars based on different geometric topologies can achieve more parallel interconnection of inputs and outputs. For example, Figure 3 (b) The butterfly topology shown in (b) saves crossbars compared to the mesh topology, while achieving parallel interconnection of 16 groups of inputs and outputs, making the accelerator cluster access parallelism 16 times higher than shared bus or multiplexer, which only allows one input to connect to 16 groups of outputs at a time.

[0074] The accelerator response crossbar module only has Figure 3 The crossbar interconnection architecture of the butterfly topology shown in (b) without the control matrix requires arbitration results based on signal multicasting and accelerator request crossbar module sharing, as shown in Figure 2 Unlike the accelerator request crossbar module, the outputs of its crossbar are connected to the corresponding accelerator access response by number.

[0075] In a preferred embodiment of the present application, the 16 central processor-accelerator request arbitration modules and the central processor-external request arbitration module are designed the same way, and the chip select input is realized by the CPU valid signal, making the accelerator access priority the lowest (the access in the embodiment of the present application is divided into three levels: external, accelerator, and CPU, with the CPU having the highest priority, the external in the middle, and the accelerator the lowest. In the central processor-external request arbitration module, the external access and the CPU are arbitrated at the same time, with the CPU having the highest priority; in the central processor-accelerator response arbitration module, it is possible that the output selected by the previous stage is the external access (when there is no simultaneous CPU access), at which time the external access and the accelerator are arbitrated at the same time, with the external access having higher priority than the accelerator; therefore, the priority of the accelerator access is the lowest among the three accesses, and the low delay of the other two accesses (CPU and external access) is guaranteed. The CPU access request is to execute instructions, and the access time is usually short and frequent. Since the accelerator cluster needs a large amount of data to start computing, the time is relatively long compared to the short delay of the CPU access, so the negative effect is not significant, while the positive effect of shortening the CPU access delay on improving the execution speed of instructions is very obvious. Figure 2 , the 16 central processor-accelerator response arbitration modules and the central processor-external response arbitration module are designed the same way, and the arbitration is shared based on signal multicasting with the central processor-accelerator request arbitration module.

[0076] In order to realize the inhibition of port contention, reduce CPU and accelerator access delay, and improve the maximum access parallelism, in a preferred embodiment of the present application, the multi-bank memory module adopts multi-bank technology and single-port storage technology, specifically:

[0077] There are various design schemes for SRAM, including dual-port and single-port designs. However, the embodiments of the present application focus on single-port storage technology. Specifically, 16 single-port SRAM banks with low access delay are used to jointly build a multi-bank memory module. This unique design scheme ensures the high efficiency of the memory.

[0078] On the basis of the multi-bank technology, the multi-bank memory module builds a complete address space, and each SRAM bank is responsible for processing 1 / 16 segment addresses in the address space and corresponds to the chip select address of the bank request chip select module. The design of this multi-bank memory module allows parallel access to different SRAM banks, thereby achieving 16 times access parallelism and significantly improving the overall performance.

[0079] In order to meet the circuit delay requirements and synchronize the timing alignment, in a preferred embodiment, 2-stage flip-flops are added on all arbitration-shared data paths, and 1-stage flip-flops are added on all data paths connected to the multi-bank memory module.

[0080] In an embodiment of the present application, the above-mentioned storage circuit is applied, as shown in Figure 4 , which is an application schematic diagram of the storage circuit directly shared by the central processor and the accelerator cluster in an AIoT chip system product. The AIoT chip system directly sharing storage by the central processor and the accelerator cluster mainly consists of an AIoT accelerator cluster, an embedded CPU, a storage circuit directly shared by the central processor and the accelerator cluster, an external device bus bridge, four peripheral interfaces, and an external global storage. The storage circuit directly shared by the central processor and the accelerator cluster is shared by the AIoT accelerator cluster, the embedded CPU, and the external device bus bridge, as shown in Figures 1-3 . The external device bus bridge is connected to the port in the present application through an external access request bus and an external access response bus, and is used for external device access to the present application for data transmission or debugging. Figure 1

[0081] As shown in Figure 4 , the AIoT accelerator cluster contains 16 accelerators which can be of different types and are used to perform key AI task acceleration. Each accelerator of the AIoT accelerator cluster has a pair of access request and access response connected to the port in the present application. Figure 1 ​The corresponding ports are connected and used for writing and reading data, respectively. Multiple accelerators may simultaneously access this solution for reading and writing. The AIoT accelerator cluster has a bidirectional bus that directly connects to the external device bus bridge, used to connect to external storage when the storage space of this invention is insufficient, or to connect to external devices during debugging or other situations. The AIoT accelerator cluster and the embedded CPU have a control bus that only supports instruction transmission, used by the CPU to allocate tasks and control the AIoT accelerator cluster. The main data transmission between the embedded CPU and the AIoT accelerator cluster is still carried out through the direct storage sharing of this invention.

[0082] The embedded CPU, used to run general-purpose AIoT software programs to perform general processing tasks, is directly connected to this solution without any other memory in between, thus resulting in high-frequency access to this invention. The embedded CPU's access to this invention is primarily for instruction execution, requiring low latency but short access durations per access. For example... Figure 4 The embedded CPU communicates with the present invention through two paths: CPU access request and CPU access response. Figure 1 Data reading and writing are achieved through the connection of ports within the device. In addition to being connected to the AIoT accelerator cluster and this invention, the embedded CPU is also connected to the external device bus controller via a bidirectional bus to control peripherals and access external memory.

[0083] This AIoT chip system, through this invention, can efficiently execute general processing tasks and AI acceleration tasks, thereby achieving intelligent control and sensing. It also possesses rich peripheral interfaces, enabling it to drive and connect to various external IoT peripherals. This AIoT chip system serves as the core control chip for circuit boards of various smart IoT products, such as smart AR / VR glasses, face / voice recognition vending machines, and smart recognition cameras.

[0084] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention. The above preferred features can be used in any combination without conflict.

Claims

1. A storage circuit for direct sharing between a central processing unit and an accelerator cluster, characterized in that, The first circuit, the second circuit and the third circuit are sequentially connected; The first circuit comprises a central processor-external request arbitration module, a memory bank request chip select module and a central processor-accelerator request arbitration module which are sequentially connected, and an accelerator request crossbar module connected with the central processor-accelerator request arbitration module; The second circuit comprises a multi-memory bank memory module; The third circuit comprises a central processor-accelerator response arbitration module, a memory bank response chip select module and a central processor-external response arbitration module which are sequentially connected, and an accelerator response crossbar module connected with the central processor-accelerator response arbitration module; The arbitration result of the first circuit is connected to the third circuit to realize multiplexing; The first circuit, the second circuit and the third circuit are based on multi-memory bank technology, single-port storage technology, fixed priority arbitration technology, butterfly topology crossbar interconnection technology and signal multiplexing technology, and are used to reduce CPU and accelerator access delay and improve maximum access parallelism.

2. The circuit of claim 1, wherein, In the first circuit, the external access request and the CPU access request are connected to the central processor-external request arbitration module; meanwhile, the N accelerator cluster access requests are connected to the accelerator request crossbar module; The central processor-external request arbitration module is connected to the memory bank request chip select module; The memory bank request chip select module output is simultaneously connected to the N central processor-accelerator request arbitration modules; The N outputs of the accelerator request crossbar module are connected to the N central processor-accelerator request arbitration modules; the outputs of the N central processor-accelerator request arbitration modules are connected to the second circuit; In the third circuit, the N groups of outputs of the second circuit are respectively connected to the N central processor-accelerator response arbitration modules; Each of the central processor-accelerator response arbitration modules has two outputs, one of which is connected to the memory bank response chip select module, and the other of which is connected to the accelerator response crossbar module; The memory bank response chip select module output is connected to the central processor-external response arbitration module; The N groups of outputs of the accelerator response crossbar module are connected to the N access responses of the accelerator cluster; The central processor-external response arbitration module has two groups of outputs, one of which is connected to the CPU access response, and the other of which is connected to the external access response.

3. The circuit of claim 1, wherein, The central processor-external request arbitration module and the central processor-accelerator request arbitration module use CPU priority fixed priority arbitration to realize CPU access without waiting and reduce average delay, including that the central processor-external request arbitration module and the central processor-accelerator request arbitration module realize fixed priority arbitration based on a 2-to-1 multiplexer, and the valid signal of the CPU access request is selected as the CPU side as soon as it is valid; The central processor-external response arbitration module is based on a 2-to-1 demultiplexer, and the central processor-external request arbitration module is based on signal multiplexing technology, and the CPU access request responds to the CPU access, and the external access request responds to the external access.

4. The circuit of claim 1, wherein, The memory bank request chip select module is based on an N-way multiplexer, and according to the address accessed by the CPU or the outside, the address is gated to the corresponding central processor-accelerator request arbitration module; The memory bank response chip select module is based on an N-way multiplexer, and based on signal multiplexing technology, the memory bank response chip select module shares arbitration with the memory bank request chip select module, and ensures that the response data comes from the correct access request.

5. The circuit of claim 1, wherein, The accelerator request crossbar module adopts a butterfly topology crossbar interconnection technology, allows multiple accelerators to access multiple different memory banks at the same time, and is used to improve the parallelism of accelerator access and suppress port contention, and includes: The accelerator request crossbar module adopts a butterfly topology crossbar interconnection architecture on a path containing an address, data, and an effective signal; Each crossbar can change the connection between two inputs and two outputs to be parallel or cross, so that two input and output paths are connected at the same time, and the parallelism is improved. Each crossbar includes a crossbar control matrix.

6. The circuit of claim 5, wherein, The control process of the 2-to-1 arbitrator is that each arbitrator in the control matrix arbitrates according to each bit of the input effective signal and the address. The crossbar control matrix receives valid signals and address high log2 N bits from the 2-to-1 arbiter output control. The accelerator response crossbar module only includes a butterfly topology crossbar interconnection architecture, and the required arbitration result is shared with the accelerator request crossbar module based on signal multiplexing technology.

7. The circuit of claim 5, wherein, The central processor-accelerator request arbitration module and the central processor-external request arbitration module have the same structure, and the chip select input is realized through the CPU effective signal, the access priority of the accelerator is realized to be the lowest, and the address and data are realized to have low delay.

8. The circuit of claim 1, wherein, The central processor-accelerator response arbitration module and the central processor-external response arbitration module have the same structure, and share arbitration with the central processor-accelerator request arbitration module based on signal multiplexing technology. The multi-memory bank memory module adopts a multi-memory bank technology and a single-port storage technology, is used to suppress port contention, reduce CPU and accelerator access delay, and improve the maximum access parallelism, and includes:

9. The circuit of claim 1, wherein, The multi-memory bank memory module includes N single-port SRAM memory banks; the multi-memory bank memory module constitutes a complete address space, each SRAM memory bank corresponds to 1 / N of the address, and the chip select address of the memory bank request chip select module corresponds to the chip select address; the multi-memory bank memory module allows parallel access to different SRAM memory banks, and provides N times access parallelism. Two-stage flip-flops are added to all arbitration-shared data paths, and one-stage flip-flops are added to all data paths connected to the multi-memory bank memory module, so as to meet the circuit delay requirement and synchronize the timing alignment.

10. The circuit of claim 1, wherein, ​

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