Driving circuit of display panel, display panel and display device

Abstract

The application relates to a driving circuit of a display panel, the display panel and a display device. The driving circuit comprises a plurality of gate lines and a timing controller. The pixel architecture of the display panel is a double-gate architecture. In the driving circuit, the gate lines correspond to scanning lines one by one. The gate lines are used for providing scanning signals to the scanning lines. An output switching circuit is arranged between a gate line G4n+2 and a gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected with the output switching circuit, and the output switching circuit is used for switching the outputs of the gate line G4n+2 and the gate line G4n+3 when receiving a double-line gate function selection signal sent by the timing controller. The application exchanges the outputs of the gate line G4n+2 and the gate line G4n+3, so that the DRD architecture does not misfire when performing double-line gate output, perfectly adapts to the double-line gate function, and solves the technical problem that the double-gate architecture misfires when the double-line gate function is started.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to a driving circuit of a display panel, a display panel and a display device. BACKGROUND

[0002] Currently, the commonly used panel architecture in the market is Strip architecture and Z architecture. Currently, there is Dual Gate architecture (i.e., DRD architecture, double-gate architecture) glass. Compared with the above glass architecture, the number of COF (Chip on Film, chip soft packaging technology) is small, and the cost is lower. However, the mainstream DRD architecture has the problem of incorrect charging due to the fact that two adjacent pixels connected to the same data line in the same row of pixels are connected to two adjacent gate lines. Once the DLG (Dual Line Gate, double-line gate) function is turned on, the problem of incorrect charging occurs.

[0003] Currently, there is no effective solution to the problem of incorrect charging when the DLG function of the DRD architecture is turned on. SUMMARY

[0004] The present application provides a driving circuit of a display panel, a display panel and a display device to solve the technical problem of incorrect charging when the double-gate architecture turns on the double-line gate function.

[0005] According to an aspect of an embodiment of the present application, the present application provides a driving circuit of a display panel, comprising a plurality of gate lines and a timing controller, the pixel architecture of the display panel is a double-gate architecture, and in the double-gate architecture, every two pixels in the same row of pixels are connected to a data line, and two adjacent pixels connected to the same data line in the same row of pixels are connected to different scanning lines. In the driving circuit, the gate lines correspond one-to-one to the scanning lines, the gate lines are used to provide scanning signals to the scanning lines, an output switching circuit is arranged between gate line G4n+2 and gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected to the output switching circuit, and the output switching circuit is used to exchange the outputs of the gate line G4n+2 and the gate line G4n+3 when receiving a double-line gate function selection signal sent by the timing controller.

[0006] Optionally, the output switching circuit comprises an output truncation component, an output switching component and a switching control component, the output truncation component is arranged on the gate line G4n+2 and the gate line G4n+3 respectively, the input end of the output switching component is connected before the position of the output truncation component on the gate line G4n+2 and the gate line G4n+3, the output end of the output switching component is connected after the position of the output truncation component on the gate line G4n+2 and the gate line G4n+3, and the switching control component is connected to the output switching component.

[0007] Optionally, the output switching component comprises a first transistor and a second transistor, a first end of the first transistor is connected with an input end of the gate line G4n+3, a second end of the first transistor is connected with an output end of the gate line G4n+3, a control end of the first transistor is connected with the switching control component and the timing controller, a first end of the second transistor is connected with an input end of the gate line G4n+2, a second end of the second transistor is connected with an output end of the gate line G4n+2, a control end of the second transistor is connected with the switching control component and the timing controller.

[0008] Optionally, the output switching component comprises a third transistor and a fourth transistor, a first end of the third transistor is connected with an input end of the gate line G4n+2, a second end of the third transistor is connected with an output end of the gate line G4n+3, a control end of the third transistor is connected with the switching control component, a first end of the fourth transistor is connected with an input end of the gate line G4n+3, a second end of the fourth transistor is connected with an output end of the gate line G4n+2, a control end of the fourth transistor is connected with the switching control component.

[0009] Optionally, the first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors.

[0010] Optionally, the switching control component comprises a first capacitor, a second capacitor, a first diode and a second diode, one end of the first capacitor is connected with the timing controller, the other end is connected with a positive electrode of the first diode, a negative electrode of the first diode is grounded, one end of the second capacitor is connected with a negative electrode of the first diode, the other end is connected with a positive electrode of the second diode, the other end is also connected with control ends of the third transistor and the fourth transistor respectively, a negative electrode of the second diode is connected with a positive electrode of the first diode.

[0011] Optionally, when the timing controller does not send the double-line gate function selection signal, the working state of the driving circuit comprises: one end of the first capacitor is high potential, the other end is inputted to ground by the second diode and reflected as low potential, so that the control ends of the third transistor and the fourth transistor receive low potential, control the third transistor and the fourth transistor to be closed, the control ends of the first transistor and the second transistor receive high potential, control the first transistor and the second transistor to be opened.

[0012] Optionally, when the timing controller sends the double-line gate function selection signal, the working state of the driving circuit includes: the double-line gate function selection signal is at low level, the control ends of the first transistor and the second transistor receive low level, the first transistor and the second transistor are controlled to be closed, one end of the first capacitor receives low level, the other end is reflected as a lower level reaching the turn-on voltage of the third transistor and the fourth transistor due to the limitation of the voltage difference unable to jump, the third transistor and the fourth transistor are turned on, and the output of the gate line G4n+2 and the gate line G4n+3 is exchanged.

[0013] Optionally, the timing controller is further configured to: send the double-line gate function selection signal to exchange the output of the gate line G4n+2 and the gate line G4n+3 when it is determined that the display panel is running in the DLG mode; and not send the double-line gate function selection signal when it is determined that the display panel is running in the HSR mode or the normal mode.

[0014] According to still another aspect of the embodiments of the present application, the present application provides a display panel, comprising an array substrate, a color film substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate, and the array substrate comprises the driving circuit as described above.

[0015] According to still another aspect of the embodiments of the present application, the present application provides a display device, comprising a backlight module and the display panel as described above, and the backlight module is arranged on the backlight side of the array substrate and is configured to provide a light source for the display panel.

[0016] The above technical solutions provided by the embodiments of the present application have the following advantages compared with related art:

[0017] The application provides a driving circuit of a display panel, comprising a plurality of gate lines and a timing controller, a pixel architecture of the display panel is a double-gate architecture, in the double-gate architecture, every two pixels of the same row of pixels are connected with a data line, and two adjacent pixels connected with the same data line in the same row of pixels are connected with different scanning lines respectively, in the driving circuit, the gate lines correspond to the scanning lines one by one, the gate lines are used for providing scanning signals to the scanning lines, an output switching circuit is arranged between a gate line G4n+2 and a gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected with the output switching circuit, and the output switching circuit is used for switching the output of the gate line G4n+2 and the gate line G4n+3 when receiving a double-line gate function selection signal sent by the timing controller. The application exchanges the output of the gate line G4n+2 and the gate line G4n+3, so that the DRD architecture does not misfire when performing double-line gate output, perfectly adapts to the double-line gate function, and solves the technical problem that the double-gate architecture misfires when the double-line gate function is started. Meanwhile, the output switching circuit can also control whether to switch the output of the gate line G4n+2 and the gate line G4n+3 according to different display modes, so as to ensure normal display under different modes. BRIEF DESCRIPTION OF DRAWINGS

[0018] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0020] Figure 1 The driving circuit structure diagram of the display panel provided in the first embodiment of the application;

[0021] Figure 2 The stripe architecture diagram provided in the first embodiment of the application;

[0022] Figure 3 The DLG function timing diagram of the stripe architecture provided in the first embodiment of the application;

[0023] Figure 4 The DRD architecture diagram provided in the first embodiment of the application;

[0024] Figure 5 The DLG function timing diagram of the DRD architecture provided in the first embodiment of the application;

[0025] Figure 6 FIG. 1 is a schematic diagram of a driving circuit of a display panel according to an embodiment of the present application;

[0026] Figure 7 FIG. 2 is a schematic diagram of a structure of another display panel according to an embodiment of the present application;

[0027] Figure 8 FIG. 3 is a schematic diagram of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0029] In the following description, the suffixes such as "module", "part", or "unit" used for an element are merely for facilitating the description of the present application, and have no specific meaning by themselves. Thus, "module" and "part" can be used interchangeably.

[0030] In order to solve the problems mentioned in the background, according to an aspect of an embodiment of the present application, a driving circuit of a display panel is provided, the pixel architecture of the display panel is a dual gate architecture, in the dual gate architecture, every two pixels of the same row of pixels are connected with a data line, and two adjacent pixels in the same row of pixels connected with the same data line are respectively connected with different scan lines, as shown in FIG. 1, the driving circuit includes a plurality of gate lines (gate lines G4n+2 and G4n+3 are shown in the figure) and a timing controller Tcon, in the driving circuit, the gate lines correspond to the scan lines one by one, an output switching circuit is arranged between the gate line G4n+2 and the gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected with the output switching circuit, and the output switching circuit is used for switching the output of the gate line G4n+2 and the gate line G4n+3 when receiving a dual line gate function selection signal sent by the timing controller. Figure 1 The DLG (Dual Line Gate) function is to scan once every two rows, on a 4K screen (3840X2160), a total of 2160 rows need to be scanned for each frame of image, and 60 frames of screen can be scanned per second. Now only 1080 times need to be scanned, the time is reduced by half, and 120 frames of screen can be scanned per second.

[0031] As shown in FIG. 2, the display panel includes a plurality of gate lines (gate lines G4n+2 and G4n+3 are shown in the figure) and a timing controller Tcon, in the driving circuit, the gate lines correspond to the scan lines one by one, an output switching circuit is arranged between the gate line G4n+2 and the gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected with the output switching circuit, and the output switching circuit is used for switching the output of the gate line G4n+2 and the gate line G4n+3 when receiving a dual line gate function selection signal sent by the timing controller.

[0032] Figure 2 ​In the stripe architecture shown, pixels in the same row are connected to different data lines. Therefore, when the stripe architecture enables DLG functionality, its timing is as follows: Figure 3 As shown, each pair of adjacent scan lines (grid lines) are opened simultaneously. Taking a full blue screen as an example, since the blue and green pixels in the first row of the stripe architecture are connected to different data lines, when the first and second grid lines are opened, only blue pixels will be written with blue pixel data, and green pixels will not be overwritten.

[0033] And when Figure 4 When enabling DLG functionality in the DRD architecture shown, since two adjacent pixels in the same row are connected to the same data line, then according to... Figure 3 When implementing the DLG function using the timing shown, taking a full-red screen as an example, the two adjacent scan lines are turned on simultaneously. Because... Figure 4 In the DRD architecture shown, the red and green pixels in the first row are connected to the same data line, so the green pixel will also be written with the data of the red pixel, resulting in misfilling. The purpose of this application is to solve the misfilling problem that occurs when the DRD architecture enables the DLG function. To this end, this application swaps the outputs of gate lines G4n+2 and G4n+3, so that when the DRD architecture enables the DLG function, the CLK signals of gate lines G4n+2 and G4n+3 are exchanged. Figure 5 As shown, the CLK signals of G4n+1 and G4n+3 are the same, and the CLK signals of G4n+2 and G4n+4 are the same. Therefore, the DLG function of the DRD architecture can be realized without charge error, which solves the technical problem of charge error when the dual-gate architecture enables the dual-line gate function.

[0034] In the embodiments of this application, such as Figure 5 As shown, when using the DLG function, G1 and G3 need to be turned on simultaneously on the gate side, G2 and G4 need to be turned on simultaneously on the next row, and so on. Gate lines G4n+1 and G4n+3, and gate lines G4n+2 and G4n+4 are turned on alternately. Gate lines G4n+1 and G4n+3 are turned on simultaneously, and gate lines G4n+2 and G4n+4 are turned on simultaneously. When G1 and G3 are turned on simultaneously, the outputs of G2 and G3 are swapped, so the first and second rows are actually scanned. When G2 and G4 are turned on simultaneously, the outputs of G2 and G3 are swapped, so the third and fourth rows are actually scanned. Therefore, it is possible to scan rows 4n+1 and 4n+2 or rows 4n+3 and 4n+4 in one scan, thus realizing the DLG function.

[0035] In an optional embodiment, the output switching circuit includes an output cutoff component, an output switching component, and a switching control component. The output cutoff component is respectively disposed on the gate line G4n+2 and the gate line G4n+3. The input terminal of the output switching component is connected to the gate line G4n+2 and the gate line G4n+3 before the position of the output cutoff component, and the output terminal of the output switching component is connected to the gate line G4n+2 and the gate line G4n+3 after the position of the output cutoff component. The switching control component is connected to the output switching component.

[0036] In this embodiment, the CLK signal on each gate line is normally transmitted on one gate line. If gate line G4n+2 is enabled, the corresponding CLK4n+2 signal is transmitted only on gate line G4n+2. Therefore, to prevent misalignment when enabling the DLG function in the DRD architecture, this application needs to exchange the CLK signals of gate lines G4n+2 and G4n+3. Before the exchange, the output cutoff component needs to prevent the CLK4n+2 signal from continuing to transmit on gate line G4n+2. The output cutoff component can directly disconnect gate line G4n+2. The output switching component exchanges the CLK signals of gate lines G4n+2 and G4n+3; that is, it switches CLK4n+2 to gate line G4n+3 for transmission and CLK4n+3 to gate line G4n+2 for transmission. The switching control component receives and responds to the control signals from the timing controller to switch the output. The following describes the process in conjunction with... Figure 6 The circuit shown is used to illustrate the driving circuit of the display panel provided in this application.

[0037] In an optional embodiment, such as Figure 6 As shown, the output cutoff component includes a first transistor T1 and a second transistor T2, with the first terminal of the first transistor T1 connected to the gate line G4n+3 ( Figure 6 (Taking n=0 and G3 as an example for explanation) The input terminal of the first transistor T1 is connected to the input terminal of the gate line G4n+3. The second terminal of the first transistor T1 is connected to the output terminal of the gate line G4n+2. The control terminal of the first transistor T1 is connected to the timing controller TCON through the switching control component. The first terminal of the second transistor T2 is connected to the input terminal of the gate line G4n+2. The second terminal of the second transistor T2 is connected to the output terminal of the gate line G4n+2. The control terminal of the second transistor T2 is connected to the timing controller TCON through the switching control component.

[0038] In the embodiments of this application, such as Figure 6As shown, the drain D of the first transistor T1 is connected with CLK3 IN, the source S of the first transistor T1 is connected with CLK3 OUT, when the first transistor T1 is opened, the CLK3 signal is transmitted along the gate line G3, when the first transistor T1 is closed, the G3 line is disconnected. The drain D of the second transistor T2 is connected with CLK2 IN, the source S of the second transistor T2 is connected with CLK2 OUT, when the second transistor T2 is opened, the CLK2 signal is transmitted along the gate line G2, when the second transistor T2 is closed, the G2 line is disconnected. The gate G of the first transistor T1 and the gate G of the second transistor T2 are connected with the timing controller, for receiving the DLG function selection signal, when the DLG function selection signal is enabled, it is low, that is, in the normal mode, the gate G of the first transistor T1 and the gate G of the second transistor T2 all receive high potential, the first transistor T1 and the second transistor T2 are opened, when in the DLG mode, the gate G of the first transistor T1 and the gate G of the second transistor T2 all receive low potential, the first transistor T1 and the second transistor T2 are closed.

[0039] In an optional embodiment, as shown in Figure 6 The output switching component includes a third transistor Q1 and a fourth transistor Q2, the first end of the third transistor Q1 is connected with the input end of the gate line G4n+2, the second end of the third transistor Q1 is connected with the output end of the gate line G4n+3, the control end of the third transistor Q1 is connected with the switching control component, the first end of the fourth transistor Q2 is connected with the input end of the gate line G4n+3, the second end of the fourth transistor Q2 is connected with the output end of the gate line G4n+2, and the control end of the fourth transistor Q2 is connected with the switching control component.

[0040] In the embodiment of the application, as shown in Figure 6 The source S of the third transistor Q1 is connected with CLK2 IN, the drain D of the third transistor Q1 is connected with CLK3 OUT, when the third transistor Q1 is opened, the CLK2 signal is exchanged to be transmitted on G3, the source S of the fourth transistor Q2 is connected with CLK3 IN, and the drain D of the fourth transistor Q2 is connected with CLK2 OUT, when the fourth transistor Q2 is opened, the CLK3 signal is exchanged to be transmitted on G2. The gate G of the third transistor Q1 and the gate G of the fourth transistor Q2 are both connected with the switching control component.

[0041] In an optional embodiment, the first transistor T1 and the second transistor T2 are NMOS tubes, and the third transistor Q1 and the fourth transistor Q2 are PMOS tubes.

[0042] In an optional embodiment, as shown in Figure 6As shown, the switching control component includes a first capacitor C1, a second capacitor C2, a first diode D1, and a second diode D2, one end of the first capacitor C1 is connected with the timing controller, the other end is connected with the positive electrode of the first diode D1, the negative electrode of the first diode D1 is grounded, one end of the second capacitor C2 is connected with the negative electrode of the first diode D1, the other end is connected with the positive electrode of the second diode D2, and the other end is also connected with the control end of the third transistor Q1 and the fourth transistor Q2 respectively, and the negative electrode of the second diode D2 is connected with the positive electrode of the first diode D1.

[0043] In an optional embodiment, when the timing controller does not send the double-line gate function selection signal, the working state of the driving circuit includes: one end of the first capacitor C1 is high, the other end is input to ground by the second diode D2 to reflect low, so that the control ends of the third transistor Q1 and the fourth transistor Q2 receive low to control the third transistor Q1 and the fourth transistor Q2 to be closed, and the control ends of the first transistor T1 and the second transistor T2 receive high to control the first transistor T1 and the second transistor T2 to be opened.

[0044] In the embodiment of the application, as shown in the figure, Figure 6 As shown, the initial potential of DLG_ON / OFF is high (assuming that the initial high voltage is set to 15V, and the design voltage is related to the selection of MOS), the voltage of point C is 0V because one end of the diode D2 is grounded, the voltage of point B is the initial high voltage, and the voltage of point A is 0V, at this time, the first transistor T1 and the second transistor T2 are opened, the CLK is normally output, and the third transistor Q1 and the fourth transistor Q2 are closed.

[0045] In an optional embodiment, when the timing controller sends the double-line gate function selection signal, the working state of the driving circuit includes: the double-line gate function selection signal is low, the control ends of the first transistor T1 and the second transistor T2 receive low to control the first transistor T1 and the second transistor T2 to be closed, one end of the first capacitor C1 receives low, and the other end reflects a lower potential reaching the turn-on voltage of the third transistor Q1 and the fourth transistor Q2 due to the limitation of the voltage difference unable to jump, so that the third transistor Q1 and the fourth transistor Q2 are opened, and the output of the gate line G4n+2 and the gate line G4n+3 are exchanged.

[0046] In the embodiment of the application, as shown in the figure, Figure 6As shown, when the DLG_ON / OFF initial potential is low (assuming: initial setting low voltage = 0V), at this time, since the voltage difference across the capacitor cannot be abruptly changed, the voltage at point C is -15V, and through diode D1, the voltage at point A is -15V and the voltage at point B is 0V; at this time, the third transistor Q1 and the fourth transistor Q2 are turned on, the first transistor T1 and the second transistor T2 are turned off, and CLK alternately outputs. At this time, combined with the DRD architecture, CLK1 and CLK3 need to output the same signal at the same time, CLK2 and CLK4 need to output the same signal at the same time, and the rest of the CLKs are sequentially output. In this way, the normal pattern can be displayed, and the wrong charging can be avoided.

[0047] In an optional embodiment, the timing controller is further configured to: in a case where it is determined that the display panel operates in the DLG mode, output the double gate function selection signal to exchange the output of the gate line G4n+2 and the gate line G4n+3; and in a case where it is determined that the display panel operates in the HSR mode or the normal mode, the timing controller does not output the double gate function selection signal.

[0048] In the embodiments of the present application, the display mode of the display panel can include, but is not limited to, the normal mode, the HSR (Hardware Super Resolution) mode and the DLG mode. In the normal mode or the HSR mode, no exchange of output is needed, the DLG_ON / OFF potential is high, the voltage at point C is 0V due to the ground at one end of diode D2, the voltage at point B is the initial high voltage, and the voltage at point A is 0V. At this time, the first transistor T1 and the second transistor T2 are turned on, CLK normally outputs, and the third transistor Q1 and the fourth transistor Q2 are turned off. In the DLG mode, the output needs to be exchanged, the timing controller outputs the double gate function selection signal, and the DLG_ON / OFF becomes low. At this time, since the voltage difference across the capacitor cannot be abruptly changed, the voltage at point C is -15V, and through diode D1, the voltage at point A is -15V and the voltage at point B is 0V. At this time, the third transistor Q1 and the fourth transistor Q2 are turned on, the first transistor T1 and the second transistor T2 are turned off, and CLK alternately outputs.

[0049] The following is a comparison of DLG, HSR, and normal modes. As mentioned earlier, DLG mode requires scanning every two rows of pixels together, HSR mode renders only the odd or even rows of pixels in each frame, while the other row is displayed by merging information from the adjacent two rows, and normal mode completes this by scanning each row of pixels sequentially. Therefore, in normal or HSR modes, the scan lines are opened sequentially, but the opening time for each row in normal mode is longer than in HSR. In DLG mode, two scan lines may be open simultaneously. Thus, the CLK signal in normal or HSR modes can be transmitted along the original path without needing to switch the outputs of gate lines G4n+2 and G4n+3 using a switching circuit. However, in DLG mode, if adjacent scan lines are opened simultaneously, a misfilling problem will occur. Therefore, the outputs of gate lines G4n+2 and G4n+3 can be swapped, allowing scan lines in alternate rows to be opened simultaneously. This allows DLG mode to be implemented without misfilling, while ensuring normal display of other modes.

[0050] This application provides a driving circuit for a display panel, including multiple gate lines and a timing controller. In the driving circuit, an output switching circuit is provided between gate lines G4n+2 and G4n+3, where n is an integer greater than or equal to 0. The timing controller is connected to the output switching circuit. The output switching circuit is used to switch the outputs of gate lines G4n+2 and G4n+3 when it receives a dual-gate function selection signal from the timing controller. By switching the outputs of gate lines G4n+2 and G4n+3, this application ensures that the DRD architecture does not experience misalignment when performing dual-gate output, perfectly adapting to the dual-gate function and solving the technical problem of misalignment that occurs when the dual-gate architecture enables the dual-gate function.

[0051] According to another aspect of the embodiments of this application, this application provides an embodiment of a display panel, such as... Figure 7 As shown, the display panel includes an array substrate 100, a color filter substrate 300, and a liquid crystal layer 400 disposed between the array substrate 100 and the color filter substrate 300. The array substrate 100 includes the driving circuit described above.

[0052] According to another aspect of the embodiments of this application, this application provides an embodiment of a display device, such as... Figure 8 As shown, the display device includes a backlight module 200 and the aforementioned display panel. The backlight module 200 is disposed on the backlight side of the array substrate 100 and is used to provide a light source to the display panel.

[0053] The foregoing detailed description of the application has been presented for purposes of illustration and description. Various modifications and changes can be made to these embodiments without departing from the spirit and scope of the application. It is intended that the scope of the application should not be limited by the particular representative embodiments described above.

Claims

1. A driving circuit for a display panel, comprising multiple gate lines and a timing controller, characterized in that, The display panel has a dual-gate pixel architecture. In the dual-gate architecture, every two pixels in the same row are connected to a data line. Two adjacent pixels in the same row connected to the same data line are connected to different scan lines. In the driving circuit, the gate lines correspond one-to-one with the scan lines. The gate lines are used to provide scan signals to the scan lines. An output switching circuit is provided between gate lines G4n+2 and G4n+3, where n is an integer greater than or equal to 0. The timing controller is connected to the output switching circuit. The output switching circuit is used to switch the outputs of gate lines G4n+2 and G4n+3 when it receives a dual-gate function selection signal from the timing controller.

2. The driving circuit for the display panel according to claim 1, characterized in that, The output switching circuit includes an output cutoff component, an output switching component, and a switching control component. The output cutoff component is respectively disposed on the gate line G4n+2 and the gate line G4n+3. The input terminal of the output switching component is connected to the gate line G4n+2 and the gate line G4n+3 before the position of the output cutoff component. The output terminal of the output switching component is connected to the gate line G4n+2 and the gate line G4n+3 after the position of the output cutoff component. The switching control component is connected to the output switching component.

3. The driving circuit for the display panel according to claim 2, characterized in that, The output cutoff component includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the input terminal of the gate line G4n+3, and the second terminal of the first transistor is connected to the output terminal of the gate line G4n+3. The control terminal of the first transistor is connected to the timing controller through the switching control component. The first terminal of the second transistor is connected to the input terminal of the gate line G4n+2, and the second terminal of the second transistor is connected to the output terminal of the gate line G4n+2. The control terminal of the second transistor is connected to the timing controller through the switching control component.

4. The driving circuit for the display panel according to claim 3, characterized in that, The output switching component includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to the input terminal of the gate line G4n+2, the second terminal of the third transistor is connected to the output terminal of the gate line G4n+3, and the control terminal of the third transistor is connected to the switching control component. The first terminal of the fourth transistor is connected to the input terminal of the gate line G4n+3, the second terminal of the fourth transistor is connected to the output terminal of the gate line G4n+2, and the control terminal of the fourth transistor is connected to the switching control component.

5. The driving circuit for the display panel according to claim 4, characterized in that, The first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors.

6. The driving circuit for the display panel according to claim 5, characterized in that, The switching control component includes a first capacitor, a second capacitor, a first diode, and a second diode. One end of the first capacitor is connected to the timing controller, and the other end is connected to the anode of the first diode. The cathode of the first diode is grounded. One end of the second capacitor is connected to the cathode of the first diode, and the other end is connected to the anode of the second diode. The other end is also connected to the control terminals of the third transistor and the fourth transistor, respectively. The cathode of the second diode is connected to the anode of the first diode.

7. The driving circuit for the display panel according to claim 6, characterized in that, When the timing controller does not issue the dual-line gate function selection signal, the operating state of the driving circuit includes: one end of the first capacitor is at a high potential, and the other end is grounded by the second diode, reflecting a low potential, so that the control terminals of the third transistor and the fourth transistor receive a low potential, controlling the third transistor and the fourth transistor to turn off; the control terminals of the first transistor and the second transistor receive a high potential, controlling the first transistor and the second transistor to turn on. When the timing controller issues the dual-gate function selection signal, the operating state of the driving circuit includes: the dual-gate function selection signal is at a low potential, the control terminals of the first transistor and the second transistor receive a low potential, controlling the first transistor and the second transistor to turn off, one end of the first capacitor receives a low potential, and the other end is limited by the voltage difference not being able to change abruptly, reflecting a lower potential that reaches the turn-on voltage of the third transistor and the fourth transistor, causing the third transistor and the fourth transistor to turn on, and exchanging the outputs of the gate line G4n+2 and the gate line G4n+3.

8. The driving circuit for the display panel according to claim 7, characterized in that, The timing controller is also used to: when it is determined that the display panel is operating in DLG mode, issue the dual-line gate function selection signal to exchange the outputs of gate line G4n+2 and gate line G4n+3; When it is determined that the display panel is operating in HSR mode or normal mode, the timing controller does not issue the dual-line gate function selection signal.

9. A display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, characterized in that, The array substrate includes the driving circuit as described in any one of claims 1 to 8.

10. A display device, characterized in that, It includes a backlight module and a display panel as described in claim 9, wherein the backlight module is disposed on the backlight side of the array substrate and is used to provide a light source to the display panel.

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