Method and apparatus for allocating quantum chip resources, and quantum computer

Abstract

The application discloses a quantum chip resource allocation method and device and a quantum computer. First, the physical topology structure of a quantum chip is acquired, and a constraint model of a working point of a target quantum bit is constructed, which is used to limit the size of XY crosstalk and residual ZZ coupling between the target quantum bit and adjacent quantum bits. Finally, the working point of each quantum bit in the quantum chip is allocated by using the physical topology structure and the constraint model. The quantum chip resource allocation method proposed in the application can meet the demand of a large-scale quantum chip by constructing the constraint model of the working point of the target quantum bit, and can make up for the blank of the prior art.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a method, apparatus and quantum computer for allocating quantum chip resources. Background Technology

[0002] Quantum computing and quantum information is an interdisciplinary field that uses the principles of quantum mechanics to perform computational and information processing tasks. It is closely related to quantum physics, computer science, and informatics. It has experienced rapid development in the last two decades. Quantum algorithms based on quantum computers, such as factorization and unstructured search, have demonstrated performance far exceeding that of existing algorithms based on classical computers, leading to expectations that this field will surpass current computing capabilities. Because quantum computing has the potential to far exceed the performance of classical computers in solving specific problems, realizing a quantum computer requires a quantum chip containing a sufficient number and quality of qubits, capable of performing high-fidelity quantum logic gate operations and readouts on these qubits. The quantum chip is to a quantum computer what a CPU is to a traditional computer; it is the core component of a quantum computer, the processor that performs quantum computations. Before each quantum chip is officially put into use, the parameters of the qubits within the chip must be tested and characterized.

[0003] To enable the most computations to be performed within the finite lifetime of each qubit in a quantum chip, the fastest possible qubit logic gates are required. Generally, the execution time of a qubit logic gate is three to four orders of magnitude faster than the qubit's lifetime. However, fast qubit logic gate operations can lead to errors during execution. There are many reasons for qubit logic gate errors, such as parasitic coupling between nearest and second nearest neighbor qubits, spectral spread two-level system (TLS) defects, parasitic microwave modes, coupling with control lines and readout resonators, noise from frequency control electronics, frequency control pulse distortion, microwave control pulse distortion, and microwave carrier leakage. When each qubit in the quantum chip is at a suitable operating point, the effects of these interferences can be effectively reduced. Currently, in order to improve the accuracy of quantum chips in performing quantum computing tasks, the operating point of a few qubits is generally considered. There is a lack of solutions that consider the quantum chip as a whole. Existing solutions are feasible when the number of qubits in the quantum chip is small, such as only a few or a dozen qubits. However, in the foreseeable future, the number of quantum chips will inevitably increase significantly. At that time, existing solutions will not be able to meet the needs of large-scale quantum chips.

[0004] Therefore, a quantum chip resource allocation scheme that can be considered from the perspective of the quantum chip as a whole is needed.

[0005] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a method, apparatus and quantum computer for allocating quantum chip resources, in order to address the lack of a quantum chip resource allocation scheme that considers the quantum chip as a whole in the existing technology.

[0007] To address the above technical problems, this application proposes a method for allocating quantum chip resources, including:

[0008] Obtain the physical topology of a quantum chip, which reflects the physical layout of the various devices in the quantum chip;

[0009] A constraint model for the operating point of the target qubit is constructed, which is used to limit the magnitude of XY crosstalk and residual ZZ coupling between the target qubit and neighboring qubits;

[0010] Using the physical topology and the constraint model, the operating point of each qubit in the quantum chip is assigned.

[0011] Optionally, the constraint model includes:

[0012] f i -f j ≥δ A1 ;

[0013] Among them, f i f is the frequency of the target qubit. j δ is the frequency of the neighboring qubit. A1 The first threshold is set.

[0014] Optionally, the constraint model further includes:

[0015] f i -f j -α j ≥δ A2 ;

[0016] Where, α j δ is the anharmonic size of a neighboring qubit. A2 The second threshold is set.

[0017] Optionally, the constraint model further includes:

[0018]

[0019] Among them, g ik f is the value of the residual ZZ coupling between the target qubit and the diagonal qubit. k δ is the frequency of the diagonal qubit. Z1 The third threshold is defined as follows: the diagonal qubit is a qubit that has a diagonal relationship with the target qubit in the physical topology.

[0020] Optionally, the constraint model further includes:

[0021] f i -f j <δ H1 ;

[0022] Where, δ H1 This is the fourth threshold that is set.

[0023] Optionally, the operating point of each qubit in the quantum chip is sequentially allocated according to a set order using the physical topology and the constraint model.

[0024] Optionally, the operating points of all previously acquired qubits are substituted into the constraint model as known parameters to obtain the operating points of subsequently acquired qubits.

[0025] Based on the same inventive concept, this application also proposes a quantum chip resource allocation device, comprising:

[0026] A physical topology acquisition unit is configured to acquire the physical topology of a quantum chip, the physical topology being used to reflect the physical layout of the various devices in the quantum chip.

[0027] A constraint model building unit is configured to build a constraint model of the operating point of a target qubit, the constraint model being used to limit the magnitude of XY crosstalk and residual ZZ coupling between the target qubit and neighboring qubits;

[0028] An allocation unit is configured to allocate the operating point of each qubit in the quantum chip using the physical topology and the constraint model.

[0029] Based on the same inventive concept, this application also proposes a quantum control system that utilizes the quantum chip resource allocation method described in any one of the above-described features, or includes the quantum chip resource allocation device described in the above-described features.

[0030] Based on the same inventive concept, this application also proposes a quantum computer, including the quantum control system described in the above feature description.

[0031] Based on the same inventive concept, this application also proposes a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the method for allocating quantum chip resources as described in any of the above-described features.

[0032] Compared with the prior art, this application has the following beneficial effects:

[0033] This application proposes a method for allocating quantum chip resources. First, the physical topology of the quantum chip is obtained, and a constraint model of the operating point of the target qubit is constructed. This constraint model limits the magnitude of XY crosstalk and residual ZZ coupling between the target qubit and neighboring qubits. Finally, using the physical topology and the constraint model, the operating point of each qubit in the quantum chip is allocated. This proposed method, by constructing a constraint model of the operating point of the target qubit and considering the chip as a whole, can meet the needs of large-scale quantum chips and fill a gap in existing technologies.

[0034] The quantum chip resource allocation device, quantum control system, quantum computer, and readable storage medium proposed in this application belong to the same inventive concept as the quantum chip resource allocation method, and therefore have the same beneficial effects, which will not be elaborated here. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating the quantum chip resource allocation method proposed in an embodiment of this application.

[0036] Figure 2 This is a schematic diagram of the structure of a quantum chip shown in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the structure of a quantum chip resource allocation device according to another embodiment of this application. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0039] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0041] Please refer to Figure 1 This application proposes a method for allocating quantum chip resources, including:

[0042] S100: Obtain the physical topology of the quantum chip, which reflects the physical layout of the various devices in the quantum chip;

[0043] S200: Construct a constraint model for the operating point of the target qubit, wherein the constraint model is used to limit the magnitude of XY crosstalk and residual ZZ coupling between the target qubit and neighboring qubits;

[0044] S300: Using the physical topology and the constraint model, assign the operating point of each qubit in the quantum chip.

[0045] The difference from existing technologies lies in the following: This embodiment proposes a method for allocating quantum chip resources. First, it obtains the physical topology of the quantum chip and constructs a constraint model for the operating point of the target qubit. This constraint model limits the magnitude of XY crosstalk and residual ZZ coupling between the target qubit and neighboring qubits. Finally, using the physical topology and the constraint model, the operating point of each qubit in the quantum chip is allocated. This proposed method for allocating quantum chip resources, by constructing a constraint model for the operating point of the target qubit, considers the chip as a whole and can meet the needs of large-scale quantum chips, filling a gap in existing technologies.

[0046] When allocating the operating points of qubits, residual ZZ coupling and XY crosstalk are the two main considerations, as they are the primary causes of gate execution errors. Residual ZZ coupling refers to unwanted coupling that persists even after the coupling between qubits has been turned off. Coupling between two qubits is a necessary condition for implementing a two-qubit gate, but when the two-qubit gate is not operating, the coupling between them needs to be turned off to avoid exciting unnecessary terms and thus ensure computational accuracy. XY crosstalk refers to the phenomenon where the driving frequency applied to one qubit causes anharmonic driving of other neighboring qubits.

[0047] Specifically, in this embodiment, in order to control the influence of XY crosstalk, it is necessary to prevent the driving frequency of the target qubit i from causing its neighboring qubit j to transition from a 0 state to a 1 state when the target qubit i is excited. The constraint model includes:

[0048] f i -f j ≥δ A1 (1)

[0049] Among them, f i f is the frequency of the target qubit. j δ is the frequency of the neighboring qubit. A1 The first threshold is set. It should be noted that the first threshold needs to be set according to the parameters of the specific quantum chip. In this embodiment, the first threshold can be set to 40MHz. In other embodiments, the first threshold can also be other values, which are not limited here.

[0050] Furthermore, in this embodiment, in order to control the influence of XY crosstalk, it is also necessary to prevent the driving frequency of the target qubit i from causing its nearest neighbor qubit j to transition from state 1 to state 2 when the target qubit i is excited. The constraint model also includes:

[0051] f i -f j -α j ≥δ A2 (2)

[0052] Where, α j δ is the anharmonic size of a neighboring qubit. A2 The second threshold is set. It should be noted that the second threshold needs to be set according to the parameters of the specific quantum chip. In this embodiment, the second threshold can be set to 40MHz. In other embodiments, the second threshold can also be other values, which are not limited here.

[0053] Specifically, in this embodiment, in order to control the influence of residual ZZ coupling, the residual ZZ coupling between the target qubit i and its diagonal qubit k is considered, so as to... Figure 2 For example, suppose the target qubit i is qubit Q. 33 Then the diagonal qubit k is Q. 22 Q 24 Q 42 Q 44 We need to control the residual ZZ coupling value to be less than a set value to control its effect. The constraint model also includes:

[0054]

[0055] Among them, g ikf is the value of the residual ZZ coupling between the target qubit and the diagonal qubit. k δ is the frequency of the diagonal qubit. Z1 The third threshold is defined as follows: the diagonal qubit is a qubit that is diagonally related to the target qubit in the physical topology. It should be noted that the third threshold needs to be set according to the parameters of the specific quantum chip. In this embodiment, the third threshold can be set to 0.01MHz. In other embodiments, the third threshold can be other values, which are not limited here. ik In this embodiment, it is set to 0.4MHz.

[0056] Specifically, in this embodiment, considering that the quantum chip needs to execute not only single-qubit logic gates but also two-qubit logic gates, if the operating point difference between two adjacent qubits is too large, it will cause errors in the hardware when executing the two-qubit logic gates, preventing them from being executed correctly. Therefore, it is also necessary to limit the frequency difference between two adjacent qubits within a certain range. Thus, the constraint model further includes:

[0057] f i -f j <δ H1 (4)

[0058] Where, δ H1 This is the fourth threshold value set. It should be noted that the fourth threshold value needs to be set according to the parameters of the specific quantum chip. In this embodiment, the fourth threshold value can be set to 600MHz. In other embodiments, the fourth threshold value can be other values, which are not limited here.

[0059] Based on the constraints of Formulas 1, 2, and 3 above, the objective equation is constructed as follows:

[0060] Func = -f i ;

[0061] What we need is that, under the above constraints, the closer the frequency of the target qubit is to its degeneracy point, the less noise interference the qubit will experience in the entire quantum chip.

[0062] Specifically, in this embodiment, the operating points of each qubit in the quantum chip are sequentially allocated according to a set order using the physical topology and the constraint model.

[0063] Furthermore, in this embodiment, the operating points of qubits closer to the center of the physical topology can be obtained first, followed by the operating points of qubits farther from the center of the physical topology. This approach maximizes the performance of the quantum chip and ensures that qubits whose suitable operating points cannot be determined appear at the edges of the physical topology of the quantum chip, effectively improving resource utilization in the quantum chip. Figure 2 Taking the quantum chip shown in the image as an example, Figure 2 The diagram shows the physical topology of a quantum chip containing 36 qubits in one embodiment. Point A is the center of the physical topology. According to the scheme of this application, we sequentially obtain the distance of each qubit in the quantum chip from point A, and then sequentially obtain the operating point of each qubit based on the distance. The operating points can be obtained in descending order of distance, or in ascending order of distance. It should be noted that when there are several qubits at the same distance from the center of the physical topology, the corresponding operating points are obtained from these qubits in a random order. For example, Figure 2 The quantum bit Q in 33 Q 34 Q 43 Q 44 Since these four qubits are equidistant from point A, they can acquire their corresponding operating points in a random order without restriction.

[0064] Specifically, in this embodiment, the operating points of all previously acquired qubits are substituted into the constraint model as known parameters to obtain the operating points of subsequently acquired qubits.

[0065] Please refer to Figure 3 Based on the same inventive concept, embodiments of this application also propose a quantum chip resource allocation device, comprising:

[0066] Physical topology acquisition unit 100 is configured to acquire the physical topology of a quantum chip, the physical topology being used to reflect the physical layout of the various devices in the quantum chip;

[0067] The constraint model building unit 200 is configured to build a constraint model of the operating point of the target qubit, the constraint model being used to limit the magnitude of XY crosstalk and residual ZZ coupling between the target qubit and neighboring qubits;

[0068] Allocation unit 300 is configured to allocate the operating point of each qubit in the quantum chip using the physical topology and the constraint model.

[0069] It is understood that the physical topology acquisition unit 100, the constraint model construction unit 200, and the allocation unit 300 can be implemented in a single device, or any one of these modules can be split into multiple sub-modules. Alternatively, at least some of the functions of one or more modules of the physical topology acquisition unit 100, the constraint model construction unit 200, and the allocation unit 300 can be combined with at least some of the functions of other modules and implemented in a single functional module. According to embodiments of the present invention, at least one of the physical topology acquisition unit 100, the constraint model construction unit 200, and the allocation unit 300 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable manner by integrating or packaging the circuitry, or in a suitable combination of software, hardware, and firmware implementations. Alternatively, at least one of the physical topology acquisition unit 100, the constraint model construction unit 200, and the allocation unit 300 may be implemented at least partially as a computer program module, which can perform the functions of the corresponding module when the program is run by a computer.

[0070] Based on the same inventive concept, embodiments of this application also propose a quantum control system that utilizes the quantum chip resource allocation method described in any one of the above-described features, or includes the quantum chip resource allocation device described in the above-described features.

[0071] Based on the same inventive concept, embodiments of this application also propose a quantum computer, including the quantum control system described in the above feature description.

[0072] Based on the same inventive concept, embodiments of this application also propose a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the quantum chip resource allocation method described in any of the above features.

[0073] The readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage in a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.

[0074] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0075] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0076] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0077] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for allocating quantum chip resources, characterized in that, comprising: acquiring a physical topology of a quantum chip, the physical topology being used to reflect a physical layout of each device in the quantum chip, the device comprising a qubit; constructing a constraint model of an operating point of a target qubit, the constraint model being used to limit a size of XY crosstalk and residual ZZ coupling between the target qubit and a neighboring qubit; allocating an operating point of each qubit in the quantum chip using the physical topology and the constraint model, the operating point of the qubit being a frequency of the qubit; wherein the constraint model comprises: ； wherein, g ik a value of a residual ZZ coupling between the target qubit and a diagonal qubit, f i a frequency of the target qubit, f k a frequency of the diagonal qubit, δ Z1 a third threshold value set, the diagonal qubit being a qubit in the physical topology that has a diagonal relationship with the target qubit.

2. The dispensing method of claim 1, wherein, the constraint model further comprises: ； wherein, f i is a frequency of the target qubit, f j is a frequency of an adjacent qubit, δ A1 is a first threshold value set.

3. The dispensing method of claim 2, wherein, the constraint model further comprises: ； wherein a j is the anharmonic size of the neighboring qubit, δ A2 is a second threshold value set.

4. The dispensing method of claim 3, wherein, the constraint model further comprises: ； wherein δ H1 is a fourth threshold value set.

5. The dispensing method of claim 1, wherein, allocating an operating point of each qubit in the quantum chip in a set order using the physical topology and the constraint model.

6. The dispensing method of claim 5, wherein, all previously acquired operating points of the qubits are substituted into the constraint model as known parameters to acquire a subsequently acquired operating point of the qubit.

7. A quantum chip resource allocation device, characterized in that, comprising: a physical topology acquisition unit configured to acquire a physical topology of a quantum chip, the physical topology being used to reflect a physical layout of each device in the quantum chip, the device comprising a qubit; a constraint model construction unit configured to construct a constraint model of an operating point of a target qubit, the constraint model being used to limit a size of XY crosstalk and residual ZZ coupling between the target qubit and a neighboring qubit; an allocation unit configured to allocate an operating point of each qubit in the quantum chip using the physical topology and the constraint model, the operating point of the qubit being a frequency of the qubit; wherein the constraint model comprises: ； wherein, g ik is a value of a residual ZZ coupling between the target qubit and a diagonal qubit, f i is a frequency of the target qubit, f k is a frequency of the diagonal qubit, δ Z1 is a third threshold value set, the diagonal qubit is a qubit in the physical topology that has a diagonal relationship with the target qubit.

8. A quantum control system, characterized by, using the quantum chip resource allocation method of any one of claims 1-6, or the quantum chip resource allocation apparatus of claim 7.

9. A quantum computer, characterized by comprising the quantum control system of claim 8.

10. A readable storage medium, having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the quantum chip resource allocation method of any one of claims 1-6.

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