A trench gate superjunction device with reduced input capacitance and a method for manufacturing the same

Abstract

The present invention discloses a trench-gate superjunction device with reduced input capacitance, comprising a superjunction charge balance region and a body region located at the top of the superjunction charge balance region. The superjunction charge balance region includes alternating first and second conductivity type columns. A trench gate is disposed within the body region at the top of the first conductivity type column. A source region is disposed on one side of the trench gate proximate to the second conductivity type column, and the source region is located within the body region of the first conductivity type column. The source region is connected to a source metal via a source contact hole. The present invention provides a trench-gate superjunction device with reduced input capacitance. By changing the position of the source region and the connection between the source region and the trench gate, the input capacitance of the superjunction MOSFET device is reduced, thereby improving the turn-on speed of the MOSFET device.

Description

Technical Field

[0001] The present invention relates to the field of preparation of super junction devices, and in particular to a trench gate super junction device with reduced input capacitance and a preparation method thereof. Background Art

[0002] Semiconductor superjunction devices are based on charge balance technology, that is, a structure composed of multiple groups of alternating N-type columns and P-type columns. Compared with conventional high-voltage MOSFET devices, the superjunction structure inserts P-type columns in the longitudinal drift region, which not only maintains high withstand voltage, but also reduces on-resistance by increasing the doping concentration of the drift region. At the same time, it can achieve smaller chip area, faster switching speed and higher power conversion efficiency.

[0003] like Figure 1 Figure 2 shows a top view of the trench-gate superjunction device layout, with the charge flow region 200 and the termination region 300. The charge flow region 200 comprises a superjunction structure composed of multiple alternating groups of N-type pillars 101 and P-type pillars 100, both of which are long, strip-like structures. During device operation, the N-type pillars 101 provide a conduction path when the device is on, while the P-type pillars 100 mutually deplete with the N-type pillars 101 during reverse bias, providing a high withstand voltage.

[0004] During the switching process of the super device, due to changes in the depletion layer, the gate-source capacitance Cgs and the gate-drain capacitance Cgd will change with the applied voltage, and the dv / dt (the rate of change of the drain voltage with time) will be affected by the gate-drain capacitance Cgd and the gate-source capacitance Cgs, resulting in large changes in electromagnetic interference (Electromagnetic Interference), which affects the switching characteristics of the device. Summary of the Invention

[0005] The present invention aims to address, at least to some extent, one of the problems in the related art. To this end, one of the objectives of the present invention is to provide a trench gate superjunction MOSFET device with reduced input capacitance. By changing the location of the source region and the connection between the source region and the trench gate, the input capacitance of the superjunction MOSFET device is reduced, thereby increasing the turn-on speed of the MOSFET device.

[0006] In order to achieve the above-mentioned purpose, the present application adopts the following technical solution: a trench gate superjunction device with reduced input capacitance, comprising a superjunction structure charge balance region, wherein the superjunction structure charge balance region includes alternatingly distributed first conductive type columns and second conductive type columns, wherein a trench gate is arranged on the top of the first conductive type column, and a body region is arranged on one side of the trench gate close to the second conductive type column, and a source region is arranged on the top of the body region; the source region is connected to the source metal through a source contact hole.

[0007] Furthermore, the bottom of the charge balance region of the super junction structure is sequentially connected to a first conductive type buffer layer and a first conductive type substrate, and the doping concentration of the first conductive type buffer layer is lower than the doping concentration of the first conductive type substrate.

[0008] Furthermore, the total thickness of the super junction structure charge balance region and the first conductive type buffer layer is less than 55 micrometers.

[0009] Furthermore, in the direction in which the first conductive type columns and the second conductive type columns are alternately distributed, the width of the first conductive type columns is greater than the width of the second conductive type columns; and the doping concentration of the first conductive type columns is less than the doping concentration of the second conductive type columns.

[0010] Furthermore, the trench gate includes a gate dielectric layer and a gate electrode, a filling groove is provided on the top of the first conductive type column, and the gate dielectric layer and the gate electrode are sequentially filled in the filling groove.

[0011] Furthermore, the bottom of the filling groove is lower than the bottom of the body region.

[0012] Furthermore, an isolation layer is provided on the top of the super junction structure charge balance region, the source metal is located on the top of the isolation layer, and the source contact hole passes through the isolation layer and extends into the super junction structure charge balance region.

[0013] Furthermore, the source contact hole is located in the first conductive type column, and the source contact hole is located on the side of the source region away from the trench gate, the doping concentration at the bottom of the source contact hole is greater than the doping concentration of the source region, and the source metal is connected to the source region through the source contact hole.

[0014] Furthermore, the source contact hole is also located in the second conductive type column, and the source contact hole is located at the center of the second conductive type column, and the doping concentration at the bottom of the source contact hole is greater than the doping concentration of the body region.

[0015] The present application also provides a method for preparing a trench gate superjunction device with reduced input capacitance, comprising:

[0016] forming a super junction structure charge balance region on a surface of a first conductive type substrate, wherein the super junction structure charge balance region includes first conductive type columns and second conductive type columns that are alternately distributed;

[0017] Forming a body region on one side of the trench gate in the first conductive type column by an ion implantation and push-well process;

[0018] Etching a filling trench on a top of the first conductive type column, and filling a trench gate in the filling trench;

[0019] Doping a heavily doped region of the first conductivity type in the body region by a polysilicon self-aligned process to form a source region; the source region is located in the body region of the first conductivity type column, and the source region is located on one side close to the second conductivity type column;

[0020] Etching a source contact hole on the top of the charge balance region and in the body region of the super junction structure;

[0021] Filling the source metal, wherein the source region is connected to the source metal through a source contact hole;

[0022] A drain is formed on the back side of the first conductive type substrate.

[0023] The above-mentioned technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: the trench gate superjunction device of the present application that reduces input capacitance includes a superjunction structure charge balance region, and the superjunction structure charge balance region includes alternatingly distributed first conductive type columns and second conductive type columns, wherein a trench gate is provided on the top of the first conductive type column, and a body region is provided on one side of the trench gate close to the second conductive type column, and a source region is provided on the top of the body region; the source region is connected to the source metal through a source contact hole; the present application only provides a body region on one side of the trench gate, and provides a source region on the top of the body region, so that the first conductive type column is reduced in size and the doping concentration is increased, which is more advantageous for the on-resistance of the device. At the same time, the present application adjusts the body and source injection areas to reduce the actual channel density, thereby ensuring that the on-resistance of the device does not increase by more than 5% (the on-resistance of the superjunction device is mainly composed of the source resistance, channel resistance, drift region resistance, and substrate resistance, of which the drift region resistance accounts for about 95%), the input capacitance is reduced by at least about 33%, and the gate-source capacitance is reduced by about half, which achieves a good balance between the on-resistance and input capacitance, thereby improving the switching speed of the superjunction device, reducing the switching loss of the superjunction device, and increasing the frequency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] In the attached figure:

[0027] Figure 1 This is a top view schematic diagram of the P-type column layout in the super junction MOSFET device layout of this application;

[0028] Figure 2 For the comparative example, the trench gate super junction MOSFET device is along Figure 1 Schematic diagram of the cross section of the charge flow region after cutting in the AA' direction;

[0029] Figure 3 A schematic cross-sectional view of the superjunction MOSFET device structure of this application;

[0030] Figure 4 2 is a comparison diagram of the Ci ss curves of the super junction MOSFET device in this embodiment and the comparative example;

[0031] Figure 5 Comparison of Coss curves of superjunction MOSFET devices in this embodiment and the comparative example

[0032] Figure 6 Comparison of Crss curves of superjunction MOSFET devices in this embodiment and the comparative example

[0033] Figure 7 3 is a comparison diagram of the Cgs curves of the super junction MOSFET devices in this embodiment and the comparative example.

[0034] Figure numbers: 1. First conductive type substrate; 2. First conductive type buffer layer; 3. Second conductive type column; 4. First conductive type column; 5. Body region; 6. Source region; 7. Second doped region; 8. Gate dielectric layer; 9. Gate; 10. Source contact hole; 11. Source metal; 12. Isolation layer; 13. Drain; 100. P-type column; 200. N-type column; 300. Terminal region. DETAILED DESCRIPTION

[0035] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific embodiments of the present invention are now described in detail with reference to the accompanying drawings. In the following description, it should be understood that the directions or positional relationships indicated by "front", "back", "up", "down", "left", "right", "longitudinal", "horizontal", "vertical", "horizontal", "top", "bottom", "inside", "outside", "head", "tail", etc. are based on the directions or positional relationships shown in the accompanying drawings and are constructed and operated in specific directions. They are only for the convenience of describing the technical solution and do not indicate that the mechanisms or components referred to must have specific directions. Therefore, they should not be understood as limiting the present invention.

[0036] It should also be noted that, unless otherwise clearly specified and limited, terms such as "installed", "connected", "connected", "fixed", and "set" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. When an element is referred to as being "on" or "under" another element, the element can be "directly" or "indirectly" located on the other element, or there may be one or more intervening elements. The terms "first", "second", "third", etc. are only for the convenience of describing the present technical solution, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third", etc. may explicitly or implicitly include one or more of such features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0037] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, mechanisms, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0038] Example 1

[0039] See also Figure 1 and Figure 3 The present application provides a trench gate superjunction device for reducing input capacitance, including a superjunction structure charge balance region, wherein the superjunction structure charge balance region includes alternatingly distributed first conductive type columns 4 and second conductive type columns 3, wherein a trench gate is arranged in a body region 5 at the top of the first conductive type column 4, and the trench gate is provided with a body region 5 on one side close to the second conductive type column 3, and an source region 6 is arranged on the top of the body region 5, and the source region 6 is connected to the source metal 11 through a source contact hole 10.

[0040] The on-resistance of a superjunction device is mainly composed of the source region 6 resistance, the channel resistance, the drift region resistance, and the substrate resistance, of which the drift region resistance accounts for about 95%, and the channel resistance accounts for a smaller proportion. This application reduces the actual channel density by adjusting the position of the body region 5 and the source region 6 injection area, which will lead to an increase in the channel resistance. Since the channel resistance accounts for a small proportion of the device on-resistance, this application can ensure that the increase in on-resistance is less than or equal to 5% compared to the control ratio.

[0041] However, due to the reduction in actual channel density in the present application, compared with the device structure in the comparative example, the input capacitance of the superjunction device of the present application is reduced by at least 33%, and the gate-source capacitance is reduced by half, which plays a good balance between the on-resistance and the input capacitance, thereby improving the switching speed of the superjunction device, reducing the switching loss of the superjunction device, and increasing the frequency of the device.

[0042] At the same time, the present application only sets the body region 5 and the source region 6 on one side of the trench gate, so that the size of the first conductive type column 4 is reduced and the doping concentration is increased, which is more advantageous for the device on-resistance.

[0043] The present invention eliminates the presence of a body region on the other side of the trench gate. This means that the present invention optimizes capacitance performance parameters by reducing contact between the gate and the body region. This means that the present invention addresses the issue of reducing the input capacitance of trench gate devices. Furthermore, the present invention balances on-resistance and capacitance by altering the implantation region of the body and source regions, as well as the connection between the body and source regions and the trench gate.

[0044] Example 2

[0045] See also Figure 1 and Figure 3 The present application provides a trench gate superjunction device for reducing input capacitance, including a superjunction structure charge balance region, wherein the superjunction structure charge balance region includes alternatingly distributed first conductive type columns 4 and second conductive type columns 3, wherein a trench gate is arranged in a body region 5 at the top of the first conductive type column 4, and the trench gate is provided with a body region 5 on one side close to the second conductive type column 3, and an source region 6 is arranged on the top of the body region 5, and the source region 6 is connected to the source metal 11 through a source contact hole 10.

[0046] Specifically, the bottom of the charge balance region of the super junction structure is sequentially connected to a first conductive type buffer layer 2 and a first conductive type substrate 1 , and the doping concentration of the first conductive type buffer layer 2 is lower than the doping concentration of the first conductive type substrate 1 .

[0047] In the present application, a first conductive type buffer layer 2 is epitaxially grown on the surface of a first conductive type substrate 1, and then epitaxially grown on the surface of the first conductive type buffer layer 2. When the trench gate super junction device is an N-type device, the first conductive type is N-type and the second conductive type is P-type. Or when the trench gate super junction device is a P-type device, the first conductive type is P-type and the second conductive type is N-type. Therefore, the substrate in the present application can be P-type or N-type. In a specific embodiment of the present invention, the substrate is composed of first conductive type As or P doping, and the resistivity is between 0.001ohm·cm and 0.003ohm·cm.

[0048] The total thickness of the super junction structure charge balance region and the first conductive type buffer layer 2 is less than 55 micrometers, and the minimum value of the total thickness is determined by the trench depth and the etching machine capability.

[0049] The superjunction structure charge balance region includes alternating first conductivity type columns 4 and second conductivity type columns 3. The alternating first conductivity type columns 4 and second conductivity type columns 3 constitute the superjunction structure charge balance region. In this application, the superjunction structure charge balance region includes a plurality of cellular structures arranged in parallel, each cellular structure consisting of a first conductivity type column 4 and a second conductivity type column 3, and the first conductivity type column 4 and the second conductivity type column 3 are charge balanced. Multiple cellular structures are arranged in sequence to form a complete superjunction structure charge balance region.

[0050] In the present application, the body region 5 is formed on one side of the trench gate at the top of the first conductive type column 4, and the upper surface of the body region 5 is flush with the upper surface of the first conductive type column 4. Specifically, the second conductive type body region 5 can be formed locally on the surface of the first conductive type column 4 through a mask and an ion implantation and push-well process. Since the body region is formed before the trench gate, but before the body region is formed, the overall structure of the trench gate device of the present application is known, that is, the position of the trench gate is known. At this time, we can ensure that the body region is formed only on one side of the trench gate during the implantation process by designing the position and size of the through hole in the mask. Figure 3 As shown, there is no body region in the second conductive type pillar between the two trench gates and in parts of the two first conductive type pillars.

[0051] In this application, a trench gate is only provided in the first conductive type column 4. The trench gate includes a gate dielectric layer 8 and a gate electrode 9. A filling groove is provided on the top of the first conductive type column 4. The gate dielectric layer 8 and the gate electrode 9 are sequentially filled in the groove. That is, the gate dielectric layer 8 is in contact with the body region 5, and the gate electrode 9 is located inside the gate dielectric layer 8. In this application, the trench gate can extend through the body region 5 to the first conductive type column 4 below the body region 5, that is, the depth of the trench gate in the first conductive type column 4 is greater than the junction depth after the body region 5 is injected into the push-well. In this application, the gate electrodes 9 in all cells can be connected to each other.

[0052] In the present application, the dielectric layer of the gate 9 is composed of an oxide layer, and the thickness of the oxide layer can be adjusted as required.

[0053] In this application, the source region 6 is only provided on one side of the trench gate. Here, one side refers to one side of the trench gate close to or away from the second conductive type column 3 in the same cell structure. In order to simplify the process, Figure 3As shown, the cells in the charge balance region of the super junction structure can be divided into two halves. The cells on the left side have the trench gates arranged on the side away from the second conductive type column 3, that is, arranged on the left side inside the first conductive type column 4. The cells on the right side have the trench gates arranged on the side close to the second conductive type column 3, that is, arranged on the right side inside the first conductive type column 4. In this way, in the cells located on the left side of the center of the charge balance region of the super junction structure in this application, the source region 6 is arranged on the left side of the trench gates, and in the cells located on the right side of the center of the charge balance region of the super junction structure, the source region 6 is arranged on the right side of the trench gates. This can simplify the process steps for forming the source region 6.

[0054] In other embodiments, it is sufficient to ensure that the trench gate is only provided within the first conductive type column 4 in each cell, and the source region 6 is only provided on one side of the trench gate, without limiting the specific location of the source region 6. Meanwhile, in this application, no source region 6 is provided within the second conductive type column 3.

[0055] In the present application, the source region 6 is only provided on one side of the first conductive type pillar 4 , and no channel formed by the body region 5 and the source region 6 is included between two adjacent trench gate structures.

[0056] An isolation layer 12 is provided on top of the superjunction structure charge balance region. The source metal 11 is located on top of the isolation layer 12. A source contact hole 10 penetrates the isolation layer 12 and extends into the superjunction structure charge balance region. The source contact hole 10 is etched to a depth greater than 3000 Å on the upper surface of the epitaxial layer of the first conductivity type column 4 and the second conductivity type column 3. In the present application, the source contact hole 10 can be located only within the first conductivity type column 4 or within both the first conductivity type column 4 and the second conductivity type column 3.

[0057] When the source contact hole 10 is located in the first conductivity type column 4, the source contact hole 10 is located on the side of the source region 6 away from the trench gate. The doping concentration at the bottom of the source contact hole 10 is greater than the doping concentration of the source region 6. The source metal 11 is connected to the source region 6 through the source contact hole 10. The source contact hole 10 located in the first conductivity type column 4 is located at the edge of the first conductivity type column 4, that is, at the intersection of the second conductivity type column 3 and the first conductivity type column 4. The source region 6 is between the source contact hole 10 and the trench gate. Only one source contact hole 10 is set in each first conductivity type column 4. The junction depth of the source region 6 after the injection of the push-in well is less than the depth of the source contact hole 10 etched in the first conductivity type column 4.

[0058] When the source contact hole 10 is also located within the second conductivity type column 3, the source contact hole 10 is located at the center of the second conductivity type column 3, and the doping concentration at the bottom of the source contact hole 10 is greater than the doping concentration of the body region 5. Each second conductivity type column 3 is provided with only one source contact hole 10 at the center, and the size of the source contact hole 10 located within the second conductivity type column 3 can be greater than or equal to the size of the source contact hole 10 within the first conductivity type column 4. The source contact hole 10 on the second conductivity type column 3 can optimize the device electric field strength and optimize current dispersion during device operation to prevent current concentration.

[0059] Since the first conductive type column 4 in this application needs to be provided with a trench gate, a source region 6, and a source contact hole 10, while the second conductive type column 3 only needs to be provided with a source contact hole 10, the width of the first conductive type column 4 is greater than the width of the second conductive type column 3 in the direction in which the first conductive type column 4 and the second conductive type column 3 are alternately distributed; and the doping concentration of the first conductive type column 4 is less than the doping concentration of the second conductive type column 3. The first conductive type column 4 and the second conductive type column 3 in the cell have different widths, and while maintaining charge balance between the first conductive type column 4 and the second conductive type column 3, the sizes of the first conductive type column 4 and the second conductive type column 3 can be further reduced. Due to the reduction in channel density, the cell stepping of this application is twice that of the cell stepping of a conventional trench gate super junction MOSFET device, which can reduce the size of the cell and thus reduce the volume of the super junction device.

[0060] The superjunction device of the present application further includes a drain 13 , which is located on the bottom surface of the first conductive type substrate 1 and is composed of a first conductive type heavily doped region on the back surface of the first conductive type epitaxial layer.

[0061] like Figure 1 Figure 2 shows a top-down schematic diagram of the P-type pillar layout in a trench-gate superjunction MOSFET device according to an embodiment of the present invention. The central region of the layout is a charge flow region 200, with terminal regions 300-300 surrounding the charge flow region. The charge flow region 200 comprises a superjunction MOSFET structure consisting of multiple alternating P and N pillars. Each P and N pillar form a superjunction structure. Within the charge flow region 200, the superjunction device comprises multiple cellular structures. The P and N pillars are the first conductivity type pillars 4 and second conductivity type pillars 3 described above.

[0062] The present application also provides a method for preparing a trench gate superjunction device with reduced input capacitance, comprising:

[0063] S1: forming a super junction structure charge balance region on the surface of a first conductive type substrate 1 , wherein the super junction structure charge balance region includes first conductive type columns 4 and second conductive type columns 3 that are alternately distributed.

[0064] Specifically include:

[0065] forming a first conductivity type heavily doped silicon substrate, and forming a first conductivity type buffer layer 2 on the first conductivity type heavily doped silicon substrate;

[0066] A first conductivity type epitaxial layer is formed, and an etching region for the second conductivity type pillar 3 is defined on the first conductivity type silicon epitaxial layer using a photolithography process. The second conductivity type pillar 3 region on the first conductivity type silicon epitaxial layer is etched. A dry etching process can be used, and the etched region in the epitaxial layer has a trapezoidal shape, with a larger top and smaller bottom. After the etching process, a sacrificial oxidation process is used to treat the surface of the etched region.

[0067] After deep trench etching in the second conductive type column 3 region, the second conductive type source seed is doped on the bottom of the second conductive type column 3 region to form the second conductive type column 3;

[0068] After deep trench etching and implantation in the second conductivity type column 3 region, a silicon dielectric containing second conductivity type doping is filled to form a super junction structure charge balance region composed of the first conductivity type column 4 and the second conductivity type column 3 .

[0069] After filling the second conductive type doped silicon dielectric and removing the hard mask on the surface of the epitaxial layer, a chemical mechanical polishing process is required to planarize the epitaxial layer.

[0070] S2: forming a body region 5 locally on the surface of the first conductive type column 4 by using a mask and an ion implantation and push-well process; the body region 5 is a body region 5 of the second conductive type.

[0071] Since the body region is formed before the trench gate, the overall structure of the trench gate device of the present application is known before the body region is formed, that is, the position of the trench gate is known. At this time, we can design the position and size of the through hole in the mask to ensure that the body region is formed only on one side of the trench gate during the implantation process. Figure 3 As shown, there is no body region in the second conductive type pillar between the two trench gates and in parts of the two first conductive type pillars.

[0072] S3: etching to form a filling trench on the top of the first conductive type column 4, and filling the filling trench with a trench gate.

[0073] Specifically, a filling groove is formed at the top of the first conductivity type pillar 4 in the charge balance region of the superjunction structure through a photolithography process. A gate dielectric layer 8 is formed on the sidewalls and bottom of the filling groove. A gate electrode 9, which is a first conductivity type dielectric layer, is then filled in the filling groove. The gate dielectric layer 8 is formed by a thermal oxidation process, and the thickness of the oxide layer can be adjusted as needed.

[0074] S4: Doping a heavily doped region of the first conductivity type in the body region 5 using a polysilicon self-aligned process to form a source region 6; the source region 6 is located in the body region 5 of the first conductivity type column 4, and the source region 6 is located on one side close to the second conductivity type column 3. The heavily doped region of the first conductivity type is doped in the body region 5 of the second conductivity type using a polysilicon self-aligned process to form the source region 6, which is used to form a channel.

[0075] S5: etching to form a source contact hole 10 at the top of the charge balance region of the super junction structure and in the body region 5 .

[0076] First, an isolation layer 12 is deposited on top of the charge balance region of the super junction structure;

[0077] The source contact hole 10 is located in both the first conductivity type column 4 and the second conductivity type column 3 , and is located at the edge of the first conductivity type column 4 and at the center of the second conductivity type column 3 .

[0078] After forming the source contact hole 10, an ion implantation and push-well process is used to form a second doped region 7 at the bottom of the source contact hole 10. The doping type of the second doped region 7 is the same as that of the body region 5, and the doping concentration of the second doped region 7 is greater than that of the body region 5. The second doped region 7 can further improve the reliability of the device. When a single pulse is applied to the device gate, the second doped region 7 ensures that the device can withstand the maximum avalanche energy.

[0079] S6: Filling the source metal 11, the source region 6 is connected to the source metal 11 through the source contact hole 10;

[0080] S7: Thinning the back side of the heavily doped silicon substrate of the first conductivity type to form a drain 13.

[0081] Compared with the prior art, the size and concentration of the first conductive type pillars 4 and the second conductive type pillars 3 of the trench gate device of the present application can be further reduced by half, and the concentration can be further increased, thereby further optimizing the on-resistance of the device.

[0082] The source contact hole 10 on the second conductive type column 3 of the present invention can optimize the electric field strength of the device and optimize the current dispersion when the device is working so as to avoid current concentration.

[0083] The trench gate device of the present invention reduces the actual channel density by adjusting the injection area of ​​the body region 5 and the source region 6 without the need for additional masks, thereby ensuring that the on-resistance of the device does not increase by more than 5% (the on-resistance of the super junction device is mainly composed of the source region 6 resistance, the channel resistance, the drift region resistance, and the substrate resistance, of which the drift region resistance accounts for about 95%), the input capacitance is reduced by at least about 33%, and the gate-source capacitance is reduced by about half, which achieves a good balance between the on-resistance and the input capacitance, thereby improving the switching speed of the super junction device, reducing the switching loss of the super junction device, and increasing the frequency of the device.

[0084] Comparative Example

[0085] The difference between the comparative example and embodiment 1 is: Figure 2 As shown, body regions 5 and source regions 6 are provided on both sides of the trench gate, and two source contact holes 10 are provided in each cell structure, and the two source contact holes 10 are respectively located on the side of the source region 6 away from the trench gate, that is, the two source contact holes 10 are both located at the intersection of the first conductivity type column 4 and the second conductivity type column 3 in the cell. Figure 2 As shown, the body region is entirely located on the upper surfaces of the first conductive type column 4 and the second conductive type column 3 .

[0086] The difference between Example 2 of the present application and the comparative example is that in Example 1, no channel is formed between the two trench gates, wherein there is no active area 6 structure on the upper surface of the second conductive type column 3 and there is only one source contact hole 10, and there is no body region 5 between the side close to the trench gate and the top side of the second conductive type column 3, and the trench gate does not contact the body region 5.

[0087] like Figure 4-Figure 7 This is a comparison of the Ciss / Coss / Crss / Cgs curves of the trench gate super junction MOSFET device in the comparative example and the super junction MOSFET device in Example 2. Crss is the gate-drain capacitance Cgd, the input capacitance Ciss = Cgd (gate-drain capacitance) + Cgs (gate-source capacitance), and the output capacitance Coss = Cgd (gate-drain capacitance) + Cds (source-drain capacitance). Figure 4-Figure 7 The horizontal axis represents the voltage applied to the source and drain of the MOSFET device.

[0088] Assuming that the concentrations and sizes of the first conductive type columns and the second conductive type columns in Example 1 correspond one to one, the doping concentration of the body region and the doping concentration of the source region are consistent, where 500, 600, 700, and 800 are respectively the Ciss / Coss / Crss / Cgs curves of the trench gate structure in the comparative example, and 501, 601, 701, and 801 are respectively the Ciss / Coss / Crss / Cgs curves of the trench gate structure in Example 2. It can be seen that the capacitance value of Ciss of curve 501 is less than the capacitance value of Ciss of the trench gate structure curve 500 in the comparative example as the voltage increases, and the reduction percentage is 33.

[0089] The capacitance value of Coss of curve 601 as the voltage increases is comparable to the capacitance value of Coss of the trench gate structure curve 600 in the comparative example.

[0090] The capacitance value of Crss of curve 701 decreases first and then tends to be consistent with the capacitance value of Crss of the trench gate structure curve 700 in the comparative example as the voltage increases.

[0091] The capacitance value of Cgs of curve 801 is much smaller than the capacitance value of Cgs of the trench gate structure curve 800 in the comparative example as the voltage increases, and decreases by about half.

[0092] As can be seen from the above, the structure in Example 1 of the present invention can reduce the capacitance value of the input capacitor Ciss, thereby adjusting the switching speed of the device, reducing the switching loss of the device, and increasing the frequency of the device.

[0093] This application reduces the actual channel density by adjusting the positions of the body and source injection regions, which results in an increase in channel resistance. However, since channel resistance accounts for a small proportion of the device's on-resistance, this application ensures that the increase in on-resistance is less than or equal to 5% compared to the control ratio.

[0094] However, due to the reduction in actual channel density in the present application, compared with the device structure in the comparative example, the input capacitance of the superjunction device of the present application is reduced by at least 33%, and the gate-source capacitance is reduced by half, which plays a good balance between the on-resistance and the input capacitance, thereby improving the switching speed of the superjunction device, reducing the switching loss of the superjunction device, and increasing the frequency of the device.

[0095] It is understandable that the above embodiments only express the preferred implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the patent scope of the present invention. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can be made, all of which fall within the scope of protection of the present invention. Therefore, all equivalent changes and modifications made to the scope of the claims of the present invention should fall within the scope of coverage of the claims of the present invention.

Claims

1. A method for preparing a trench gate super junction device with reduced input capacitance, characterized in that: include: forming a super junction structure charge balance region on a surface of a first conductive type substrate, wherein the super junction structure charge balance region includes first conductive type columns and second conductive type columns that are alternately distributed; Forming a body region on one side of the trench gate in the first conductive type column by an ion implantation and push-well process; Etching a filling trench on a top of the first conductive type column, and filling a trench gate in the filling trench; doping a heavily doped region of the first conductivity type in the body region by a polysilicon self-aligned process to form a source region; the source region is located in the body region of the first conductivity type column, and the source region is located on one side close to the second conductivity type column; doping the heavily doped region of the first conductivity type in the body region of the second conductivity type by a polysilicon self-aligned process to form a source region for forming a channel; Etching a source contact hole on the top of the charge balance region and in the body region of the super junction structure; The source contact hole is located in both the first conductivity type column and the second conductivity type column; the source contact hole is located at the edge of the first conductivity type column and at the center of the second conductivity type column; an ion implantation and push-well process is used to form a second doped region at the bottom of the source contact hole, the doping type of the second doped region being the same as the doping type of the body region, and the doping concentration of the second doped region being greater than the doping concentration of the body region; Filling the source metal, wherein the source region is connected to the source metal through a source contact hole; A drain is formed on the back side of the first conductive type substrate.

2. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 1, wherein: The bottom of the super junction structure charge balance region is sequentially connected to a first conductive type buffer layer and a first conductive type substrate, and the doping concentration of the first conductive type buffer layer is lower than the doping concentration of the first conductive type substrate.

3. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 2, wherein: The total thickness of the super junction structure charge balance region and the first conductive type buffer layer is less than 55 micrometers.

4. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 1, wherein: In the direction in which the first conductive type columns and the second conductive type columns are alternately distributed, the width of the first conductive type columns is greater than the width of the second conductive type columns; and the doping concentration of the first conductive type columns is less than the doping concentration of the second conductive type columns.

5. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 1, wherein: The trench gate includes a gate dielectric layer and a gate electrode. A filling groove is provided on the top of the first conductive type column, and the gate dielectric layer and the gate electrode are sequentially filled in the filling groove.

6. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 5, wherein: The bottom of the filling groove is lower than the bottom of the body region.

7. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 1, wherein: An isolation layer is provided on the top of the super junction structure charge balance region, the source metal is located on the top of the isolation layer, and the source contact hole penetrates the isolation layer and extends into the super junction structure charge balance region.

8. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 7, wherein: When the source contact hole is located in the first conductive type column, the doping concentration at the bottom of the source contact hole is greater than the doping concentration of the source region, and the source metal is connected to the source region through the source contact hole.

9. The method for preparing a trench gate super junction device with reduced input capacitance according to claim 8, wherein: When the source contact hole is located in the second conductive type column, the doping concentration at the bottom of the source contact hole is greater than the doping concentration of the body region.

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