A vertical thin film transistor and a method of manufacturing the same

Abstract

The present application belongs to the technical field of semiconductor display devices, and particularly relates to a vertical thin film transistor and a preparation method thereof. In the present application, when a spacer layer thin film is patterned, after a first wet etching thin film is obtained, a first dry etching thin film is first formed; then, the first wet etching thin film is subjected to second wet etching, so that the protruding part of the first wet etching thin film relative to the first dry etching thin film is etched to be recessed, a second electrode is formed, and the contact surface of the first dry etching thin film and the second electrode is exposed, thereby solving the problem of the second electrode being suspended; the first dry etching thin film is subjected to second dry etching, so that the exposed part of the first dry etching thin film is etched. After the above etching process, the vertical channel sidewall morphology can be controlled to be a positive taper angle, thereby solving the risk of disconnection after deposition of subsequent active layer thin film, gate insulating layer thin film, gate thin film and the like, and guaranteeing the performance of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor display devices, and particularly relates to a vertical thin film transistor and a preparation method thereof. BACKGROUND

[0002] As a core component of a display screen, a thin film transistor (TFT) plays an important role. In order to reduce the size of a TFT device to improve the resolution, the most direct way for a traditional planar TFT device is to continuously reduce the size of a channel between a source electrode and a drain electrode. However, due to the limitation of display lithography tools, the size of the channel is difficult to further reduce continuously.

[0003] As one of the directions of development of a new generation of display devices, a vertical channel thin film transistor (V-TFT) can meet the needs of miniaturization and low power consumption of new display devices. By adjusting the thickness of a spacer film, the length of the channel size of the V-TFT device can be easily controlled, and the effect of greatly reducing the key size of the device can be achieved.

[0004] At present, in the process of etching a spacer to form a vertical sidewall in a V-TFT device, a typical method is to use the source / drain electrode as a hard mask after patterning the source / drain electrode, and then form a vertical sidewall through a dry etching process.

[0005] However, when the vertical sidewall channel is formed by the dry etching method, the following effects on the device will occur: the dry etching has the characteristics of a large etching aspect ratio, and during the dry etching of the spacer layer material, the drain / source electrode is used as a dry etching hard mask, and the spacer layer material will have a reverse taper angle, that is, the angle between the sidewall of the spacer layer and the bottom surface is greater than 90°; at the same time, after the dry etching process, the upper surface of the spacer layer in contact with the drain / source electrode has a loss of line width inward, and the drain / source electrode forms a suspended protruding structure; the above two cases will together cause the risk of disconnection after the deposition of the active layer material, the gate insulating layer material, the metal electrode and other thin films, resulting in no performance or performance degradation of the device; at the same time, the sidewall surface roughness of the spacer layer formed by dry etching the spacer layer material is large, and there are many interface macroscopic and microscopic defects, which affect the switching characteristics and stability of the device. SUMMARY

[0006] The present application aims to provide a vertical thin film transistor and a preparation method thereof, and the preparation method can improve the vertical sidewall morphology (reduce roughness) and taper angle (taper angle changes from negative angle to positive angle) of the V-TFT, and obtain a vertical thin film transistor device with good performance (on-off ratio, subthreshold swing, threshold voltage and mobility) and high reliability.

[0007] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0008] The present application provides a preparation method of a vertical thin film transistor, comprising the following steps:

[0009] A first electrode film is prepared on a substrate, and the first electrode film is patterned to obtain a first electrode, wherein the orthographic projection width of the first electrode on the substrate is less than the width of the substrate;

[0010] An isolation layer film and a second electrode film covering the substrate and the first electrode are sequentially prepared, and the second electrode film is subjected to photoetching and then first wet etching to obtain a first wet etching film; the first wet etching film is used as a hard mask to perform first dry etching on the isolation layer film to obtain a first dry etching film; second wet etching is performed on the first wet etching film to obtain a second electrode, wherein the orthographic projection width of the second electrode on the substrate is less than the orthographic projection width of the first electrode on the substrate; second dry etching is performed on the first dry etching film to obtain a second dry etching film; third wet etching or third dry etching is performed on the second dry etching film to obtain an isolation layer, wherein the orthographic projection width of the isolation layer on the substrate is less than the orthographic projection width of the first electrode on the substrate; the vertical sidewall of the isolation layer and the vertical sidewall of the second electrode are formed;

[0011] An active layer is prepared, wherein the active layer comprises a first part, a second part and a third part connected in sequence, the first part of the active layer is located on the first electrode, the third part of the active layer is located on the second electrode, and the second part of the active layer covers the vertical sidewall of the isolation layer and the second electrode;

[0012] A gate insulating layer is prepared, wherein the gate insulating layer comprises a first part, a second part, a third part and a fourth part connected in sequence, the first part of the gate insulating layer is located on the first electrode, the second part of the gate insulating layer covers the first part of the active layer, the third part of the gate insulating layer covers the second part of the active layer, the fourth part of the gate insulating layer covers the third part of the active layer and the second electrode, and the gate insulating layer is provided with a through hole on the second electrode;

[0013] A gate electrode is prepared, which includes a first part and a second part connected together, the first part of the gate electrode is located on the second part of the gate insulation layer, and the second part of the gate electrode covers the third part of the gate insulation layer.

[0014] Preferably, the material of the isolation layer is silicon oxide and / or silicon nitride, or Al2O3 and / or HfO2; the thickness of the isolation layer is 50nm-2000nm.

[0015] Preferably, the material of the first electrode, the second electrode and the gate electrode is independently one or more of aluminum, molybdenum, silver, copper, titanium, gold and indium tin oxide; the thickness of the first electrode, the second electrode and the gate electrode is independently 20nm-1000nm.

[0016] Preferably, the temperature of the first wet etching and the second wet etching is independently room temperature-60℃, and the etching time is independently 10-300s; the temperature of the third wet etching is room temperature-60℃, and the etching time is 1-120s.

[0017] Preferably, the etching gas used in the first dry etching, the second dry etching and the third dry etching is independently SF6, CF4, O2, He or chloride gas, the etching power is independently 100-2000W, the working gas pressure is independently 0.1-20Pa, and the etching time is independently 1-1000s.

[0018] Preferably, the isolation layer film is prepared by plasma enhanced chemical vapor deposition or atomic layer deposition; the conditions of the plasma enhanced chemical vapor deposition include: the deposition power is 0.1-2.0kW, the working gas pressure is 0.5-5Pa, and the deposition temperature is 80-350℃.

[0019] Preferably, the first electrode film and the second electrode film are prepared by magnetron sputtering, and the conditions of the magnetron sputtering include: the deposition power is 0.1-1.0kW, the working gas pressure is 10 -6 ~10 -4 Pa, and the deposition temperature is room temperature-350℃.

[0020] Preferably, the thickness of the active layer is 10nm-200nm; after the active layer is obtained, before the gate insulation layer is prepared, the active layer is further subjected to annealing treatment, and the temperature of the annealing treatment is 150℃-500℃.

[0021] Preferably, the preparation method of the active layer includes: preparing an active layer film covering the vertical side wall of the substrate, the first electrode, the isolation layer and the second electrode, and the active layer is obtained by etching after the active layer film is subjected to patterning treatment.

[0022] The active layer film is prepared by magnetron sputtering or atomic layer deposition; the conditions of the magnetron sputtering include that the deposition power is 0.1-2.0 kW, the working air pressure is 10 -6 ~10 -4 Pa, and the deposition temperature is room temperature-350 DEG C.

[0023] The application provides a vertical thin film transistor prepared by the preparation method.

[0024] The application provides a preparation method of a vertical thin film transistor, comprising the following steps: preparing a first electrode thin film on a substrate, and performing a patterning treatment on the first electrode thin film to obtain a first electrode, one end edge of the first electrode is aligned with one end edge of the substrate, and the orthogonal projection width of the first electrode on the substrate is smaller than the width of the substrate; sequentially preparing an isolation layer thin film and a second electrode thin film covering the substrate and the first electrode, performing photoetching on the second electrode thin film, and then using a first wet etching method to obtain a first wet etching thin film; using the first wet etching thin film as a hard mask to perform a patterning treatment on the isolation layer thin film, and then using a first dry etching method to obtain a first dry etching thin film; performing a second wet etching on the first wet etching thin film to obtain a second electrode, the orthogonal projection width of the second electrode on the substrate is smaller than the orthogonal projection width of the first electrode on the substrate; performing a second dry etching on the first dry etching thin film to obtain a second dry etching thin film; performing a third wet etching or a third dry etching on the second dry etching thin film to obtain an isolation layer, the orthogonal projection width of the isolation layer on the substrate is smaller than the orthogonal projection width of the first electrode on the substrate; the side wall of the isolation layer and the side wall of the second electrode form a vertical side wall; preparing an active layer, the active layer comprises a first part, a second part and a third part connected in sequence, the first part of the active layer is located on the first electrode, the third part of the active layer is located on the second electrode, and the second part of the active layer covers the vertical side walls of the isolation layer and the second electrode; preparing a gate insulating layer, the gate insulating layer comprises a first part, a second part, a third part and a fourth part connected in sequence, the first part of the gate insulating layer is located on the first electrode, the second part of the gate insulating layer covers the first part of the active layer, the third part of the gate insulating layer covers the second part of the active layer, the fourth part of the gate insulating layer covers the third part of the active layer and the second electrode, and the gate insulating layer is provided with a through hole on the second electrode; and preparing a gate, the gate comprises a first part and a second part connected in sequence, the first part of the gate is located on the second part of the gate insulating layer, and the second part of the gate covers the third part of the gate insulating layer. The preparation method provided by the application optimizes the vertical channel side wall morphology of a V-TFT device.Specifically, in the spacer layer film patterning process, the second electrode film is first subjected to first wet etching to obtain a first wet etching film, and then the spacer layer film is subjected to first dry etching to form a first dry etching film; subsequently, the first wet etching film is subjected to second wet etching, the second wet etching etches the sidewall of the first wet etching film, so that the part of the first wet etching film protruding relative to the first dry etching film is etched to be inwardly recessed, forming a second electrode, and the contact surface of the first dry etching film and the second electrode is exposed, solving the problem of the second electrode being suspended; the first dry etching film is subjected to second dry etching, so that the exposed part of the first dry etching film is etched; after the above etching process, the vertical channel sidewall morphology can be controlled to be a positive taper angle, solving the risk of disconnection after deposition of the subsequent active layer film, gate insulating layer film, gate film and the like, and guaranteeing the performance of the device; the second dry etching film is subjected to third wet etching or third dry etching to perform surface treatment on the sidewall of the second dry etching film, reducing the macroscopic and microscopic defects of the interface, and improving the switching characteristics and stability of the vertical thin film transistor. In summary, the structure of the vertical thin film transistor is reasonably arranged, and the etching method of the spacer layer and the second electrode layer in forming the vertical sidewall is strictly controlled, so that the V-TFT vertical sidewall morphology and taper angle can be effectively improved, thereby obtaining a vertical thin film transistor device with good performance (switching ratio, sub-threshold swing, threshold voltage and mobility) and high reliability. According to the results of the examples, the switching ratio of the vertical thin film transistor prepared by the present application is ≥10. 8 , the sub-threshold swing is 0.12V / dec, the threshold voltage is-0.34V, and the mobility is 14.32cm 2 ·V -1 s -1 .

[0025] Further, in the present application, the etching time of the second dry etching is 1-1000s. By adjusting the time of the second dry etching, the exposed part of the first dry etching film is etched, and the vertical channel sidewall morphology can be controlled to be a positive taper angle, solving the risk of disconnection after deposition of the subsequent active layer film, gate insulating layer film, gate film and the like, and guaranteeing the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 The preparation flow chart of the vertical thin film transistor provided by the present application is shown in the figure;

[0027] Figure 2 The structure schematic diagram of the first electrode film prepared in Example 1 of the present application is shown in the figure;

[0028] Figure 3Structure diagram of the first electrode prepared in Example 1 of the present application;

[0029] Figure 4 Structure diagram of the insulating layer film and the second electrode film prepared in Example 1 of the present application;

[0030] Figure 5 Structure diagram of the first wet etching film prepared in Example 1 of the present application;

[0031] Figure 6 Structure diagram of the first dry etching film prepared in Example 1 of the present application;

[0032] Figure 7 Structure diagram of the second electrode prepared in Example 1 of the present application;

[0033] Figure 8 Structure diagram of the second dry etching film prepared in Example 1 of the present application;

[0034] Figure 9 Structure diagram of the insulating layer prepared in Example 1 of the present application;

[0035] Figure 10 Structure diagram of the active layer film prepared in Example 1 of the present application;

[0036] Figure 11 Structure diagram of the active layer prepared in Example 1 of the present application;

[0037] Figure 12 Structure diagram of the gate insulating layer film prepared in Example 1 of the present application;

[0038] Figure 13 Structure diagram of the gate insulating layer prepared in Example 1 of the present application;

[0039] Figure 14 Structure diagram of the gate film prepared in Example 1 of the present application;

[0040] Figure 15 Structure diagram of the vertical thin film transistor prepared in Example 1 of the present application;

[0041] Figure 16 Transfer characteristic curve diagram of the vertical thin film transistor prepared in Example 1 of the present application;

[0042] Figure 17 Structure diagram of the active layer film prepared in Comparative Example 1 of the present application;

[0043] Figure 18 Structure diagram of the active layer prepared in Comparative Example 1 of the present application;

[0044] Wherein: 100 is a substrate, 200 is a first electrode thin film, 201 is a first electrode, 300 is an isolation layer thin film, 400 is a second electrode thin film, 401 is a first wet etching thin film, 301 is a first dry etching thin film, 402 is a second electrode, 302 is a second dry etching thin film, 303 is an isolation layer, 500 is an active layer thin film, 501 is an active layer, 600 is a gate insulating layer thin film, 601 is a gate insulating layer, 602 is a gate insulating layer through hole, 700 is a gate thin film, and 701 is a gate. DETAILED DESCRIPTION

[0045] The application provides a preparation method of a vertical thin film transistor, comprising the following steps:

[0046] A first electrode thin film is prepared on a substrate, and the first electrode thin film is patterned to obtain a first electrode, wherein the orthographic projection width of the first electrode on the substrate is less than the width of the substrate;

[0047] An isolation layer thin film and a second electrode thin film covering the substrate and the first electrode are sequentially prepared, the second electrode thin film is subjected to photoetching, and then a first wet etching method is used to obtain a first wet etching thin film; the isolation layer thin film is subjected to patterning treatment using the first wet etching thin film as a hard mask, and then a first dry etching method is used to obtain a first dry etching thin film; the first wet etching thin film is subjected to a second wet etching, to obtain a second electrode, wherein the orthographic projection width of the second electrode on the substrate is less than the orthographic projection width of the first electrode on the substrate; the first dry etching thin film is subjected to a second dry etching, to obtain a second dry etching thin film; the second dry etching thin film is subjected to a third wet etching or a third dry etching, to obtain an isolation layer, wherein the orthographic projection width of the isolation layer on the substrate is less than the orthographic projection width of the first electrode on the substrate; the side wall of the isolation layer and the side wall of the second electrode form vertical side walls;

[0048] An active layer is prepared, wherein the active layer comprises a first part, a second part and a third part connected in sequence, the first part of the active layer is located on the first electrode, the third part of the active layer is located on the second electrode, and the second part of the active layer covers the vertical side walls of the isolation layer and the second electrode;

[0049] A gate insulating layer is prepared, wherein the gate insulating layer comprises a first part, a second part, a third part and a fourth part connected in sequence, the first part of the gate insulating layer is located on the first electrode, the second part of the gate insulating layer covers the first part of the active layer, the third part of the gate insulating layer covers the second part of the active layer, the fourth part of the gate insulating layer covers the third part of the active layer and the second electrode, and the gate insulating layer is provided with a through hole on the second electrode;

[0050] A gate is prepared, the gate including a first portion and a second portion connected, the first portion of the gate being on the second portion of the gate insulating layer, and the second portion of the gate covering the third portion of the gate insulating layer.

[0051] In the present application, all the raw materials / components are commercially available products well known to those skilled in the art, unless otherwise specified.

[0052] The present application prepares a first electrode thin film on a substrate, and performs a patterning process on the first electrode thin film to obtain a first electrode, one end edge of the first electrode aligning with one end edge of the substrate, and the first electrode having a width of a normal projection on the substrate less than the width of the substrate. In the present application, the substrate is preferably glass. The material of the first electrode is preferably one or more of aluminum, molybdenum, silver, copper, titanium, gold and indium tin oxide. The thickness of the first electrode is preferably 20 nm to 1000 nm. The first electrode thin film is preferably prepared by magnetron sputtering, and the conditions of the magnetron sputtering are preferably as follows: the deposition power is preferably 0.1 to 1.0 kW, the working pressure is preferably 10 -6 ~10 -4 Pa, and the deposition temperature is preferably room temperature to 350°C. The patterning process preferably includes performing photoetching and etching in sequence, and the etching is wet etching or dry etching.

[0053] After obtaining the first electrode, the present application sequentially prepares a separation layer thin film and a second electrode thin film covering the substrate and the first electrode, performs photoetching on the second electrode thin film, and then uses a first wet etching method to obtain a first wet etching thin film; uses the first wet etching thin film as a hard mask to perform a first dry etching on the separation layer thin film to obtain a first dry etching thin film; performs a second wet etching on the first wet etching thin film to obtain a second electrode, one end edge of the second electrode aligning with one end edge of the substrate, and the second electrode having a width of a normal projection on the substrate less than the width of the normal projection of the first electrode on the substrate; performs a second dry etching on the first dry etching thin film to obtain a second dry etching thin film; and performs a third wet etching or a third dry etching on the second dry etching thin film to obtain a separation layer, one end edge of the separation layer aligning with one end edge of the substrate, and the separation layer having a width of a normal projection on the substrate less than the width of the normal projection of the first electrode on the substrate; the side wall of the separation layer and the side wall of the second electrode form a vertical side wall.

[0054] In the present application, the material of the separation layer is preferably an oxide of silicon (SiO x ) and / or a nitride of silicon (SiN x ), or Al2O3 and / or HfO2. In the present application, the material of the separation layer is preferably an oxide of silicon (SiO x ) and a nitride of silicon (SiNx ) the isolation layer is a laminated film layer structure of a silicon oxide film layer and a silicon nitride film layer. When the material of the isolation layer is preferably Al2O3 and HfO2, the isolation layer is a laminated film layer structure of an Al2O3 film layer and an HfO2 film layer. The thickness of the isolation layer is preferably 50 nm to 2000 nm. The isolation layer film is preferably prepared by plasma enhanced chemical vapor deposition or atomic layer deposition; the conditions of the plasma enhanced chemical vapor deposition preferably include: the deposition power is preferably 0.1 to 2.0 kW, the working pressure is preferably 0.5 to 5 Pa, and the deposition temperature is preferably 80 to 350 °C.

[0055] In the present application, the material of the second electrode is preferably one or more of aluminum, molybdenum, silver, copper, titanium, gold, and indium tin oxide. The thickness of the second electrode is preferably 20 nm to 1000 nm. The second electrode film is preferably prepared by magnetron sputtering, and the conditions of the magnetron sputtering preferably include: the deposition power is preferably 0.1 to 1.0 kW, the working pressure is preferably 10 -6 ~10 -4 Pa, and the deposition temperature is preferably room temperature to 350 °C.

[0056] In the present application, the temperature of the first wet etching is preferably room temperature to 60 °C, and the etching time is preferably 10 to 300 s; the first wet etching is preferably performed using an etching solution corresponding to the second electrode film which is well known in the art.

[0057] In the present application, the temperature of the second wet etching is preferably room temperature to 60 °C, and the etching time is preferably 10 to 300 s. The second wet etching is preferably performed using an etching solution corresponding to the second electrode film which is well known in the art.

[0058] In the present application, the temperature of the third wet etching is preferably room temperature to 60 °C, and the etching time is preferably 1 to 120 s. The third wet etching is preferably performed using an etching solution corresponding to the isolation layer film which is well known in the art.

[0059] In the present application, the etching gas used in the first dry etching is preferably SF6, CF4, O2, He, or a chloride gas, the etching power is preferably 100 to 2000 W, the working pressure is preferably 0.1 to 20 Pa, and the etching time is preferably 1 to 1000 s.

[0060] In the present application, the etching gas used in the second dry etching is preferably SF6, CF4, O2, He, or a chloride gas, the etching power is preferably 100 to 2000 W, the working pressure is preferably 0.1 to 20 Pa, and the etching time is preferably 1 to 1000 s.

[0061] In the present application, the third dry etching uses etching gas preferably SF6, CF4, O2, He or chloride gas, the power of etching is preferably 100-2000W, the working gas pressure is preferably 0.1-20Pa, and the etching time is preferably 1-1000s. The third dry etching slightly etches the vertical sidewall surface of the isolation layer, reduces the surface roughness and lowers the surface defects.

[0062] After obtaining the isolation layer and the second electrode, the present application prepares an active layer, which comprises a first part, a second part and a third part connected in sequence, the first part of the active layer is located on the first electrode, the third part of the active layer is located on the second electrode, and the second part of the active layer covers the vertical sidewalls of the isolation layer and the second electrode.

[0063] In the present application, the material of the active layer is preferably IGZO. The thickness of the active layer is preferably 10-200nm.

[0064] In the present application, the preparation method of the active layer preferably comprises: preparing an active layer thin film covering the substrate, the first electrode, the vertical sidewalls of the isolation layer and the second electrode, and the second electrode; and etching the active layer thin film after a patterning treatment to obtain the active layer. The active layer thin film is preferably prepared by magnetron sputtering or atomic layer deposition. The conditions of the magnetron sputtering preferably comprise: the deposition power is preferably 0.1-2.0kW, the working gas pressure is preferably 10 -6 ~10 -4 Pa, and the deposition temperature is preferably room temperature-350℃.

[0065] After obtaining the active layer, the present application preferably further comprises annealing the active layer before preparing the gate insulating layer. The annealing temperature is preferably 150-500℃.

[0066] After the annealing treatment of the active layer, the present application prepares a gate insulating layer, which comprises a first part, a second part, a third part and a fourth part connected in sequence, the first part of the gate insulating layer is located on the first electrode, the second part of the gate insulating layer covers the first part of the active layer, the third part of the gate insulating layer covers the second part of the active layer, the fourth part of the gate insulating layer covers the third part of the active layer and the second electrode, and the gate insulating layer is provided with a through hole on the second electrode.

[0067] In the present application, the material of the gate insulating layer is preferably silicon oxide (SiO x ) and / or silicon nitride (SiN x), or Al2O3 and / or HfO2. In the present application, the material of the gate insulating layer is preferably silicon oxide (SiO x ) and silicon nitride (SiN x ). When the material of the gate insulating layer is silicon oxide and silicon nitride, the gate insulating layer is a laminated film structure of a silicon oxide film layer and a silicon nitride film layer. When the material of the gate insulating layer is Al2O3 and HfO2, the gate insulating layer is a laminated film structure of an Al2O3 film layer and an HfO2 film layer. The thickness of the gate insulating layer is preferably 140 nm.

[0068] In the present application, the preparation method of the gate insulating layer preferably comprises: preparing a gate insulating layer thin film covering the partial first electrode, the active layer and the second electrode; and etching the gate insulating layer thin film after patterning treatment to obtain the gate insulating layer. In the present application, the gate insulating layer thin film is preferably prepared by plasma enhanced chemical vapor deposition or atomic layer deposition; and the conditions of the plasma enhanced chemical vapor deposition preferably comprise: a deposition power of 0.1-2.0 kW, a working pressure of 0.5-5 Pa, and a deposition temperature of 80-350℃.

[0069] After obtaining the gate insulating layer, the present application prepares a gate electrode, which comprises a first part and a second part connected together, the first part of the gate electrode is located on the second part of the gate insulating layer, and the second part of the gate electrode covers the third part of the gate insulating layer.

[0070] In the present application, the material of the gate electrode is preferably one or more of aluminum, molybdenum, silver, copper, titanium, gold and indium tin oxide. The thickness of the gate electrode is preferably 20-1000 nm.

[0071] In the present application, the preparation method of the gate electrode preferably comprises: preparing a gate electrode thin film covering the substrate, the first electrode, the gate insulating layer and the second electrode in the through hole of the gate insulating layer; and etching the gate electrode thin film after patterning treatment to obtain the gate electrode. The gate electrode thin film is preferably prepared by magnetron sputtering, and the conditions of the magnetron sputtering preferably comprise: a deposition power of 0.1-1.0 kW, a working pressure of 10 -6 ~10 -4 Pa, and a deposition temperature of room temperature-350℃.

[0072] The present application provides a vertical thin film transistor prepared by the preparation method.

[0073] In the present application, the vertical thin film transistor comprises a substrate, a first electrode arranged on the surface of the substrate, and the orthogonal projection width of the first electrode on the substrate is smaller than the width of the substrate; and the edge of one end of the first electrode is aligned with the edge of one end of the substrate.

[0074] a separation layer disposed on the surface of the first electrode, one end edge of the separation layer aligns with one end edge of the substrate, the orthogonal projection width of the separation layer on the substrate is less than the orthogonal projection width of the first electrode on the substrate;

[0075] a second electrode disposed on the surface of the separation layer, one end edge of the second electrode aligns with one end edge of the substrate, the orthogonal projection width of the second electrode on the substrate is less than the orthogonal projection width of the first electrode on the substrate;

[0076] the sidewall of the separation layer and the sidewall of the second electrode form vertical sidewalls;

[0077] an active layer, the active layer comprises a first part, a second part and a third part connected in sequence, the first part of the active layer is located on the first electrode, the third part of the active layer is located on the second electrode, and the second part of the active layer covers the vertical sidewalls of the separation layer and the second electrode

[0078] a gate insulating layer, the gate insulating layer comprises a first part, a second part, a third part and a fourth part connected in sequence, the first part of the gate insulating layer is located on the first electrode, the second part of the gate insulating layer covers the first part of the active layer, the third part of the gate insulating layer covers the second part of the active layer, the fourth part of the gate insulating layer covers the third part of the active layer and the second electrode, and the gate insulating layer is provided with a through hole on the second electrode;

[0079] a gate, the gate comprises a first part and a second part connected in sequence, the first part of the gate is located on the second part of the gate insulating layer, and the second part of the gate covers the third part of the gate insulating layer.

[0080] In the present application, the first electrode is a source electrode or a drain electrode, and the second electrode is a source electrode or a drain electrode. When the first electrode is a source electrode, the second electrode is a drain electrode. When the first electrode is a drain electrode, the second electrode is a source electrode.

[0081] In order to further illustrate the present application, the technical solutions provided by the present application are described in detail below in conjunction with the embodiments, but they should not be understood as limiting the scope of protection of the present application.

[0082] The following examples are prepared according to the preparation process shown in the preparation flow Figure 1 , and the structure schematic diagram of the thin film and each part in the preparation process is shown in Figures 2 to 15 .

[0083] Example 1

[0084] The TFT glass substrate 100 is cleaned and a first electrode thin film 200 is deposited in the TFT glass substrate 100. The first electrode 201 is formed by a patterning process such as photolithography and etching.

[0085] The isolation layer thin film 300 and the second electrode thin film 400 are deposited in sequence on the TFT glass substrate 100 and the first electrode 201. The first wet etching thin film 401 is formed by using a first wet etching process after the second electrode thin film 400 is photolithographed.

[0086] The first dry etching thin film 301 is formed by using the first wet etching thin film 401 as a hard mask to perform a first dry etching on the isolation layer thin film 300.

[0087] The second electrode 402 is formed by performing a second wet etching on the first wet etching thin film 401.

[0088] The second dry etching thin film 302 is formed by performing a second dry etching on the first dry etching thin film 301.

[0089] The isolation layer 303 is formed by performing a third wet etching or a third dry etching on the second dry etching thin film 302.

[0090] The active layer thin film 500 is deposited on the TFT glass substrate 100, the first electrode 201, the isolation layer 303 and the vertical sidewall of the second electrode 402, and the second electrode 402. The active layer 501 of the device is formed by a patterning process such as photolithography and etching.

[0091] The gate insulating layer thin film 600 is deposited on part of the first electrode 201, the active layer 501 and the second electrode 402. The gate insulating layer 601 with a through hole 602 on the second electrode 402 is formed by a patterning process such as photolithography and etching.

[0092] The gate thin film 700 is deposited on the TFT glass substrate 100, the first electrode 201, the gate insulating layer 601 and the second electrode 402 in the gate insulating layer through hole 602. The gate 701 of the device is formed by a patterning process such as photolithography and etching. The vertical thin film transistor is completed.

[0093] In the embodiment, the first electrode thin film 200, the second electrode thin film 400 and the gate thin film 700 are prepared by using a magnetron sputtering method. The deposition power is 0.1 KW to 1.0 KW, the working pressure is 10 -6 Pa to 10 -4Pa, the deposition temperature is from room temperature to 350℃. The thickness of the first electrode thin film 200, the second electrode thin film 400 and the gate thin film 700 is 20nm-1000nm; the material of the first electrode thin film 200, the second electrode thin film 400 and the gate thin film 700 is aluminum (Al), molybdenum (Mo), silver (Ag), copper (Cu), titanium (Ti), gold (Au), indium tin oxide (ITO) or a stack of two or more of the above materials.

[0094] The isolation layer thin film 300 and the gate insulation layer thin film 600 are prepared by plasma enhanced chemical vapor deposition, and the material is SiO x , SiN x or SiO x / SiN x stack thin film, wherein the value of x has no special requirement, the deposition power is 0.5KW, the working pressure is 0.6Pa, and the deposition temperature is from 350℃. The thickness of the isolation layer thin film 300 is 300nm. The thickness of the gate insulation layer thin film 600 is 200nm.

[0095] The active layer thin film 500 is prepared by magnetron sputtering deposition, the deposition power is 0.5KW, the working pressure is 10 - 5 Pa, and the deposition temperature is room temperature. The thickness of the active layer thin film 500 is 40nm. After obtaining the active layer 501, annealing treatment is performed on the active layer 501, and the annealing temperature is 220℃.

[0096] The first wet etching process and the second wet etching process adopt the electrode thin film 400 corresponding metal etching solution which is well known in the art, the etching process temperature is 40℃, and the etching time is 120s. The third wet etching process adopts the isolation layer thin film 300 etching solution which is well known in the art for etching reaction, the etching process temperature is 40℃, and the etching time is 5s.

[0097] The first dry etching process, the second dry etching process and the third dry etching process adopt the etching process gas and other related materials and parameters which are well known in the art. The etching gas can be selected from SF6, CF4, O2, He, chloride gas, etc., the etching RF power is 500W, the working pressure is 0.8Pa, and the etching time is 280s, 20s and 6s respectively.

[0098] Figure 16 The transfer characteristic curve diagram of the vertical thin film transistor prepared in Example 1 of the present application. The on-off ratio of the vertical thin film transistor prepared in the present example is ≥10 8 , the sub-threshold swing is 0.12V / dec, the threshold voltage is -0.34V, and the mobility is 14.32cm 2 ·V -1s -1 .

[0099] Comparative Example 1

[0100] The preparation method is basically the same as that of Example 1, except that the TFT glass substrate 100 is cleaned and a first electrode thin film 200 is deposited in the TFT glass substrate 100, and the first electrode 201 is made through a patterning process such as photolithography and etching;

[0101] The insulating layer thin film 300 and the second electrode thin film 400 are sequentially deposited on the TFT glass substrate 100 and the first electrode 201, and the second electrode thin film 400 is photolithographed and then the second electrode 402 is formed by using a first wet etching process;

[0102] The insulating layer thin film 300 is etched by using the second electrode 402 as a hard mask to form the insulating layer 303;

[0103] The active layer thin film prepared in the comparative example and the structure of the active layer are shown in Figure 17 and Figure 18 .

[0104] The on-off ratio of the vertical thin film transistor prepared in the comparative example is ≥10 6 , the sub-threshold swing is 0.52V / dec, the threshold voltage is -0.6V, and the mobility is 5.61cm 2 ·V -1 s -1 .

[0105] From the above examples, it can be seen that the structure of the vertical thin film transistor is reasonably set, and the etching method of the insulating layer and the second electrode layer in forming the vertical side wall is strictly controlled, which can effectively improve the V-TFT vertical side wall morphology and the taper angle, so as to obtain a vertical thin film transistor device with good performance (on-off ratio, sub-threshold swing, threshold voltage and mobility) and high reliability. From the results of the examples, the on-off ratio of the vertical thin film transistor prepared by the present application is ≥10 8 , the sub-threshold swing is 0.12V / dec, the threshold voltage is -0.34V, and the mobility is 14.32cm 2 ·V -1 s -1 .

[0106] Although the above examples have made a detailed description of the present application, it is only a part of the examples of the present application, not all the examples, and other examples can be obtained under the premise of not being creative according to the present examples, and these examples all belong to the protection scope of the present application.

Claims

1. A method for fabricating a vertical thin-film transistor, characterized in that, The method comprises the following steps: preparing a first electrode film on a substrate, and patterning the first electrode film to obtain a first electrode, wherein a normal projection width of the first electrode on the substrate is less than a width of the substrate; sequentially preparing an isolation layer film and a second electrode film covering the substrate and the first electrode, performing first wet etching on the second electrode film after photoetching to obtain a first wet etching film, performing first dry etching on the isolation layer film by taking the first wet etching film as a hard mask to obtain a first dry etching film, and performing second wet etching on the first wet etching film to obtain a second electrode, wherein a normal projection width of the second electrode on the substrate is less than the normal projection width of the first electrode on the substrate; performing second dry etching on the first dry etching film to obtain a second dry etching film; performing third wet etching or third dry etching on the second dry etching film to obtain an isolation layer, wherein a normal projection width of the isolation layer on the substrate is less than the normal projection width of the first electrode on the substrate; sidewalls of the isolation layer and the second electrode form vertical sidewalls; preparing an active layer, wherein the active layer comprises a first part, a second part and a third part connected in sequence, the first part of the active layer is located on the first electrode, the third part of the active layer is located on the second electrode, and the second part of the active layer covers the vertical sidewalls of the isolation layer and the second electrode; preparing a gate insulating layer, wherein the gate insulating layer comprises a first part, a second part, a third part and a fourth part connected in sequence, the first part of the gate insulating layer is located on the first electrode, the second part of the gate insulating layer covers the first part of the active layer, the third part of the gate insulating layer covers the second part of the active layer, and the fourth part of the gate insulating layer covers the third part of the active layer and the second electrode, and the gate insulating layer is provided with a through hole on the second electrode; preparing a gate, wherein the gate comprises a first part and a second part connected in sequence, the first part of the gate is located on the second part of the gate insulating layer, and the second part of the gate covers the third part of the gate insulating layer.

2. The method of claim 1, wherein The material of the isolation layer is an oxide of silicon and / or a nitride of silicon, or Al2O3 and / or HfO2; and the thickness of the isolation layer is 50 nm-2000 nm.

3. The preparation method according to claim 1, characterized in that, The material of the first electrode, the second electrode and the gate is independently one or more of aluminum, molybdenum, silver, copper, titanium, gold and indium tin oxide; and the thickness of the first electrode, the second electrode and the gate is independently 20 nm-1000 nm.

4. The process according to any one of claims 1 to 3, characterized in that, The temperature of the first wet etching and the second wet etching is independently room temperature-60 ℃, and the etching time is independently 10-300 s; the temperature of the third wet etching is room temperature-60 ℃, and the etching time is 1-120 s.

5. The production method according to claim 1 or 2, characterized by, The etching gas used in the first dry etching, the second dry etching and the third dry etching is independently SF6, CF4, O2, He or a chloride gas, the etching power is independently 100-2000 W, the working air pressure is independently 0.1-20 Pa, and the etching time is independently 1-1000 s.

6. The production method according to claim 1 or 2, characterized by, The isolation layer film is prepared by plasma enhanced chemical vapor deposition or atomic layer deposition; the conditions of the plasma enhanced chemical vapor deposition include a deposition power of 0.1-2.0 kW, a working air pressure of 0.5-5 Pa and a deposition temperature of 80-350 ℃.

7. The preparation method according to claim 1, characterized in that, The first electrode thin film and the second electrode thin film are prepared by magnetron sputtering, and the magnetron sputtering conditions include: a deposition power of 0.1-1.0 kW, a working pressure of 10 -6 ~10 -4 Pa, and a deposition temperature of room temperature-350℃.

8. The method of claim 1, wherein, The thickness of the active layer is 10-200 nm; after the active layer is obtained, the active layer is subjected to annealing treatment before the gate insulating layer is prepared, and the annealing treatment is performed at a temperature of 150-500 ℃.

9. The production method according to claim 1 or 8, characterized by, The preparation method of the active layer comprises: preparing an active layer film covering the vertical side wall of the substrate, the first electrode, the isolation layer and the second electrode, and the second electrode; and etching the active layer film after a patterning treatment to obtain the active layer. The active layer thin film is prepared by magnetron sputtering or atomic layer deposition; the magnetron sputtering conditions include: a deposition power of 0.1-2.0 kW, a working air pressure of 10 -6 -10 -4 Pa, and a deposition temperature of room temperature-350℃.

10. A vertical thin film transistor prepared by the preparation method in any one of claims 1-9.

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