Method for manufacturing crystalline silicon battery and crystalline silicon battery

Abstract

The present application discloses a method for manufacturing a crystalline silicon cell and a crystalline silicon cell, belonging to the field of battery technology. The method for manufacturing the crystalline silicon cell comprises: providing a substrate, a tunneling oxide layer located on the back of the substrate, and a polycrystalline silicon layer located on the side of the tunneling oxide layer away from the substrate; performing a hydrogenation treatment on the polycrystalline silicon layer, and forming an anti-reflection structure on the side of the polycrystalline silicon layer away from the tunneling oxide layer. The present application can improve the passivation effect of the battery, and improve the open circuit voltage and short circuit current of the battery.

Description

Technical Field

[0001] The present application belongs to the field of battery technology, and in particular relates to a method for manufacturing a crystalline silicon battery and a crystalline silicon battery. Background Art

[0002] The back of the crystalline silicon cell uses a tunneling oxide layer and a polysilicon layer to form a tunneling oxide layer passivation contact structure, which realizes selective carrier transmission, thereby achieving excellent passivation quality and contact performance. However, because the doped polysilicon surface atoms inside the polysilicon layer have a large number of unsaturated chemical bonds, and there are many impurities and defects in the polysilicon material, when electrons pass through the tunneling oxide layer, certain carrier recombination will occur in the polysilicon layer, affecting the passivation effect, thereby reducing the open circuit voltage and short circuit current of the battery. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for manufacturing a crystalline silicon cell and a crystalline silicon cell, which can improve the passivation effect of the cell and increase the open circuit voltage and short circuit current of the cell.

[0004] In a first aspect, the present application provides a method for manufacturing a crystalline silicon cell, comprising:

[0005] Providing a substrate, a tunneling oxide layer located on the back side of the substrate, and a polysilicon layer located on a side of the tunneling oxide layer away from the substrate;

[0006] The polysilicon layer is subjected to hydrogenation treatment to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer.

[0007] According to the manufacturing method of the crystalline silicon battery of the present application, after the tunneling oxide layer and the polysilicon layer are formed in sequence on the back of the battery, the polysilicon layer is hydrogenated to diffuse hydrogen into the polysilicon, thereby passivating defects in the polysilicon body, reducing the number of dangling bonds on the surface, and improving the passivation effect of the polysilicon layer, thereby improving the passivation effect of the battery, and increasing the open circuit voltage and short-circuit current of the battery.

[0008] According to one embodiment of the present application, the anti-reflection structure includes a first anti-reflection layer and a second anti-reflection layer;

[0009] The step of performing hydrogen treatment on the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer comprises:

[0010] Using hydrogen-containing gas to perform a first hydrogenation treatment on the polysilicon layer;

[0011] forming the first anti-reflection layer on a side of the polysilicon layer away from the tunnel oxide layer;

[0012] Using hydrogen-containing gas to perform a second hydrogenation treatment on the polysilicon layer;

[0013] The second anti-reflection layer is formed on a side of the first anti-reflection layer facing away from the polysilicon layer.

[0014] According to one embodiment of the present application, the anti-reflection structure further includes a third anti-reflection layer;

[0015] The step of performing hydrogen treatment on the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer further comprises:

[0016] Using hydrogen-containing gas to perform a third hydrogenation treatment on the polysilicon layer;

[0017] The third anti-reflection layer is formed on a side of the second anti-reflection layer facing away from the first anti-reflection layer.

[0018] According to one embodiment of the present application, the hydrogen-containing gas includes ammonia.

[0019] According to one embodiment of the present application, the first hydroprocessing satisfies at least one of the following characteristics:

[0020] The flow rate of the ammonia gas is 10000 sccm to 15000 sccm;

[0021] The first hydrotreatment time is 30s to 50s;

[0022] The pressure of the first hydrotreatment is 1500mTor to 2000mTor;

[0023] The power of the first hydrogenation treatment is 14000W to 17000W.

[0024] According to one embodiment of the present application, the second hydroprocessing satisfies at least one of the following characteristics:

[0025] The flow rate of the ammonia gas is 11000 sccm to 16000 sccm;

[0026] The first hydrotreatment time is 30s to 50s;

[0027] The pressure of the first hydrotreatment is 1500mTor to 2000mTor;

[0028] The power of the first hydrogenation treatment is 14000W to 17000W.

[0029] According to one embodiment of the present application, the third hydroprocessing satisfies at least one of the following characteristics:

[0030] The flow rate of the ammonia gas is 11000 sccm to 16000 sccm;

[0031] The first hydrotreatment time is 40s to 80s;

[0032] The pressure of the first hydrotreatment is 1500mTor to 2000mTor;

[0033] The power of the first hydrogenation treatment is 14000W to 17000W.

[0034] According to one embodiment of the present application, the first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer each include at least one passivation layer.

[0035] According to an embodiment of the present application, the first anti-reflection layer and the second anti-reflection layer each include a passivation layer, and the third anti-reflection layer includes three stacked passivation layers.

[0036] According to an embodiment of the present application, in a direction in which the polysilicon layer is away from the tunnel oxide layer, the refractive index of the passivation layer gradually decreases.

[0037] According to an embodiment of the present application, before performing hydrogen treatment on the polysilicon layer and forming an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer, the method further includes:

[0038] The polysilicon layer is thinned.

[0039] According to an embodiment of the present application, the step of thinning the polysilicon layer includes:

[0040] Plasma gas is used to perform plasma etching on the polysilicon layer to reduce the thickness of the polysilicon layer.

[0041] According to one embodiment of the present application, the plasma gas includes ammonia gas.

[0042] According to one embodiment of the present application, the plasma etching satisfies at least one of the following characteristics:

[0043] The flow rate of the ammonia gas is 10000 sccm to 15000 sccm

[0044] The temperature of the plasma etching is 450°C to 550°C;

[0045] The power of the plasma etching is 10000W to 15000W;

[0046] The pressure of the plasma etching is 1500mTor to 2000mTor;

[0047] The plasma etching time is 100s to 300s.

[0048] According to an embodiment of the present application, the polysilicon layer is thinned to a thickness of 5 nm to 10 nm.

[0049] According to an embodiment of the present application, forming an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer includes:

[0050] Based on the reaction gas, an anti-reflection structure is formed on a side of the polysilicon layer away from the tunnel oxide layer.

[0051] According to one embodiment of the present application, the reaction gas includes silane and ammonia.

[0052] In a second aspect, the present application provides a crystalline silicon cell, which is manufactured using the manufacturing method of the crystalline silicon cell as described in the first aspect.

[0053] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0054] After the tunnel oxide layer and the polysilicon layer are formed on the back of the battery in sequence, the polysilicon layer is hydrogenated to diffuse hydrogen into the polysilicon, thereby passivating the defects in the polysilicon body, reducing the number of dangling bonds on the surface, and improving the passivation effect of the polysilicon layer, thereby improving the passivation effect of the battery, increasing the open circuit voltage and short circuit current of the battery, and improving the photoelectric conversion efficiency of the battery;

[0055] The thickness of the polysilicon layer can be reduced by plasma etching the polysilicon layer using a specific type of gas, ammonia. The radius of hydrogen ions ionized by ammonia is small, so the damage caused by ionization is small, and the thickness uniformity of the polysilicon layer after thinning is better, which effectively reduces parasitic absorption, thereby further increasing the short-circuit current and further improving the photoelectric conversion efficiency of the battery.

[0056] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0058] Figure 1 This is one of the flow charts of the method for manufacturing a crystalline silicon cell provided in an embodiment of the present application;

[0059] Figure 2 This is one of the structural schematic diagrams of the method for manufacturing a crystalline silicon cell provided in an embodiment of the present application;

[0060] Figure 3 This is one of the structural schematic diagrams of the crystalline silicon cell provided in the embodiment of the present application;

[0061] Figure 4 This is the second flow chart of the method for manufacturing a crystalline silicon cell provided in an embodiment of the present application;

[0062] Figure 5 This is the second structural schematic diagram of the method for manufacturing a crystalline silicon cell provided in an embodiment of the present application;

[0063] Figure 6 This is the third structural schematic diagram of the method for manufacturing a crystalline silicon cell provided in an embodiment of the present application;

[0064] Figure 7 This is the second structural schematic diagram of the crystalline silicon cell provided in the embodiment of the present application;

[0065] Figure 8 This is the third structural schematic diagram of the crystalline silicon cell provided in the embodiment of the present application;

[0066] Fig. 9 This is the fourth structural schematic diagram of the crystalline silicon battery provided in the embodiment of the present application;

[0067] Fig.10 This is the third flow chart of the method for manufacturing a crystalline silicon cell provided in the embodiment of the present application. DETAILED DESCRIPTION

[0068] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0069] The following describes the manufacturing method of the crystalline silicon cell and the crystalline silicon cell provided in the embodiments of the present application with reference to the accompanying drawings.

[0070] Figure 1 A schematic diagram of the process of manufacturing a crystalline silicon cell provided in an embodiment of the present application.

[0071] like Figure 1 As shown, the method for manufacturing a crystalline silicon cell provided in the embodiment of the present application includes step 110 and step 120.

[0072] Step 110: providing a substrate, a tunneling oxide layer on the back side of the substrate, and a polysilicon layer on a side of the tunneling oxide layer away from the substrate.

[0073] like Figure 2As shown, a substrate 1, a tunneling oxide layer 2 and a polysilicon layer 3 are provided. The tunneling oxide layer 2 is located on the back side of the substrate 1, and the polysilicon layer 3 is located on the side of the tunneling oxide layer 2 away from the substrate 1. The tunneling oxide layer 2 and the polysilicon layer 3 can form a tunneling oxide passivation contact (TOPCon) structure to achieve selective carrier transport, thereby achieving excellent passivation quality and contact performance.

[0074] During the manufacturing process, a substrate 1 may be provided first. In some embodiments, the substrate 1 may be polished on the back side or have a fine velvet surface on the back side. Then, a tunnel oxide layer 2 is formed on the back side of the substrate 1 by a thin film deposition process. A polysilicon layer 3 is formed on the side of the tunnel oxide layer 2 away from the substrate 1 by a thin film deposition process. The thin film deposition process may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc.

[0075] It can be understood that when the tunnel oxide layer 2 and the polysilicon layer 3 are formed in sequence on the back side of the substrate 1, the tunnel oxide layer 2 and the polysilicon layer 3 will wrap around to the front side of the substrate 1, and the tunnel oxide layer 2 and the polysilicon layer 3 wrapped around to the front side of the substrate 1 need to be RCA cleaned to remove the tunnel oxide layer 2 and the polysilicon layer 3 wrapped around to the front side of the substrate 1. Among them, the reagent used to remove the tunnel oxide layer 2 wrapped around to the front side of the substrate 1 may include HF, etc., and the reagent used to remove the polysilicon layer 3 wrapped around to the front side of the substrate 1 may include alkali solution, etc. Among them, the alkali solution may include sodium hydroxide solution, etc.

[0076] In some embodiments, the substrate 1 may include an N-type silicon substrate. The tunnel oxide layer 2 may include silicon oxide, etc., and the thickness of the tunnel oxide layer 2 may be between 1 nm and 2 nm. The polysilicon layer 3 may include P-type polysilicon (poly), etc., and the thickness of the polysilicon layer 3 may be between 90 nm and 115 nm.

[0077] In some embodiments, before the tunneling oxide layer 2 and the polysilicon layer 3 are sequentially formed on the back side of the substrate 1 , a PN junction is formed on the front side of the substrate 1 , and the front side and the back side of the substrate 1 are arranged opposite to each other.

[0078] The step of forming a PN junction on the front side of the substrate 1 may include:

[0079] Boron diffusion is performed on the front side of the substrate 1 to prepare a PN junction.

[0080] It is understandable that the boron diffusion step can be performed in a boron diffusion furnace. The gases used for boron diffusion include but are not limited to BCl3 and oxygen.

[0081] It is understandable that when the front side of the substrate 1 is subjected to boron diffusion, a BSG (borosilicate glass layer) will be formed on the back side of the substrate 1, and the BSG on the back side of the silicon wafer needs to be removed. The reagent used to remove the BSG on the back side of the substrate 1 includes but is not limited to HF.

[0082] In some embodiments, a passivation film is further formed on the front surface of the substrate 1, and the passivation film is located on the side of the PN junction away from the substrate 1. The passivation film includes at least one of aluminum oxide film, silicon nitride, silicon oxynitride and silicon oxide. The thickness of the passivation film is 65nm to 85nm.

[0083] Step 120 , performing hydrogenation treatment on the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer away from the tunneling oxide layer.

[0084] like Figure 3 As shown, after the polysilicon layer 3 is formed, the polysilicon layer 3 is subjected to a hydrogenation treatment, and an anti-reflection structure 4 is formed on a side of the polysilicon layer 3 away from the tunnel oxide layer 2 .

[0085] Since the polysilicon layer 3 is doped with ions, the surface atoms of the doped polysilicon have a large number of unsaturated chemical bonds, and there are many impurities and defects in the polysilicon material. When electrons pass through the tunneling oxide layer 2, certain carrier recombination will occur in the polysilicon layer 3, affecting the passivation effect, thereby reducing the open circuit voltage and short-circuit current of the battery.

[0086] Therefore, after forming the polysilicon layer 3, this embodiment performs a hydrogenation treatment on the polysilicon layer 3 to diffuse hydrogen into the polysilicon, thereby passivating defects in the polysilicon body, reducing the number of surface dangling bonds, and improving the passivation effect of the polysilicon layer 3, thereby improving the passivation effect of the battery, increasing the open circuit voltage and short circuit current of the battery, and improving the overall performance of the battery.

[0087] The anti-reflection structure 4 can increase the absorption of light and reduce the reflection of light. When the crystalline silicon cell is applied to the solar cell, it can effectively improve the photoelectric conversion efficiency of the solar cell. Moreover, during the formation process, the anti-reflection structure 4 also has a passivation effect on the polysilicon layer 3, further improving the passivation effect of the cell.

[0088] In some embodiments, the step 120 of hydrogenating the polysilicon layer includes:

[0089] The polysilicon layer is subjected to hydrogenation treatment using hydrogen-containing gas.

[0090] Among them, the hydrogenation treatment of the polysilicon layer 3 can be carried out in a reaction chamber. The structure composed of the substrate 1, the tunneling oxide layer 2 and the polysilicon layer 3 can be placed in a reaction chamber, and then a hydrogen-containing gas is introduced into the reaction chamber. The polysilicon layer 3 is hydrogenated using a hydrogen-containing gas. Among them, parameters such as the flow rate of the hydrogen-containing gas, the treatment time, the RF power and the pressure can be adjusted according to actual needs to ensure that the hydrogenation treatment effect of the polysilicon layer 3 meets the needs.

[0091] In some embodiments, the hydrogen-containing gas includes ammonia. It should be noted that the hydrogen-containing gas may also include other gases as long as they can satisfy the requirements for hydrogenation treatment of the polysilicon layer 3, and no specific limitation is made here.

[0092] In some embodiments, forming an anti-reflection structure on a side of the polysilicon layer away from the tunneling oxide layer in step 120 includes:

[0093] Based on the reaction gas, an anti-reflection structure is formed on a side of the polysilicon layer away from the tunnel oxide layer.

[0094] The formation of the anti-reflection structure 4 can be carried out in a reaction chamber. The structure composed of the substrate 1, the tunneling oxide layer 2 and the polysilicon layer 3 can be placed in a reaction chamber. After the polysilicon layer 3 is hydrogenated, a reaction gas is introduced into the reaction chamber. Based on the reaction gas, an anti-reflection structure 4 is formed on the side of the polysilicon layer 3 away from the tunneling oxide layer 2. Parameters such as the flow rate of the reaction gas, the processing time, the RF power and the pressure can be adjusted according to actual needs to ensure that the formation effect of the anti-reflection structure 4 meets the needs.

[0095] In some embodiments, the reaction gas includes silane and ammonia. It should be noted that the reaction gas may also include other gases as long as they can form the anti-reflection structure 4, which is not specifically limited here. The flow ratio of each gas in the reaction gas can be set according to actual needs, which is not specifically limited here.

[0096] In some embodiments, the polysilicon layer 3 may be subjected to a hydrogenation treatment, that is, after the polysilicon layer 3 is formed and before the anti-reflection structure 4 is formed, the polysilicon layer 3 may be subjected to a hydrogenation treatment to improve the passivation effect of the polysilicon layer 3. In some embodiments, a hydrogen-containing gas is used to perform a hydrogenation treatment on the polysilicon layer 3. Then, the anti-reflection structure 4 is formed on the side of the polysilicon layer 3 away from the tunneling oxide layer 2.

[0097] The anti-reflection structure 4 may be a single-layer structure or a stacked structure. For example, the anti-reflection structure 4 may include a plurality of passivation layers stacked. The step of forming the anti-reflection structure 4 on the side of the polysilicon layer 3 away from the tunneling oxide layer 2 may include: using a thin film deposition process to sequentially form a plurality of passivation layers on the side of the polysilicon layer 3 away from the tunneling oxide layer 2.

[0098] In some embodiments, the polysilicon layer 3 may be subjected to multiple hydrogenation treatments. The anti-reflection structure 4 may be a stacked structure, for example, the anti-reflection structure 4 includes multiple anti-reflection layers stacked in layers. After the polysilicon layer 3 is formed and before each anti-reflection layer is formed, the polysilicon layer 3 is subjected to hydrogenation treatment.

[0099] The anti-reflection structure 4 includes a first anti-reflection layer and a second anti-reflection layer. Figure 4 As shown, in step 120, the polysilicon layer is subjected to hydrogenation treatment to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer, including:

[0100] Step 121, using hydrogen-containing gas to perform a first hydrogenation treatment on the polysilicon layer;

[0101] Step 122, forming a first anti-reflection layer on a side of the polysilicon layer away from the tunnel oxide layer;

[0102] Step 123, using hydrogen-containing gas to perform a second hydrogenation treatment on the polysilicon layer;

[0103] Step 124 , forming a second anti-reflection layer on a side of the first anti-reflection layer away from the polysilicon layer.

[0104] After forming the polysilicon layer 3 and before forming the first anti-reflection layer 41, a hydrogen-containing gas is used to perform a first hydrogenation treatment on the polysilicon layer 3. The hydrogen-containing gas may include ammonia. Ammonia is introduced into the reaction chamber to perform a hydrogenation treatment on the polysilicon layer 3 using ammonia to improve the passivation effect of the polysilicon layer 3.

[0105] Wherein, the first hydroprocessing satisfies at least one of the following characteristics:

[0106] The flow rate of ammonia is 10000sccm to 15000sccm;

[0107] The first hydrotreatment time is 30s to 50s;

[0108] The pressure of the first hydrotreatment is 1500mTor~2000mTor;

[0109] The power of the first hydrogenation treatment is 14000W to 17000W.

[0110] Then, if Figure 5As shown, a first anti-reflection layer 41 is formed on the side of the polysilicon layer 3 away from the tunnel oxide layer 2. In some embodiments, based on the reaction gas, the first anti-reflection layer 41 is formed on the side of the polysilicon layer 3 away from the tunnel oxide layer 2. The reaction gas may include silane and ammonia. Silane and ammonia are introduced into the reaction chamber to form the first anti-reflection layer 41 on the side of the polysilicon layer 3 away from the tunnel oxide layer 2 based on silane and ammonia and using a thin film deposition process.

[0111] The first anti-reflection layer 41 may be a single-layer structure or a stacked-layer structure. The first anti-reflection layer 41 may include at least one passivation layer. In some embodiments, the first anti-reflection layer 41 may include a passivation layer. The passivation layer may include at least one of an aluminum oxide film, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. For example, the first anti-reflection layer 41 may include a silicon nitride layer (first silicon nitride layer).

[0112] In the case where the first anti-reflection layer 41 includes a silicon nitride layer, a first silicon nitride layer is formed on the side of the polysilicon layer 3 away from the tunneling oxide layer 2 based on silane and ammonia and a thin film deposition process. The ratio of the flow rate of silane and ammonia can be between 0.23 and 0.28, the reaction time can be between 50s and 80s, the pressure can be between 1500Pa and 2000Pa, and the power can be between 14000W and 17000W.

[0113] After forming the first anti-reflection layer 41 and before forming the second anti-reflection layer 42, a hydrogen-containing gas is used to perform a second hydrogenation treatment on the polysilicon layer 3. The hydrogen-containing gas may include ammonia. Ammonia is introduced into the reaction chamber to perform a hydrogenation treatment on the polysilicon layer 3 again using ammonia to further improve the passivation effect of the polysilicon layer 3.

[0114] Wherein, the second hydroprocessing satisfies at least one of the following characteristics:

[0115] The flow rate of ammonia is 11000sccm to 16000sccm;

[0116] The first hydrotreatment time is 30s to 50s;

[0117] The pressure of the first hydrotreatment is 1500mTor~2000mTor;

[0118] The power of the first hydrogenation treatment is 14000W to 17000W.

[0119] Then, if Figure 6As shown, a second anti-reflection layer 42 is formed on a side of the first anti-reflection layer 41 away from the polysilicon layer 3. In some embodiments, based on the reaction gas, the second anti-reflection layer 42 is formed on a side of the first anti-reflection layer 41 away from the polysilicon layer 3. The reaction gas may include silane and ammonia. Reaction silane and ammonia are introduced into the reaction chamber to form the second anti-reflection layer 42 on a side of the first anti-reflection layer 41 away from the polysilicon layer 3 based on silane and ammonia and using a thin film deposition process.

[0120] The second anti-reflection layer 42 may be a single-layer structure or a stacked-layer structure. The second anti-reflection layer 42 may include at least one passivation layer. In some embodiments, the second anti-reflection layer 42 may include a passivation layer. The passivation layer may include at least one of an aluminum oxide film, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. For example, the first anti-reflection layer 41 may include a silicon nitride layer (second silicon nitride layer).

[0121] In the case where the second anti-reflection layer 42 includes a silicon nitride layer, the second silicon nitride layer is formed on the side of the first anti-reflection layer 41 away from the polysilicon layer 3 based on silane and ammonia and a thin film deposition process. The ratio of the flow rate of silane and ammonia can be between 0.15 and 0.23, the reaction time can be between 50s and 80s, the pressure can be between 1500mTor and 2000mTor, and the power can be between 14000w and 17000w.

[0122] In some embodiments, the anti-reflection structure 4 further includes a third anti-reflection layer. Figure 4 As shown, in step 120, the polysilicon layer is subjected to hydrogenation treatment to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer, and further includes:

[0123] Step 125, performing a third hydrogenation treatment on the polysilicon layer;

[0124] Step 126: forming a third anti-reflection layer on a side of the second anti-reflection layer away from the first anti-reflection layer.

[0125] After forming the second anti-reflection layer 42 and before forming the third anti-reflection layer 43, a hydrogen-containing gas is used to perform a third hydrogenation treatment on the polycrystalline silicon layer 3. The hydrogen-containing gas may include ammonia. Ammonia is introduced into the reaction chamber to perform a hydrogenation treatment on the polycrystalline silicon layer 3 again using ammonia to further improve the passivation effect of the polycrystalline silicon layer 3.

[0126] Wherein, the third hydroprocessing satisfies at least one of the following characteristics:

[0127] The flow rate of ammonia is 11000sccm to 16000sccm;

[0128] The first hydrotreatment time is 40s to 80s;

[0129] The pressure of the first hydrotreatment is 1500mTor~2000mTor;

[0130] The power of the first hydrogenation treatment is 14000W to 17000W.

[0131] Then, if Figure 7 As shown, a third anti-reflection layer 43 is formed on a side of the second anti-reflection layer 42 away from the first anti-reflection layer 41. In some embodiments, based on the reaction gas, the third anti-reflection layer 43 is formed on a side of the second anti-reflection layer 42 away from the first anti-reflection layer 41. The reaction gas may include silane and ammonia. Reaction silane and ammonia are introduced into the reaction chamber to form the third anti-reflection layer 43 on a side of the second anti-reflection layer 42 away from the first anti-reflection layer 41 based on silane and ammonia and using a thin film deposition process.

[0132] The third anti-reflection layer 43 may be a single-layer structure or a stacked structure. The third anti-reflection layer 43 may include at least one passivation layer. In some embodiments, the third anti-reflection layer 43 may include three passivation layers stacked. The passivation layer may include at least one of an aluminum oxide film, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. For example, the third anti-reflection layer 43 may include three silicon nitride layers (a third silicon nitride layer, a fourth silicon nitride layer, and a fifth silicon nitride layer) stacked.

[0133] In the case where the third anti-reflection layer 43 includes three stacked silicon nitride layers, based on silane and ammonia, and using a thin film deposition process, three silicon nitride layers are sequentially formed on the side of the second anti-reflection layer 42 away from the first anti-reflection layer 41. In other words, the third silicon nitride layer is first formed on the side of the second anti-reflection layer 42 away from the first anti-reflection layer 41, and then the fourth silicon nitride layer is formed on the side of the third silicon nitride layer away from the second anti-reflection layer 42, and then the fifth silicon nitride layer is formed on the side of the fourth silicon nitride layer away from the third silicon nitride layer.

[0134] During the formation of the third silicon nitride layer, the flow rate ratio of silane and ammonia can be between 0.11 and 0.15, the reaction time can be between 90s and 120s, the pressure can be between 1500mTor and 2000mTor, and the power can be between 14000w and 17000w.

[0135] During the formation of the fourth silicon nitride layer, the flow rate ratio of silane and ammonia can be between 0.08 and 0.13, the reaction time can be between 110s and 140s, the pressure can be between 1500mTor and 2000mTor, and the power can be between 14000w and 17000w.

[0136] During the formation of the fifth silicon nitride layer, the flow rate ratio of silane and ammonia can be between 0.06 and 0.11, the reaction time can be between 180s and 230s, the pressure can be between 1500mTor and 2000mTor, and the power can be between 14000w and 17000w.

[0137] In the case where the anti-reflection structure 4 includes five passivation layers, the first anti-reflection layer 41 and the second anti-reflection layer 42 may each include one passivation layer, and the third anti-reflection layer 43 may include a plurality of passivation layers stacked. In the manufacturing process, after the polysilicon layer 3 is formed, the polysilicon layer 3 may be subjected to a first hydrogenation treatment. Then, in combination with Figure 8 As shown, a first passivation layer 40a is formed on the side of the polysilicon layer 3 away from the tunnel oxide layer 2. The polysilicon layer 3 is subjected to a second hydrogenation treatment. Then, a second passivation layer 40b is formed on the side of the first silicon nitride layer away from the polysilicon layer 3. The polysilicon layer 3 is subjected to a third hydrogenation treatment. Then, a third passivation layer 40c, a fourth passivation layer 40d and a fifth passivation layer 40e are sequentially formed on the side of the second silicon nitride layer away from the first silicon nitride layer.

[0138] In this embodiment, after the polysilicon layer 3 is formed, the polysilicon layer 3 is subjected to hydrogenation treatment, which effectively improves the passivation effect of the polysilicon layer 3. After forming a passivation layer (the first passivation layer 40a), the polysilicon layer 3 is subjected to a second hydrogenation treatment to avoid the passivation layer being too thick and affecting the diffusion effect of hydrogen, and further improve the passivation effect of the polysilicon layer 3. After forming another passivation layer (the second passivation layer 40b), the polysilicon layer 3 is subjected to a third hydrogenation treatment to avoid the passivation layer being too thick and affecting the diffusion effect of hydrogen, and further improve the passivation effect of the polysilicon layer 3.

[0139] In the case where the anti-reflection structure 4 includes five passivation layers, the first anti-reflection layer 41, the second anti-reflection layer 42 and the third anti-reflection layer 43 may also include other numbers of passivation layers. For example, the first anti-reflection layer 41 and the second anti-reflection layer may each include two passivation layers stacked, and the third anti-reflection layer 43 may include one passivation layer. In the manufacturing process, after the polysilicon layer 3 is formed, the polysilicon layer 3 may be subjected to a first hydrogenation treatment. Then, in combination with Fig. 9 As shown, a first passivation layer 40a and a second passivation layer 40b are sequentially formed on the side of the polysilicon layer 3 away from the tunnel oxide layer 2. The polysilicon layer 3 is subjected to a second hydrogenation treatment. Then, a third passivation layer 40c and a fourth passivation layer 40d are sequentially formed on the side of the second passivation layer 40b away from the first passivation layer 40a. The polysilicon layer 3 is subjected to a third hydrogenation treatment. Then, a fifth passivation layer 40e is sequentially formed on the side of the fourth passivation layer 40d away from the third passivation layer 40c.

[0140] In some embodiments, when the anti-reflection structure 4 includes a plurality of passivation layers that are stacked, the refractive index of the plurality of passivation layers gradually decreases in a direction in which the polysilicon layer 3 is away from the tunneling oxide layer 2 .

[0141] In this embodiment, the refractive indexes of the multiple passivation layers in the anti-reflection structure 4 are different, which can effectively reduce the reflection of light and improve the photoelectric conversion efficiency of the battery. In addition, the refractive index of the passivation layer arranged close to the polysilicon layer 3 is higher, which has a better body surface passivation effect.

[0142] In some embodiments, Fig.10 As shown, before the polysilicon layer is subjected to hydrogenation treatment in step 120 and an anti-reflection structure is formed on a side of the polysilicon layer away from the tunnel oxide layer, the step further includes:

[0143] Step 111 , thinning the polysilicon layer.

[0144] In the related art, the thickness of the polysilicon layer in the crystalline silicon cell is relatively large, which leads to higher parasitic absorption, affects the short-circuit current of the crystalline silicon cell, and further leads to lower conversion efficiency of the solar cell. However, in this embodiment, the polysilicon layer 3 is thinned to make the thickness uniformity of the polysilicon layer 3 better after thinning, effectively reduce parasitic absorption, further increase short-circuit current, and further improve conversion efficiency of the solar cell.

[0145] In some embodiments, the step 111 of thinning the polysilicon layer includes:

[0146] Plasma gas is used to perform plasma etching on the polysilicon layer to reduce the thickness of the polysilicon layer.

[0147] The thickness reduction process of the polysilicon layer 3 can be performed in a reaction chamber. The structure composed of the substrate 1, the tunneling oxide layer 2 and the polysilicon layer 3 can be placed in a reaction chamber, and then plasma gas is introduced into the reaction chamber. The polysilicon layer 3 is plasma etched using plasma gas. Parameters such as the plasma gas flow rate, processing time, radio frequency power and pressure can be adjusted according to actual needs to ensure that the thickness reduction effect of the polysilicon layer 3 meets the needs.

[0148] In some embodiments, the plasma gas includes ammonia. It should be noted that the plasma gas may also include other gases as long as they can meet the requirements of the thinning process for the polysilicon layer 3, and no specific limitation is made here.

[0149] In this embodiment, a specific type of ammonia gas is used to perform plasma etching on the polysilicon layer 3 on the back side of the substrate 1, so that the polysilicon layer 3 can be thinned. The radius of hydrogen ions ionized by ammonia gas is small, so that the damage caused by ionization is small, and the thickness uniformity of the polysilicon layer 3 after thinning is better, which effectively reduces parasitic absorption, further increases short-circuit current, and further improves the conversion efficiency of solar cells.

[0150] In some embodiments, the thickness of the polysilicon layer 3 after thinning is 5 nm to 10 nm, that is, the difference in thickness of the polysilicon layer 3 before and after plasma etching is 5 nm to 10 nm.

[0151] In some embodiments, the thickness of the polysilicon layer 3 after plasma etching is 70 nm to 100 nm.

[0152] In some embodiments, the plasma etching satisfies at least one of the following characteristics:

[0153] The flow rate of ammonia is 10000sccm~15000sccm

[0154] The temperature of plasma etching is 450℃~550℃;

[0155] The power of plasma etching is 10000W~15000W;

[0156] The pressure of plasma etching is 1500mTor~2000mTor;

[0157] The plasma etching time is 100s to 300s.

[0158] In some embodiments, the front and back sides of the crystalline silicon cell are further formed with a first electrode and a second electrode, respectively. The first electrode is located on the side of the PN junction away from the substrate 1 , and the second electrode is located on the side of the anti-reflection structure away from the substrate 1 .

[0159] The manufacturing process of the first electrode and the second electrode may include printing and other processes. For example, electrode grid lines are printed on the front and back of the substrate 1, respectively, and sintered to form the first electrode and the second electrode. It can be further understood that the present application does not limit the materials of the first electrode and the second electrode.

[0160] According to the manufacturing method of the crystalline silicon battery provided in the embodiment of the present application, after the tunneling oxide layer and the polycrystalline silicon layer are formed in sequence on the back of the battery, the polycrystalline silicon layer is hydrogenated to diffuse hydrogen into the polycrystalline silicon, thereby passivating the defects in the polycrystalline silicon body, reducing the number of dangling bonds on the surface, and improving the passivation effect of the polycrystalline silicon layer, thereby improving the passivation effect of the battery, and increasing the open circuit voltage and short-circuit current of the battery.

[0161] Correspondingly, an embodiment of the present application further provides a crystalline silicon cell, which can be manufactured using the manufacturing method of the crystalline silicon cell in the above embodiment.

[0162] like Figure 3 As shown, the crystalline silicon cell includes a substrate 1, a tunneling oxide layer 2, a polysilicon layer 3 and an anti-reflection structure 4. The tunneling oxide layer 2 is located on the back of the substrate 1, the polysilicon layer 3 is located on the side of the tunneling oxide layer 2 away from the substrate 1, and the anti-reflection structure 4 is located on the side of the polysilicon layer 3 away from the tunneling oxide layer 2.

[0163] Wherein, the substrate 1 may include an N-type silicon substrate. The tunneling oxide layer 2 and the polysilicon layer 3 may constitute a tunneling oxide passivation contact (TOPCon) structure to achieve selective carrier transport, thereby achieving excellent passivation quality and contact performance. The tunneling oxide layer 2 may include silicon oxide, and the thickness of the tunneling oxide layer 2 may be between 1.5nm and 2nm. The polysilicon layer 3 may include P-type polysilicon (poly), and the thickness of the polysilicon layer 3 may be between 105nm and 115nm.

[0164] The polysilicon layer 3 in this embodiment is subjected to a separate hydrogenation treatment to passivate defects in the polysilicon body and reduce the number of dangling bonds on the surface, so that the polysilicon layer 3 has a good passivation effect, improves the open circuit voltage and short circuit current of the battery, and improves the overall performance of the battery. In addition, the anti-reflection structure 4 can increase the absorption of light and reduce the reflection of light. When the crystalline silicon cell is applied to a solar cell, the photoelectric conversion efficiency of the solar cell is effectively improved.

[0165] The anti-reflection structure 4 may be a single-layer structure or a stacked-layer structure.

[0166] In some embodiments, Figure 7 As shown, the anti-reflection structure 4 includes a first anti-reflection layer 41 and a second anti-reflection layer 42 stacked. The first anti-reflection layer 41 is located on the side of the polysilicon layer 3 away from the tunneling oxide layer 2, and the second anti-reflection layer 42 is located on the side of the first anti-reflection layer 41 away from the polysilicon layer 3.

[0167] In some embodiments, Figure 7 As shown, the anti-reflection structure 4 further includes a third anti-reflection layer 43. The third anti-reflection layer 43 is located on a side of the second anti-reflection layer 42 away from the first anti-reflection layer 41.

[0168] In some embodiments, the first anti-reflection layer 41 , the second anti-reflection layer 42 , and the third anti-reflection layer 43 each include at least one passivation layer.

[0169] For example Figure 8As shown, the first anti-reflection layer 41 includes a passivation layer (first passivation layer 40a), the second anti-reflection layer 42 includes a passivation layer (second passivation layer 40b), and the third anti-reflection layer 43 includes three stacked passivation layers (third passivation layer 40c, fourth passivation layer 40d and fifth passivation layer 40e).

[0170] For another example, the first anti-reflection layer 41 includes two stacked passivation layers (a first passivation layer 40a and a second passivation layer 40b), the second anti-reflection layer 42 includes two stacked passivation layers (a third passivation layer 40c and a fourth passivation layer 40d), and the third anti-reflection layer 43 includes one passivation layer (a fifth passivation layer 40e).

[0171] In some embodiments, the passivation layer includes a silicon nitride layer.

[0172] According to the crystalline silicon cell provided by the embodiment of the present application, after the tunneling oxide layer and the polysilicon layer are formed in sequence on the back of the cell, the polysilicon layer is subjected to hydrogenation treatment to diffuse hydrogen into the polysilicon, thereby passivating the defects in the polysilicon body, reducing the number of dangling bonds on the surface, and improving the passivation effect of the polysilicon layer, thereby improving the passivation effect of the battery, increasing the open circuit voltage and short circuit current of the battery, and improving the photoelectric conversion efficiency of the battery. Moreover, the thickness of the polysilicon layer can be thinned by plasma etching the polysilicon layer using a specific type of gas ammonia, and the radius of the hydrogen ions ionized by ammonia is small, so that the damage caused by ionization is small, and the thickness uniformity of the polysilicon layer after thinning is better, effectively reducing parasitic absorption, thereby further increasing the short circuit current and further improving the photoelectric conversion efficiency of the battery.

[0173] Correspondingly, an embodiment of the present application further provides a solar cell, comprising the crystalline silicon cell in the above embodiment.

[0174] This embodiment can improve the passivation effect of the battery, increase the open circuit voltage and short circuit current of the battery, and effectively improve the photoelectric conversion efficiency of the solar cell.

[0175] Correspondingly, an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell in the above embodiment.

[0176] The photovoltaic module of the present application includes the solar cell provided by the present application, and thus has at least the same advantages as the above-mentioned solar cell.

[0177] Correspondingly, an embodiment of the present application also provides an electrical device, including the above-mentioned photovoltaic component.

[0178] The electrical device of the present application includes the photovoltaic module provided by the present application, and thus has at least the same advantages as the above-mentioned photovoltaic module.

[0179] In some embodiments, the electrical equipment includes but is not limited to transportation equipment such as cars and airplanes, and electrical equipment such as car aromatherapy that requires power to drive.

[0180] The present application is further described in detail below in conjunction with specific implementation methods, but the implementation methods of the present application are not limited thereto.

[0181] Example 1

[0182] (1) Cleaning and texturing an N-type silicon wafer to form a pyramid-shaped textured surface structure on the surface of the silicon wafer;

[0183] (2) Boron diffusion is performed on the front side of the cleaned and textured silicon wafer to form a P-type region to obtain a PN junction;

[0184] (3) performing alkaline polishing on the back side of the silicon wafer to remove the PN junction that is wound to the back side and edge of the silicon wafer during the boron diffusion on the front side in step (2);

[0185] (4) A tunneling oxide layer and a Poly layer (polycrystalline silicon layer) are sequentially prepared on the back of the silicon wafer after alkali polishing. The tunneling oxide layer is SiO 2 layer, with a thickness of 1.5nm; the thickness of the Poly layer is 90nm;

[0186] (5) RCA cleaning to remove the tunneling oxide layer and polysilicon layer that are wrapped around the front side of the silicon wafer when the tunneling oxide layer and poly layer are prepared on the back side of the silicon wafer in step (4);

[0187] (6) ALD front deposition of aluminum oxide: Aluminum oxide (Al2O3) is deposited on the PN junction surface of the silicon wafer after RCA cleaning. 2 O 3 ) film layer, with a thickness of 8 nm;

[0188] (7) Preparation of a passivation film on the front side: silicon oxynitride, silicon nitride, and silicon oxide are deposited on the surface of the aluminum oxide film layer to a thickness of 75 nm;

[0189] (8) Plasma etching the polysilicon layer on the back of the silicon wafer using ammonia gas; wherein the flow rate of ammonia gas is 12000 sccm, the temperature of plasma etching is 500°C, the power is 13500 W, the pressure is 1800 mTor, and the time is 200 s; the thickness of the Poly layer after plasma etching is 80 nm;

[0190] (9) hydrogenating the polysilicon layer on the back of the silicon wafer using ammonia gas; wherein the flow rate of the ammonia gas is 10000 sccm, the hydrogenation time is 30 s, the pressure is 1500 mTor, and the power is 14000 W;

[0191] (10) Preparation of anti-reflection structure on the back: silicon oxynitride and silicon nitride are deposited on the surface of the polysilicon layer of the silicon wafer after plasma etching, with a thickness of 85 nm;

[0192] (11) Printing electrode grid lines on the front and back sides: Print electrode grid lines on the surface of the passivation film and the surface of the anti-reflection structure respectively, and sinter them to prepare crystalline silicon cells.

[0193] Example 2

[0194] The method is basically the same as Example 1, except that in step (8) of Example 2, the plasma etching time is 100 s. Step (8) is as follows:

[0195] (8) Plasma etching the intermediate obtained in step (7) using ammonia gas; wherein the flow rate of ammonia gas is 12000 sccm, the temperature of plasma etching is 500° C., the power is 13500 W, the pressure is 1800 mTor, and the time is 100 s.

[0196] Example 3

[0197] The method is basically the same as Example 1, except that in step (8) of Example 3, the plasma etching time is 300 s. Step (8) is as follows:

[0198] (8) Plasma etching the intermediate obtained in step (7) using ammonia gas; wherein the flow rate of ammonia gas is 12000 sccm, the temperature of plasma etching is 500° C., the power is 13500 W, the pressure is 1800 mTor, and the time is 300 s.

[0199] Example 4

[0200] The method is basically the same as Example 1, except that in step (8) of Example 4, the power of plasma etching is 10000 W. Step (8) is as follows:

[0201] (8) Plasma etching the intermediate obtained in step (7) using ammonia gas; wherein the flow rate of ammonia gas is 12000 sccm, the temperature of plasma etching is 500° C., the power is 10000 W, the pressure is 1800 mTor, and the time is 200 s.

[0202] Example 5

[0203] The method is basically the same as Example 1, except that the power of the plasma etching is 15000 W. Step (8) of Example 5 is as follows:

[0204] (8) Plasma etching the intermediate obtained in step (7) using ammonia gas; wherein the flow rate of ammonia gas is 12000 sccm, the temperature of plasma etching is 500° C., the power is 15000 W, the pressure is 1800 mTor, and the time is 200 s.

[0205] Example 6

[0206] The method is basically the same as Example 1, except that in step (8) of Example 6, the flow rate of ammonia is 15000 sccm. Step (8) is as follows:

[0207] The flow rate of ammonia is 15000 sccm, the temperature of plasma etching is 500°C, the power is 13500 W, the pressure is 1800 mTor, and the time is 200 s.

[0208] Example 7

[0209] The method is basically the same as Example 1, except that in step (8) of Example 7, the flow rate of ammonia is 10000 sccm. Step (8) is as follows:

[0210] The flow rate of ammonia gas is 10000 sccm, the temperature of plasma etching is 500°C, the power is 13500 W, the pressure is 1800 mTor, and the time is 200 s.

[0211] Comparative Example 1

[0212] The method is basically the same as Example 1, except that in step (8) of Comparative Example 1, ammonia is replaced by nitrous oxide (laughing gas), and other parameters are the same; step (8) is as follows:

[0213] (8) Plasma etching the intermediate obtained in step (7) using nitrous oxide; wherein the flow rate of nitrous oxide is 12000 sccm, the temperature of plasma etching is 500° C., the power is 13500 W, the pressure is 1800 mTor, and the time is 200 s.

[0214] Comparative Example 2

[0215] The method is basically the same as Example 1, except that in step (8) of Comparative Example 3, the gas used for plasma etching is a mixed gas of ammonia and nitrous oxide, and the flow rates of ammonia and nitrous oxide are both 6000 sccm; step (8) is as follows:

[0216] (8) Plasma etching the intermediate obtained in step (7) using a mixed gas of ammonia and nitrous oxide; wherein the flow rate of ammonia is 6000 sccm, the flow rate of nitrous oxide is 6000 sccm, the temperature of plasma etching is 500° C., the power is 13500 W, the pressure is 1800 mTor, and the time is 200 s.

[0217] Comparative Example 3

[0218] The method is basically the same as Example 1, except that in step (4) of Comparative Example 3, the thickness of the Poly layer is 80 nm, and step (8) is omitted, as follows:

[0219] (1) Cleaning and texturing an N-type silicon wafer to form a pyramid-shaped textured surface structure on the surface of the silicon wafer;

[0220] (2) Boron diffusion is performed on the front side of the cleaned and textured silicon wafer to form a P-type region to obtain a PN junction;

[0221] (3) performing alkaline polishing on the back side of the silicon wafer to remove the PN junction that is wound to the back side and edge of the silicon wafer during the boron diffusion on the front side in step (2);

[0222] (4) a tunneling oxide layer and a Poly layer (polycrystalline silicon layer) are sequentially prepared on the back of the alkali-polished silicon wafer, wherein the tunneling oxide layer is a SiO2 layer with a thickness of 1.5 nm; and the thickness of the Poly layer is 80 nm;

[0223] (5) RCA cleaning to remove the tunneling oxide layer and polysilicon layer that are wrapped around the front side of the silicon wafer when the tunneling oxide layer and poly layer are prepared on the back side of the silicon wafer in step (4);

[0224] (6) ALD front deposition of aluminum oxide: an aluminum oxide (Al2O3) film with a thickness of 8 nm is deposited on the PN junction surface of the silicon wafer after RCA cleaning;

[0225] (7) Preparation of a passivation film on the front side: silicon oxynitride, silicon nitride, and silicon oxide are deposited on the surface of the aluminum oxide film layer to a thickness of 75 nm;

[0226] (8) hydrogenating the polysilicon layer on the back of the silicon wafer using ammonia gas; wherein the flow rate of the ammonia gas is 10000 sccm, the time of the hydrogenation treatment is 30 s, the pressure is 1500 mTor, and the power is 14000 W;

[0227] (9) Preparation of anti-reflection structure on the back: silicon oxynitride and silicon nitride are deposited on the surface of the polysilicon layer of the silicon wafer after plasma etching, with a thickness of 85 nm;

[0228] (10) Printing electrode grid lines on the front and back surfaces: Printing electrode grid lines on the surface of the first passivation film layer and the surface of the second passivation film layer respectively, and sintering to prepare a crystalline silicon cell.

[0229] The crystalline silicon cells prepared in each embodiment and comparative example were subjected to performance tests, and IV tests were performed using an electrochemical workstation, and the test conditions were: using an AM1.5 xenon lamp as a simulated light source. The results are shown in Table 1 below, where the photoelectric conversion efficiency, open circuit voltage and short circuit current of comparative example 3 are taken as the benchmark, recorded as 0, the photoelectric conversion efficiency improvement rate of other embodiments and comparative examples = the photoelectric conversion efficiency of other embodiments or comparative examples - the photoelectric conversion efficiency of comparative example 3, the open circuit voltage improvement rate of other embodiments and comparative examples = the open circuit voltage of other embodiments or comparative examples - the open circuit voltage of comparative example 3, and the short circuit current improvement rate of other embodiments and comparative examples = the short circuit current of other embodiments or comparative examples - the short circuit current of comparative example 3.

[0230] Table 1

[0231]

[0232] As can be seen from Table 1, compared with Comparative Example 3 in which the thickness of the Poly layer is directly controlled to 80 nm when preparing the Poly layer, each embodiment first prepares a Poly layer having a thickness greater than this, and then thins the Poly layer by plasma etching. The uniformity of the obtained Poly layer is better than that of Comparative Example 3, so that the photoelectric conversion efficiency of the crystalline silicon battery prepared in each embodiment is greatly improved; while in Comparative Examples 1 and 2, nitrous oxide or a combination of nitrous oxide and ammonia is used, and the Poly layer is thinned by plasma etching, and the photoelectric conversion efficiency of the crystalline silicon battery prepared is not as good as that of the embodiments. Analysis shows that the radius of the oxygen ions ionized by nitrous oxide is larger, which may damage the Poly layer and cause poor uniformity.

[0233] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0234] In the description of the present application, “plurality” means two or more.

[0235] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0236] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a crystalline silicon cell, characterized in that: include: Providing a substrate, a tunneling oxide layer located on the back side of the substrate, and a polysilicon layer located on a side of the tunneling oxide layer away from the substrate; Performing a hydrogenation treatment on the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer; Before performing hydrogen treatment on the polysilicon layer and forming an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer, the method further includes: Ammonia gas is used to perform plasma etching on the polysilicon layer to reduce the thickness of the polysilicon layer.

2. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The anti-reflection structure comprises a first anti-reflection layer and a second anti-reflection layer; The step of performing hydrogen treatment on the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer comprises: Using hydrogen-containing gas to perform a first hydrogenation treatment on the polysilicon layer; forming the first anti-reflection layer on a side of the polysilicon layer away from the tunnel oxide layer; Using hydrogen-containing gas to perform a second hydrogenation treatment on the polysilicon layer; The second anti-reflection layer is formed on a side of the first anti-reflection layer facing away from the polysilicon layer.

3. The method for manufacturing a crystalline silicon cell according to claim 2, characterized in that: The anti-reflection structure further includes a third anti-reflection layer; The step of performing hydrogen treatment on the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer away from the tunnel oxide layer further comprises: Using hydrogen-containing gas to perform a third hydrogenation treatment on the polysilicon layer; The third anti-reflection layer is formed on a side of the second anti-reflection layer facing away from the first anti-reflection layer.

4. The method for manufacturing a crystalline silicon cell according to claim 3, characterized in that: The hydrogen-containing gas includes ammonia.

5. The method for manufacturing a crystalline silicon cell according to claim 4, characterized in that: The first hydroprocessing satisfies at least one of the following characteristics: The flow rate of the ammonia gas is 10000 sccm to 15000 sccm; The first hydrotreatment time is 30s to 50s; The pressure of the first hydrotreatment is 1500mTor to 2000mTor; The power of the first hydrogenation treatment is 14000W to 17000W.

6. The method for manufacturing a crystalline silicon cell according to claim 4, characterized in that: The second hydroprocessing satisfies at least one of the following characteristics: The flow rate of the ammonia gas is 11000 sccm to 16000 sccm; The first hydrotreatment time is 30s to 50s; The pressure of the first hydrotreatment is 1500mTor to 2000mTor; The power of the first hydrogenation treatment is 14000W to 17000W.

7. The method for manufacturing a crystalline silicon cell according to claim 4, characterized in that: The third hydroprocessing satisfies at least one of the following characteristics: The flow rate of the ammonia gas is 11000 sccm to 16000 sccm; The first hydrotreatment time is 40s to 80s; The pressure of the first hydrotreatment is 1500mTor to 2000mTor; The power of the first hydrogenation treatment is 14000W to 17000W.

8. The method for manufacturing a crystalline silicon cell according to claim 3, characterized in that: The first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer each include at least one passivation layer.

9. The method for manufacturing a crystalline silicon cell according to claim 8, characterized in that: The first anti-reflection layer and the second anti-reflection layer each include a passivation layer, and the third anti-reflection layer includes three stacked passivation layers.

10. The method for manufacturing a crystalline silicon cell according to claim 8, characterized in that: In a direction in which the polysilicon layer is away from the tunnel oxide layer, the refractive index of the passivation layer gradually decreases.

11. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The plasma etching satisfies at least one of the following characteristics: The flow rate of the ammonia gas is 10000 sccm to 15000 sccm The temperature of the plasma etching is 450°C to 550°C; The power of the plasma etching is 10000W to 15000W; The pressure of the plasma etching is 1500mTor to 2000mTor; The plasma etching time is 100s to 300s.

12. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The polysilicon layer is thinned to a thickness of 5 nm to 10 nm.

13. A crystalline silicon battery, characterized in that: The crystalline silicon cell is manufactured by the manufacturing method according to any one of claims 1 to 12.

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