Semiconductor device fabrication methods

Abstract

This invention provides a method for fabricating a semiconductor device, comprising: providing a substrate, on which a source structure and a gate structure are formed stacked sequentially from bottom to top, and a first isolation material layer is formed between the source structure and the gate structure; forming a second isolation material layer filling the spaces between adjacent gate structures and located on the gate structures; forming a gate dielectric layer penetrating a portion of the second isolation material layer and the gate structure; forming a channel layer penetrating a portion of the second isolation material layer, the gate structure, and the first isolation material layer and contacting the source structure, with a portion of the gate dielectric layer located between the gate structure and the channel layer; performing a first annealing process on the surface of the channel layer; forming a drain semiconductor layer located within the channel layer and on the second isolation material layer; and performing a second annealing process on the surface of the drain semiconductor layer. This invention enables the channel layer and the drain semiconductor layer to meet corresponding performance requirements, thereby improving the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device. Background Technology

[0002] Semiconductor transistors (such as metal-oxide-semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, and switches. Traditional MOS transistors employ a planar structure. However, with the continuous development of semiconductor integrated circuit technology, MOS transistors have adopted a stacked structure to achieve transistor miniaturization. In the design of stacked structures, several amorphous material layers are typically formed and then annealed together to crystallize them into crystalline layers. However, annealing several amorphous material layers together can make it difficult to ensure that the different crystalline material layers meet the corresponding performance requirements, thus affecting the reliability of the device. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating semiconductor devices, such that the channel layer and drain semiconductor layer meet the corresponding performance requirements, thereby improving the reliability of the semiconductor devices.

[0004] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:

[0005] A substrate is provided on which source structures and gate structures are formed in sequence from bottom to top, the source structures extending along a first direction, the gate structures being arranged at intervals from each other in the first direction, and a first isolation material layer being formed between the source structures and the gate structures.

[0006] A second isolation material layer is formed, filling the space between adjacent gate structures and located on the gate structures;

[0007] A gate dielectric layer is formed that penetrates the second isolation material layer and the gate structure;

[0008] A channel layer is formed that penetrates a portion of the second isolation material layer, the gate structure, and the first isolation material layer and is in contact with the source structure; a portion of the gate dielectric layer is located between the gate structure and the channel layer.

[0009] A first annealing process is performed on the surface of the channel layer;

[0010] A drain semiconductor layer is formed within the channel layer and on the second isolation material layer; and,

[0011] A second annealing process is performed on the surface of the drain semiconductor layer.

[0012] Optionally, the first annealing process is a flash annealing process, and the second annealing process is a laser annealing process.

[0013] Optionally, the annealing time of the first annealing process is 0.21ms to 4ms, and the annealing temperature of the first annealing process is 600℃ to 1400℃.

[0014] Optionally, the laser light source used in the second annealing process is a continuous light source or a pulsed light source.

[0015] Optionally, the channel layer and the drain semiconductor layer have a lattice structure.

[0016] Optionally, the channel layer and the drain semiconductor layer have different grain sizes.

[0017] Optionally, the channel layer and the drain semiconductor layer are made of the same material, but the doping concentrations of the channel layer and the drain semiconductor layer are different.

[0018] Optionally, after performing the second annealing process, the process further includes:

[0019] The drain semiconductor layer on the second isolation material layer is etched away to retain the drain semiconductor layer within the channel layer;

[0020] A third annealing process is performed on the surface of the etched drain semiconductor layer.

[0021] Optionally, the third annealing process includes flash annealing, laser annealing, or furnace tube annealing.

[0022] Optionally, after performing the third annealing process, the process further includes:

[0023] A drain metal layer is formed on the drain semiconductor layer;

[0024] The drain sidewall is formed on the sidewall of the drain metal layer.

[0025] The method for fabricating a semiconductor device provided by this invention includes: providing a substrate on which source structures and gate structures are formed in a bottom-to-top sequence, the source structures extending along a first direction, and the gate structures spaced apart from each other in the first direction; forming a first isolation material layer between the source structures and the gate structures; forming a second isolation material layer filling the spaces between adjacent gate structures and located on the gate structures; forming a gate dielectric layer penetrating a portion of the second isolation material layer and the gate structures; forming a channel layer penetrating a portion of the second isolation material layer, the gate structures, and the first isolation material layer and contacting the source structures, with a portion of the gate dielectric layer located between the gate structures and the channel layer; performing a first annealing process on the surface of the channel layer; forming a drain semiconductor layer located within the channel layer and on the second isolation material layer; and performing a second annealing process on the surface of the drain semiconductor layer. This invention performs a first annealing process after forming the channel layer and a second annealing process after forming the drain semiconductor layer, annealing the channel layer and the drain semiconductor layer separately, enabling the channel layer and the drain semiconductor layer to meet corresponding performance requirements, thereby improving the reliability of the semiconductor device. Attached Figure Description

[0026] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0027] Figures 2 to 17 This is a cross-sectional schematic diagram of the corresponding steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0028] The attached figures are labeled as follows:

[0029] 10-Substrate; 20-Dielectric layer; 22-Electrical connector; 30-Source structure; 31-First source barrier layer; 32-Source metal layer; 33-Second source barrier layer; 34-Source semiconductor layer; 41-First isolation material layer; 42-Second isolation material layer; 43-Third isolation material layer; 50-Gate structure; 51-Gate barrier layer; 52-Gate metal layer; 54-Through hole; 60-Gate dielectric layer; 62-Sacrificial layer; 70-Channel layer; 80-Drain semiconductor layer; 81-First drain metal layer; 82-Second drain metal layer; 90-Sidewall; 110-First mask layer; 120-Second mask layer. Detailed Implementation

[0030] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0031] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] Figure 1 A flowchart illustrating the method for fabricating the semiconductor device provided by this invention. Please refer to... Figure 1 This invention provides a method for fabricating a semiconductor device, comprising:

[0033] Step S1: Provide a substrate on which a source structure and a gate structure are formed in sequence from bottom to top. The source structure extends along a first direction, and the gate structures are arranged at intervals in the first direction. A first isolation material layer is formed between the source structure and the gate structure.

[0034] Step S2: Form a second isolation material layer that fills the space between adjacent gate structures and is located on the gate structure;

[0035] Step S3: Form the second isolation material layer and gate structure through the gate dielectric layer;

[0036] Step S4: A channel layer is formed that penetrates part of the second isolation material layer, the gate structure and the first isolation material layer and is in contact with the source structure, and part of the gate dielectric layer is located between the gate structure and the channel layer;

[0037] Step S5: Perform a first annealing process on the surface of the channel layer;

[0038] Step S6: Form a drain semiconductor layer located inside the channel layer and on the second isolation material layer;

[0039] Step S7: Perform a second annealing process on the surface of the drain semiconductor layer.

[0040] Figures 2 to 17 This is a cross-sectional schematic diagram of the corresponding steps in the fabrication method of the semiconductor device provided in this embodiment. The following is in conjunction with... Figures 2 to 17 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0041] Execution step S1: Please refer to Figure 2A substrate 10 is provided, which may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully depleted silicon-on-insulator substrate, or is not limited thereto; and other components (e.g., transistors) and / or circuits may be formed on the substrate 10. Please refer to [reference needed]. Figure 3 A source structure 30 and a gate structure 50 are formed on the substrate 10, stacked sequentially from bottom to top. The source structures 30 extend along a first direction (D1), and the gate structures 50 are spaced apart from each other along the first direction and extend along a second direction (D2). A first isolation material layer 41 is formed between the source structures 30 and the gate structures 50. Specifically, the steps for forming the gate structure include: Please refer to... Figure 2 A source structure 30, a first isolation material layer 41, a gate barrier layer 51, a gate metal layer 52, and a first mask layer 110 are sequentially formed on the substrate 10, with the source structure 30 extending along a first direction; please refer to Figure 3 The first mask layer 110, the gate metal layer 52, the gate barrier layer 51 and the first isolation material layer 41 are etched sequentially to expose the source structure 30. The remaining gate metal layer 52 and the gate barrier layer 51 form a plurality of gate structures 50. The gate structures 50 are arranged at intervals in the first direction. The remaining first isolation material layer 41 is located between the gate structure 50 and the source structure 30. Then the first mask layer 110 is removed.

[0042] Furthermore, a dielectric layer 20 is formed on the substrate 10. The dielectric layer 20 can be a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it can be a single material layer, such as an oxide layer or a nitride layer, and is not limited thereto. An electrical connector 22 is formed in the dielectric layer 20. The electrical connector 22 penetrates the dielectric layer 20 and contacts the substrate 10 and the source structure 30. The electrical connector 22 is formed by forming a connection hole in the dielectric layer 20, forming a barrier layer to cover the inner wall of the connection hole, and forming a metal material to fill the connection hole to form the electrical connector 22.

[0043] In this embodiment, the source structure 30 includes a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33, and a source semiconductor layer 34 stacked sequentially from bottom to top. The materials of the first source barrier layer 31 and the second source barrier layer 33 may include one or more combinations of RuO2, ReO3, CdO, IrO2, CrO2, SnO2, InO, GeO, ZnO, TiN, TaN, WN, and TiSiN, respectively. The material of the source metal layer 32 may include one or more combinations of Ru, Rh, Ir, Pd, Pt, Co, Pd, Al, Ti, Ta, W, Nb, Mo, Cu, Ni, and Pb. The material of the source semiconductor layer 34 may include one or more combinations of Si, SiC, SiGe, III-V compound semiconductor materials, oxide semiconductor materials, nitride semiconductor materials, and oxynitride semiconductor materials, and is not limited to the above materials.

[0044] In this embodiment, the gate structure 50 includes a gate barrier layer 51 and a gate metal layer 52 stacked sequentially from bottom to top. The material of the gate barrier layer 51 may include one or more combinations of RuO2, ReO3, CdO, IrO2, CrO2, SnO2, InO, GeO, ZnO, TiN, TaN, WN, and TiSiN. The material of the gate metal layer 52 may include one or more combinations of Ru, Rh, Ir, Pd, Pt, Co, Pd, Al, Ti, Ta, W, Nb, Mo, Cu, Ni, and Pb, and is not limited to the above materials.

[0045] In this embodiment, the material of the first insulating material layer 41 may include one of the following: low-k dielectric material, high-k dielectric material, oxide, nitride, oxynitride, and silicon oxynitride. The low-k dielectric material may be a material with a dielectric constant lower than that of silicon oxide. The low-k dielectric material may include flowable oxide (FOX), TOSZ, undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), and plasma-enhanced tetraethyl orthosilicate (PETEOS). One or more of fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide; the high-k dielectric material can be a material with a higher dielectric constant than silicon oxide, and the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate, and is not limited to the above materials.

[0046] Execution step S2: Please refer to Figure 4A second isolation material layer 42 is formed, filling the spaces between adjacent gate structures 50 and located on the gate structure 50. The second isolation material layer 42 can be a stacked structure. The material of the second isolation material layer 42 can include one of the following: low-k dielectric material, oxide, nitride, oxynitride, and silicon carbide oxynitride. The low-k dielectric material can be a material with a dielectric constant lower than that of silicon oxide. The low-k dielectric material can include one or more of the following: flowable oxide (FOX), TOSZ, undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide, and is not limited to the above materials.

[0047] Step S3: The steps of forming the second isolation material layer and the gate structure through the gate dielectric layer include: Please refer to... Figure 5 The second isolation material layer 42 and the gate structure 50 are etched to form a via 54 exposing the first isolation material layer 41; please refer to Figure 6 The gate dielectric layer 60 conformally covers the bottom surface and sidewalls of the via 54 and the top surface of the second isolation material layer 42. After forming the gate dielectric layer 60, a sacrificial layer 62 is also formed to conformally cover the gate dielectric layer 60. Please refer to [reference needed]. Figure 7 The bottom surface of the via 54 is etched to expose a portion of the sacrificial layer 62, a portion of the gate dielectric layer 60, and a portion of the first isolation material layer 41 to expose a portion of the surface of the source structure 30. The bottom surface of the via 54 extends to the surface of the source structure 30. Simultaneously, the gate dielectric layer 60 and the sacrificial layer 62 on the top surface of the second isolation material layer 42 are etched away, so that the gate dielectric layer 60 and the sacrificial layer 62 penetrate a portion of the second isolation material layer 42 and the gate structure 50. The gate dielectric layer 60 covers a portion of the surface of the first isolation material layer 41, and the portion of the gate dielectric layer 60 is located between the sacrificial layer 62 and the gate structure 50.

[0048] In this embodiment, the gate dielectric layer 60 may be made of silicon oxide and silicon nitride, or may include silicon oxide, silicon nitride, doped ions, and metal silicides, or may include ferroelectric materials or high-k dielectric materials, and is not limited to the above materials. The sacrificial layer 62 may be made of polysilicon, wherein the polysilicon contains doped ions, and is not limited to the above materials.

[0049] Execution step S4: Please refer to Figure 8A channel layer 70 is formed, penetrating a portion of the second isolation material layer 42, the gate structure 50, and the first isolation material layer 41, and contacting the source structure 30. A portion of the gate dielectric layer 60 and the sacrificial layer 62 are located between the gate structure 50 and the channel layer 70. Specifically, the channel layer 70 covers the sidewalls and bottom surface of the via 54 and the top surface of the second isolation material layer 42. In this embodiment, the channel layer 70 formed in this step is amorphous and has an irregular lattice structure. The material of the channel layer 70 may include amorphous semiconductor materials, such as silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, etc., but is not limited thereto.

[0050] Execution step S5: Please refer to Figure 9 A first annealing process is performed on the surface of the channel layer 70. The first annealing process is preferably flash annealing, which is characterized by large area, deep annealing depth, and fast annealing speed. The annealing time of the first annealing process can be 0.21 ms to 4 ms, and the annealing temperature can be 600℃ to 1400℃, but is not limited to these ranges. After performing the first annealing process, the amorphous channel layer 70 crystallizes to form a crystalline channel layer 70, giving the channel layer 70 a regular crystal lattice structure.

[0051] Further, please refer to Figure 10 After performing a first annealing process on the surface of the channel layer 70, the process further includes: forming a third isolation material layer 43 within the channel layer 70; specifically, the third isolation material layer 43 fills a portion of the depth of the via 54. In this embodiment, the material of the third isolation material layer 43 may include, but is not limited to, a low-k dielectric material, an oxide, a nitride, an oxynitride, and silicon oxycarbide. Subsequently, the channel layer 70 on the top surface of the second isolation material layer 42 is etched away.

[0052] Execution step S6: Please refer to Figure 11 A drain semiconductor layer 80 is formed within the channel layer 70 and on the second isolation material layer 42. Specifically, the drain semiconductor layer 80 fills the remaining depth of the via 54 and is located on the third isolation material layer 43. In this embodiment, the drain semiconductor layer 80 formed in this step is amorphous and has an irregular lattice structure. The material of the drain semiconductor layer 80 may include amorphous semiconductor materials, such as silicon, germanium, germanium silicon, silicon carbide, gallium arsenide, etc., but is not limited thereto.

[0053] Execution step S7: Please refer to Figure 12A second annealing process is performed on the surface of the drain semiconductor layer 80. The second annealing process is preferably laser annealing, which has the characteristic of point-to-point penetration. The laser light source used in the second annealing process is a continuous light source or a pulsed light source. After performing the second annealing process, the amorphous drain semiconductor layer 80 crystallizes to form a crystalline drain semiconductor layer 80, giving the drain semiconductor layer 80 a regular crystal lattice structure. In this embodiment, the channel layer 70 and the drain semiconductor layer 80 have different grain sizes; the grain size of the channel layer 70 can be smaller than the grain size of the drain semiconductor layer 80. The channel layer 70 and the drain semiconductor layer 80 are made of the same material, but their doping concentrations are different.

[0054] Furthermore, after performing the second annealing process, it also includes: Please refer to... Figure 13 The drain semiconductor layer on the second isolation material layer 42 is etched away to retain the drain semiconductor layer 80 within the channel layer 70. After etching, the surface of the drain semiconductor layer 80 has etching damage. Please refer to [reference needed]. Figure 14 A third annealing process is performed on the surface of the etched drain semiconductor layer 80 to repair the etching damage on the surface of the drain semiconductor layer 80. The third annealing process includes flash annealing, laser annealing, or furnace tube annealing, and is not limited to these.

[0055] Furthermore, after performing the third annealing process, the process also includes: forming a drain metal layer on the drain semiconductor layer, please refer to [reference needed]. Figure 15 A first drain metal layer 81, a second drain metal layer 82, and a second mask layer 120 are sequentially formed to cover the second isolation material layer 42 and the drain semiconductor layer 80; please refer to Figure 16 The second mask layer 120, the second drain metal layer 82, the first drain metal layer 81, and a portion of the second isolation material layer 42 are sequentially etched to form several openings (not shown in the figure). The bottom of the openings extends into the second isolation material layer 42. The remaining second drain metal layer 82 and first drain metal layer 81 are in contact with the channel layer 70 and the drain semiconductor layer 80. The remaining second drain metal layer 82, first drain metal layer 81, and drain semiconductor layer 80 constitute the drain structure. Then, the second mask layer 120 is removed. Further, please refer to... Figure 17The drain sidewall 90 is formed on the sidewall of the drain metal layer (the second drain metal layer 82 and the first drain metal layer 81). In this embodiment, the material of the first drain metal layer 81 may include one or more combinations of RuO2, ReO3, CdO, IrO2, CrO2, SnO2, InO, GeO, ZnO, TiN, TaN, WN, and TiSiN. The material of the second drain metal layer 82 may include one or more combinations of Ru, Rh, Ir, Pd, Pt, Co, Pd, Al, Ti, Ta, W, Nb, Mo, Cu, Ni, and Pb. The material of the drain sidewall 90 may include one of low-k dielectric materials, high-k dielectric materials, oxides, nitrides, oxynitrides, and silicon carbide oxynitride, and is not limited thereto.

[0056] In this embodiment, a first annealing process is performed after the channel layer 70 is formed and a second annealing process is performed after the drain semiconductor layer 80 is formed. Annealing the channel layer 70 and the drain semiconductor layer 80 respectively enables the channel layer 70 and the drain semiconductor layer 80 to meet the corresponding performance requirements (e.g., different doping concentrations and different grain sizes) to improve the reliability of the semiconductor device.

[0057] In summary, the method for fabricating a semiconductor device provided by this invention includes: providing a substrate on which source structures and gate structures are formed in a bottom-to-top sequence, the source structures extending along a first direction, and the gate structures spaced apart from each other in the first direction, with a first isolation material layer formed between the source structures and the gate structures; forming a second isolation material layer filling the spaces between adjacent gate structures and located on the gate structures; forming a gate dielectric layer penetrating a portion of the second isolation material layer and the gate structures; forming a channel layer penetrating a portion of the second isolation material layer, the gate structures, and the first isolation material layer and contacting the source structures, with a portion of the gate dielectric layer located between the gate structures and the channel layer; performing a first annealing process on the surface of the channel layer; forming a drain semiconductor layer located within the channel layer and on the second isolation material layer; and performing a second annealing process on the surface of the drain semiconductor layer. This invention performs a first annealing process after forming the channel layer and a second annealing process after forming the drain semiconductor layer, annealing the channel layer and the drain semiconductor layer separately, enabling the channel layer and the drain semiconductor layer to meet corresponding performance requirements, thereby improving the reliability of the semiconductor device.

[0058] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which source structures and gate structures are formed in sequence from bottom to top, the source structures extending along a first direction, the gate structures being arranged at intervals from each other in the first direction, and a first isolation material layer being formed between the source structures and the gate structures. A second isolation material layer is formed, filling the space between adjacent gate structures and located on the gate structures; A gate dielectric layer is formed that penetrates the second isolation material layer and the gate structure; A channel layer is formed that penetrates a portion of the second isolation material layer, the gate structure, and the first isolation material layer and is in contact with the source structure; a portion of the gate dielectric layer is located between the gate structure and the channel layer. A first annealing process is performed on the surface of the channel layer; A drain semiconductor layer is formed within the channel layer and on the second isolation material layer; as well as, A second annealing process is performed on the surface of the drain semiconductor layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The first annealing process is a flash annealing process, and the second annealing process is a laser annealing process.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The annealing time of the first annealing process is 0.21ms to 4ms, and the annealing temperature of the first annealing process is 600℃ to 1400℃.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The laser light source used in the second annealing process is a continuous light source or a pulsed light source.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The channel layer and the drain semiconductor layer have a crystal lattice structure.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The channel layer and the drain semiconductor layer have different grain sizes.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The channel layer and the drain semiconductor layer are made of the same material, but the doping concentrations of the channel layer and the drain semiconductor layer are different.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After performing the second annealing process, the process further includes: The drain semiconductor layer on the second isolation material layer is etched away to retain the drain semiconductor layer within the channel layer; A third annealing process is performed on the surface of the etched drain semiconductor layer.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The third annealing process includes flash annealing, laser annealing, or furnace tube annealing.

10. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After performing the third annealing process, the process further includes: A drain metal layer is formed on the drain semiconductor layer; The drain sidewall is formed on the sidewall of the drain metal layer.

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