Integrated circuit packaging structure and integrated circuit packaging method

Abstract

The present invention discloses an integrated circuit packaging structure and an integrated circuit packaging method, wherein the packaging structure comprises a positive chip, a flip chip and a connecting plate; the connecting plate is placed between the positive chip and the flip chip; the connecting plate comprises a substrate, an electrical contact portion and a through-connection portion located on the substrate; the types of the electrical contact portion are divided into a signal contact portion and a ground contact portion; the through-connection portion passes through the substrate and connects the electrical contact portions located on the front and back sides of the substrate; the connecting plate further comprises a shielding net and a first insulating layer; the front and back surfaces of the substrate have ion permeation layers, and the shielding net contacts the ion permeation layers; the signal contact portion is isolated on the outside of the shielding net by the first insulating layer; the ground contact portion comprises a main body portion placed on the outside of the shielding net, and a lead-through portion that passes through the shielding net and directly contacts the silicon body of the substrate. The present invention can enhance the shielding effect of electromagnetic interference between chips on different surfaces, and can also suppress electromagnetic interference between chips on the same surface.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to an integrated circuit packaging structure and an integrated circuit packaging method. Background Art

[0002] The three-dimensional packaging of integrated circuits is an advanced packaging technology that achieves higher integration and better performance by vertically stacking and interconnecting multiple chips or circuit layers. This packaging method uses technologies such as through-silicon vias to create direct electrical connections between silicon wafers, allowing complex integrated circuit designs to achieve higher functional density and faster signal transmission speeds in a smaller space, while also providing better thermal management and electromagnetic compatibility. It is widely used in high-performance computing, high-speed communications, and advanced sensors. The development of three-dimensional packaging technology has not only promoted the innovation of semiconductor processes, but also opened up new possibilities for the design and application of electronic devices.

[0003] In the three-dimensional packaging of integrated circuits, crosstalk between chips is a difficult problem. For chips that are more sensitive to electromagnetic interference, effective measures need to be taken to suppress the mutual interference between chips and between signal transmission paths. In the prior art, patent CN 103296008 A provides a method of reducing the near-field coupling between chips by setting multiple layers of metal planes and at least one layer of the metal plane is etched with a periodic EBG structure, which has a good shielding effect. This structure is not only more complex and difficult to process, but also cannot effectively suppress the signal crosstalk between signal transmission paths. Summary of the invention

[0004] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides an integrated circuit packaging structure and an integrated circuit packaging method that can simultaneously suppress electromagnetic interference between chips on different surfaces and electromagnetic interference between chips on the same surface.

[0005] Technical solution: To achieve the above-mentioned purpose, the packaging structure of the integrated circuit of the present invention comprises:

[0006] Formal chip;

[0007] Flip chip;

[0008] A connecting plate, which is placed between the front-mounted chip and the flip-chip;

[0009] The connecting plate comprises a base plate and located on the base plate:

[0010] Electrical contacts, which are divided into signal contacts and ground contacts;

[0011] A through-connecting portion, which passes through the substrate and connects the electrical contact portions located on the front and back sides of the substrate;

[0012] Shielding net;

[0013] a first insulating layer;

[0014] The front and back surfaces of the substrate are provided with ion permeation layers, and the shielding net is in contact with the ion permeation layers;

[0015] The signal contact portion is isolated on the outside of the shielding mesh by the first insulating layer;

[0016] The ground contact portion has:

[0017] a main body disposed outside the shielding net, and

[0018] A lead-through portion passes through the shielding mesh and directly contacts the silicon body of the substrate.

[0019] Furthermore, the connecting plate also has a vertical shielding portion, and the vertical shielding portion includes:

[0020] a shielding column extending along a thickness direction of the substrate; and

[0021] A shielding bar extending continuously in the length direction or the width direction of the substrate and extending inwardly to the inside of the substrate; a plurality of shielding columns extending from one side of the shielding bar to the other side of the substrate;

[0022] The through-connecting portions are arranged in rows, at least two groups of the vertical shielding portions are arranged between two adjacent rows of the through-connecting portions, and the shielding bars of two adjacent groups of the vertical shielding portions are located on different sides of the substrate.

[0023] Furthermore, the shielding strip extends to half the thickness of the substrate.

[0024] Furthermore, the vertical shielding portion and the shielding net are both made of copper.

[0025] Furthermore, the shielding net has a second solder pad, and the second solder pad is connected to the isolation unit through a second solder ball.

[0026] An integrated circuit packaging method, which is used to form the above-mentioned packaging structure, comprises:

[0027] Obtaining a substrate, and etching a through hole on the substrate;

[0028] The front and back surfaces of the substrate are processed by ion implantation to form an ion permeation layer; and the inner wall of the through hole is processed by chemical vapor deposition to form a second insulating layer;

[0029] Filling the through hole with a metal filling process to form a through-connection portion;

[0030] Performing metal deposition operation on the substrate to form a grid-like shielding net on the outer surface of the ion permeation layer;

[0031] forming a first insulating layer covering the shielding mesh and the outer surface of the ion permeable layer by chemical vapor deposition;

[0032] Etching blind holes on the front and back sides of the substrate, wherein the blind holes penetrate the first insulating layer and the ion permeation layer, and the blind holes are located in the mesh holes of the shielding net when viewed in a direction perpendicular to the front side;

[0033] Filling the blind hole with a metal filling process to form a lead-in portion, and continuing to form a main body portion and a signal contact portion by depositing a metal layer;

[0034] Connect the face-up chip and the flip-chip to corresponding electrical contacts through solder balls.

[0035] Beneficial effects: The integrated circuit packaging structure and integrated circuit packaging method of the present invention have the following beneficial effects:

[0036] (1) By providing an ion permeation layer on the substrate, and making the signal contact part completely isolated from the substrate by the shielding net, and making the ground contact part semi-isolated by the shielding net and in direct contact with the silicon body, it can be achieved that: on the one hand, the ion permeation layer is formed by ion implantation, and has good conductivity. Its contact with the shielding net can effectively expand the ability to shield electromagnetic waves, especially prevent low-frequency electromagnetic waves from passing through, and can more effectively shield the signal crosstalk between the front-mounted chip and the flip-chip on the front and back sides of the substrate; on the other hand, since the lead-in part of the ground contact part is in direct contact with the silicon body, the electromagnetic coupling relationship between the electrical contact part, the first insulating layer and the external medium in the prior art can be changed. Since the ground contact part is directly connected to the silicon body and the ground contact part and the signal contact part are staggered, unnecessary electromagnetic coupling relationships can be effectively reduced, thereby reducing crosstalk between electrical contacts on the same surface, and suppressing mutual interference between electrical contacts corresponding to multiple front-mounted chips and suppressing mutual interference between electrical contacts corresponding to multiple flip-chips. That is, the packaging structure of the present invention can simultaneously enhance the shielding effect of electromagnetic interference between chips on different sides, and can also suppress electromagnetic interference between chips on the same side, and is suitable for chip packaging with high electromagnetic interference sensitivity.

[0037] (2) The provision of the ion permeation layer can make the mesh of the shielding net appropriately larger, reduce the manufacturing difficulty, and facilitate the lead-in portion to pass through the mesh of the shielding net to establish the connection between the ground contact portion and the silicon body.

[0038] (3) The structural design and layout of the vertical shielding parts ensure the basic strength of the substrate. At the same time, a three-dimensional shielding structure consisting of shielding strips, shielding columns and shielding nets is formed between two adjacent rows of vertical shielding parts, which can effectively shield the electromagnetic interference between the penetrating connecting parts inside the substrate.

[0039] (4) By presetting the second pad on the shielding net, a shielding unit connected to the shielding net can be set as needed to block the electromagnetic interference generated between adjacent chips on the same surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the overall structure of the packaging structure of an integrated circuit;

[0041] Figure 2 is a cross-sectional view of the connecting plate of the first embodiment;

[0042] Figure 3 for Figure 2 The composition diagram of the middle BB section;

[0043] Figure 4 for Figure 2 The composition diagram of the CC section;

[0044] Figure 5 It is a structural diagram of a connecting plate in a preferred embodiment;

[0045] Figure 6 It is a cross-sectional view of the connecting plate of the second embodiment.

[0046] In the figure: 1-upright chip; 2-flip chip; 3-connecting board; 301-substrate; 301a-ion permeation layer; 301b-silicon body; 302-first electrical contact portion; 303-second electrical contact portion; 304-through connection portion; 305-shielding mesh; 305b-second solder pad; 306-second insulating layer; 307-first insulating layer; 308-vertical shielding portion; 308a-shielding column; 308b-shielding bar; 309-second solder ball; 310-isolation unit; 3a-signal contact portion; 3b-ground contact portion; a-main body; b-through portion. DETAILED DESCRIPTION

[0047] The present invention will be further described below in conjunction with the accompanying drawings.

[0048] Embodiment 1

[0049] like Figure 1 The packaging structure of the integrated circuit shown includes a front-mounted chip 1, a flip-chip 2 and a connecting board 3; wherein the connecting board 3 is placed between the front-mounted chip 1 and the flip-chip 2, and the front-mounted chip 1 and the flip-chip 2 are respectively located on the back and front sides of the connecting board 3.

[0050] like Figure 2 As shown, the connection board 3 has a substrate 301 and an electrical contact portion, a through-connection portion 304, a shielding mesh 305 and a first insulating layer 307 located on the substrate 301;

[0051] The types of electrical contacts are divided into signal contacts 3a and ground contacts 3b; and the electrical contacts placed on the front and back sides of the substrate 301 are respectively called first electrical contacts 302 and second electrical contacts 303, the first electrical contacts 302 are placed on the front side of the connecting board 3, and are used to connect the flip chip 2; the second electrical contacts 303 are placed on the back side of the connecting board 3, and are used to connect the upright chip 1; the upright chip 1 and the flip chip 2 are respectively connected to the corresponding electrical contacts through the first solder pad and the first solder ball;

[0052] The through-connection part 304 passes through the substrate 301 and connects the electrical contact parts located on the front and back sides of the substrate 301; that is, the substrate 301 has a hole for the through-connection part 304 to pass through, and a second insulating layer 306 is provided between the through-connection part 304 and the hole wall;

[0053] The connecting plate 3 has the shielding net 305 on both the front and back sides; the shielding net 305 is used to prevent the front-mounted chip 1 and the flip-chip 2 from generating electromagnetic interference through the substrate 301; the front and back surfaces of the substrate 301 have ion permeation layers 301a, and the shielding net 305 is in contact with the ion permeation layers 301a.

[0054] The signal contact portion 3a is isolated from the outside of the shielding net 305 by the first insulating layer 307; the ground contact portion 3b has a main body portion a placed outside the shielding net 305, and a lead portion b passing through the shielding net 305 and directly contacting the silicon body 301b of the substrate 301. That is, the through-connection portion 304 passes through the shielding net 305 and connects the corresponding electrical contact portion, and the through-connection portion 304 does not contact the shielding net 305; the lead portion b not only passes through the shielding net 305, but also passes through the ion permeation layer 301a to contact the silicon body 301b that has not been subjected to the permeation treatment. The ground contact portion 3b is isolated from the shielding net 305 by the first insulating layer 307. In the above structure, the signal contact portion 3a and the ground contact portion 3b are arranged alternately, that is, there is a signal contact portion 3a between two adjacent ground contact portions 3b, and there is a ground contact portion 3b between two adjacent signal contact portions 3a.

[0055] By adopting the above structure, by arranging an ion permeation layer 301a on the substrate 301, and making the signal contact part 3a completely isolated from the substrate 301 by the shielding net 305, and making the ground contact part 3b semi-isolated by the shielding net 305 and directly contacting with the silicon body 301b, it can be achieved that: on the one hand, the ion permeation layer 301a is formed by ion implantation, and has good conductivity. It contacts with the shielding net 305, and the contact resistance between the two can be ignored, which can effectively expand the ability to shield electromagnetic waves, especially prevent low-frequency electromagnetic waves from passing through, and more effectively shield the signal crosstalk between the front-mounted chip 1 and the flip-chip 2 on the front and back sides of the substrate 301; secondly, On the one hand, since the lead-in portion b of the ground contact portion 3b is in direct contact with the silicon body 301b, the electromagnetic coupling relationship between the electrical contact portion, the first insulating layer 307 and the external medium (such as air or the first insulating layer 307 and the outer medium) in the prior art can be changed. Since the ground contact portion 3b is directly connected to the silicon body 301b, and the ground contact portion 3b and the signal contact portion 3a are arranged in an interlaced manner, unnecessary electromagnetic coupling relationships can be effectively reduced, thereby reducing the crosstalk between the electrical contacts on the same side (front or back), and achieving the suppression of mutual interference between the electrical contacts corresponding to multiple front-mounted chips 1 and the suppression of mutual interference between the electrical contacts corresponding to multiple flip-chip chips 2. On the third hand, the provision of the ion permeation layer 301a can make the mesh of the shielding net 305 appropriately larger, reduce the difficulty of manufacturing, and facilitate the lead-in portion b to pass through the mesh of the shielding net 305.

[0056] The above-mentioned principle of reducing the interference between the electrical contact parts on the same surface is as follows: for adjacent signal contact parts 3a, the coupling interference between the signal contact parts 3a is caused by mutual inductance and reciprocal admittance. By making the ground contact part 3b adjacent to the signal contact part 3a contact with the silicon body 301b, the electromagnetic coupling between the signal contact part 3a and the adjacent ground contact part 3b can be increased, and the reciprocal admittance between the signal contact part 3a and the other signal contact parts 3a and the ground contact part 3b is reduced. Therefore, the electromagnetic field is more concentrated inside the contact group formed by the signal contact part 3a and the two ground contact parts 3b adjacent to it, thereby suppressing unnecessary electromagnetic coupling between different contact groups and achieving the purpose of suppressing mutual interference between the signal contact parts 3a.

[0057] It can be seen that the above structure can enhance the shielding effect of electromagnetic interference between chips on different sides, and can also suppress electromagnetic interference between chips on the same side, and is suitable for chip packaging with high electromagnetic interference sensitivity.

[0058] A plurality of lead-through portions b are distributed in the extension direction of the main body portion a, so that effective connection between the ground contact portion 3b and the silicon body 301b can be achieved, and unnecessary electromagnetic coupling relationship can be effectively eliminated.

[0059] During specific manufacturing, after performing heavy infiltration operations on both sides of the substrate 301 to form the ion permeation layer 301a, the shielding mesh 305 and the first insulating layer 307, a blind hole passing through the ion permeation layer 301a is etched on the substrate 301, and then the blind hole is filled with copper metal to form a through-hole b, and metal deposition is performed on the basis of the through-hole b to form the main body.

[0060] Preferably, if Figure 2 As shown, the connecting plate 3 also has a vertical shielding portion 308, which extends along the thickness direction of the substrate 301, and an insulating layer is provided between the vertical shielding portion 308 and the substrate 301; the vertical shielding portion 308 includes a shielding column 308a and a shielding strip 308b; the shielding column 308a extends along the thickness direction of the substrate 301; the shielding strip 308b extends continuously in the length direction or the width direction of the substrate 301, and extends inward to the interior of the substrate 301; a plurality of the shielding columns 308a extend from the inner side of the shielding strip 308b to the other side of the substrate 301.

[0061] The through-connecting portions 304 are arranged in rows, and at least two groups of the vertical shielding portions 308 are arranged between two adjacent rows of the through-connecting portions 304, and the shielding strips 308b of the two adjacent groups of the vertical shielding portions 308 are located on different sides of the substrate 301, that is, of the two shielding strips 308b corresponding to the two adjacent groups of the vertical shielding portions 308, one shielding strip 308b is located on the front side of the substrate 301, and the other shielding strip 308b is located on the reverse side of the substrate 301, as shown in FIG. Figure 3 and Figure 4 shown.

[0062] In this embodiment, the shielding strip 308b extends to half the thickness of the substrate 301, and three groups of vertical shielding portions 308 (such as Figure 1 As shown in the figure, in this way, there is no need to cut through the substrate 301, and each shielding strip 308b plays a role in lateral interception of electromagnetic waves, and multiple groups of shielding posts 308a and shielding strips 308b of vertical shielding parts 308 form a multiple interception network. The shielding strips 308b and shielding posts 308a of each vertical shielding part 308 are respectively connected to the shielding net 305 on the corresponding side. A three-dimensional shielding structure consisting of shielding strips 308b, shielding posts 308a and shielding net 305 is formed between two adjacent rows of vertical shielding parts 308, which can effectively shield the electromagnetic interference between the through-connecting parts 304 inside the substrate 301.

[0063] The vertical shielding portion 308 and the shielding net 305 are both made of copper.

[0064] like Figure 5As shown, the shielding net 305 has a second pad 305b, and the second pad 305b is connected to the isolation unit 310 through a second solder ball 309. The isolation unit 310 is placed between two adjacent face-up chips 1, or between two adjacent flip-chips 2, and the isolation unit 310 can isolate the radio electromagnetic waves generated between adjacent chips to prevent signal crosstalk.

[0065] An integrated circuit packaging method is used to form the above-mentioned packaging structure, and the method comprises the following steps S1-S8:

[0066] Step S1, obtaining a substrate 301, and etching a through hole on the substrate 301;

[0067] Step S2, treating the front and back surfaces of the substrate 301 by ion implantation to form an ion permeation layer 301a; and treating the inner wall of the through hole by chemical vapor deposition to form a second insulating layer 306;

[0068] Step S3, filling the through hole with a metal filling process to form a through connection portion 304;

[0069] Step S4, performing metal deposition on the substrate 301, forming a grid-shaped shielding net 305 on the outer surface of the ion permeable layer 301a; the end of the penetrating connecting portion 304 is higher than the shielding net 305;

[0070] Step S5, forming a first insulating layer 307 covering the outer surface of the shielding mesh 305 and the ion permeation layer 301a by chemical vapor deposition; the outer end surface of the first insulating layer 307 is flush with the end of the through-connection portion 304;

[0071] Step S6, etching blind holes on the front and back sides of the substrate 301, wherein the blind holes penetrate the first insulating layer 307 and the ion permeation layer 301a, and the blind holes are located in the mesh of the shielding net 305 when viewed in a direction perpendicular to the front side;

[0072] Step S7, filling the blind hole with a metal filling process to form a lead-in portion b, and continuing to form a main body portion a and a signal contact portion 3a by metal layer deposition;

[0073] Step S8, connecting the front-mounted chip 1 and the flip-chip 2 to corresponding electrical contacts through solder balls.

[0074] In a preferred embodiment, when the connecting plate 3 also has a vertical shielding portion 308, in step S1, a receiving structure corresponding to the structure of the vertical shielding portion 308 is etched while etching a through hole on the substrate 301, and an insulating layer is formed on the inner wall of the receiving structure while processing the inner wall of the through hole by chemical vapor deposition to form the second insulating layer 306 in the above step S1. In step S3, the vertical shielding portion 308 is formed while forming the through-connecting portion 304. In step S4, the shielding net 305 is formed while contacting the vertical shielding portion 308.

[0075] Embodiment 2

[0076] Based on the first embodiment, the difference between this embodiment and the first embodiment is that: Figure 6 As shown, for all through-connecting portions 304, there is a second insulating layer 306 between the through-connecting portion 304 (hereinafter referred to as the first connecting portion) connected to the signal contact portion 3a and the corresponding hole wall. The through-connecting portion 304 (hereinafter referred to as the second connecting portion) connected to the ground contact portion 3b is directly in contact with the silicon body 301b, so that two adjacent second connecting portions and the first connecting portion between the two can form a group, and within each group, the electromagnetic coupling between the first connecting portion and the second connecting portion of the same group can be increased, and the reciprocal admittance between the first connecting portion and the second connecting portion of other groups and the first connecting portion is reduced, so that the electromagnetic field is more concentrated inside each group, and unnecessary electromagnetic coupling between different groups is suppressed, so as to achieve the purpose of suppressing mutual interference between the through-connecting portions 304 in the same row.

[0077] In view of the above improvements, the packaging method of integrated circuits has also been adjusted accordingly, specifically:

[0078] The following adjustments are made based on the packaging method in Example 1: when etching the through hole in the above step S1, only the through hole corresponding to the first connection part is etched; the metal filling process in step S3 is only performed on the first connection part; in the above step S6, the through hole corresponding to the second connection part is etched while etching the blind hole; and in step S7, while filling the blind hole with metal, the through hole corresponding to the second connection part is filled to obtain the second connection part.

[0079] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An integrated circuit packaging structure, comprising: Formal chip; Flip chip; A connecting plate, which is placed between the front-mounted chip and the flip-chip; The connecting plate comprises a base plate and located on the base plate: Electrical contacts, which are divided into signal contacts and ground contacts; A through-connecting portion, which passes through the substrate and connects the electrical contact portions located on the front and back sides of the substrate; Shielding net; a first insulating layer; Features: The front and back surfaces of the substrate are provided with ion permeation layers, and the shielding net is in contact with the ion permeation layers; The signal contact portion is isolated on the outside of the shielding mesh by the first insulating layer; The ground contact portion has: a main body disposed outside the shielding net, and A lead-through portion passes through the shielding mesh and directly contacts the silicon body of the substrate.

2. The integrated circuit packaging structure according to claim 1, characterized in that: The connecting plate also has a vertical shielding portion, and the vertical shielding portion includes: a shielding column extending along a thickness direction of the substrate; and A shielding bar extending continuously in the length direction or the width direction of the substrate and extending inwardly to the inside of the substrate; a plurality of shielding columns extending from one side of the shielding bar to the other side of the substrate; The through-connecting portions are arranged in rows, at least two groups of the vertical shielding portions are arranged between two adjacent rows of the through-connecting portions, and the shielding bars of two adjacent groups of the vertical shielding portions are located on different sides of the substrate.

3. The integrated circuit packaging structure according to claim 1, characterized in that: The shielding strip extends to half the thickness of the substrate.

4. The integrated circuit packaging structure according to claim 2, characterized in that: The vertical shielding part and the shielding net are both made of copper.

5. The integrated circuit packaging structure according to claim 3, characterized in that: The shielding net has a second pad, and the second pad is connected to the isolation unit through a second solder ball.

6. An integrated circuit packaging method, used to form the packaging structure of claim 1, characterized in that: The method comprises: Obtaining a substrate, and etching a through hole on the substrate; The front and back surfaces of the substrate are processed by ion implantation to form an ion permeation layer; and the inner wall of the through hole is processed by chemical vapor deposition to form a second insulating layer; Filling the through hole with a metal filling process to form a through-connection portion; Performing metal deposition operation on the substrate to form a grid-like shielding net on the outer surface of the ion permeation layer; forming a first insulating layer covering the shielding mesh and the outer surface of the ion permeable layer by chemical vapor deposition; Etching blind holes on the front and back sides of the substrate, wherein the blind holes penetrate the first insulating layer and the ion permeation layer, and the blind holes are located in the mesh holes of the shielding net when viewed in a direction perpendicular to the front side; Filling the blind hole with a metal filling process to form a lead-in portion, and continuing to form a main body portion and a signal contact portion by depositing a metal layer; Connect the face-up chip and the flip-chip to corresponding electrical contacts through solder balls.

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