Management controller, method, and non-transitory machine-readable storage medium

Abstract

The present disclosure relates to dynamic changing of bus parameters. In some examples, during a process in which an electronic device performs a cryptographic operation, a management controller will dynamically change parameters that control operating characteristics of a bus through which different portions of information from a memory are communicated. The different portions of information from the memory will be communicated through the bus with different operating characteristics of the bus.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a management controller. BACKGROUND

[0002] Memory devices can be used to store program code (including machine-readable instructions such as firmware and / or software) and data. Examples of program code include boot code that is executed during a startup of an electronic device. Boot code can be stored in a non-volatile memory device such as a flash read-only memory (ROM) device. SUMMARY

[0003] According to an aspect of the present disclosure, a management controller includes a processor to dynamically change a parameter that controls an operating characteristic of a bus while different portions of information from a memory are transferred through the bus during a process in which a cryptographic operation is performed by an electronic device, wherein the different portions of the information from the memory are to be transferred through the bus with different operating characteristics of the bus, and wherein the different portions of the information include different portions of boot code stored in the memory.

[0004] According to another aspect of the present disclosure, a management controller includes a bus controller, a processor to dynamically change a parameter that controls an operating characteristic of the bus controlled by the bus controller while different portions of information from a memory are transferred through the bus during a process in which a cryptographic operation is performed by an electronic device, wherein the different portions of the information from the memory are to be transferred through the bus with different operating characteristics of the bus, send first control information to the bus controller, the first control information specifying a first value of a parameter of the bus connected to the memory, the first value of the parameter to control transfer of a first portion of the information from the memory through the bus, and send second control information to the bus controller, the second control information specifying a second value of the parameter of the bus connected to the memory, the second value of the parameter to control transfer of a second portion of the information from the memory through the bus, the second value being different from the first value.

[0005] According to another aspect of the present disclosure, a management controller includes a processor to dynamically change a parameter that controls an operating characteristic of a bus while different portions of information from a memory are transferred through the bus during a process in which a cryptographic operation is performed by an electronic device, wherein the different portions of the information from the memory are to be transferred through the bus with different operating characteristics of the bus, wherein the parameter to be dynamically changed relates to a width of a data portion of the bus, and wherein different values of the parameter indicate different bus widths of the data portion of the bus.

[0006] According to another aspect of the disclosure, a method of managing a controller includes configuring configuration logic of a bus controller with respective different values of a parameter during a boot process of an electronic device, transferring first information between the bus controller and a memory according to first operating characteristics of a bus connecting the bus controller and the memory specified by a first value of the different values of the parameter through the bus during the boot process, and transferring second information between the bus controller and the memory according to different second operating characteristics of the bus specified by a second value of the different values of the parameter through the bus during the boot process.

[0007] According to another aspect of the disclosure, a non-transitory machine-readable storage medium includes instructions that, when executed, cause a controller to dynamically change a bus attribute parameter to change operating characteristics of a bus connecting a bus controller and a memory during a process of performing a cryptographic operation, wherein the dynamic change of the bus attribute parameter includes writing a first value of the bus attribute parameter to a configuration register of the bus controller to produce first operating characteristics of the bus in transferring a first boot code portion from the memory and writing a second value of the bus attribute parameter to the configuration register of the bus controller to produce different second operating characteristics of the bus in transferring a second boot code portion from the memory, wherein each of the first and second operating characteristics relates to one or more of a frequency of a clock signal of the bus and a width of a data portion of the bus. BRIEF DESCRIPTION OF DRAWINGS

[0008] Some embodiments of the disclosure are described with respect to the following figures.

[0009] Figure 1 is a block diagram of an arrangement including a management controller, a bus controller, and a target device connected to the bus controller through a bus according to some examples.

[0010] Figure 2 is a timing diagram of a process of dynamically changing a bus clock frequency according to some examples.

[0011] Figure 3 is a timing diagram of a process of dynamically changing a bus data portion width according to some examples.

[0012] Figure 4 is a block diagram of a management controller according to some examples.

[0013] Figure 5 is a flowchart of a process according to some examples.

[0014] Figure 6is a block diagram of a storage medium storing machine-readable instructions according to some examples.

[0015] In all of the drawings, like reference numerals refer to like parts throughout the several views. The drawings are not necessarily to scale, with emphasis generally being placed upon illustrating the examples and / or embodiments depicted therein. Additionally, the drawings provide examples and / or embodiments consistent with the description; however, the description is not limited to the examples and / or embodiments provided in the drawings. DETAILED DESCRIPTION

[0016] Flash read-only memory (ROM) devices are non-volatile, electrically erasable, and reprogrammable memory devices. An example type of flash ROM is NOR flash ROM. Another example type of flash ROM is NAND flash ROM. In electronic devices, certain information, including program code and data, can be stored in a flash ROM device or another type of non-volatile memory device. For example, boot code, device configuration data, and other sensitive data can be stored in a flash ROM device. A basic input / output system (BIOS) code is an example of boot code that is executed when an electronic device is booted to initialize components of the electronic device and load an operating system (OS) of the electronic device.

[0017] An attacker can attempt to gain access to an electronic device by observing operations related to program code (e.g., a segment of BIOS code) stored in a flash ROM device. An example attack type is a side-channel attack in which an attacker monitors certain components of an electronic device (e.g., bus signals transmitted over a bus, electrical behavior of a power component such as a power supply or power regulator, etc.) and / or electromagnetic emissions of the components to observe characteristics of the electronic device including any or some combination of: timing of operations in the electronic device, power consumption in the electronic device, and electromagnetic radiation levels of the electronic device. Examples of techniques that can be used to monitor the aforementioned observed characteristics can include monitoring a bus connected to a flash ROM device using a probing device (e.g., a signal tracer), probing a power connection of a power component using a device that can capture electrical signals (e.g., an oscilloscope), measuring electromagnetic emissions using an electromagnetic measurement device (e.g., an electromagnetic field meter), and so on.

[0018] The aforementioned observed characteristics can be used by an attacker to derive sensitive information used in the electronic device, such as information related to cryptographic operations of a security system of the electronic device (e.g., cryptographic operations of a segment of code stored in a flash ROM device). Changes in power consumption and / or electromagnetic emissions and timing of such changes can be captured and used to reveal properties of computations performed by the electronic device. Examples of sensitive information that can be derived from the observed characteristics can include cryptographic keys and / or secrets used in cryptographic operations.

[0019] An attacker can use various techniques (e.g., by changing parameters such as voltage, current, etc.) to attempt to cause a malfunction of an electronic device. By monitoring the aforementioned observed characteristics, an attacker can exploit the repeatability of the operation of the electronic device (such as the security system of the electronic device) to predict the deterministic behavior of the electronic device. The attacker can then guess when to change a particular set of parameters (one parameter or multiple parameters) to induce a malfunction at a target time (e.g., an elapsed time measured from a fixed starting point such as a reset time of the electronic device). For example, the attacker can repeatedly inject voltage spikes (and / or one or more other parameters) in the electronic device at one or more target times (such as during a boot sequence of the electronic device) multiple times (e.g., thousands to millions of times) to induce a malfunction that can result in the attacker obtaining sensitive information.

[0020] An attacker can use the obtained cryptographic key and / or secret to steal information in the electronic device or another device coupled with the electronic device (such as over a network). The attacker can also use the cryptographic key and / or secret to control the operation of the electronic device or another device coupled with the electronic device.

[0021] According to some embodiments of the present disclosure, the attack mitigation engine is capable of dynamically changing acquisition parameters that control the communication properties of a bus between a non-volatile memory device storing target program code and a bus controller for the bus. By changing the communication properties of the bus, portions of the target program code can be fetched from the non-volatile memory device in an unpredictable manner (e.g., at different rates, different sizes of fragments, etc.), which affects the timing of delivery of the portions of the target program code for execution on a processor. The attack mitigation engine is capable of preventing or reducing the likelihood of success of any other attack on the electronic device that exploits the repeatability of the operation of the electronic device determined by observing the behavior of the electronic device during certain operations of the electronic device (such as during a boot process, during a process that performs cryptographic operations, etc.). As described above, by changing the communication properties of the bus, each occurrence of the operation such as the boot process of the electronic device can be made unique such that an attacker cannot determine when to schedule an attack time.

[0022] Figure 1is a block diagram of an example electronic device 100 that includes a bus controller 102 coupled to various target devices by a bus 108. As used herein, a "controller" can refer to one or more hardware processing circuits, which can include any one or a combination of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, or other hardware processing circuit. Alternatively, a "controller" can refer to a combination of one or more hardware processing circuits and machine-readable instructions (software and / or firmware) that are executable on the one or more hardware processing circuits. In a more particular example, the bus controller 102 can be implemented using a hardware state machine that operates independent of machine-readable instructions. In some examples, the bus controller 102 can be part of a management controller, such as a baseboard management controller (BMC) 112. Details regarding "BMCs" are provided further below. In other examples, the bus controller 102 can be external to the BMC 112.

[0023] Examples of electronic devices include any one or more of: a computer (e.g., a server computer, a desktop computer, a notebook computer, a tablet computer, etc.), a smartphone, a wearable device, a gaming device, an electronic component of a vehicle or a vehicle, a storage system, a communication system, a home appliance, etc.

[0024] Target devices connected to the bus 108 include a non-volatile memory device 104 and another target device 106. A "bus" can refer to any communication link that includes a set of signal lines (single signal line or multiple signal lines) through which data can be transferred. In some examples, the non-volatile memory device 104 is a flash ROM device. In other examples, the non-volatile memory device 104 can be implemented using different types of memory devices.

[0025] A "non-volatile" memory device is capable of persistently storing data even if the memory device is powered off. In some examples, the target device 106 can be another non-volatile memory device or another type of device.

[0026] Although Figure 1 Although multiple target devices are shown connected to the bus 108, in other examples, a single target device (e.g., the non-volatile memory device 106) or more than two target devices can be connected to the bus 108.

[0027] The bus controller 102 includes a bus control engine 103 that controls communications with the target devices 104 and 106 over the bus 108. The bus control engine 103 can be implemented using hardware processing circuitry or a portion of machine-readable instructions of the bus controller 102.

[0028] In some examples, the bus 108 can be a serial peripheral interface (SPI) bus. In other examples, the bus 108 can be a different type of bus, such as an internal integrated circuit (I2C) bus or other type of bus.

[0029] SPI is a synchronous serial communication interface for short distance communication. In examples in which the bus 108 is an SPI bus, the controller 102 is an SPI controller. On an SPI bus, a master device (e.g., the SPI controller) controls operations on the SPI bus, including providing a clock signal and one or more select signals to select a respective one or more target devices (or peripherals) with which the master device will communicate. Additionally, the SPI bus includes an input / output (I / O) data portion through which the master device can send and receive data bits to and from the target device. In some examples, the SPI bus can be a configurable quad SPI bus, which can be configured in any of an xl mode, an x2 mode, or an x4 mode. In the xl mode, the I / O data portion of the SPI bus communicates data bits in each direction over one data signal line (one unidirectional data signal line communicates data bits from the master device to the target device, and another unidirectional data signal line communicates data bits from the target device to the master device). In the x2 mode, the I / O data portion communicates data bits between the master device and the target device over two bidirectional data signal lines. The master device can drive these two data signal lines to output commands and addresses. When the master device expects a response from the target device, the master device can tri-state its output drivers to the bus so that the target device can send data to the master device over these two data signal lines. Commands, addresses, and data on the SPI bus can be sent in respective command, address, and data phases (further described below). In the x4 mode, the I / O data portion communicates data bits between the master device and the target device over four bidirectional data signal lines (similar to the x2 mode, but with more data signal lines).

[0030] Although SPI buses are mentioned in some examples, in other examples, other types of buses can be used to transfer data to and from non-volatile memory devices and other target devices.

[0031] In further examples, the electronic device 100 can include multiple bus controllers to communicate with other target devices over respective buses (e.g., SPI buses).

[0032] The electronic device 100 also includes a host processor 110 (or multiple host processors) that can be coupled to the BMC 112 to allow the host processor 110 to communicate with target devices connected to the bus 108. The host processor 110 is separate from the BMC 112. In an example, the host processor 110 can fetch a boot code snippet 116 stored in the non-volatile memory device 104 for the host processor 110 to execute during a boot process of the electronic device 100.

[0033] A “host processor” can refer to a processor that executes programs of the electronic device 100, such as an OS, an application, system firmware, etc. The host processor 110 can be coupled to the BMC 112 through intermediary components, such as through a network interface controller, an I / O hub, etc. The BMC 112 includes a communication interface 130, such as a Peripheral Component Interconnect (PCI) Express (PCIe) interface, an enhanced Serial Peripheral Interface (eSPI), a Low Pin Count (LPC) interface, or a network interface controller or another type of interface that allows the BMC 112 to communicate with another component external to the BMC 112.

[0034] In some examples of the present disclosure, the BMC 112 includes a root of trust engine 114. In some examples, the root of trust engine 114 in the BMC 112 is implemented in hardware, such as in the form of a hardware state machine. In other examples, the root of trust engine 114 can be implemented using machine-readable instructions, such as firmware or software executed by the BMC 112 (rather than by the host processor 110 of the electronic device 100).

[0035] The root of trust engine 114 can perform verification of certain components and processes of the electronic device 100 to ensure that the components and processes can be trusted and have not been compromised. For example, the root of trust engine 114 can verify a boot process of the electronic device 100 to ensure that the electronic device 100 was launched using trusted boot code (or more specifically, using the trusted boot code snippet 116 in the non-volatile memory device 104). A “boot process” refers to a process that runs when an electronic device is initially launched, where the boot process performs component testing and initialization of the electronic device and loading of an OS of the electronic device. The verification of the boot process performed by the root of trust engine 114 can include verifying the boot code snippet 116 stored in the non-volatile memory device 104.

[0036] The boot code snippet 116 can include a snippet of boot code (e.g., of the BMC 112, of BIOS code (e.g., a boot block of BIOS code), etc.) that performs a specified initial function at the start of the boot process of the electronic device 100. In some examples, the boot code of the BMC 112 is verified by the root-of-trust engine 114 before it is allowed to execute after the root-of-trust engine 114 determines that the digital signature of the boot code of the BMC 112 matches an expected value. The boot code of the BMC 112 then verifies the next portion of the boot code before it is allowed to execute, and so on.

[0037] The root-of-trust engine 114 performs the verification of the boot code snippet 116 by computing a cryptographic value (such as a cryptographic hash value) from the boot code snippet. The cryptographic value is computed using a cryptographic operation that employs a cryptographic key and / or another secret.

[0038] According to some embodiments of the present disclosure, the root-of-trust engine 114 includes an attack mitigation module 120 that is capable of performing actions to prevent an attacker from successfully performing a side-channel attack and / or a man-in-the-middle attack. The attack mitigation module 120 can be implemented using a portion of the hardware or machine-readable instructions of the root-of-trust engine 114.

[0039] Although Figure 1 Although the attack mitigation module 120 is shown as part of the root-of-trust engine 114, in other examples, the attack mitigation module 120 can be in the bus controller 102 and separate from the root-of-trust engine 114. In further examples, the attack mitigation module 120 can be implemented using another component of the electronic device 100.

[0040] The bus controller 102 includes programmable configuration logic 122 that can be configured by the attack mitigation module 120 to dynamically change one or more bus property parameters that will change one or more respective operating characteristics of the bus 108.

[0041] In some examples, the bus property parameters that can be dynamically changed by configuring the programmable configuration logic 122 include any or some combination of a bus clock parameter related to a clock frequency of a clock signal 124 of the bus 108, and a data width parameter related to a width of a data portion 126 of the bus 108.

[0042] The clock parameter can be set to one of a variety of different values corresponding to different frequencies of the bus clock signal 124. The bus width parameter can be set to one of a variety of different values corresponding to different widths of the data portion 126 of the bus 108. For example, if the bus 108 is a configurable quad SPI bus, the bus width parameter can be set to one of several different values for selecting an xl mode, an x2 mode, or an x4 mode. More generally, different values of the bus width parameter can specify a respective different number of data signal lines of the bus 108 and / or a respective different behavior of the data signal lines of the bus 108 (e.g., an xl mode uses two unidirectional data signal lines, while an x2 mode uses two bidirectional data signal lines) for carrying data between the bus controller 102 and a target device (e.g., the non-volatile memory device 104). In examples where different phases of a bus transaction are used to carry commands, addresses, and data over the bus 108 (e.g., an SPI bus), different modes can be set for different phases (discussed further below). Also, in some cases (such as with an SPI bus), different commands can specify a respective data width to be used for addresses and data; in such examples, different values of the bus width parameter can control which command is issued; in other words, different commands can be associated with respective data widths. For example, a first command can perform an xl SPI read (reading data in an xl mode), a second command can perform an x2 SPI read (reading data in an x2 mode), and a third command can perform an x4 SPI read (reading data in an x4 mode). The bus controller 102 can change the command being sent to be consistent with the desired data width.

[0043] In some examples, the programmable configuration logic 122 includes a configuration register 128 (or multiple configuration registers). A “register” refers to a storage component that is capable of storing a data value. The configuration register 128 can store values of a plurality of bus property parameters P1 through Pm (m > 1). As an example, the bus property parameters P1 through Pm include the clock parameter and the bus width parameter described above. In further examples, different bus property parameters P1 through Pm can be stored in respective different configuration registers 128.

[0044] In some examples, the attack mitigation module 120 can write the bus property parameters to the configuration register 128 (or multiple configuration registers). Although Figure 1 A direct connection between the root-of-trust engine 114 and the bus controller 102 is shown, but in further examples, one or more intermediate components can be between the root-of-trust engine 114 and the bus controller 102.

[0045] In the ensuing discussion, it is assumed that there is only one configuration register 128 that is programmed with parameter values Pi to Pm to change the operating characteristics of the bus 108. Further example techniques or mechanisms can employ multiple configuration registers in the configuration logic 122 of the bus controller 102 to store respective bus attribute parameters.

[0046] To program the configuration register 128, the attack mitigation module 120 can send control information to the bus controller 102. The control information can include a configuration write command, e.g., that includes an indication that the command is to write the configuration register 128, and a value to write to the configuration register 128 (e.g., a value of a bus attribute parameter).

[0047] The bus control engine 103 of the bus controller 102 can control the frequency of the bus clock signal 124 based on the clock parameter programmed into the configuration register 128. For example, the bus control engine 103 can provide control indications 134 (e.g., one or more control signals) to a clock generator 132 of the bus controller 102. The clock generator 132 can include a controllable oscillator that outputs the bus clock signal 124. The control indications 134 to the clock generator 132 can vary based on different values of the clock parameter to adjust the frequency of the bus clock signal 124 output by the clock generator 132. Alternatively, the bus clock signal 124 can be generated by a programmable divisor internal to the clock generator 132 that takes a common input reference signal and divides the input clock by a value programmed in the configuration register 128.

[0048] The bus control engine 103 of the bus controller 102 can control the bus width of the data portion 126 based on the bus width parameter programmed into the configuration register 128. For example, the bus control engine 103 can provide control indications 138 (e.g., one or more control signals) to the data interface 136 of the bus controller 102. The data interface 136 can include interface circuitry (e.g., I / O buffers, etc.) that can be controlled to activate corresponding data signal lines of the bus 108. For example, a data signal line can be activated by enabling an I / O buffer of the data interface 136 for the data signal line. A data signal line can be deactivated by disabling an I / O buffer of the data interface 136 for the data signal line. The control indications 138 to the data interface 136 can vary based on different values of the bus width parameter to adjust the bus width of the bus 108. In further examples, the bus control engine 103 can send different commands based on different values of the bus width parameter in the configuration register 128. For example, the bus control engine 103 can send a first command specifying a first bus width in response to a first value of the bus width parameter, the bus control engine 103 can send a second command specifying a second bus width in response to a second value of the bus width parameter, and so on. In general, the bus control engine 103 will modify the command based on the width setting and the target operation. The target device (e.g., 104 or 106) can interpret the incoming command from the bus controller 102 and adjust the data width accordingly.

[0049] In alternative examples, the attack mitigation module 120 can program the configuration register 128 or another configuration register with a command parameter to indicate the command to issue that is consistent with the value of the bus width parameter in the configuration register 128. Different values of the command parameter will indicate respective different commands to use. Thus, the attack mitigation module 120 can control the bus width and the command to use that is consistent with the bus width by programming the value of the bus width parameter in the configuration register 128 and the value of the command parameter in the configuration register 128 or another configuration register.

[0050] In some examples, mapping information 140 (e.g., in the form of a lookup table) can be stored in a memory of the bus controller 102 to map bus attribute parameter values to respective different operational characteristics (e.g., bus clock frequency and / or bus data portion width).

[0051] Figure 2 An example timing diagram is shown that illustrates how the frequency of the bus clock signal 124 can dynamically change at different times to read respective different portions of the boot code segment 116 from the non-volatile memory device 104 (at Figure 2denoted as portions Dl, D2, D3, and D4), such as during a boot-up process of an electronic device.

[0052] As part of reading the boot code segment 116 from the non-volatile memory device 104, the attack mitigation module 120 can write successive different clock parameter values to the configuration register 128. For example, at time tl, the attack mitigation module 120 can write a clock parameter value Cl to the configuration register 128; at time t2, the attack mitigation module 120 can write a clock parameter value C2 (different from Cl) to the configuration register 128; at time t3, the attack mitigation module 120 can write the clock parameter value Cl to the configuration register 128; and at time t4, the attack mitigation module 120 can write a clock parameter value C3 (different from each of Cl and C2) to the configuration register 128.

[0053] The different values of the clock parameter (Cl, C2, and C3) can correspond to different clock frequencies of the bus clock signal 124. As shown, Figure 2 writing the value Cl of the clock parameter to the configuration register 128 at time tl causes the bus controller 102 to set a first clock frequency fl for the bus clock signal 124 during a time interval TA; writing the value C2 of the clock parameter to the configuration register 128 at time t2 causes the bus controller 102 to set a second clock frequency f2 (different from fl) for the bus clock signal 124 during a time interval TB; writing the value Cl of the clock parameter to the configuration register 128 at time t3 causes the bus controller 102 to set the first clock frequency fl for the bus clock signal 124 during a time interval TC, and writing the value Cl of the clock parameter to the configuration register 128 at time tl causes the bus controller 102 to set a third clock frequency f3 for the bus clock signal 124 during a time interval TD.

[0054] During the time interval TA in which the bus clock signal 124 is running at the first clock frequency fl, the bus controller 102 reads the portion Dl of the boot code segment 116 from the non-volatile memory device 104; during the time interval TB in which the bus clock signal 124 is running at the second clock frequency f2, the bus controller 102 reads the portion D2 of the boot code segment 116 from the non-volatile memory device 104; during the time interval TC in which the bus clock signal 124 is running at the first clock frequency fl, the bus controller 102 reads the portion D3 of the boot code segment 116 from the non-volatile memory device 104; and during the time interval TD in which the bus clock signal 124 is running at the third clock frequency f3, the bus controller 102 reads the portion D4 of the boot code segment 116 from the non-volatile memory device 104.

[0055] In the example shown in FIG. 1, the attack mitigation module 120 can write the clock parameter values Cl, C2, and C3 to the configuration register 128 in response to detecting a boot code segment 116 that is being read from the non-volatile memory device 104. Figure 2In the example of FIG. 1, clock frequency f1 is greater than clock frequency f2, and clock frequency f2 is greater than clock frequency f3. When bus clock signal 124 is running at a higher frequency, the respective portions of boot code snippet 116 are read through bus 108 at a higher data rate. Thus, in Figure 2 In the example of FIG. 1, bus controller 102 can read portion D1 at a higher data rate at time interval TA than when reading second portion D2 at time interval TB. In Figure 2 In the example of FIG. 1, time interval TA is shorter than each of time intervals TB and TD, meaning that the amount of time to read portion D1 is less than the amount of time to read either portion D2 or portion D4 (assuming portions D1, D2, and D4 have the same size).

[0056] In some examples, attack mitigation module 120 can dynamically change the clock parameter value, and the corresponding bus clock frequency, in a random manner. For example, attack mitigation module 120 can include a random number generator that generates random numbers. Attack mitigation module 120 can obtain different clock parameter values based on different random numbers. In other examples, attack mitigation module 120 can dynamically change the clock parameter value in another unpredictable manner to mitigate attacks on electronic device 100.

[0057] As noted above, some buses (such as SPI buses) transfer different information (e.g., commands, addresses, and data) at respective different phases (command phase, address phase, and data phase). More generally, different frequencies can be specified for different phases (e.g., a first frequency for the command phase, a second frequency for the address phase, and a third frequency for the data phase, where the first, second, and third frequencies can be the same as or different from each other).

[0058] Figure 3 An example timing diagram is shown that illustrates how the bus width of bus 108 can dynamically change at different times to read respective different portions of boot code snippet 116 from non-volatile memory device 104 (represented in Figure 3 FIG. 1 as portions D5, D6, D7, and D8), such as during a boot process of the electronic device.

[0059] As part of reading boot code segment 116 from non-volatile memory device 104, attack mitigation module 120 can write consecutively different bus width parameter values ​​to configuration register 128. For example, at time t5, attack mitigation module 120 can write bus width parameter value BW1 to configuration register 128; at time t6, attack mitigation module 120 can write bus width parameter value BW2 (different from BW1) to configuration register 128; at time t7, attack mitigation module 120 can write bus width parameter value BW3 (different from each of BW1 and BW2) to configuration register 128; and at time t8, attack mitigation module 120 can write bus width parameter value BW2 to configuration register 128.

[0060] Different values ​​of the bus width parameters (BW1, BW2, and BW3) can correspond to different bus widths of bus 108. For example, if bus 108 is an SPI bus, the different bus width parameter values ​​BW1, BW2, and BW3 correspond to the following different SPI modes: x1, x2, and x4.

[0061] like Figure 2 As shown, at time t5, the value BW1 of the bus width parameter is written to the configuration register 128, causing the bus controller 102 to set the bus 108 to x1 mode (e.g., the width of the data portion 126 of the bus 108 is 1) during the time interval TE; at time t6, the value BW2 of the bus width parameter is written to the configuration register 128, causing the bus controller 102 to set the bus 108 to x2 mode (e.g., the width of the data portion 126 of the bus 108 is 2) during the time interval TF; at time t7, the value BW3 of the bus width parameter is written to the configuration register 128, causing the bus controller 102 to set the bus 108 to x4 mode (e.g., the width of the data portion 126 of the bus 108 is 1) during the time interval TG; and at time t8, the value BW2 of the bus width parameter is written to the configuration register 128, causing the bus controller 102 to set the bus 108 to x2 mode during the time interval TH.

[0062] During a time interval TE in which the bus 108 is set to xl mode, the bus controller 102 reads the portion D5 of the boot code segment 116 from the non-volatile memory device 104; during a time interval TF in which the bus 108 is set to x2 mode, the bus controller 102 reads the portion D6 of the boot code segment 116 from the non-volatile memory device 104; during a time interval TG in which the bus 108 is set to x4 mode, the bus controller 102 reads the portion D7 of the boot code segment 116 from the non-volatile memory device 104; and during a time interval TH in which the bus 108 is set to x2 mode, the bus controller 102 reads the portion D8 of the boot code segment 116 from the non-volatile memory device 104.

[0063] In the example of FIG. 1, the bus controller 102 is configured to read the boot code segment 116 from the non-volatile memory device 104 using xl mode during a time interval TE, using x2 mode during a time interval TF, using x4 mode during a time interval TG, and using x2 mode during a time interval TH. The time intervals TE, TF, TG, and TH are determined by the bus controller 102 based on the bus width parameter value and the corresponding bus clock frequency. Figure 3 In the example of FIG. 1, the bus controller 102 is configured to read the boot code segment 116 from the non-volatile memory device 104 using xl mode during a time interval TE, using x2 mode during a time interval TF, using x4 mode during a time interval TG, and using x2 mode during a time interval TH. The time intervals TE, TF, TG, and TH are determined by the bus controller 102 based on the bus width parameter value and the corresponding bus clock frequency.

[0064] In the example of FIG. 1, the bus controller 102 is configured to read the boot code segment 116 from the non-volatile memory device 104 using xl mode during a time interval TE, using x2 mode during a time interval TF, using x4 mode during a time interval TG, and using x2 mode during a time interval TH. The time intervals TE, TF, TG, and TH are determined by the bus controller 102 based on the bus width parameter value and the corresponding bus clock frequency. Figure 3 In the example of FIG. 1, the time interval TE is greater than each of the time intervals TF and TG, and the time interval TF is greater than the time interval TG.

[0065] In some examples, the attack mitigation module 120 can dynamically change the bus width parameter value and the corresponding bus clock frequency in a random or another unpredictable manner.

[0066] In some examples, different information can be communicated over the bus 108 (e.g., an SPI bus) in multiple phases of a transaction. A “transaction” refers to a collection of actions performed together on the bus 108 to accomplish a target task, such as reading or writing non-volatile memory. For example, the multiple phases of a transaction can include a command phase, an address phase, and a data phase. In the command phase, a command is communicated over the data portion 126 of the bus 108, in the address phase, an address is communicated over the data portion 126 of the bus 108, and in the data phase, data is communicated over the data portion 126 of the bus 108. As an example, the command communicated in the command phase can be a read command (to read data from the non-volatile memory device 104) or a write command (to write data to the non-volatile memory device 104). The address communicated in the address phase can be an address of a storage location in the non-volatile memory device 104 from which data is read or to which data is written. The data communicated in the data phase can be read data (data read from the non-volatile memory device 104) or write data (data written to the non-volatile memory device 104).

[0067] The width of the data portion 126 of the bus 108 used to communicate different information in the multiple phases of a transaction can be the same or different. More specifically, the data portion 126 used to communicate a command in the command phase can have a first width, the data portion 126 used to communicate an address in the address phase can have a second width, and the data portion 126 used to communicate data in the data phase can have a third width. The first width, the second width, and the third width can be the same or different from one another.

[0068] The bus controller 102 can independently control the width of the data portion 126 used in each phase of a transaction. The width of the data portion 126 used in a respective multi-phase can be set according to a multi-phase bus width configuration. For example, a 1-1-1 multi-phase bus width configuration specifies that the width of the data portion 126 in each of the command phase, the address phase, and the data phase is 1. As another example, a 4-4-4 multi-phase bus width configuration specifies that the width of the data portion 126 in the command phase, the address phase, and the data phase is 4. As a further example, a 1-2-2 multi-phase bus width configuration specifies that the width of the data portion 126 in the command phase is 1, the width of the data portion 126 in the address phase is 2, and the width of the data portion 126 in the data phase is 2. As yet another example, a 4-1-2 multi-phase bus width configuration specifies that the width of the data portion 126 in the command phase is 4, the width of the data portion 126 in the address phase is 1, and the width of the data portion 126 in the data phase is 2. More generally, an x-y-z multi-phase bus width configuration specifies that the width of the data portion 126 in the command phase is x, the width of the data portion 126 in the address phase is y, and the width of the data portion 126 in the data phase is z, where, in examples in which the data portion 126 is configurable to widths 1, 2, or 4, x e (1, 2, 4), y e (1, 2, 4), and z e (1, 2, 4). In other examples, other values of x, y, and z can be employed.

[0069] In such examples, different bus width parameters can specify different multi-phase bus width configurations, such that successive portions of the boot code segment 116 can use different multi-phase bus width configurations. For example, a first bus width parameter can specify a first combination of widths (x, y, z) of the data portion of the bus used to transfer a command, an address, and data of a first transaction over the bus, and a different second value of the bus width parameter specifies a second combination of widths (x, y, z) of the data portion of the bus used to transfer a command, an address, and data of a second transaction over the bus. As an example, the first transaction is used to transfer a first portion of the boot code segment 116, and the second transaction is used to transfer a first portion of the boot code segment 116.

[0070] By modifying bus attribute parameters according to some examples of this disclosure, the behavior of an electronic device can be dynamically altered, potentially leading to changes in the operating timing, power consumption, and electromagnetic radiation levels of the electronic device. Techniques or mechanisms according to some embodiments of this disclosure can prevent attempts to easily repeat electronic device operations (e.g., boot sequences) in an attempt to increase the likelihood of malfunction. Therefore, attacks on electronic devices based on the repeatability of electronic device operations determined by observing the behavior of the electronic device during specific operations (e.g., boot sequences) can be mitigated.

[0071] The dynamic alteration of the bus operating characteristics according to some embodiments of this disclosure is not intended to improve performance, but rather to improve the security of electronic device 100. In fact, dynamic alterations to the bus operating characteristics can impact performance during the boot process, such as when retrieving a portion of the boot code from non-volatile memory 104 using a slower bus clock and / or a narrower data portion width of bus 108. Dynamic alterations to the bus operating characteristics introduce unpredictability into the power consumption, electromagnetic emissions, latency, and retrieval pacing of cryptographic operations involving data retrieval via bus 108. For example, dynamically altering bus behavior during operation makes it more difficult to obtain meaningful insights into the cryptographic operations of BMC 112 based on measured power and / or electromagnetic emissions and the time taken for electronic device 100 to perform the boot process. Furthermore, random alterations to the address and data portion width create additional barriers against attacks from any intermediate entities on bus 108.

[0072] Figure 4 This is a block diagram of a management controller 400 according to some examples of this disclosure. For example, the management controller 400 may be... Figure 1 BMC 112.

[0073] The management controller 400 includes a processor 402, which includes cryptographic process bus attribute parameter changing logic 404. The processor 402 includes processing circuitry within the management controller 400, and the processor 402 of the management controller 400 is connected to the main processor of the electronic device (e.g., Figure 1 (110) Separate from the trust root engine 114. For example, processor 402 may be part of the trust root engine 114. In a more specific example, processor 402 may be implemented using a hardware state machine that does not rely on machine-readable instructions for execution. In other examples, processor 402 may execute machine-readable instructions. Note that processor 402, as part of management controller 400 (e.g., BMC 112), is separate from... Figure 1 The main processor 110 of the electronic device 100 is separated.

[0074] The cryptographic process bus attribute parameter change logic 404 can be implemented using hardware or machine-readable instructions. The cryptographic process bus attribute parameter change logic 404 can be an example of the attack mitigation module 120 of Figure 1

[0075] During a process in which the electronic device performs a cryptographic operation, the cryptographic process bus attribute parameter change logic 404 dynamically changes a bus attribute parameter that controls an operating characteristic of a bus (e.g., 108 in Figure 1 During a process in which the electronic device performs a cryptographic operation, the cryptographic process bus attribute parameter change logic 404 dynamically changes a bus attribute parameter that controls an operating characteristic of a bus (e.g., 108 in Figure 1 The process can be a boot process of the electronic device, for example.

[0076] Different portions of information from the memory are passed over the bus with different operating characteristics of the bus. Examples of different operating characteristics include one or more of a different bus clock frequency and a width of a data portion of the bus.

[0077] In some examples, the different portions of information include different portions of program code stored in the memory. The program code can include boot code, for example, the boot code segment 116 of Figure 1

[0078] In some examples, the management controller 400 includes a bus controller (e.g., 102 in Figure 1 The cryptographic process bus attribute parameter change logic 404 dynamically changes the bus attribute parameter by sending first control information to the bus controller. The first control information specifies a first value of the bus attribute parameter of the bus connected to the memory. The first value of the bus attribute parameter controls passing of a first portion of information from the memory over the bus. The cryptographic process bus attribute parameter change logic 404 further sends second control information to the bus controller. The second control information specifies a second value (different from the first value) of the bus attribute parameter of the bus connected to the memory. The second value of the bus attribute parameter controls passing of a second portion of information from the memory over the bus.

[0079] In some examples, the first control information and the second control information are to program a configuration register (e.g., 128 in Figure 1 of the bus controller related to control of the bus attribute parameter. For example, the first control information and the second control information can include first and second configuration write commands to write to the configuration register.

[0080] In some examples, the bus attribute parameter to be dynamically changed by the cryptographic process bus attribute parameter change logic 404 is a clock signal (e.g., 106 in Figure 1 ​​The clock frequency (124) is related to the bus attribute parameter, where different values ​​of the bus attribute parameter indicate different clock frequencies of the clock signal. In a further example, the bus attribute parameter to be dynamically changed by the cryptographic process bus attribute parameter changing logic 404 is related to the width of the bus data portion, where different values ​​of the parameter indicate different bus widths and / or the behavior of the bus data portion. In some cases (such as using an SPI bus), different commands can specify the corresponding data width to be used for address and data; in such examples, different values ​​of the bus width parameter can control which command is issued.

[0081] In some examples, the management controller 400 includes a bus controller (e.g., Figure 1 (102 in the example). In some examples, the bus controller dynamically changes the commands issued by the bus to match the width of the data portion of the bus specified by the parameters. In a further example, the cryptographic process bus attribute parameter changing logic 404 dynamically changes the command parameters of the bus controller's configuration register to dynamically change the commands issued by the bus controller by the bus to match the width of the data portion of the bus specified by the parameters.

[0082] In some examples, the data portion of the bus will transmit one or more of commands, addresses, and data to memory. For instance, the data portion of the bus will transmit commands, addresses, and data to memory via the bus at the appropriate stage of a transaction. The bus attribute parameters that can be dynamically changed by the controller are related to the width of the data portion of the bus used to transmit commands, addresses, and data. As discussed above, bus attribute parameters can specify multi-stage bus width configurations.

[0083] Figure 1 It is a management controller (such as) Figure 5 The flowchart of process 500 of BMC 112 is shown below. Process 500 includes configuring (at 502) the configuration logic of the bus controller using corresponding different values ​​of parameters during the boot process of the electronic device. For example, the management controller may write dynamically changing bus attribute parameter values ​​to the configuration register (or multiple configuration registers) of the bus controller to cause dynamic changes in the operating characteristics of the bus.

[0084] Process 500 includes, during the boot process, transmitting (at 504) first information between the bus controller and the memory via the bus according to a first operating characteristic of the bus, specified by a first value among different values ​​of parameters. For example, the first operating characteristic may be a first clock frequency and / or a first width of the data portion of the bus.

[0085] The process 500 includes transferring (at 506) second information between the bus controller and the memory over the bus according to different, second operating characteristics of the bus specified by a second value of the parameter during the boot process. For example, the second operating characteristics can be a second clock frequency and / or a second width of a data portion of the bus. In some examples, changing the operating characteristics of the bus based on programming the configuration logic with respective different values of the parameter prevents a side-channel attack or a man-in-the-middle attack.

[0086] Figure 1 is a block diagram of a non-transitory machine-readable or computer-readable storage medium 600 that stores machine-readable instructions that, when executed, cause a controller to perform various tasks. The controller can be, for example, Figure 6 the BMC 112 of FIG. 1, or another type of controller.

[0087] The machine-readable instructions include dynamic bus attribute parameter changing instructions 602 to dynamically change a bus attribute parameter during a process that performs a cryptographic operation to change operating characteristics of a bus (e.g., 108 in FIG. 1) that connects a bus controller (e.g., 108 in FIG. 1) and a memory (e.g., 104 in FIG. 1). For example, the process can be a boot process. Figure 1 Figure 1 Figure 1

[0088] The dynamic bus attribute parameter changing instructions 602 include first configuration write instructions 604 to write a first value of the bus attribute parameter to a configuration register (e.g., 128 in FIG. 1) of the bus controller to produce first operating characteristics of the bus when passing a first boot code portion from the memory. The bus controller uses the first value of the bus attribute parameter to control the first operating characteristics of the bus. Figure 1 Figure 1

[0089] The dynamic bus attribute parameter changing instructions 602 include second configuration write instructions 606 to write a second value of the bus attribute parameter to the configuration register of the bus controller to produce different, second operating characteristics of the bus when passing second information with the memory. The bus controller uses the second value of the bus attribute parameter to control the second operating characteristics of the bus.

[0090] Each of the first operating characteristics and the second operating characteristics relates to one or more of a frequency of a clock signal of the bus and a width of a data portion of the bus.

[0091] ​​​​The storage medium 600 can include any one or some combination of the following: a semiconductor memory device such as a dynamic or static random access memory (DRAM or SRAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), and flash memory; a magnetic storage medium such as a fixed disk, a floppy disk, and a tape; another magnetic medium including tape; an optical medium such as a compact disc (CD) or a digital video disc (DVD); or another type of storage device. Note that the instructions discussed above can be provided on one computer-readable or machine-readable storage medium, or alternatively, can be provided on multiple computer-readable or machine-readable storage media in one system depending upon the configuration of the system. Such computer-readable or machine-readable storage medium or media is (are) considered to be part of an article (or article of manufacture). An article or article of manufacture can refer to one or more of a single component or multiple components. The one or more storage media can be located either in the machine that runs the machine-readable instructions, or located at a remote site from which machine-readable instructions can be downloaded over a network for execution.

[0092] A "BMC" can refer to a professional services controller that monitors a physical state of an electronic system using sensors and communicates with a remote management system (remote from the electronic system) over a separate "out-of-band" connection. The BMC can perform management tasks that manage components of the electronic system. Examples of management tasks that can be performed by the BMC can include any one or some combination of: power control that powers manages the electronic system (e.g., transitions the electronic system between different power consumption states in response to detected events), thermal monitoring and control of the electronic system (e.g., monitors temperatures of the electronic system and controls thermal management states of the electronic system), fan control of fans in the electronic system, system health monitoring based on monitoring measurement data of various sensors of the electronic system, remote access of the electronic system (e.g., accessing the electronic system over a network), remote reboot of the electronic system (triggering a reboot of the electronic system using a remote command), system settings and deployment of the electronic system, system security that implements security procedures in the electronic system, and so on.

[0093] In some examples, the BMC can provide a so-called "unattended" function for the electronic system. The unattended function can allow a user such as a system administrator to perform management operations on the electronic system even if an operating system (OS) is not installed on the electronic system or the operating system does not function.

[0094] Further, in some examples, the BMC is able to operate on auxiliary power provided by an auxiliary power source (e.g., a battery); thus, the electronic system does not have to be powered on to allow the BMC to perform operations of the BMC. The auxiliary power source is separate from a main power source that powers other components of the electronic system (e.g., a main processor, memory, input / output (I / O) devices, etc.).

[0095] In some examples, in addition to the BMC in each electronic system, an additional management controller (separate from the BMC) can be used to interact with the BMC to perform management of the electronic system. In examples where the electronic system is a server computer (or other type of electronic system) installed in a rack, the additional management controller can be referred to as a rack management controller (RMC). A "rack" refers to a mounting structure having a stand for a plurality of electronic systems.

[0096] In this disclosure, the use of the term "a," "an," or "the" is intended to mean "one or more" unless the context clearly indicates otherwise. Likewise, the use of the term "includes," "including," "comprises," or "comprising" means "has / having, or comprises / comprising," but does not mean "consists of / consisting of." As used in this disclosure, the term "plurality" means "two or more."

[0097] In the foregoing description, numerous details are set forth to facilitate understanding of the subject matter disclosed herein. However, implementations can be practiced without some or all of these details. Other implementations can include modifications and changes to the details discussed above. The attached claims are intended to cover such modifications and changes.

Claims

1. A management controller comprising: a processor to: dynamically change a parameter controlling an operating characteristic of a bus during a process of an electronic device performing a cryptographic operation as different portions of information from a memory are transferred over the bus, wherein the different portions of the information from the memory are to be transferred over the bus with different operating characteristics of the bus, wherein the different portions of the information include different portions of boot code stored in the memory.

2. The management controller of claim 1, wherein, The processor is implemented using a hardware state machine.

3. The management controller of claim 1, wherein, The parameter to be dynamically changed relates to a clock frequency of a clock signal of the bus, and wherein different values of the parameter indicate different clock frequencies of the clock signal.

4. The management controller of claim 1, wherein, The process of the electronic device during which the parameter is dynamically changed is a boot process of the electronic device.

5. A management controller comprising: a bus controller; a processor to: dynamically change a parameter controlling an operating characteristic of a bus controlled by the bus controller during a process of an electronic device performing a cryptographic operation as different portions of information from a memory are transferred over the bus, send first control information to the bus controller, the first control information specifying a first value of a parameter of the bus connected to the memory, the first value of the parameter to control transfer of a first portion of the information from the memory over the bus; and send second control information to the bus controller, the second control information specifying a second value of the parameter of the bus connected to the memory, the second value of the parameter to control transfer of a second portion of the information from the memory over the bus, the second value being different from the first value.

6. The management controller of claim 5, wherein, The first control information and the second control information are to program a configuration register of the bus controller, the configuration register relating to control of the parameter.

7. A management controller comprising: a processor to: dynamically change a parameter controlling an operating characteristic of a bus during a process of an electronic device performing a cryptographic operation as different portions of information from a memory are transferred over the bus, wherein the different portions of the information from the memory are to be transferred over the bus with different operating characteristics of the bus, wherein the parameter to be dynamically changed relates to a width of a data portion of the bus, and wherein different values of the parameter indicate different bus widths of the data portion of the bus.

8. The management controller of claim 7, further comprising a bus controller to dynamically change a command issued over the bus to be consistent with the width of the data portion of the bus specified by the parameter.

9. The management controller of claim 7, further comprising a bus controller for the bus, the bus controller comprising a configuration register, wherein The processor is to dynamically change a command parameter of the configuration register to dynamically change commands issued by the bus controller over the bus to be consistent with a width of the data portion of the bus specified by the parameter.

10. The management controller of claim 7, wherein, The data portion of the bus comprises a set of data signal lines, and wherein different values of the parameter indicate a respective different number or behavior of using data signal lines of the set of data signal lines.

11. The management controller of claim 7, wherein, The data portion of the bus is to communicate one or more of a command, an address, and data with the memory.

12. The management controller of claim 11, wherein, The data portion of the bus is to communicate the command, the address, and the data with the memory over the bus at respective phases of a transaction.

13. The management controller of claim 11, wherein, The parameter to be dynamically changed relates to a width of the data portion of the bus used to communicate the command, the address, and the data.

14. The management controller of claim 13, wherein, A first value of the parameter indicates a first combination of a width of the data portion of the bus used to communicate a command, an address, and data of a first transaction over the bus, and wherein a different second value of the parameter indicates a second combination of a width of the data portion of the bus used to communicate a command, an address, and data of a second transaction over the bus, wherein data of the first transaction comprises a first portion of the information and data of the second transaction comprises a second portion of the information.

15. A method of managing a controller, the method comprising: configuring configuration logic of a bus controller with respective different values of a parameter during a boot process of an electronic device; during the boot process, communicating first information between the bus controller and a memory over a bus according to first operating characteristics of the bus specified by a first value of the different values of the parameter; and during the boot process, communicating second information between the bus controller and the memory over the bus according to different second operating characteristics of the bus specified by a second value of the different values of the parameter.

16. The method of claim 15, wherein, The first and second operating characteristics of the bus comprise different clock frequencies of a clock signal of the bus.

17. The method of claim 15, wherein, The first and second operating characteristics of the bus comprise different widths of a data portion of the bus.

18. A non-transitory machine-readable storage medium comprising instructions that upon execution cause a controller to: During the execution of the cryptographic operation, the bus attribute parameters are dynamically changed to change the operating characteristics of the bus connecting the bus controller and the memory, wherein The dynamic change of the bus property parameter comprises: writing a first value of the bus property parameter to a configuration register of the bus controller to produce first operating characteristics of the bus in communicating a first portion of boot code from the memory, and writing a second value of the bus property parameter to the configuration register of the bus controller to produce different second operating characteristics of the bus in communicating a second portion of boot code from the memory, wherein each of the first and second operating characteristics relates to one or more of a frequency of a clock signal of the bus and a width of a data portion of the bus.

19. The non-transitory machine-readable storage medium of claim 18, wherein, Each of the first and second operating characteristics relates to a width of the data portion of the bus used during a plurality of phases of a transaction on the bus.

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