Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a substrate and a drive circuit. The first transistor comprises a second gate electrode, the second gate electrode is located on one side of the first active layer close to the substrate, and the second gate electrode is used for receiving a first fixed potential signal; the second transistor comprises a fourth gate electrode, the fourth gate electrode is used for receiving a second fixed potential signal; and the potential of the first fixed potential signal is different from that of the second fixed potential signal. The present application is beneficial to realizing the anti-static performance of the drive circuit and avoiding the direct breakdown of the transistor device by static electricity or a strong electric field. The first fixed potential received by the first floating gate of the first transistor is different from the second fixed potential received by the second floating gate of the second transistor, thereby avoiding the influence of the positive or negative bias of the threshold voltage of the transistor when a four-terminal device is used. It is beneficial to improve the positive or negative bias influence of the threshold voltage of the transistor by adjusting the fixed potential, and improve the accuracy of the output control signal of the shift register unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, and particularly to a display panel and a display device. BACKGROUND

[0002] In a display device, a pixel circuit for driving a light emitting device to emit light usually needs to be controlled by a control signal. Therefore, a control driving circuit is arranged in the display device to generate the light emitting control signal, a scanning signal and the like control signals.

[0003] In the prior art, in order to avoid damage to devices in the circuit caused by strong electric field, static electricity and the like, a four-terminal device is usually used. The four-terminal device is a device with an added bottom gate on the basis of a three-terminal device, which can block static electricity or strong electric field at the bottom gate and thus does not directly damage the device. However, in the driving circuit, the four-terminal device is more likely to have a phenomenon of positive or negative bias of threshold voltage than the three-terminal device, which further causes the control effect of the output control signal on the pixel circuit to be poor and affects the display effect. SUMMARY

[0004] Therefore, the present application provides a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a substrate and a driving circuit located on one side of the substrate, the driving circuit comprising a plurality of cascaded shift register units, each shift register unit comprising:

[0006] a first output unit, an input end of the first output unit being electrically connected with a first signal line and an output end of the first output unit being electrically connected with an output end of the shift register unit; the first output unit comprising a first transistor, the first transistor being connected in series between the first signal line and the output end of the shift register unit, the first transistor comprising a first active layer and a first gate and a first floating gate located on opposite sides of the first active layer, the first floating gate being located on a side of the first active layer close to the substrate, the first gate being configured to receive a control signal and the second gate being configured to receive a first fixed potential signal;

[0007] a second output unit, an input end of the second output unit being electrically connected with a second signal line and an output end of the second output unit being electrically connected with the output end of the shift register unit; the second output unit comprising a second transistor, the second transistor being connected in series between the second signal line and the output end of the shift register unit, the second transistor comprising a second active layer and a second gate and a second floating gate located on opposite sides of the second active layer, the second floating gate being located on a side of the second active layer close to the substrate, the second gate being configured to receive the control signal and the second floating gate being configured to receive a second fixed potential signal;

[0008] wherein the first fixed potential signal and the second fixed potential signal are different in potential.

[0009] In a second aspect, the embodiments of the present application provide a display device comprising the display panel provided in the first aspect.

[0010] In the embodiments of the present application, the first transistor in the first output unit comprises the first floating gate, and the second transistor M2 in the second output unit comprises the second floating gate. The first floating gate and the second floating gate are both located on the side close to the substrate, which is conducive to achieving the anti-static performance of the driving circuit. When there is static electricity, the static electricity can be first received by the first floating gate or the second floating gate, which is a bottom gate, so as to avoid that the static electricity or strong electric field directly breaks through the transistor device, thereby causing damage to the device and affecting the driving work of the shift register unit. This is conducive to protecting the device and ensuring the normal operation of the display panel.

[0011] In addition, the first fixed potential received by the first floating gate of the first transistor is different from the second fixed potential received by the second floating gate of the second transistor. Therefore, the first fixed potential signal and the second fixed potential signal can be flexibly set according to the actual situation of the shift register unit. This avoids the case that the bottom gates of all transistors are connected to the same potential, and further avoids the problem that the threshold voltage of at least part of the transistors is positively or negatively biased when a four-terminal device is used. This is conducive to improving the influence of the threshold voltage bias of the first transistor and the second transistor by adjusting the first fixed potential and the second fixed potential, and is conducive to improving the accuracy of the output control signal of the shift register unit. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1 A schematic diagram of a display panel provided in the embodiments of the present application;

[0014] Figure 2 A partial structure schematic diagram of a shift register unit provided in the embodiments of the present application;

[0015] Figure 3 A schematic diagram of a shift register unit provided in the embodiments of the present application;

[0016] Figure 4 A schematic diagram of another shift register unit provided in the embodiments of the present application;

[0017] Figure 5 A schematic diagram of another shift register unit provided in the embodiments of the present application;

[0018] Figure 6A timing circuit diagram provided for an embodiment of the present application;

[0019] Figure 7 A schematic diagram of another shift register unit provided for an embodiment of the present application;

[0020] Figure 8 A timing diagram of the shift register unit shown in Figure 3

[0021] Figure 9 A circuit schematic diagram of the shift register unit shown in Figure 8

[0022] Figure 10 A circuit schematic diagram of the shift register unit shown in Figure 5

[0023] Figure 11 A timing diagram of the shift register unit shown in Figure 10

[0024] A structure schematic diagram of a transistor provided for an embodiment of the present application; Figure 12

[0025] A schematic diagram of a pixel circuit provided for an embodiment of the present application; Figure 13

[0026] A timing diagram of a pixel circuit provided for an embodiment of the present application; Figure 14

[0027] A schematic diagram of a display device provided for an embodiment of the present application. Figure 15 DETAILED DESCRIPTION In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0028] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0029] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0030]

[0031] ​​​​It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0033] It should be understood that although the terms "first," "second," etc., may be used to describe output units, signal lines, gates, etc. in the embodiments of this application, these output units, signal lines, gates, etc., should not be limited to these terms. These terms are only used to distinguish output units, signal lines, gates, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first gate may also be referred to as a second gate, and similarly, a second gate may also be referred to as a first gate.

[0034] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 2 This is a partial structural diagram of a shift register unit provided in an embodiment of this application. Figure 3 This is a schematic diagram of a shift register unit provided in an embodiment of this application.

[0035] This application embodiment provides a display panel 100, combined with... Figures 1-3 As shown, the display panel 100 includes a substrate A10 and a driving circuit 200 located on one side of the substrate A10. The driving circuit 200 is used to drive the operation of the display panel 100. The driving circuit 200 includes multiple cascaded shift register units 300, each shift register unit 300 being a unit capable of outputting control signals. (In conjunction with...) Figure 3 As shown, the shift register unit 300 includes:

[0036] The first output unit 10 has an input terminal 101 electrically connected to the first signal line SL1 and an output terminal 102 electrically connected to the output terminal 301 of the shift register unit 300.

[0037] The first signal line SL1 can be used to transmit control signals such as voltage signals and clock signals. When the first output unit 10 is turned on, the signal transmitted by the first signal line SL1 is transmitted to the output end 301 of the shift register unit 300 by the first output unit 10. The control signal receiving end of the pixel circuit and the like in the display panel 100 is electrically connected with the output end 301 of the shift register unit 300, and receives the control signal generated by the shift register unit 300.

[0038] In the prior art, the driving circuit is easily affected by strong electric field or static electricity, thereby damaging the device. In order to avoid the influence of strong electric field or static electricity, it is common to use low-temperature process to prepare the transistor or add static liquid and the like. However, there are problems such as easy generation of residual image, influence on display, high cost and the like.

[0039] Therefore, in order to avoid the above problems, the present inventors propose that the transistor device prepared in the driving circuit is prepared by using a four-terminal device, so as to avoid damage caused by strong electric field or static electricity.

[0040] However, it is found in the application research process that, due to the influence of the potential and the turn-off characteristics of the transistor, the threshold voltage of the transistor is positively or negatively biased, so that the output control signal is inaccurate, for example, the high level is not high enough or the low level is not low enough. After the transistor in the driving circuit is prepared by using a four-terminal device, the bottom gates of all the four-terminal devices are usually connected to the same potential, and different potentials cannot be connected to different bottom gates according to the characteristics of the devices. Therefore, in some four-terminal devices, the positive or negative bias caused by the voltage difference between the bottom gate and the source of the transistor is increased, which aggravates the positive or negative bias of the threshold voltage of the transistor, and is not conducive to the normal work of the driving circuit.

[0041] Among them, the source is a pole connected to the power supply in the transistor, the positive bias is the deviation of the threshold voltage of the transistor, so that the threshold voltage after the deviation is higher than the normal threshold voltage of the transistor itself. Similarly, the negative bias is the case that the threshold voltage after the deviation is lower than the normal threshold voltage of the transistor itself.

[0042] Therefore, the inventors also propose that the first output unit 10 comprises a first transistor M1 connected in series between the first signal line SL1 and the output end 301 of the shift register unit 300. The first transistor M1 comprises a first active layer M10 and a first gate M11 and a first floating gate M12 located on the opposite sides of the first active layer M10. The first floating gate M12 is located on the side of the first active layer M10 close to the substrate A10, the first gate M11 is used to receive a control signal, and the second gate M12 is used to receive a first fixed potential signal V1.

[0043] The first transistor M1 includes a first gate M11, a first floating gate M12, and a source and a drain of the first transistor M1, and forms a four-terminal device. The first gate M11 is configured to receive a control signal, and control the conduction or the cutoff of the first transistor M1. The first floating gate M12 is located on a side of the first active layer M10 close to the substrate A10. Optionally, the first floating gate M12 includes a metal material, and can prevent static electricity. When the static electricity reaches the first transistor M1, the static electricity can be first received by the first floating gate M12, and then dispersed at the first floating gate M12, so as not to directly enter the device inside the first transistor M1, and break the device. In addition, the first floating gate M12 receives a first fixed potential signal V1, and the first fixed potential signal V1 can be flexibly set. In addition, the first floating gate M12 can be a light-proof or light-shielding material.

[0044] Optionally, the first fixed potential signal V1 is set to be the same as the potential of the active electrode connected to the first signal line SL1 in the first transistor M1, so as to avoid the pressure difference between the first floating gate M12 and the active electrode of the first transistor M1, and avoid further positive or negative bias.

[0045] In actual application, when the potential of the first floating gate M12 is higher than the potential of the active electrode in the first transistor M1, the threshold voltage of the first transistor M1 is negatively biased. When the potential of the first floating gate M12 is lower than the potential of the active electrode in the first transistor M1, the threshold voltage of the first transistor M1 is positively biased.

[0046] Therefore, optionally, in the shift register unit 300, when the first gate M11 of the first transistor M1 is in a high level state for a long time, so that the threshold voltage of the first transistor M1 is positively biased, the first fixed potential signal V1 can be set to be higher than the potential of the active electrode connected to the first signal line SL1 in the first transistor M1, so that the threshold voltage of the first transistor M1 is negatively biased. In this way, the positive bias effect of the first gate M11 on the first transistor M1 is offset by the negative bias effect of the first floating gate M12 on the first transistor M1, and the threshold voltage deviation of the first transistor M1 is improved.

[0047] Optionally, in the shift register unit 300, when the first gate M11 of the first transistor M1 is in a low level state for a long time, so that the threshold voltage of the first transistor M1 is negatively biased, the first fixed potential signal V1 can be set to be lower than the potential of the active electrode connected to the first signal line SL1 in the first transistor M1, so that the threshold voltage of the first transistor M1 is positively biased. In this way, the negative bias effect of the first gate M11 on the first transistor M1 is offset by the positive bias effect of the first floating gate M12 on the first transistor M1, and the threshold voltage deviation of the first transistor M1 is improved.

[0048] The second output unit 20 has an input end 201 electrically connected to the second signal line SL2 and an output end 202 electrically connected to the output end 301 of the shift register unit 300.

[0049] The second signal line SL2 can be used to transmit a voltage signal, a clock signal, or the like. When the second output unit 20 is turned on, the signal transmitted by the second signal line SL2 is transmitted to the output end 301 of the shift register unit 300 by the second output unit 20. The control signal receiving end of the pixel circuit or the like in the display panel 100 is electrically connected to the output end 301 of the shift register unit 300 to receive the control signal generated by the shift register unit 300.

[0050] The second output unit 20 includes a second transistor M2 connected in series between the second signal line SL2 and the output end 301 of the shift register unit 300. The second transistor M2 includes a second active layer M20 and a second gate M21 and a second floating gate M22 located on opposite sides of the second active layer M20. The second floating gate M22 is located on the side of the second active layer M20 close to the substrate A10. The second gate M21 is configured to receive a control signal, and the second floating gate M22 is configured to receive a second fixed potential signal V2.

[0051] The second transistor M2 includes the second gate M21 and the second floating gate M22, and the source and the drain of the second transistor M2 together form a four-terminal device. The second gate M21 is configured to receive a control signal to control the conduction or cutoff of the second transistor M2. The second gate M21 is located on the side of the second active layer M20 close to the substrate A10. Optionally, the second floating gate M22 includes a metal material to prevent static electricity from reaching the second transistor M2, so that the static electricity is first received by the second floating gate M22 and then dispersed at the second floating gate M22, without directly entering the internal device of the second transistor M2 to break the device. In addition, the second floating gate M22 receives the second fixed potential signal V2, and the second fixed potential signal V2 can be flexibly set. In addition, the second floating gate M22 can be a non-light-transmitting or light-blocking material.

[0052] Optionally, the second fixed potential signal V2 has the same potential as the active electrode of the second transistor M2 connected to the second signal line SL2, so as to avoid a pressure difference between the second floating gate M22 and the active electrode of the second transistor M2, thereby avoiding further positive or negative bias.

[0053] In actual application, when the potential of the second floating gate M22 is higher than the potential of the active electrode of the second transistor M2, the threshold voltage of the second transistor M2 is negatively biased. When the potential of the second floating gate M22 is lower than the potential of the active electrode of the second transistor M2, the threshold voltage of the second transistor M2 is positively biased.

[0054] Therefore, in the shift register unit 300, if the second gate M21 of the second transistor M2 is in a high level state for a long time, so that the threshold voltage of the second transistor M2 is positively biased, the second fixed potential signal V2 can be set to be higher than the potential of the active electrode of the second transistor M2 connected to the second signal line SL2, so that the threshold voltage of the second transistor M2 is negatively biased. In this way, the positive bias of the second gate M21 on the second transistor M2 is offset by the negative bias of the second floating gate M22 on the second transistor M2, and the threshold voltage deviation of the second transistor M2 is improved.

[0055] Alternatively, in the shift register unit 300, if the second gate M21 of the second transistor M2 is in a low level state for a long time, so that the threshold voltage of the second transistor M2 is negatively biased, the second fixed potential signal V2 can be set to be lower than the potential of the active electrode of the second transistor M2 connected to the second signal line SL2, so that the threshold voltage of the second transistor M2 is positively biased. In this way, the negative bias of the second gate M21 on the second transistor M2 is offset by the positive bias of the second floating gate M22 on the second transistor M2, and the threshold voltage deviation of the second transistor M2 is improved.

[0056] The potential of the first fixed potential signal V1 is different from the potential of the second fixed potential signal V2.

[0057] It can be understood that in the shift register unit 300, the control signals output by the first output unit 10 and the second output unit 20 are usually different. Therefore, in the shift register unit 300, the opening periods of the first output unit 10 and the second output unit 20 are usually different, and the potentials connected to the respective poles of the first transistor M1 in the first output unit 10 and the second transistor M2 in the second output unit 20 are different. By setting the potential of the first fixed potential signal V1 to be different from the potential of the second fixed potential signal V2, the first fixed potential signal V1 and the second fixed potential signal V2 can be flexibly set according to the actual output of the shift register unit 300.

[0058] In the embodiments of the present application, the first transistor M1 in the first output unit 10 includes the first floating gate M12, and the second transistor M2 in the second output unit 20 includes the second floating gate M22. The first floating gate M12 and the second floating gate M22 are located on the side close to the substrate A10, which is beneficial to realize the anti-static performance of the driving circuit. When there is static electricity, the static electricity can be first received by the first floating gate M12 or the second floating gate M22, which is a bottom gate, so as to avoid that the static electricity or strong electric field directly breaks through the transistor device, thereby causing damage to the device and affecting the driving work of the shift register unit 300; and it is beneficial to protect the device and ensure the normal operation of the display panel 100.

[0059] And, the first fixed potential V1 received by the first floating gate M12 of the first transistor M1 is different from the second fixed potential V2 received by the second floating gate M22 of the second transistor M2, so that the first fixed potential signal V1 and the second fixed potential signal V2 can be flexibly set according to the actual situation of the shift register unit 300. Avoiding the situation that the bottom gates of all transistors are connected to the same potential, and further avoiding the problem of aggravating the threshold voltage positive bias or negative bias of at least part of the transistors when using four-terminal devices. It is beneficial to improve the influence of the threshold voltage bias of the first transistor and the second transistor by adjusting the first fixed potential V1 and the second fixed potential V2, and it is beneficial to improve the accuracy of the output control signal of the shift register unit 300.

[0060] In an embodiment of the present application, as shown in Figure 3 The first electrode of the first transistor M1 is electrically connected with the first signal line SL1, and the second electrode is electrically connected with the output end 301 of the shift register unit 300.

[0061] When the first gate M11 of the first transistor M1 receives the enable signal, the first transistor M1 is turned on, and the first signal line SL1 transmits the signal to the output end 301 of the shift register unit through the first transistor M1.

[0062] The first electrode of the second transistor M2 is electrically connected with the second signal line SL2, and the second electrode is electrically connected with the output end 301 of the shift register unit 300.

[0063] When the second gate M21 of the second transistor M2 receives the enable signal, the second transistor M2 is turned on, and the second signal line SL2 transmits the signal to the output end 301 of the shift register unit through the second transistor M2.

[0064] The channel type of the first transistor M1 is the same as that of the second transistor M2.

[0065] Optionally, the first transistor M1 and the second transistor M2 are both P-type transistors. Of course, the first transistor M1 and the second transistor M2 can also be both N-type transistors.

[0066] The channel type of the first transistor M1 is the same as that of the second transistor M2, but the control signal lines connected are different, so that the first transistor M1 and the second transistor M2 will not be turned on at the same time.

[0067] It should be noted that in some other embodiments, the channel type of the first transistor M1 and the second transistor M2 can also be different.

[0068] In an embodiment of the present application, continuing to refer to Figure 3As shown, the first signal line SL1 transmits a first voltage signal VGH, and the second signal line SL2 transmits a second voltage signal VGL, the potential of the second voltage signal VGL is less than the potential of the first voltage signal VGH, the first voltage signal VGH can be a high level signal, such as 8V; and the second voltage signal VGL can be a low level signal, such as -7V. The driving circuit 200 is configured to output a light emitting control signal EMIT.

[0069] Optionally, in the light emitting control signal EMIT output by the driving circuit 200, a low level signal is configured to control the light emitting device to emit light, and a high level signal is configured to control the light emitting device to be turned off. In the driving circuit 200, the first signal line SL1 transmits a high level signal, and the second signal line SL2 transmits a low level signal.

[0070] In the operation of the driving circuit 200, when the first transistor M1 is turned on, the second transistor M2 is turned off, and the first transistor M1 receives the first voltage signal VGH transmitted by the first signal line SL1 and outputs the first voltage signal VGH to the output end 301 of the shift register unit 300; when the second transistor M2 is turned on, the first transistor M1 is turned off, and the second transistor M2 receives the second voltage signal VGL transmitted by the second signal line SL2 and outputs the second voltage signal VGL to the output end 301 of the shift register unit 300.

[0071] In the working time of the display panel 100, the light emitting time of the light emitting device is usually greater than the turn-off time, so that the first transistor M1 is in the off state for a long time and the second transistor M2 is in the on state for a long time. That is, the first gate M11 of the first transistor M1 receives a high level for a long time, which is easy to cause the threshold voltage of the first transistor M1 to be positively biased; and the second gate M21 of the second transistor M2 receives a low level for a long time, which is easy to cause the threshold voltage of the second transistor M2 to be negatively biased.

[0072] Therefore, for the first transistor M1, when the first floating gate M12 is connected to the first fixed potential signal V1, the threshold voltage of the first transistor M1 should be considered to be positively biased; and for the second transistor M2, when the second floating gate M22 is connected to the second fixed potential signal V2, the threshold voltage of the second transistor M2 should be considered to be negatively biased.

[0073] In an embodiment of the present application, as shown in Figure 3 the potential of the first fixed potential signal V1 is greater than or equal to the potential of the first voltage signal VGH transmitted by the first signal line SL1. The potential of the second fixed potential signal V2 is less than or equal to the potential of the second voltage signal VGL transmitted by the second signal line SL2.

[0074] In the first transistor M1, one pole connected to the first signal line SL1 is an active pole.

[0075] Optionally, when the potential of the first fixed potential signal V1 received by the first floating gate M12 of the first transistor M1 is greater than the first voltage signal VGH transmitted by the first signal line SL1, a negative bias effect is generated on the threshold voltage of the first transistor M1. In this way, the threshold voltage of the first transistor M1 is simultaneously affected by the positive bias and the negative bias, and the positive bias and the negative bias offset each other, thereby improving the positive bias of the threshold voltage of the first transistor M1.

[0076] Optionally, when the potential of the first fixed potential signal V1 received by the first floating gate M12 of the first transistor M1 is equal to the first voltage signal VGH transmitted by the first signal line SL1, the potential difference between the first fixed potential signal V1 received by the second gate M12 and the first voltage signal VGH is small, and after the first floating gate M12 is set, the further positive bias effect on the threshold voltage of the first transistor M1 is avoided.

[0077] In the second transistor M2, one pole connected with the second signal line SL2 is an active pole.

[0078] Optionally, when the potential of the second fixed potential signal V2 received by the second floating gate M22 of the second transistor M2 is less than the second voltage signal VGL transmitted by the second signal line SL2, a positive bias effect is generated on the threshold voltage of the second transistor M2. In this way, the threshold voltage of the second transistor M2 is simultaneously affected by the negative bias and the positive bias, and the positive bias and the negative bias offset each other, thereby improving the negative bias of the threshold voltage of the second transistor M2.

[0079] Optionally, when the potential of the second fixed potential signal V2 received by the second floating gate M22 of the second transistor M2 is equal to the second voltage signal VGL transmitted by the second signal line SL2, the potential difference between the second fixed potential signal V2 received by the second floating gate M22 and the second voltage signal VGL is small, and after the second floating gate M22 is set, the further negative bias effect on the threshold voltage of the second transistor M2 is avoided.

[0080] In the embodiment of the present application, the potential of the first fixed potential signal V1 is greater than or equal to the potential of the first voltage signal VGH. The potential of the second fixed potential signal V2 is less than or equal to the potential of the second voltage signal VGL. The potential of the first fixed potential signal V1 and the potential of the second fixed potential signal V2 are used to suppress the positive bias of the threshold voltage of the first transistor M1 and suppress the negative bias of the threshold voltage of the second transistor M2, so as to avoid other adverse effects on the driving circuit caused by the first floating gate M12 and the second floating gate M22 in addition to the electrostatic protection effect on the transistors. The applicability of the four-terminal device in the driving circuit 200 is improved, and the accuracy of the light-emitting control signal EMIT output by the driving circuit 200 is improved, so as to ensure the display effect of the display panel 100.

[0081] Figure 4 A schematic diagram of another shift register unit for embodiments of the present application is provided.

[0082] In an embodiment of the present application, as shown in Figure 4 The first floating gate M12 is electrically connected with the first signal line SL1, and the second floating gate M22 is electrically connected with the second signal line SL2.

[0083] In the technical solution, the first floating gate M12 is electrically connected with the first signal line SL1, so that the potential of the first floating gate M12 is the same as the potential of the active electrode in the first transistor M1, which is beneficial to avoid aggravating the threshold voltage shift of the first transistor M1. The second floating gate M22 is electrically connected with the second signal line SL2, so that the potential of the second floating gate M22 is the same as the potential of the active electrode in the second transistor M2, which is beneficial to avoid aggravating the threshold voltage shift of the second transistor M2. In addition, it is beneficial to reduce the voltage ports in the driving circuit 200, reduce the number of lines and interfaces in the circuit, reduce the circuit preparation cost, and improve the circuit utilization efficiency.

[0084] Figure 5 A schematic diagram of another shift register unit for embodiments of the present application is provided.

[0085] In an embodiment of the present application, as shown in Figure 5 The first signal line SL1 transmits a first voltage signal VGH, the second signal line SL2 transmits a clock signal XCK, and the driving circuit 200 is used to output a scan control signal SCAN.

[0086] In the driving circuit 200 for outputting the scan control signal SCAN, the present application takes a low-level signal in the scan control signal SCAN as an example for description, and the time when the scan control signal SCAN is at a high level is greater than the time when the scan control signal SCAN is at a low level.

[0087] When the first transistor M1 is turned on, the second transistor M2 is turned off, and the first transistor M1 receives the first voltage signal VGH transmitted by the first signal line SL1 and outputs it to the output end 301 of the shift register unit 300; when the second transistor M2 is turned on, the first transistor M1 is turned off, and the second transistor M2 receives the clock signal XCK transmitted by the second signal line SL2 and outputs it to the output end 301 of the shift register unit 300.

[0088] Because the time of the high level (non-enabled level, making the transistor off) in the scan control signal SCAN is greater than the time of the low level (enabled level, making the transistor on), the first transistor M1 is in the on state for a long time and the second transistor M2 is in the off state for a long time. That is, the first gate M11 of the first transistor M1 receives the low level for a long time, which easily makes the threshold voltage of the first transistor M1 negatively biased; the second gate M21 of the second transistor M2 receives the high level for a long time, which easily makes the threshold voltage of the second transistor M2 positively biased.

[0089] Therefore, for the first transistor M1, when the second gate M12 is connected to the first fixed potential signal V1, the negatively biased threshold voltage of the first transistor M1 should be considered to be improved; for the second transistor M2, when the fourth gate M22 is connected to the second fixed potential signal V2, the positively biased threshold voltage of the second transistor M2 should be considered to be improved.

[0090] Figure 6 A timing circuit diagram is provided in the embodiments of the present application.

[0091] In one embodiment of the present application, in combination with Figures 5-6 As shown in FIG. 2, in the on period t1 of the second output unit 200, the second signal line SL2 transmits the second voltage signal VGL, and the potential of the second voltage signal VGL is less than the potential of the first voltage signal VGH.

[0092] In the shift register unit 300, the clock signal XCK includes both the high level signal and the low level signal. Generally, in the shift register unit 300, the high level signal refers to the first voltage signal VGH, and the low level signal refers to the second voltage signal VGL.

[0093] The second signal line SL2 transmits the clock signal XCK, the high level signal included in the clock signal XCK is the first voltage signal VGH, the low level signal included in the clock signal XCK is the second voltage signal VGL, and the on period T1 of the second output unit 200 is the period in which the second transistor M2 is on, that is, the period in which the scan control signal SCAN output by the second output unit 200 is the low level signal.

[0094] In one embodiment of the present application, continuing to refer to Figures 5-6 As shown in FIG. 2, the potential of the first fixed potential signal V1 is less than the potential of the first voltage signal VGH transmitted by the first signal line SL1, and the potential of the second fixed potential signal V2 is greater than the potential of the second voltage signal VGL transmitted by the second signal line SL2.

[0095] One pole of the first transistor M1 connected to the first signal line SL1 is the source, and one pole of the second transistor M2 connected to the second signal line SL2 is the source.

[0096] The first fixed potential signal V1 received by the first floating gate M12 of the first transistor M1 has a potential less than the first voltage signal VGH, i.e., the potential of the first floating gate M12 is less than the active potential in the first transistor M1, which has a positive bias effect on the threshold voltage of the first transistor M1. In this way, the threshold voltage of the first transistor M1 is simultaneously affected by the positive bias and the negative bias, which can offset the positive bias and the negative bias, thereby improving the threshold voltage negative bias of the first transistor M1.

[0097] The second fixed potential signal V2 received by the second floating gate M22 of the second transistor M2 has a potential greater than the second voltage signal VGL transmitted by the second signal line SL2, which has a negative bias effect on the threshold voltage of the second transistor M2. In this way, the threshold voltage of the second transistor M2 is simultaneously affected by the positive bias and the negative bias, which can offset the positive bias and the negative bias, thereby improving the threshold voltage positive bias of the second transistor M2.

[0098] In the embodiment of the present application, the first fixed potential signal V1 has a potential less than the first voltage signal VGH. The second fixed potential signal V2 has a potential greater than the second voltage signal VGL. This is advantageous in that the potentials of the first fixed potential signal V1 and the second fixed potential signal V2 can be used to improve the threshold voltage negative bias of the first transistor M1 and improve the threshold voltage positive bias of the second transistor M2, thereby improving the accuracy of the scan control signal SCAN output by the driving circuit 200 and ensuring the display effect of the display panel 100. This is also advantageous in that it can avoid aggravating the threshold voltage negative bias of the first transistor M1 or the threshold voltage positive bias of the second transistor M2 after the first floating gate M12 and the second floating gate M22 are prepared. This is also advantageous in that it can ensure that the first floating gate M12 and the second floating gate M22 can not have other adverse effects on the driving circuit in addition to the electrostatic protection effect on the transistor. This is also advantageous in that it can provide the applicability of the four-terminal device in the driving circuit 200.

[0099] Figure 7 Another schematic diagram of a shift register unit provided in an embodiment of the present application.

[0100] In one embodiment of the present application, as shown in Figure 7 The second floating gate M22 is electrically connected to the first signal line SL1.

[0101] In the technical solution, the second floating gate M22 of the second transistor M2 is electrically connected with the first signal line SL1, so that the potential of the second floating gate M22 is always the same as the first voltage signal VGH. As known from the above, the first signal line SL1 is used to transmit the first voltage signal VGH, and the first voltage signal VGH is a high-level signal. In the shift register unit 300, the high-level signal generally refers to the first voltage signal VGH, and the low-level signal generally refers to the second voltage signal VGL. Therefore, the clock signal XCK transmitted by the second voltage signal line SL2 includes a high-level signal and a low-level signal, and can also be expressed as that the clock signal XCK includes the first voltage signal VGH and the second voltage signal VGL, and the potential of the first voltage signal VGH is higher than that of the second voltage signal VGL.

[0102] When the active electrode of the second transistor M2 receives the clock signal XCK in the high level, that is, the first voltage signal VGH, because the potential of the second floating gate M22 is also the first voltage signal VGH, the voltage difference between the active electrode of the second transistor M2 and the second floating gate M22 is small, which can avoid that the second floating gate M22 further positively biases the threshold voltage of the second transistor M2. When the active electrode of the second transistor M2 receives the clock signal XCK in the low level, that is, the second voltage signal VGL, because the potential of the second floating gate M22 is a high-level signal, that is, the first voltage signal VGH is higher than the second voltage signal VGL, the second floating gate M22 negatively biases the threshold voltage of the second transistor M2. In this way, the threshold voltage of the second transistor M2 is simultaneously positively and negatively biased, which can offset the positive and negative biases, thereby inhibiting the positive bias of the threshold voltage of the second transistor M2. In addition, the second floating gate M22 is directly electrically connected with the first signal line SL1, which is beneficial to reduce the voltage port in the driving circuit 200, reduce the number of lines and interfaces in the circuit, reduce the circuit preparation cost, and improve the circuit utilization efficiency.

[0103] It should be noted that the threshold voltage of the first transistor M1 is negatively biased, which can make the first floating gate M12 of the first transistor M1 receive a voltage signal smaller than the first voltage signal VGH, so that the first floating gate M12 positively biases the threshold voltage of the first transistor M1, thereby offsetting the positive and negative biases and further inhibiting the negative bias of the first transistor M1. Because in the shift register unit 300, the second voltage signal VGL is smaller than the first voltage signal VGH, the first floating gate M11 of the first transistor M1 can be electrically connected with the signal line that always transmits the second voltage signal VGL in the shift register unit 300. In this way, it is beneficial to improve the threshold voltage negative bias of the first transistor M1 to a certain extent, and it is also beneficial to further reduce the number of voltage ports and lines in the driving circuit 200, and further reduce the circuit preparation cost.

[0104] Figure 8 As shown in the circuit schematic of the shift register unit, Figure 3 As shown in the circuit schematic of the shift register unit, Figure 9 As shown in the circuit schematic of the shift register unit, Figure 8 As shown in the timing diagram of the shift register unit, Figure 10 As shown in the circuit schematic of the shift register unit, Figure 5 As shown in the circuit schematic of the shift register unit, Figure 11 As shown in the timing diagram of the shift register unit. Figure 10 As shown in the structure schematic of the transistor provided by an embodiment of the present application. Figure 12

[0105] In an embodiment of the present application, as shown in Figure 3 , Figure 5 , Figure 8 , Figure 10 The shift register unit 300 further comprises:

[0106] The first control unit 30 is electrically connected to the control end 103 of the first output unit 10, and the first control unit 30 is used to control the switching state of the first output unit 10.

[0107] The second control unit 40 is electrically connected to the control end 203 of the second output unit 20, and the second control unit 40 is used to control the switching state of the second output unit 20.

[0108] The first control unit 30 and the second control unit 40 each comprise at least one transistor, as shown in Figure 12 The transistor comprises an active layer M30 and a gate G1 and a floating gate G2 located on both sides of the active layer M30, the floating gate G2 of the transistor is located on the side of the active layer C1 of the transistor facing the substrate A10, the floating gate of the transistor receives a third fixed potential signal V3, the potential of the third fixed potential signal V3 is different from the potential of the first fixed potential signal V1, and is also different from the potential of the second fixed potential signal V2.

[0109] Of course, in some other embodiments, the third fixed potential signal V3 can be the same as the first fixed potential signal V1 or the second fixed potential signal V2.

[0110] Figure 8 The shift register unit 300 shown in can be used to output a light-emitting control signal EMIT, Figure 8 The first control unit 30 in comprises a third transistor M3 to an eighth transistor M8 and a twelfth transistor M12. The connection mode of the third transistor M3 to the eighth transistor M8 and the twelfth transistor M12 is as shown in Figure 8 ​As shown, the signals cooperatively transmitted by the third transistor M3 to the eighth transistor M8 and the twelfth transistor M12 can be used to control the switching state of the first output unit 10. Figure 8 The second control unit 40 in the second control unit 40 includes the ninth transistor, the tenth transistor M10, and the eleventh transistor M11, and the connection mode of the ninth transistor, the tenth transistor M10, and the eleventh transistor M11 is as shown in the following figure. Figure 8 As shown, the signals cooperatively transmitted by the ninth transistor, the tenth transistor M10, and the eleventh transistor M11 can be used to control the switching state of the second output unit 20.

[0111] The working process of the shift register unit 300 will be described below. Figure 9 The shift register unit 300 is used for Figure 8 The working process of the shift register unit 300 will be described below.

[0112] At the t2 stage, the trigger signal IN / STV is a high-level signal, the pulse signal CK is a low-level signal, the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are turned on, the first node N1 is set to a low-level state, the high-level signal transmitted by the trigger signal IN / STV sets the third node N3 to a high-level state, and the second transistor M2 is closed; the clock signal XCK transmits a high-level signal, the fourth transistor M4 and the tenth transistor M10 are closed, the second node N2 maintains a high-level state, and the first transistor M1 is also closed.

[0113] At the t3 stage, the pulse signal CK is a high-level signal, the clock signal XCK is a low-level signal, the fourth transistor M4 and the tenth transistor M10 are turned on, the second node N2 is pulled low, the third node N3 is pulled high, the first transistor M1 is turned on, and the second transistor M2 is closed, and the first transistor M1 transmits the first voltage signal VGH transmitted by the first signal line SL1 to the output end 301.

[0114] At the t4 stage, the pulse signal CK is a low-level signal, the clock signal XCK is a high-level signal, the trigger signal IN / STV writes the third node N3 high, the turned-on sixth transistor M6 transmits the second voltage signal VGL to write the first node N1 low; the fourth transistor M4 is closed, the second node N2 maintains the low-level state of the previous stage, the first transistor M1 is continuously turned on, the second transistor M7 is continuously closed, and the first transistor M2 transmits the first voltage signal VGH transmitted by the first signal line SL1 to the output end 301.

[0115] In the t5 stage, the pulse signal CK is a high level signal, the clock signal XCK is a low level signal, the fourth transistor M4 and the tenth transistor M10 are turned on, the second node N2 is pulled low, the third node N3 is pulled high, the first transistor M1 is turned on, the second transistor M2 is turned off, and the first transistor M1 transmits the first voltage signal VGH transmitted by the first signal line SL1 to the output end 301.

[0116] In the t6 stage, the pulse signal CK is a low level signal, the clock signal XCK is a high level signal, the trigger signal IN / STV pulls the third node N3 low, the third transistor M3 is turned on, the fourth transistor M4 is turned off, the second node N2 is pulled high by the first voltage signal VGH, the first transistor M1 is turned off, and the second transistor M2 is turned on. The second transistor M2 transmits the second voltage signal VGL transmitted by the second signal line SL2 to the output end 301.

[0117] In the t7 stage, the pulse signal CK is a high level signal, the clock signal XCK is a low level signal, and the third node N3 remains in a low level state due to the action of the first capacitor C1. At this time, the third transistor M3 is turned on, the second node N2 is continuously pulled high by the first voltage signal VGH, the first transistor M1 is turned off, and the second transistor M2 is turned on. The second transistor M2 transmits the second voltage signal VGL transmitted by the second signal line SL2 to the output end 301.

[0118] In the t8 stage, the pulse signal CK is a low level signal, the clock signal XCK is a high level signal, the trigger signal IN / STV pulls the third node N3 low, the third transistor M3 is continuously turned on, the fourth transistor M4 is turned off, and the second node N2 is pulled high by the first voltage signal VGH. The first transistor M1 is turned off, and the second transistor M2 is turned on. The second transistor M2 transmits the second voltage signal VGL transmitted by the second signal line SL2 to the output end 301.

[0119] Figure 10 The shift register unit 300 shown can be used to output a scan control signal SCAN, Figure 10 The first control unit 30 in the first output unit 10 includes a third sub-transistor M3' and a sixth sub-transistor M6'. The connection mode of the third sub-transistor M3' and the sixth sub-transistor M6' is as shown in Figure 10 The connection mode of the third sub-transistor M3' and the sixth sub-transistor M6' is as shown in Figure 10 The signal cooperatively transmitted by the third sub-transistor M3' and the sixth sub-transistor M6' can be used to control the switching state of the first output unit 10. Figure 10 The second control unit 40 in the second output unit 20 includes a fourth sub-transistor M4', a fifth sub-transistor M5', a seventh sub-transistor M7', and an eighth sub-transistor M8'. The connection mode of the fourth sub-transistor M4', the fifth sub-transistor M5', the seventh sub-transistor M7', and the eighth sub-transistor M8' is as shown in Figure 10As shown, the signals transmitted in cooperation by the fourth sub-transistor M4', the fifth sub-transistor M5', the seventh sub-transistor M7' and the eighth sub-transistor M8' can be used to control the switching state of the second output unit 20.

[0120] The working process of the shift register unit 300 will be described below in combination with Figure 11 The shift register unit 300 is used to control the switching state of the second output unit 20. Figure 10 The working process of the shift register unit 300 will be described below in combination with

[0121] At the t9 stage, the trigger signal IN / STV is a low-level signal, the pulse signal CK is a low-level signal, and the clock signal XCK is a high-level signal. Then the third sub-transistor M3' and the fifth sub-transistor M5' are turned on, and the gates of the first transistor M1 and the second transistor M2 both receive the low-level signal, so that the first transistor M1 and the second transistor M2 are both turned on. During this period, the signal output by the first transistor M1 and transmitted by the first signal line SL1 is the first voltage signal VGH, i.e. a high-level signal; the signal output by the second transistor M2 and transmitted by the second signal line SL2 is the clock signal XCK, which is also a high-level signal. Therefore, at the t9 stage, the output end 301 of the shift register unit 300 outputs a high-level signal.

[0122] At the t10 stage, the trigger signal IN / STV is a high-level signal, the pulse signal CK is a high-level signal, and the clock signal XCK is a low-level signal. During this period, the gate of the second transistor M2 remains low-level due to the action of the second capacitor C2, i.e. the second transistor M2 is continuously turned on. At this time, the fourth sub-transistor M4' is always on because the gate of the fourth sub-transistor M4' continuously receives the second voltage signal VGL, and a path is formed between the gate of the second transistor M2 and the gate of the sixth sub-transistor M6', so that the sixth sub-transistor M6' is also turned on. The high-level signal of the trigger signal IN / STV at this time can be transmitted along the first sub-transistor M6' to the gate of the first transistor M1, and the first transistor M1 is turned off. Since the clock signal XCK at this time is a low-level signal, at the t10 stage, the second transistor M2 is turned on and outputs the clock signal XCK transmitted by the second signal line SL2, and the output end 301 of the shift register unit 300 outputs a low-level signal.

[0123] During stage t11, the trigger signal IN / STV is high, the pulse signal CK is low, and the clock signal XCK is high. During this period, the third sub-transistor M3' and the fifth sub-transistor M5' are turned on. The high-level trigger signal IN / STV is output along the fifth sub-transistor M5' to the gate of the second transistor M2, turning off the second transistor M2. The first voltage signal VGL is output along the third sub-transistor M3' to the gate of the first transistor M1, turning on the first transistor M1 and outputting the first voltage signal VGL transmitted via the first signal line SL1. Therefore, during stage t11, the output terminal 301 of the shift register unit 300 outputs a high-level signal.

[0124] Figure 13 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 14 This is a timing diagram of a pixel circuit provided in an embodiment of this application.

[0125] like Figure 13 As shown, the pixel circuit 400 includes transistors T1-T7, wherein transistor T3 is used to generate a light-emitting driving current to drive the light-emitting device 500 to emit light. Transistor T1 is used to receive the power supply voltage signal PVDD. When transistor T1 receives the light-emitting control signal EMIT output by the shift register unit 300 as an enable signal, it turns on and transmits the power supply voltage signal PVDD to transistor T3. The third fixed voltage signal V3 can be equal to the power supply voltage signal PVDD.

[0126] Transistor T2 is used to receive the data voltage Vdata, and the scan control signal SCAN output by the shift register unit 300 includes the control signals S1-S2 from the pixel circuit 400. Combined with... Figure 14As shown, the working process of the pixel circuit 400 in a frame is E0-E2. In the E0 stage, the light emitting control signal EMIT is a non-enabling signal, the control signal S1 is also a non-enabling signal, and the control signal S2 is an enabling signal. Then the transistor T4 is turned on, and the transistor T4 is used to transmit the reset voltage Vref1 to the gate of the transistor T3, so as to reset the gate of the transistor T3. In the E1 stage, the light emitting control signal EMIT is a non-enabling signal, the control signal S2 is changed to a non-enabling signal, and the control signal S1 is changed to an enabling signal. Then the transistors T2, T5 and T7 are turned on. The transistor T2 is used to transmit the data voltage Vdata to the transistor T3, and the data voltage Vdata can be used to control the size of the light emitting driving current generated by the transistor T3, so as to control the light emitting brightness of the light emitting device 500. The transistor T5 is used to compensate the threshold voltage of the transistor T3. The transistor T7 is used to transmit the reset voltage Vref2 to the first electrode 5001 of the light emitting device 500, so as to reset the first electrode 5001 of the light emitting device 500. In the E2 stage, the control signal S1 is changed to a non-enabling signal, the control signal S2 is also a non-enabling signal, and the light emitting control signal EMIT is changed to an enabling signal. Then the transistors T1 and T6 are turned on. The transistor T1 is turned on and transmits the power voltage signal PVDD to the transistor T3. The transistor T6 is used to control whether the light emitting driving current generated by the transistor T3 is output to the first electrode 5001 of the light emitting device 500. Then in the E2 stage, the light emitting control signal EMIT signal output by the shift register unit 300 makes the transistor T6 conduct, the light emitting driving current is transmitted to the light emitting device 500, and the light emitting device 500 emits light.

[0127] In the embodiments of the present application, the first control unit 30 and the second control unit 40 each include at least one transistor, and the structure of the transistor is provided with a floating gate G2, and the floating gate G2 is connected to the third fixed potential signal V3. This is beneficial to avoid the transistor in the first control unit 30 and the second control unit 40 from being affected by a strong electric field and avoid static electricity from damaging the transistor. In addition, the third fixed potential signal V3 is different from the first fixed potential signal V1 and the second fixed potential signal V2. This is beneficial to flexibly set the potential connected to each floating gate G2 and avoid the threshold voltage of the transistor from being positively or negatively biased.

[0128] In one embodiment of the present application, the first signal line SL1 transmits a first voltage signal VGH; and in the opening period T1 of the second output unit 20, the second signal line SL2 transmits a second voltage signal VGL, and the potential of the first voltage signal VGH is greater than the potential of the second voltage signal VGL.

[0129] The potential of the third fixed potential signal V3 is less than the potential of the first voltage signal VGH and greater than the potential of the second voltage signal VGL.

[0130] The first voltage signal VGH has a higher potential level in the shift register unit 300, and the second voltage signal VGL has a lower potential level in the shift register unit 300, so that there is a higher threshold shift risk when the floating gate of the transistor in the first control unit 30 and the second control unit 40 is connected to the first voltage signal VGH or the second voltage signal VGL.

[0131] In the embodiments of the present application, a third fixed potential signal V3 is selected, and the potential of the third fixed potential signal V3 is set to be less than the first voltage signal VGH and greater than the second voltage signal VGL, which is beneficial to avoid the threshold shift risk of the transistor in the first control unit 30 and the second control unit 40, and is beneficial to reduce the influence of the third fixed potential signal V3 connected to the floating gate on the threshold positive shift or negative shift of the transistor.

[0132] In an embodiment of the present application, continuing to refer to Figures 8-9 As shown in the figure, the third fixed potential signal V3 is a power voltage signal PVDD.

[0133] In the embodiments of the present application, the third fixed potential signal V3 connected to the floating gate G2 of the transistor in the first control unit 30 and the second control unit 40 is set to be the power voltage signal PVDD, and the third fixed potential signal V3 is the same as the power voltage signal PVDD of the display panel 100, which is beneficial to reduce the types of output voltage signals, reduce the circuit complexity of the shift register unit 300, and reduce the preparation cost and circuit operation cost.

[0134] Figure 15 A schematic diagram of a display device provided in an embodiment of the present application is provided.

[0135] An embodiment of the present application provides a display device 600, as shown in the figure, which includes the display panel 100 provided in the above embodiments. The display device 600 provided in the embodiments of the present application can be a mobile phone, and in addition, the display device 600 provided in the embodiments of the present application can also be a computer, a television, or the like. Figure 15 As shown in the figure, the third fixed potential signal V3 is a power voltage signal PVDD.

[0136] In the display device 600, the first transistor M1 in the first output unit 10 includes a first floating gate M12, and the second transistor M2 in the second output unit 20 includes a second floating gate M22, and the first floating gate M12 and the second floating gate M22 are located on the side close to the substrate A10, which is beneficial to realize the anti-static performance of the driving circuit. When there is static electricity, the static electricity can be first received by the first floating gate M12 or the second floating gate M22, which is a bottom gate, so as to avoid that the static electricity or strong electric field directly breaks through the transistor device, thereby causing damage to the device and affecting the driving work of the shift register unit 300; and it is beneficial to protect the device and ensure the normal operation of the display panel 100.

[0137] And, the first fixed potential V1 received by the first floating gate M12 of the first transistor M1 is different from the second fixed potential V2 received by the second floating gate M22 of the second transistor M2, so that the first fixed potential signal V1 and the second fixed potential signal V2 can be flexibly set according to the actual situation of the shift register unit 300. Avoid the situation that the bottom gates of all transistors are connected to the same potential, and further avoid the problem that the threshold voltage of at least part of the transistors is positively or negatively biased when a four-terminal device is used. It is beneficial to improve the influence of the threshold voltage bias of the first transistor and the second transistor by adjusting the first fixed potential V1 and the second fixed potential V2, and it is beneficial to improve the accuracy of the output control signal of the shift register unit 300.

[0138] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that, The system includes a substrate and a driving circuit located on one side of the substrate. The driving circuit includes multiple cascaded shift register units, each shift register unit comprising: A first output unit, wherein the input terminal of the first output unit is electrically connected to a first signal line and the output terminal is electrically connected to the output terminal of the shift register unit; the first output unit includes a first transistor, which is connected in series between the first signal line and the output terminal of the shift register unit. The first transistor includes a first active layer and a first gate and a first floating gate located on opposite sides of the first active layer. The first floating gate is located on the side of the first active layer closer to the substrate. The first gate is used to receive a control signal, and the first floating gate is used to receive a first fixed potential signal. The second output unit has its input terminal electrically connected to the second signal line and its output terminal electrically connected to the output terminal of the shift register unit. The second output unit includes a second transistor connected in series between the second signal line and the output terminal of the shift register unit. The second transistor includes a second active layer and a second gate and a second floating gate located on opposite sides of the second active layer. The second floating gate is located on the side of the second active layer closer to the substrate. The second gate is used to receive a control signal, and the second floating gate is used to receive a second fixed potential signal. A first control unit, the output terminal of which is electrically connected to the control terminal of the first output unit, is used to control the switching state of the first output unit; The second control unit has its output terminal electrically connected to the control terminal of the second output unit, and the second control unit is used to control the switching state of the second output unit; Wherein, the first fixed potential signal and the second fixed potential signal have different potentials; the first control unit and the second control unit each include at least one transistor, the transistor includes an active layer and a gate and a floating gate located on both sides of the active layer, the floating gate of the transistor is located on the side of its active layer facing the substrate, and the floating gate of the transistor receives a third fixed potential signal, the third fixed potential signal being a power supply voltage signal.

2. The display panel according to claim 1, characterized in that, The first terminal of the first transistor is electrically connected to the first signal line, and the second terminal is electrically connected to the output terminal of the shift register unit; the first terminal of the second transistor is electrically connected to the second signal line, and the second terminal is electrically connected to the output terminal of the shift register unit. The first transistor and the second transistor have the same channel type.

3. The display panel according to claim 1, characterized in that, The first signal line transmits a first voltage signal, the second signal line transmits a second voltage signal, the potential of the second voltage signal is less than the potential of the first voltage signal, and the driving circuit is used to output a light-emitting control signal.

4. The display panel according to claim 3, characterized in that, The potential of the first fixed potential signal is greater than or equal to the potential of the first voltage signal transmitted by the first signal line, and the potential of the second fixed potential signal is less than or equal to the potential of the second voltage signal transmitted by the second signal line.

5. The display panel according to claim 4, characterized in that, The first floating gate is electrically connected to the first signal line, and the second floating gate is electrically connected to the second signal line.

6. The display panel according to claim 2, characterized in that, The first signal line transmits a first voltage signal, the second signal line transmits a clock signal, and the driving circuit is used to output a scan control signal.

7. The display panel according to claim 6, characterized in that, During the on-time of the second output unit, the second signal line transmits a second voltage signal, the potential of which is less than that of the first voltage signal.

8. The display panel according to claim 7, characterized in that, The potential of the first fixed potential signal is less than the potential of the first voltage signal transmitted by the first signal line, and the potential of the second fixed signal is greater than the potential of the second voltage signal transmitted by the second signal line.

9. The display panel according to claim 8, characterized in that, The second floating gate is electrically connected to the first signal line.

10. The display panel according to claim 1, characterized in that, The potential of the third fixed potential signal is different from the potential of the first fixed potential signal and also different from the potential of the second fixed signal.

11. The display panel according to claim 10, characterized in that, The first signal line transmits a first voltage signal; during the turn-on period of the second output unit, the second signal line transmits a second voltage signal, and the potential of the first voltage signal is greater than the potential of the second voltage signal; The potential of the third fixed potential signal is less than the potential of the first voltage signal and greater than the potential of the second voltage signal.

12. The display panel according to claim 2, characterized in that, Both the first transistor and the second transistor are P-type transistors.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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