Compensation methods and storage media for display devices, electronic devices, and display panels.

Abstract

This application provides a compensation method and storage medium for a display device, an electronic device, a display panel, and a storage medium. The display device includes: a display panel; a logic integrated circuit configured to monitor the common electrode signal of the display panel in the current frame, determine fluctuations in the common electrode voltage and a target gate line, and issue a first determination signal or a second determination signal; and a compensation structure configured to compensate for the fluctuating common electrode voltage in the next frame based on the first determination signal and the common electrode signal, so that the common electrode voltage fluctuations in the next frame at least partially cancel each other out at the target gate line; or, based on the second determination signal and a data signal, to adjust the polarity of the data signals of some data lines in the next frame, so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line. This application can solve the technical problem of display abnormalities in the prior art.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display device, electronic device, a compensation method for a display panel, and a storage medium. Background Technology

[0002] Liquid crystal display (LCD) technology boasts advantages such as thinness, wide viewing angles, and high resolution, and has gradually matured into a mature technology, gaining widespread market acceptance. However, downstream customers and consumers have increasingly higher demands for display panels (such as requirements for resolution and refresh rate). Summary of the Invention

[0003] This application proposes a compensation method and storage medium for a display device, electronic device, display panel.

[0004] In a first aspect, embodiments of this application provide a display device, comprising:

[0005] The display panel has a display area and includes several data lines and several gate lines arranged in a cross configuration, as well as a common electrode.

[0006] A logic integrated circuit, connected to a common electrode, is configured to monitor the common electrode signal of the current frame display panel, determine the fluctuation of the common electrode voltage and the target gate line, the position of the target gate line corresponding to the position of the common electrode voltage fluctuation; based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, issue a first determination signal; or, detect the data signals of each data line and issue a second determination signal based on the detection result and the gate line information of the target gate line.

[0007] The compensation structure, connected to the data line, the common electrode, and the logic integrated circuit respectively, is configured to acquire the data signal, the common electrode signal fed back by the common electrode, and the first determination signal or the second determination signal emitted by the logic integrated circuit. Based on the acquired first determination signal and the common electrode signal, it compensates for the fluctuating common electrode voltage in the next frame so that the common electrode voltage fluctuations in the next frame at least partially cancel each other out at the target gate line; or, based on the second determination signal and the data signal, it adjusts the polarity of the data signals of some data lines in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line.

[0008] Optionally, the first determination signal includes the amplitude information of the fluctuation of the common electrode voltage and the gate line information of the target gate line;

[0009] The compensation structure includes a power supply integrated circuit, which is connected to a common electrode and a logic integrated circuit respectively. It is configured to receive a first determination signal emitted by the logic integrated circuit and a common electrode signal fed back by the common electrode, and to perform inverse compensation on the fluctuating common electrode voltage in the next frame based on the first determination signal and the common electrode signal, so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line.

[0010] Optionally, the second determination signal includes data line information of the first target data line and gate line information of the target gate line, wherein the first target data line is a data line whose polarity needs to be reversed;

[0011] The compensation structure includes a timing controller and a data driving circuit. The timing controller is connected to the logic integrated circuit and the data driving circuit, respectively. The data driving circuit is connected to the logic integrated circuit and the data line, respectively.

[0012] The timing controller is configured to receive a second determination signal from the logic integrated circuit and output a polarity reversal signal and a data signal to the data driving circuit; the data driving circuit is configured to output the received data signal to the logic integrated circuit and, based on the received polarity reversal signal and data signal, adjust the polarity of the data signal of the first target data line in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line; the logic integrated circuit is configured to determine the voltage value and polarity of the data signal of each data line according to the received data signal, determine the second target data line, the voltage value and / or polarity of the data signal of the second target data line changes at the target gate line, and determine the first target data line according to the second target data line, the first target data line including at least one second target data line.

[0013] Optionally, the compensation structure includes a power supply integrated circuit, a data driving circuit, and a timing controller. The power supply integrated circuit is connected to a common electrode and a logic integrated circuit, respectively, and is also connected to the data driving circuit and the timing controller to supply power to the data driving circuit and the timing controller, respectively. The timing controller is connected to the logic integrated circuit and the data driving circuit, and the data driving circuit is connected to the data line and the logic integrated circuit, respectively.

[0014] Optionally, the first determination signal also includes inverting amplifier information, which includes the amplification factor of the inverting amplifier, and the amplification factor of the inverting amplifier is adapted to the magnitude of the fluctuation of the common electrode voltage.

[0015] The power supply integrated circuit includes multiple inverting amplifiers, each with a different amplification factor;

[0016] The power supply integrated circuit is configured to receive a first determination signal and a common electrode signal, and based on the first determination signal, determine an inverting amplifier, and use the inverting amplifier in the next frame to invert and amplify the common electrode voltage of the common electrode signal to compensate for the common electrode voltage.

[0017] Optionally, the amplification factor of the selected inverting amplifier is proportional to the fluctuation amplitude of the common electrode voltage; and / or,

[0018] The amplification factor of multiple inverting amplifiers is greater than or equal to 5 and less than or equal to 50.

[0019] Optionally, the inverting amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a reference electrode voltage, the common electrode is connected to the inverting input terminal to input a common electrode signal, and the output terminal is connected to the common electrode and configured to output a common electrode compensation signal amplified by inversion to the common electrode.

[0020] Secondly, embodiments of this application provide an electronic device, including the display device described above.

[0021] Thirdly, embodiments of this application provide a compensation method for a display panel, including:

[0022] The common electrode signal of the display panel in the current frame is monitored to determine the fluctuation of the common electrode voltage and the target gate line. The position of the target gate line corresponds to the position where the common electrode voltage fluctuates.

[0023] Based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, a first determination signal is issued; based on the acquired first determination signal and common electrode signal, the fluctuating common electrode voltage is compensated in the next frame so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line.

[0024] or,

[0025] The data signals of each data line are detected, and a second determination signal is issued based on the detection results and the gate line information of the target gate line. Based on the second determination signal and the data signal, the polarity of the data signals of some data lines is adjusted in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line.

[0026] Optionally, the common electrode signal of the display panel in the current frame is monitored to determine the fluctuation of the common electrode voltage and the target gate line, wherein the position of the target gate line corresponds to the position where the common electrode voltage fluctuates, including:

[0027] Obtain the common electrode signal of the display panel in the current frame;

[0028] If the common electrode voltage of the current frame display panel is pulled up or pulled down relative to the reference electrode voltage at the moment when at least one row of gate lines is turned on, the common electrode voltage fluctuates at the at least one row of gate lines, which is the target gate line.

[0029] Otherwise, the common electrode signal of the display panel in the current frame does not fluctuate.

[0030] Optionally, the fluctuation of the common electrode voltage at the target gate line relative to the reference electrode voltage is characterized by the variation of the voltage value of the data signal at each data line at the target gate line, including:

[0031] If the sum of the voltage changes of the data signals on each data line from the previous row of gate lines to the target gate line is greater than 0, then the common electrode voltage is pulled up relative to the reference electrode voltage at the target gate line; or...

[0032] If the sum of the voltage changes of the data signals on each data line from the previous row of gate lines to the target gate line is less than 0, then the common electrode voltage is pulled down relative to the reference electrode voltage at the target gate line; or...

[0033] If the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is equal to 0, then the common electrode voltage does not fluctuate relative to the reference electrode voltage at the target gate line.

[0034] Optionally, the data signals of each data line are detected, including:

[0035] Obtain the data signals of each data line on the display panel in the current frame;

[0036] Determine the voltage value and polarity of the data signal for each data line.

[0037] Optionally, based on the acquired first determination signal and common electrode signal, compensation is performed on the fluctuating common electrode voltage in the next frame so that the common electrode voltage fluctuations in the next frame at least partially cancel each other out at the target gate line, including:

[0038] Determine the magnitude of the fluctuation in the common electrode voltage.

[0039] Depending on the magnitude of the fluctuation, the common electrode voltage that has fluctuated is inverted in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line.

[0040] And / or,

[0041] Based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line, including:

[0042] Determine the data line information of the first target data line, wherein the first target data line includes a data line whose polarity needs to be reversed, and the data line whose polarity needs to be reversed includes at least one data signal whose voltage value or polarity changes at the target gate line;

[0043] In the next frame, the polarity of the data signal of the first target data line is adjusted so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line.

[0044] Optionally, if the common electrode voltage of the current frame display panel fluctuates relative to the reference electrode voltage at multiple gate lines, then the common electrode voltage at each of the multiple gate lines is compensated.

[0045] Based on the first determination signal and the common electrode signal, the fluctuating common electrode voltage is compensated in the next frame so that the fluctuation of the common electrode voltage in the next frame is at least partially canceled out at multiple target gate lines; or, based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuation of each data line is at least partially canceled out at multiple target gate lines.

[0046] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by an electronic device, implements the compensation method for the display panel as described above.

[0047] The beneficial technical effects of the technical solutions provided in this application include:

[0048] In this embodiment, the logic integrated circuit is connected to the common electrode, and the common electrode feeds back the common electrode signal to the logic integrated circuit. The logic integrated circuit is configured to monitor the common electrode signal of the current frame display panel and determine at which gate lines the common electrode voltage fluctuates. The compensation structure is connected to the common electrode, and the common electrode feeds back the common electrode signal to the compensation structure. The compensation structure is connected to the logic integrated circuit, and the compensation structure feeds back the received data signal to the logic integrated circuit so that the logic integrated circuit can analyze the data signal.

[0049] In this embodiment of the application, the logic integrated circuit is further configured to issue a first determination signal based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, or it is further configured to detect the data signals of each data line and issue a second determination signal based on the detection result and the gate line information of the target gate line.

[0050] When the logic integrated circuit issues a first determination signal, the compensation structure is configured to acquire the first determination signal and the common electrode signal. Furthermore, the compensation structure is also configured to compensate for the fluctuating common electrode voltage in the next frame based on the acquired first determination signal and the common electrode signal, so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line. The compensation structure is also connected to the data line, and the compensation structure provides the acquired data signal to the data line.

[0051] When the logic integrated circuit issues a second determination signal, the compensation structure is configured to acquire the second determination signal and the data signal. Furthermore, the compensation structure is also configured to adjust the polarity of the data signal of a portion of the data lines in the next frame based on the acquired second determination signal and the data signal, so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line. The compensation structure is connected to the common electrode, and the compensation structure provides the acquired common electrode signal to the common electrode.

[0052] By using the above settings, the fluctuating common electrode voltage can be compensated in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. Alternatively, the polarity of the data signal of some data lines can be adjusted in the next frame so that the fluctuations in the data voltage of each data line at least partially cancel each other out at the target gate line. This can reduce or even eliminate the phenomenon of ripple fluctuations in the common electrode voltage, solve the technical problem of display abnormality, and avoid weak lines or crosstalk.

[0053] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0054] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0055] Figure 1 This is a schematic diagram illustrating a windowed display of an Excel spreadsheet on a display panel, based on related technologies.

[0056] Figure 2 This is a real-life illustration of the weak line phenomenon caused by the dividing line of an Excel spreadsheet in related technologies;

[0057] Figure 3 A pixel architecture diagram illustrating the weak line phenomenon caused by Excel spreadsheet boundary lines in related technologies;

[0058] Figure 4 A schematic diagram illustrating the mechanism by which weak lines are caused by Excel spreadsheet boundaries in related technologies;

[0059] Figure 5 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0060] Figure 6 A schematic diagram illustrating the mechanism of a Vcom compensation scheme for a display device provided in an embodiment of this application;

[0061] Figure 7 A circuit diagram of a display device with a non-opening gate row provided for an embodiment of this application;

[0062] Figure 8 A circuit diagram of a gate-open row of a display device provided in an embodiment of this application;

[0063] Figure 9 A schematic diagram of the structure of a power integrated circuit for a display device provided in an embodiment of this application;

[0064] Figure 10 This is a schematic diagram illustrating the polarity reversal of the original data signal in a display device in related technologies;

[0065] Figure 11 This application provides a schematic diagram of the polarity reversal of a data signal in a display device.

[0066] Figure 12 A schematic diagram illustrating the mechanism of polarity reversal of the original data signal in a display device in related technologies;

[0067] Figure 13 A schematic diagram illustrating the mechanism of data signal polarity reversal in a display device provided in an embodiment of this application;

[0068] Figure 14 A flowchart illustrating a compensation method for a display panel provided in an embodiment of this application;

[0069] Figure 15 This is a schematic flowchart illustrating another compensation method for a display panel provided in an embodiment of this application.

[0070] Figure label:

[0071] 100 - Display device; 10 - Display panel; 11 - Display area; 12 - Common electrode; 20 - Logic integrated circuit; 31 - Power integrated circuit; 32 - Data drive circuit; 33 - Inverting amplifier; 34 - Non-inverting input terminal; 35 - Inverting input terminal; 36 - Output terminal; 40 - Timing controller. Detailed Implementation

[0072] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0073] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, “connected” or “coupled” as used herein may include wireless connection or wireless coupling. The term “and / or” as used herein means at least one of the items defined by the term; for example, “A and / or B” may be implemented as “A,” or as “B,” or as “A and B.”

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0075] Liquid crystal display (LCD) technology boasts advantages such as thinness, wide viewing angles, and high resolution, and has gradually matured into a mature technology, gaining widespread market acceptance. However, downstream customers and consumers have increasingly higher demands for display panels (such as requirements for resolution and refresh rate).

[0076] As display panels become increasingly faster, with higher refresh rates, higher resolutions, and larger sizes, the difference in grayscale between adjacent rows can cause voltage fluctuations in the display image. This can lead to voltage fluctuations on the common electrode, resulting in abnormal display images.

[0077] The following is combined with Figures 1 to 4 Explanation of the relevant technologies:

[0078] As display panel resolution and refresh rate increase, when an Excel spreadsheet is displayed in a window with a grayscale background, an abnormal display condition occurs. For example... Figure 1 As shown, the display panel shows an Excel spreadsheet window in the center, surrounded by a grayscale background. Figure 1 The image shows two Excel table boundaries. These boundaries can cause abnormal grayscale display, such as weak lines or crosstalk.

[0079] Specific display errors are as follows: Figure 2 and Figure 3 As shown, Figure 2 A real-life photo showing an abnormal display of weak lines caused by Excel spreadsheet dividing lines. Figure 2 The brighter areas are the Excel area, and the darker areas are the grayscale background area. The Excel table area has three Excel table boundaries, which cause weak lines to appear (weak lines appear in both the Excel area and the grayscale background area, with the weak lines being more obvious in the grayscale background area).

[0080] Specific examples Figure 3 As shown, the data signal uses a column-flipping method. The nth row of the gate line is the Excel table boundary line. The Excel table boundary line represents one pixel bright and one pixel dark, cycling every two pixels. The table boundary line causes two weak lines to appear in the nth and (n+1)th rows of the gate line. These two weak lines will cause sub-pixel brightness or darkness display anomalies depending on the polarity of the data voltage charged to the sub-pixel, which is more obvious and easier to identify, especially in the grayscale area.

[0081] During the data writing process, when data is written to the row of gate lines corresponding to the Excel spreadsheet boundary, the data signal for that row of gate lines alternates between one pixel being bright and one pixel being dark, repeating in a cycle. This results in the data signal for that row of gate lines appearing to rise or fall overall. Through the coupling of the parasitic capacitance Cdc between the ITO (Indium Tin Oxide) layer used for the data signal and the ITO layer used for the common electrode (com) signal, ripple fluctuations occur in the common electrode voltage, causing display abnormalities for that row of gate lines. This is especially noticeable in the grayscale background area around the Excel spreadsheet, where the subpixels of these two rows of gate lines appear brighter or darker than expected.

[0082] Specifically, Figure 4 A schematic diagram explaining the mechanism of this display defect. Figure 4 S1 to S6 in the text represent respectively Figure 3 The Excel area has 6 data lines, and the polarity of the data lines is reversed column-wise. Rows n-1, n+1, n+2, etc. of the gate lines are displayed normally. An Excel table boundary line appears in row n of the gate lines. The Excel table boundary line changes from one pixel to one pixel, and the cycle is two pixels.

[0083] Figure 4In the diagram, Vdata+ and Vdata- represent the positive and negative polarities of the data signal, respectively. For example, Vdata+ is 3V, Vdata- is -3V, and Vcom is 0V.

[0084] Specifically, for S1, S2, and S3, from the (n-1)th row to the (n+2)th row of the gate line, these three data signals remain unchanged, maintaining either Vdata+ or Vdata- voltage. For S4, the (n-1)th row of the gate line has Vdata- voltage (-3V), the nth row has Vcom voltage (0V), and the (n+1)th and (n+2)th rows of the gate line have Vdata- voltage (-3V). For S5, the (n-1)th row of the gate line has Vdata+ voltage (+3V), the nth row has Vcom voltage (0V), and the (n+1)th and (n+2)th rows of the gate line have Vdata- voltage (+3V). For S6, the (n-1)th row of the gate line has Vdata- voltage (-3V), the nth row has Vcom voltage (0V), and the (n+1)th and (n+2)th rows of the gate line have Vdata- voltage (-3V).

[0085] Therefore, it's easy to see that the data signal at the Excel spreadsheet's boundary line has a cycle of 6 lines. From the (n-1)th row of the gate line to the nth row of the gate line, 3 data lines have a constant voltage, two data lines rise from -3V to 0V, and one data line falls from +3V to 0V. Overall, the data signal voltage is rising. There is generally a parasitic capacitance Cdc between the ITO layer used for the data lines and the ITO layer used for the COM signal. This parasitic capacitance Cdc receives rising coupling from the data signal, resulting in a positive voltage peak that deviates from the original Vcom voltage. This causes subpixels in the grayscale background area to appear darker or brighter. If the original data signal charging the subpixel is positive, the subpixel will appear darker; otherwise, it will appear brighter.

[0086] Similarly, from row n to row (n+1) of the gate lines, among these 6 data lines, 3 data line signal voltages remain constant, 2 data line signal voltages decrease from Vcom voltage (0V) to Vdata- voltage (-3V), and 1 data line signal voltage increases from Vcom voltage (0V) to Vdata+ voltage (+3V). Overall, the data signal voltage decreases. This parasitic capacitance Cdc couples with the decrease in the Vcom signal, causing subpixels in the grayscale background area to appear either too dark or too bright. If the original data signal charged to the subpixel is positive, then the subpixel will appear brighter; otherwise, it will appear darker.

[0087] In the (n+2)th row of subsequent gate lines, since the voltages of the 6 data signals remain unchanged, the voltage of the common electrode signal (Vcom) does not fluctuate. The same applies to subsequent gate lines, and will not be repeated here, unless a specific data signal appears again (such as when the voltage of the data signal is pulled up or down).

[0088] It should be noted that if the voltage of the coupled pull-up or pull-down common electrode signal can return to the original Vcom voltage within the charging time, then there will be no display defect. However, as display panel refresh rates and resolutions become higher and higher, and even as display panel sizes become larger, the voltage of the coupled pull-up or pull-down common electrode signal is difficult to recover within the required time, resulting in crosstalk problems in the display panel.

[0089] To address this issue, common methods include reducing the resistance of the common electrode and decreasing the coupling capacitance (Cdc). For example, an additional metal layer can be added to the ITO used for the common electrode signal to reduce resistance and thus shorten the signal recovery time. However, these methods increase the manufacturing process, complexity, and cost of the display panel.

[0090] Furthermore, it should be noted that because the size of an Excel spreadsheet window can be adjusted freely according to the user's habits, there is no fixed position for the Excel spreadsheet dividing line to appear in any row, making it difficult to accurately determine the location of any display anomalies.

[0091] As a common work software, Excel is prone to this kind of display anomaly. Therefore, display panel manufacturers, consumers, and downstream manufacturers all attach great importance to this issue, which urgently needs to be resolved.

[0092] The display device, electronic device, display panel compensation method, and storage medium provided in this application are intended to solve at least one of the above-mentioned technical problems in the prior art.

[0093] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0094] This application provides a display device, the structural schematic diagram of which is shown below. Figure 5 As shown, it includes: a display panel 10, a logic integrated circuit 20 and a compensation structure. The display panel 10 has a display area 11 and includes a plurality of data lines and a plurality of gate lines arranged in a cross configuration, as well as a common electrode 12.

[0095] The logic integrated circuit 20 is connected to the common electrode 12 and is configured to monitor the common electrode signal of the current frame display panel, determine the fluctuation of the common electrode voltage and the target gate line, the position of the target gate line corresponding to the position of the common electrode voltage fluctuation; based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, a first determination signal is issued; or, the data signals of each data line are detected, and a second determination signal is issued based on the detection result and the gate line information of the target gate line.

[0096] The compensation structure is connected to the data line, the common electrode 12, and the logic integrated circuit 20, respectively. It is configured to acquire the data signal, the common electrode signal fed back by the common electrode, and the first determination signal or the second determination signal issued by the logic integrated circuit. Based on the acquired first determination signal and the common electrode signal, it compensates for the fluctuating common electrode voltage in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. Alternatively, based on the second determination signal and the data signal, it adjusts the polarity of the data signal of some data lines in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line.

[0097] In this embodiment, the logic integrated circuit 20 is connected to the common electrode 12, and the common electrode 12 feeds back the common electrode signal to the logic integrated circuit 20. The logic integrated circuit 20 is configured to monitor the common electrode signal of the current frame display panel and determine at which gate lines the common electrode voltage fluctuates. The compensation structure is connected to the common electrode 12, and the common electrode 12 feeds back the common electrode signal to the compensation structure. The compensation structure is also connected to the logic integrated circuit 20, and the compensation structure feeds back the received data signal to the logic integrated circuit 20 for analysis.

[0098] In this embodiment, the logic integrated circuit 20 is further configured to issue a first determination signal based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, or it is further configured to detect the data signals of each data line and issue a second determination signal based on the detection result and the gate line information of the target gate line.

[0099] When the logic integrated circuit 20 issues a first determination signal, the compensation structure is configured to acquire the first determination signal and the common electrode signal. Furthermore, the compensation structure is also configured to compensate for the fluctuating common electrode voltage in the next frame based on the acquired first determination signal and the common electrode signal, so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line. The compensation structure is also connected to the data line, and the compensation structure provides the acquired data signal to the data line.

[0100] When the logic integrated circuit 20 issues a second determination signal, the compensation structure is configured to acquire the second determination signal and the data signal. Furthermore, the compensation structure is also configured to adjust the polarity of the data signal of a portion of the data lines in the next frame based on the acquired second determination signal and the data signal, so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line. The compensation structure is connected to the common electrode 12, and the compensation structure provides the acquired common electrode signal to the common electrode 12.

[0101] By using the above settings, the fluctuating common electrode voltage can be compensated in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. Alternatively, the polarity of the data signal of some data lines can be adjusted in the next frame so that the fluctuations in the data voltage of each data line at least partially cancel each other out at the target gate line. This can reduce or even eliminate the phenomenon of ripple fluctuations in the common electrode voltage, solve the technical problem of display abnormality, and avoid weak lines or crosstalk.

[0102] Optionally, in this embodiment, the fluctuation of the common electrode voltage includes information such as the location and amplitude of the fluctuation. The location of the common electrode voltage fluctuation and the target gate line can be determined by identifying which gate lines the common electrode voltage fluctuates at. The "which gate lines" in "where the common electrode voltage fluctuates" form the target gate line, and the location of the target gate line corresponds to the location of the common electrode voltage fluctuation.

[0103] It should be noted that, in this embodiment, the structure of the display panel 10 is described using the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example. In this embodiment, the gate line information includes the row information of the gate line, such as which row the gate line is in; the data line information includes the column information of the data line, such as which column the data line is in.

[0104] In this embodiment, the display panel 10 has a display area 11. The display panel 10 includes a plurality of data lines and a plurality of gate lines. The plurality of data lines and the plurality of gate lines are intersected to define a plurality of pixel areas. Each pixel area is provided with a pixel unit, and the corresponding pixel area is illuminated and displayed through the pixel unit. The display area 11 includes all pixel areas to realize the display of images and text in the display area 11.

[0105] Optionally, the multiple pixel areas may include multiple red pixel areas, multiple green pixel areas, and multiple blue pixel areas.

[0106] In this embodiment, when driving the display panel 10 to display, gate scan signals can be written to the gate lines line by line according to the image to be displayed, and data signals can be written to each data line simultaneously, so that the pixel units in the display panel 10 are lit up line by line. The gate scan signals are provided by the gate driving circuit, and the data signals are provided by the data driving circuit 32.

[0107] Optionally, in this embodiment, the gate driving circuit can be integrated into the gate driving chip or directly integrated onto the array substrate, and the data driving circuit 32 can be integrated into the data driving chip, depending on actual needs.

[0108] In the embodiments of this application, such as Figure 5 As shown, the display panel 10 also includes a common electrode 12 and pixel electrodes (not shown). The common electrode 12 is located on at least one side of the display area 11 and is disposed opposite to the pixel electrodes. The common electrode 12 is configured to apply a common voltage to generate an electric field with the pixel electrodes that drives the liquid crystal molecules in the liquid crystal layer (located between the common electrode 12 and the pixel electrodes) to deflect. The liquid crystal molecules change the transmittance of the liquid crystal layer by deflection, thereby achieving the display of a desired grayscale image.

[0109] It should be noted that in this embodiment, the structure of the display panel 10 (including the display area 11, several data lines, several gate lines, common electrode 12 and pixel electrode, etc.) is similar to that of the prior art, and will not be described again here.

[0110] Optionally, such as Figure 5 As shown in the embodiment of this application, the compensation structure includes a power integrated circuit 31, a data driving circuit 32, and a timing controller 40. The power integrated circuit 31 is connected to the common electrode 12 and the logic integrated circuit 20, respectively. The power integrated circuit 31 is also connected to the data driving circuit 32 and the timing controller 40 to supply power to the data driving circuit 32 and the timing controller 40, respectively. The timing controller 40 is connected to the logic integrated circuit 20 and the data driving circuit 32. The data driving circuit 32 is connected to the data line and the logic integrated circuit 20, respectively.

[0111] In this embodiment, the power supply integrated circuit 31 is connected to the common electrode 12, and the common electrode 12 feeds back the common electrode signal to the power supply integrated circuit 31. The power supply integrated circuit 31 is connected to the logic integrated circuit 20, and the power supply integrated circuit 31 can supply power to the logic integrated circuit 20. The power supply integrated circuit 31 is configured to acquire a first determination signal issued by the logic integrated circuit 20. When the logic integrated circuit 20 issues a second determination signal, the power supply integrated circuit 31 provides the common electrode signal fed back by the common electrode 12 to the common electrode 12. The timing controller 40 is connected to the logic integrated circuit 20 and is configured to acquire the second determination signal issued by the logic integrated circuit 20. The data driving circuit 32 is configured to acquire the polarity reversal signal and data signal output by the timing controller 40. The data driving circuit 32 is connected to the data line and the logic integrated circuit 20. The data driving circuit 32 feeds back the data signal to the logic integrated circuit 20 for the logic integrated circuit 20 to analyze the data signal. When the logic integrated circuit 20 issues the first determination signal, the data driving circuit 32 provides the acquired data signal to the data line.

[0112] The display device 100 includes a display panel 10, a logic integrated circuit 20, a data driving circuit 32, a timing controller 40, and a power integrated circuit 31. The power integrated circuit 31 supplies power to the timing controller 40, the data driving circuit 32, and the logic integrated circuit 20. The timing controller 40 provides the data driving circuit 32 with a polarity reversal signal and a reference data signal. The data driving circuit 32 either reverses the polarity of the data signals on the data lines of the display panel 10 or provides data signals to the data lines of the display panel 10.

[0113] Furthermore, the common electrode 12 of the display panel 10 feeds back the common electrode signal to the logic integrated circuit 20 and the power integrated circuit 31. The logic integrated circuit 20 simultaneously receives the data signal provided by the data driving circuit 32 and the common electrode signal fed back by the common electrode 12. The logic integrated circuit 20 monitors the common electrode signal fed back to it in real time. If there is no ripple fluctuation in the fed-back common electrode signal, the logic integrated circuit 20 does not take any action. If a ripple fluctuation in the common electrode voltage occurs when a certain row of gate lines is turned on in the nth frame, there are two solutions (Solution 1 and Solution 2 as follows). In some embodiments, the logic integrated circuit 20 immediately analyzes the data signal when the gate line of this row is turned on to determine whether it is an Excel spreadsheet boundary line. If it is determined to be yes, there are two solutions (Solution 1 and Solution 2 as follows); if it is determined not to be yes, it is ignored.

[0114] The two subsequent solutions are:

[0115] Option 1: The logic integrated circuit 20 calculates the magnitude of the Vcom voltage ripple in the nth frame and provides a first determination signal to the power integrated circuit 31 in the (n+1)th frame. The power integrated circuit 31 outputs the corresponding compensation to the common electrode 12 of the display panel 10. This corresponding compensation will accelerate the recovery of the Vcom ripple, so that the voltage fluctuation of the common electrode in the next frame will at least partially cancel each other out at the target gate line.

[0116] Option 2: Based on the data information detected in the nth frame, the logic integrated circuit 20 adjusts the polarity of the data signals of some data lines in the next frame, so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line.

[0117] It should also be noted that the logic integrated circuit 20 detects the ripple of the common electrode voltage in the (n+1)th frame, analyzes the data signal, and performs subsequent judgment actions, using either Scheme 1 or Scheme 2 in the same manner as the nth frame, and so on for subsequent frames. This allows for high-speed, efficient, real-time, and accurate circuit signal adjustments based on the size or dragging of the Excel spreadsheet window, improving or avoiding display anomalies caused by Excel spreadsheet boundaries.

[0118] It should be noted that, in the embodiments of this application, the gate line corresponding to the fluctuating common electrode signal specifically includes the Excel spreadsheet boundary line.

[0119] In one specific embodiment of this application, such as Figure 5 As shown, the first determination signal includes information on the amplitude of the fluctuation in the common electrode voltage (e.g., the magnitude of the fluctuation) and the gate line information of the target gate line. The compensation structure includes a power supply integrated circuit 31, which is connected to the common electrode 12 and the logic integrated circuit 20. The power supply integrated circuit 31 is configured to receive the first determination signal emitted by the logic integrated circuit and the common electrode signal fed back by the common electrode, and based on the first determination signal and the common electrode signal, to perform inverse compensation on the fluctuating common electrode voltage in the next frame, so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. At this time, the data driving circuit 32 provides the acquired data signal to the data line (corresponding to the above-described scheme one).

[0120] Specifically, such as Figure 6The diagram shows the Vcom compensation scheme used in Scheme 1. Specifically, in frame n, the display device 100 first monitors the common electrode signal of the display panel in the current frame through the logic integrated circuit 20 to detect whether there are abnormal fluctuations in the Vcom signal and determine which row of gate lines has a fluctuating common electrode signal. Further, based on the fluctuating common electrode signal, the gate lines with ripples are identified, for example, those appearing in rows 1000 (G1000) and 1001 (G1001). If so, the data signals of these two rows are analyzed to determine if they are the grayscale background data signal and the Excel table boundary line data signal described earlier. This is relatively regular and easy to detect; the only issue is the mixing ratio of the grayscale background data signal and the Excel table boundary line data signal. This mixing ratio is determined by the user's habits (adjusting the display window to scale the Excel table to a suitable position) and is subjective. If the detection confirms that the Vcom ripple of these two lines is caused by the specific data signal of these two lines of gate signals (G1000 and G1001), then the display device is required to compensate for the Vcom signal when these two lines of gate lines (G1000 and G1001) are turned on starting at frame n+1.

[0121] In frame n+1, when rows G1000 and G1001 are enabled, the Vcom voltage output should be the opposite of the detected Vcom signal in frame n. The common electrode voltage and ripple shape in rows G1000 and G1001 of frames n+1 and n should be either opposite or a multiple of each other (the exact relationship between the compensated Vcom voltage and the Vcom signal voltage in frame n can be adjusted based on the specific circumstances). The compensated Vcom signal voltage is pulled down by the data signal in rows G1000 and G1001. It's easy to see that compared to the uncompensated Vcom signal, it's easier to recover the original Vcom signal voltage.

[0122] Simultaneously, the logic integrated circuit 20 of the display device 100 is required to continue detecting other gate lines where Vcom ripples appear, and whether they are specific data signals. If they continue to appear in rows G1000 and G1001, then in the (n+2)th frame, the detected Vcom ripples are amplified and compensated in reverse when the gate lines in these two rows are turned on. Otherwise, Vcom compensation is performed when the gate lines of newly appearing Vcom ripples are turned on in the (n+2)th frame, and the old compensation in the (n+1)th frame is canceled. In this way, when the user drags the Excel spreadsheet in windowed mode, the gate lines where the Excel spreadsheet boundary appears will definitely change with each frame, but the Vcom compensation mentioned above will also change with the change of the Excel spreadsheet boundary. Until the user stops dragging the Excel spreadsheet, the Excel spreadsheet boundary is fixed on certain gate lines. In this way, the Vcom compensation proposed in Scheme 1 can be performed on fixed gate lines, perfectly solving the problem of Vcom fluctuation. Although dragging the Excel spreadsheet previously caused some fluctuations in the Vcom signal, this time was during non-user experience and did not affect the user experience. Once the Excel spreadsheet is finished being dragged out, the Vcom signal compensation can immediately and efficiently take effect.

[0123] It should also be noted that although the Vcom signal is compensated in specific gate-enabled rows (e.g., rows G1000 + G1001), and the Vcom signal is also panel-wide, it does not affect the normal brightness of pixels on other non-enabled gate lines. See [link to explanation] for details. Figure 7 and Figure 8 .like Figure 7 This shows a row where the gate is not turned on, and the pixel TFT (Thin Film Transistor) is in the off state, while... Figure 8 The diagram shows the gate-on row, where the pixel TFT is in the on state.

[0124] Assuming the data signal is supplied with a voltage of 3V, if the Vcom signal fluctuates, for example, by being pulled up from 0V to 1V, in Figure 7 For pixels in rows where the gate is not turned on, the pixel voltage is coupled from 3V to 4V due to the coupling between the storage capacitor and the liquid crystal capacitor. At this point, it's easy to see that although the Vcom signal changes, the voltage difference across the liquid crystal remains the same as the original value of 3V, so the pixel brightness does not change. Afterwards, Vcom returns to normal, from 1V back to 0V, and the pixel voltage is coupled back to 3V. Thus, the voltage difference across the liquid crystal remains 3V, and the pixel brightness still does not change. Figure 8In the case of a pixel in the open row, Vcom rises from 0V to 1V. Although the transient pixel voltage will also change from 3V to 4V, since the TFT is in the open state at this time, the pixel voltage will quickly return to the data voltage, i.e., 3V. Assuming that the Vcom voltage has not returned to the original 0V voltage before the TFT is turned off, that is, after the pixel TFT is turned off, Vcom is 1V and the pixel voltage is 3V. Then the Vcom voltage recovers from 1V to 0V. Due to the capacitive coupling, the pixel voltage will change from 3V to 2V. In this way, the actual voltage difference on the liquid crystal will become smaller, and the pixel will become darker.

[0125] In this embodiment, the Vcom signal compensation for the gate lines (G1000 and G1001 rows) exhibiting Vcom ripples aims to quickly pull back the Vcom signal to its original voltage value before the pixel TFTs of those gate lines (G1000 and G1001 rows) are turned off. While compensation is performed on G1000 and G1001 rows, although the Vcom signal is panel-wide and simultaneously affects the Vcom voltage of other gate line pixels, as mentioned earlier, it does not affect the normal display brightness of the pixels.

[0126] Optionally, in the embodiments of this application, the common electrode voltage and ripple shape of the (n+1)th frame and the nth frame in rows G1000 and G1001 are required to be in opposite or multiple relationships. The technique to achieve the above-mentioned opposite or multiple relationship can be completely solved by using the inverting amplifier of the prior art.

[0127] Optionally, such as Figure 9 As shown in the embodiment of this application, the first determination signal further includes inverting amplifier information, which includes the amplification factor of the inverting amplifier. The amplification factor of the inverting amplifier is adapted to the magnitude of the fluctuation amplitude of the common electrode voltage. The power supply integrated circuit 31 includes multiple inverting amplifiers 33, which have different amplification factors. The power supply integrated circuit 31 is configured to receive the first determination signal and the common electrode signal, and based on the first determination signal, determine an inverting amplifier, and use the inverting amplifier in the next frame to perform inverting amplification compensation on the common electrode voltage of the common electrode signal.

[0128] In this embodiment, the inverting amplifier 33 can invert and compensate the common electrode voltage by a factor, enabling the common electrode voltage to recover to the original Vcom signal voltage more quickly and easily. By setting multiple inverting amplifiers 33 and selecting one of them to invert the common electrode voltage, an inverting amplifier 33 with a suitable amplification factor can be selected according to the magnitude of the fluctuation amplitude of the fluctuating common electrode signal. The selected inverting amplifier 33 provides suitable and accurate inversion compensation for the common electrode voltage, accelerating the recovery of the Vcom ripple and ensuring that the common electrode voltage fluctuations in the next frame at least partially cancel each other out at the target gate line, thus improving adaptability and flexibility.

[0129] Optionally, such as Figure 9 As shown in the embodiment of this application, the inverting amplifier 33 has a non-inverting input terminal 34, an inverting input terminal 35, and an output terminal 36. The non-inverting input terminal 34 is connected to the reference electrode voltage, the common electrode 12 is connected to the inverting input terminal 35 to input the common electrode signal, and the output terminal 36 is connected to the common electrode 12 and is configured to output the inverted amplified common electrode compensation signal to the common electrode.

[0130] In this embodiment, the non-inverting input terminal 34 is connected to the reference electrode voltage, and the common electrode 12 is connected to the non-inverting input terminal 34. The common electrode 12 inputs the common electrode signal in the positive phase to the inverting amplifier 33. If the power supply integrated circuit 31 receives the first determination signal from the logic integrated circuit 20, the inverting amplifier 33 amplifies the common electrode signal in reverse and outputs it to the common electrode 12 through the output terminal 36, performing inverting compensation for the fluctuating common electrode voltage in the next frame. If the logic integrated circuit 20 sends a second determination signal, the power supply integrated circuit 31 outputs the common electrode signal to the common electrode 12.

[0131] Optionally, in this embodiment, the amplification factor of the selected inverting amplifier 33 is proportional to the fluctuation amplitude of the common electrode voltage. The first determination signal also includes inverting amplifier information with an amplification factor adapted to the amplitude information (e.g., the magnitude of the fluctuation amplitude) of the common electrode voltage. The power supply integrated circuit 31 determines, based on the received first determination signal, that the corresponding inverting amplifier 33 performs inverse amplification of the common electrode signal.

[0132] In this embodiment, if the fluctuation amplitude of the fluctuating common electrode voltage is large, the amplification factor of the selected inverting amplifier 33 will be large; if the fluctuation amplitude of the fluctuating common electrode voltage is small, the amplification factor of the selected inverting amplifier 33 will be small. This configuration allows for the selection of an inverting amplifier 33 with a suitable amplification factor based on the magnitude of the fluctuation amplitude of the fluctuating common electrode voltage. By using the inverting amplifier 33 to perform appropriate and accurate inversion compensation of the common electrode voltage, the recovery of the Vcom ripple can be accelerated, ensuring that the fluctuations in the common electrode voltage of the next frame at least partially cancel each other out at the target gate line, thus improving adaptability and flexibility.

[0133] Optionally, in this embodiment of the application, the amplification factor of the plurality of inverting amplifiers 33 is greater than or equal to 5 and less than or equal to 50.

[0134] In this embodiment, if the amplification factor is less than 5, the amplification factor is too small, requiring a longer time to recover the Vcom ripple. If the amplification factor is greater than 50, the amplification factor is too large, making it difficult to control and prone to overcompensation. In this embodiment, the amplification factors of the multiple inverting amplifiers 33 are greater than or equal to 5 and less than or equal to 50. This allows for fast and accurate inverting compensation of the common electrode voltage, accelerating the recovery of the Vcom ripple, while also avoiding overcompensation.

[0135] Specifically, Figure 9 This is a schematic diagram of the internal structure of the power supply integrated circuit 31 according to an embodiment of this application. The power supply integrated circuit 31 receives the first determination signal provided by the logic integrated circuit 20 at the nth frame and the common electrode (Vcom) signal fed back by the common electrode 12 of the display panel 10. At the same time, it provides the common electrode 12 of the display panel 10 with either a Vcom signal or a Vcom compensation signal (the Vcom compensation signal is obtained by the power supply integrated circuit 31 by performing inverse compensation on the fluctuating common electrode signal based on the first determination signal and the common electrode signal). If the power supply integrated circuit 31 performs a compensation operation, it provides the common electrode 12 with a Vcom compensation signal; if the power supply integrated circuit 31 does not perform a compensation operation, it provides the common electrode 12 with a normal Vcom signal. The first determination signal provided by the logic integrated circuit 20 includes the main information of determining which row of gate lines has a common electrode voltage fluctuation, that is, determining which row of gate lines is the Excel table boundary line. The power integrated circuit 31 enables Vcom compensation when the gate line corresponding to the fluctuating common electrode voltage and its next gate line are turned on in the (n+1)th frame. For example, if the gate line in the nth row of the current frame is determined to be the Excel table boundary line, the power integrated circuit 31 enables Vcom compensation when the gate line in the nth row and the (n+1)th gate line are turned on in the (n+1)th frame.

[0136] In addition, the first determination signal provided by the logic integrated circuit 20 to the power integrated circuit 31 also contains an important piece of information: the logic integrated circuit 20 will calculate the magnitude of Vcom ripple (i.e. the magnitude of the fluctuation of the common electrode voltage) and select the corresponding inverting amplifier 33 in the power integrated circuit 31 according to the magnitude of Vcom ripple.

[0137] If the Vcom ripple is large, choose an inverting amplifier 33 with a higher gain; conversely, choose an inverting amplifier 33 with a lower gain. This is because when the Vcom ripple is large, using an inverting amplifier 33 with a higher gain will quickly recover the Vcom signal, while using an inverting amplifier 33 with a lower gain will take longer. When the Vcom ripple is small, using an inverting amplifier 33 with a higher gain may lead to overcompensation of the Vcom ripple. For example, if the peak-up Vcom ripple voltage is 1V and the original Vcom voltage is 0V, choosing an excessively large 50x inverting amplifier 33 will result in a peak-down Vcom voltage of -50V, leading to overcompensation and more severe Vcom ripple problems. Therefore, choosing a suitable inverting amplifier is crucial.

[0138] Figure 9 The diagram schematically illustrates inverting amplifiers 33 with a magnification of 50x, 20x, and 10x. In practice, the power supply integrated circuit 31 can contain inverting amplifiers with higher magnification, which are not shown in the diagram. Each inverting amplifier 33 has three terminals: a non-inverting input, an inverting input, and an output. The non-inverting input is connected to the reference electrode voltage, the inverting input is connected to the Vcom signal fed back from the common electrode 12, and the output signal is either the original Vcom signal or the Vcom compensation signal. It is important to note that the capacitor at the inverting input acts as a filter, and the ratio of resistors R2 and R1 represents the magnification factor. For example, if R2 is 50kΩ and R1 is 1kΩ, the magnification factor is 50x. The power supply integrated circuit 31 selects the appropriate inverting amplifier 33 based on the input information to output either the original Vcom signal or the Vcom compensation signal.

[0139] In another specific embodiment of this application, such as Figure 5As shown, the second determination signal includes data line information of the first target data line and gate line information of the target gate line, wherein the first target data line is a data line whose polarity needs to be reversed; the compensation structure includes a timing controller 40 and a data driving circuit 32, the timing controller 40 is connected to the logic integrated circuit 20 and the data driving circuit 32 respectively, and the data driving circuit 32 is connected to the logic integrated circuit 20 and the data line respectively; the timing controller 40 is configured to receive the second determination signal issued by the logic integrated circuit 20 and output a polarity reversal signal and a data signal to the data driving circuit 32; the data driving circuit 32 is configured to receive the second determination signal issued by the logic integrated circuit 20 and output a polarity reversal signal and a data signal to the data driving circuit 32; the data driving circuit 32 is configured to receive the second determination signal issued by the logic integrated circuit 20 and output a polarity reversal signal and a data signal to the data driving circuit 32. The data signal is output to the logic integrated circuit 20, and based on the received polarity reversal signal and data signal, the polarity of the data signal of the first target data line is adjusted in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line. The logic integrated circuit is configured to determine the voltage value and polarity of the data signal of each data line according to the received data signal, determine the second target data line, the voltage value and / or polarity of the data signal of the second target data line changes at the target gate line, and determine the first target data line according to the second target data line, the first target data line including at least one second target data line. At this time, the power supply integrated circuit 31 provides the acquired common electrode signal to the common electrode 12 (corresponding to the above-described scheme two).

[0140] Specifically, in the nth frame, the display device 100 first monitors the common electrode signal of the display panel of the current frame through the logic integrated circuit 20 to detect whether there is abnormal fluctuation in the Vcom signal and determine which row of gate lines has fluctuating common electrode signal. Further, it identifies the gate lines with Vcom ripples and detects whether the data signals of these two rows are specific Excel spreadsheet boundaries. If so, it adjusts the polarity of the data signals to cancel each other out, thus resolving the Vcom fluctuation problem.

[0141] Specifically, such as Figure 10 and Figure 11 As shown, the display device 100 first determines which column of data lines in the current frame constitutes the Excel table range, then determines which row of gate lines in the current frame is the Excel table boundary line, and then, starting in the next frame, adjusts or modifies the polarity of the data signals of a portion of the data columns of the gate lines within this Excel table range, so that the sum of the data voltage changes from the data signals of each column of data signals in the previous row of the gate line to the data signals of each column of data signals in the gate line is 0, and the sum of the data voltage changes from the data signals of each column of data signals in the previous row of the gate line to the data signals of each column of data signals in the next row of the gate line is 0.

[0142] Optionally, in this embodiment, the display device 100 first determines the range of the Excel table in the current frame to facilitate subsequent adjustment or modification of the polarity of the data signal of a portion of the gate line in that row within the Excel table range. Of course, in an optional embodiment of this application, the display device 100 may also first determine the range of other areas in the current frame that need adjustment, such as grayscale background areas or any other areas that require compensation, depending on actual needs.

[0143] Figure 10 and Figure 11 The image shows pixels within the Excel spreadsheet area. The (Gn+2)th row of the gate line is the Excel spreadsheet boundary. In this row, one pixel is bright and one pixel is dark, cycling in two-pixel increments. Figure 10 In the middle, instead of the original data signal polarity reversal method, a column reversal method has been adopted. Figure 10 Two pixels, or six sub-pixels, form a minimum repeating unit. The polarities of the data signals of these six sub-pixels are positive, negative, positive, negative, positive, negative, as follows: Figure 10 and Figure 12 As shown, from row Gn+1 to row Gn+2, the sum of the data voltages of the data columns R2, G2, B2, R4, G4, and B4 is pulled up, causing the common electrode voltage to be pulled up; from row Gn+2 to row Gn+3, the sum of the data voltages of the data columns R2, G2, B2, R4, G4, and B4 is pulled down, causing the common electrode voltage to be pulled down. Figure 11 In this process, the polarity of the data signal was adjusted. Four pixels (12 sub-pixels) form a minimum repeating unit, with polarities sequentially: positive, negative, positive, positive, negative, positive, positive, negative, positive, negative, positive, negative. The polarity of the data signals in columns R2, G2, and B2 was adjusted, as follows: Figure 11 and Figure 13 As shown, from row Gn+1 to row Gn+2, the sums of the data voltages in columns R2, G2, B2, R4, G4, and B4 cancel each other out, and the common electrode voltage does not fluctuate; from row Gn+2 to row Gn+3, the sums of the data voltages in columns R2, G2, B2, R4, G4, and B4 cancel each other out, and the common electrode voltage does not fluctuate. Adjusting the polarity significantly improves the issue of boundary lines in Excel spreadsheets.

[0144] Figure 12 and Figure 13 The diagram below provides a detailed analysis of the principle. The gate line, row Gn+2, is represented by the Excel spreadsheet boundary lines; one pixel represents a bright pixel, and one pixel represents a dark pixel.

[0145] Figure 12The original data signal polarity pattern uses a column-flipping method, with six subpixels forming a minimum loop unit. Analysis of the six subpixels R1, G1, B1, R2, G2, and B2 reveals that the voltages of R1, G1, and B1 remain unchanged at the Excel table boundary, while the data voltages of R2, G2, and B2 change instantaneously between the gate line at row Gn+1 and row Gn+2 (row Gn+2 being the Excel table boundary). R2 and G2 are pulled up from Vdata- (e.g., -3V) to Vcom (e.g., 0V), while B2 is pulled down from Vdata+ (e.g., 3V) to Vcom (e.g., 0V). In this way, within the 6 columns of pixels in the minimum repetition period, two columns of data signals will be pulled up to Vcom, and one column of data signals will be pulled down to Vcom. The Vcom signal as a whole will be pulled up, resulting in an upward ripple. Similarly, at the instant from row Gn+2 (the row Gn+2 is the Excel spreadsheet boundary) to row Gn+3, R2 and G2 are pulled down from Vcom voltage (e.g., 0V) to Vdata- voltage (e.g., -3V), while B2 is pulled up from Vcom voltage (e.g., 0V) to Vdata+ voltage (e.g., 3V). Therefore, the Vcom signal as a whole will be pulled down, resulting in a downward ripple.

[0146] and Figure 13 After polarity adjustment, row Gn+2 remains the Excel spreadsheet boundary. Four large pixels, or 12 sub-pixels, form the smallest loop unit. At the instant between row Gn+1 and row Gn+2 (row Gn+2 being the Excel spreadsheet boundary), the data voltage changes. R2, B2, and G4 are pulled down from Vdata+ (e.g., 3V) to Vcom (e.g., 0V), while G2, R4, and B4 are pulled up from Vdata- (e.g., -3V) to Vcom (e.g., 0V). This results in three columns of data signals being pulled up and three columns being pulled down, canceling each other out. Vcom remains almost unaffected by the data signal coupling. Similarly, at the instant between row Gn+2 (the dividing line of the Excel spreadsheet) and row Gn+3, the data voltage changes. R2, B2, and G4, initially at Vcom (e.g., 0V), are pulled up to Vdata+ (e.g., 3V), while G2, R4, and B4, initially at Vcom (e.g., 0V), are pulled down to Vdata- (e.g., -3V). This results in three columns of data signals being pulled up and three columns of data signals being pulled down. The Vcom signal remains unchanged, unaffected by the data signal coupling.

[0147] Similar to Scheme 1, the specific compensation steps are as follows: First, determine which row of the gate line the common electrode signal fluctuation (i.e., the Excel table boundary line) of the nth frame's display panel appears in. Then, determine the size of the Excel table area and how many columns of data signals require polarity adjustment (the grayscale background area does not require data signal polarity adjustment). Then, starting from the (n+1)th frame, adjust the polarity of the data signals in this row. Specifically, for the data columns within the Excel table area, change the minimum repeating unit from 6 subpixels to 12 subpixels, and adjust the polarity of some data signals in this row (see details for data signal polarity adjustment method). Figures 10 to 13 In this way, the pull-up and pull-down of the data signal in these 12 sub-pixels can cancel each other out, thereby weakening or completely canceling the coupling of the data signal to the Vcom signal, and thus avoiding the display abnormality caused by the fluctuation of the common electrode signal or the Excel table boundary line mentioned above.

[0148] Similar to Scheme 1, detection will still occur in frame n+1, and the polarity of the data signal will be adjusted in frame n+2, with subsequent frames following the same pattern. The compensation will remain constant until the Excel spreadsheet is in a fixed position and size.

[0149] This application provides a display solution for improving weak lines or crosstalk problems in display panels, such as improving abnormal display of dividing lines in Excel spreadsheets. The display device in this application can be applied to technologies such as liquid crystal displays.

[0150] Specifically, the display device can be any of the following: LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode), Micro LED (Micro Light Emitting Diode), or Mini LED (Mini Light Emitting Diode). The display device can also be any product or component with display function, such as a monitor, television, digital camera, mobile phone, or tablet computer.

[0151] Based on the same inventive concept, this application provides an electronic device, which includes the above-described display device 100.

[0152] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application may be specifically designed and manufactured for the desired purpose, or may include known devices in general-purpose computers.

[0153] It should be noted that since the electronic device in this application embodiment includes the display device in this application embodiment, the electronic device in this application embodiment also has the above-mentioned beneficial effects of the display device in this application embodiment, which will not be repeated here.

[0154] Specifically, the electronic device can be any device with any display function, such as a computer, television, digital camera, mobile phone, tablet computer, or watch.

[0155] Based on the same inventive concept, this application provides a compensation method for a display panel, the flowchart of which is shown below. Figure 14 and Figure 15 As shown, the method includes:

[0156] S101. Monitor the common electrode signal of the display panel in the current frame, determine the fluctuation of the common electrode voltage and the target gate line, and the position of the target gate line corresponds to the position where the common electrode voltage fluctuates.

[0157] S102. Based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, a first determination signal is issued; based on the acquired first determination signal and the common electrode signal, compensation is performed on the fluctuating common electrode voltage in the next frame so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line (e.g., ...). Figure 14 (as shown); or,

[0158] S103. Detect the data signals of each data line, and based on the detection results and the gate line information of the target gate line, issue a second determination signal; based on the second determination signal and the data signals, adjust the polarity of the data signals of some data lines in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line (e.g., Figure 15 (As shown).

[0159] In this embodiment, firstly, the common electrode signal of the display panel in the current frame is monitored to determine the fluctuation of the common electrode voltage and the target gate line; after determining which gate lines the common electrode voltage fluctuates, a first determination signal is issued based on the fluctuation of the common electrode voltage and the gate line information of the target gate line; then, based on the acquired first determination signal and the common electrode signal, the fluctuating common electrode voltage is compensated in the next frame so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line; or, after determining which gate lines the common electrode voltage fluctuates, the data signal of each data line is detected, and a second determination signal is issued based on the detection result and the gate line information of the target gate line; then, based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuation of each data line at least partially cancels each other out at the target gate line.

[0160] By using the above settings, the fluctuating common electrode voltage can be compensated in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. Alternatively, the polarity of the data signal of some data lines can be adjusted in the next frame so that the fluctuations in the data voltage of each data line at least partially cancel each other out at the target gate line. This can reduce or even eliminate the phenomenon of ripple fluctuations in the common electrode voltage, solve the technical problem of display abnormality, and avoid weak lines or crosstalk.

[0161] Specifically, such as Figure 14 and Figure 15 As shown in this embodiment, the logic integrated circuit 20 of the display device 100 first determines which row of gate lines exhibits a Vcom ripple. Then, it probes the data signal of this row of gate lines to determine if it corresponds to the aforementioned Excel table boundary line problem. Since the data signals at the Excel table boundary line and the grayscale background are relatively regular, it is not difficult to determine whether it is an Excel table boundary line based on the data signal of this row of gate lines. If it is, the two solutions provided in this embodiment (including the aforementioned Solution 1 and Solution 2) are used to solve the display abnormality problem caused by the Vcom ripple. If not, it is ignored. Specifically, Solution 1 involves performing Vcom inverted amplification compensation on the gate line exhibiting a Vcom ripple in the nth frame when the gate line is turned on in the (n+1)th frame, so that the common electrode voltages of the gate lines corresponding to the fluctuating common electrode signals in the next frame cancel each other out. Solution 2 involves determining which row of gate lines is the Excel table boundary line based on the data information detected in the nth frame, and adjusting the polarity of a portion of the data signal of that gate line in the (n+1)th frame, so that the data voltages of each column of data signals of the gate line cancel each other out.

[0162] This application proposes a novel approach to solving display anomaly problems. First, it detects which row of gate lines the Vcomripple voltage or its corresponding data signal appears in the nth frame. Then, starting from the (n+1)th frame, it compensates for the Vcom signal of that row of gate lines (see Scheme 1) or adjusts the polarity of the data signal (see Scheme 2). This approach perfectly solves weak lines or crosstalk problems on the display panel. This method of detection followed by compensation or adjustment is simple and effective.

[0163] The technical solutions provided in this application can be used to solve the signal crosstalk problem caused by specific data signal arrangement methods, such as the dividing lines in an Excel spreadsheet.

[0164] Optionally, in this embodiment of the application, monitoring the common electrode signal of the current frame display panel to determine the fluctuation of the common electrode voltage and the target gate line, wherein the position of the target gate line corresponds to the position where the common electrode voltage fluctuates, includes:

[0165] Obtain the common electrode signal of the display panel in the current frame;

[0166] If the common electrode voltage of the current frame display panel is pulled up or pulled down relative to the reference electrode voltage at the moment when at least one row of gate lines is turned on, the common electrode voltage fluctuates at the at least one row of gate lines, which is the target gate line.

[0167] Otherwise, if the common electrode signal of the current frame display panel does not fluctuate, there is no need to compensate for the common electrode signal and data signal of the current frame display panel.

[0168] Optionally, in this embodiment of the application, the fluctuation of the common electrode voltage at the target gate line relative to the reference electrode voltage is characterized by the variation of the voltage value of the data signal of each data line at the target gate line, including:

[0169] If the sum of the voltage changes of the data signals on each data line from the previous row of gate lines to the target gate line is greater than 0, then the common electrode voltage is pulled up relative to the reference electrode voltage at the target gate line; or...

[0170] If the sum of the voltage changes of the data signals on each data line from the previous row of gate lines to the target gate line is less than 0, then the common electrode voltage is pulled down relative to the reference electrode voltage at the target gate line; or...

[0171] If the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is equal to 0, then the common electrode voltage does not fluctuate relative to the reference electrode voltage at the target gate line.

[0172] Optionally, in this embodiment, the reference electrode voltage is Vcom, which is 0V. Specifically, if the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is greater than 0, then the common electrode voltage is pulled up relative to the reference electrode voltage at the target gate line; if the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is less than 0, then the common electrode voltage is pulled down relative to the reference electrode voltage at the target gate line; if the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is equal to 0, then the common electrode voltage does not fluctuate relative to the reference electrode voltage at the target gate line, and in this case, there is no need to compensate for the common electrode signal and data signal of the current frame display panel.

[0173] Optionally, in this embodiment of the application, based on the acquired first determination signal and common electrode signal, compensation is performed on the fluctuating common electrode voltage in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line, including:

[0174] Determine the magnitude of the fluctuation in the common electrode voltage.

[0175] Depending on the magnitude of the fluctuation, the common electrode voltage that is fluctuating is inverted in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line.

[0176] In this embodiment, based on the common electrode voltage of the display panel fluctuating in the current frame, the magnitude of the fluctuation of the common electrode voltage is determined. Based on the magnitude of the Vcom ripple fluctuation measured in the current frame (e.g., the nth frame), the fluctuating common electrode signal is inverted in the next frame (e.g., the n+1th frame) to compensate for the Vcom ripple fluctuation. This causes the common electrode voltages of the gate lines corresponding to the fluctuating common electrode signal in the next frame to cancel each other out, thereby accelerating the recovery of Vcom ripple and solving the problem of display abnormalities caused by Vcom ripple fluctuations.

[0177] Optionally, in this embodiment of the application, the magnitude of the fluctuation amplitude of the fluctuating common electrode signal can be determined based on the difference between the common electrode voltage of the fluctuating common electrode signal and the reference electrode voltage.

[0178] Optionally, in this embodiment of the application, the detection of data signals on each data line includes:

[0179] Obtain the data signals of each data line on the display panel in the current frame;

[0180] Determine the voltage value and polarity of the data signal for each data line.

[0181] Optionally, in this embodiment of the application, based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line, including:

[0182] Determine the data line information of the first target data line, wherein the first target data line includes a data line whose polarity needs to be reversed, and the data line whose polarity needs to be reversed includes at least one data signal whose voltage value or polarity changes at the target gate line;

[0183] In the next frame, the polarity of the data signal of the first target data line is adjusted so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line.

[0184] In this embodiment, based on the second determination signal and the data signal, according to the data information (including data voltage value and polarity) detected in the current frame (e.g., the nth frame), a portion of the data signal whose polarity needs to be adjusted is determined. In the next frame (e.g., the n+1th frame), the polarity of this portion of the data signal is flipped, so that the data voltages of each column of data signals of the gate line corresponding to the common electrode signal that fluctuates in the current frame can cancel each other in the next frame, eliminating Vcom ripple fluctuations, thereby solving the problem of display abnormalities caused by Vcom ripple fluctuations.

[0185] Optionally, in this embodiment of the application, if the common electrode voltage of the current frame display panel fluctuates relative to the reference electrode voltage at multiple gate lines, then the common electrode voltage at each of the multiple gate lines is compensated.

[0186] Based on the first determination signal and the common electrode signal, the fluctuating common electrode voltage is compensated in the next frame so that the fluctuation of the common electrode voltage in the next frame is at least partially canceled out at multiple target gate lines; or, based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuation of each data line is at least partially canceled out at multiple target gate lines.

[0187] In this embodiment, when the common electrode voltages corresponding to multiple rows of gate lines fluctuate relative to the reference electrode voltage, compensation is performed on each gate line in the multiple rows of gate lines. For example, if the common electrode voltages corresponding to the nth and n+1th or the nth and n+mth rows of gate lines fluctuate relative to the reference electrode voltage, then compensation is performed on the nth and n+1th or the nth and n+mth rows respectively.

[0188] For example, in this embodiment of the application, Vcom signal compensation with inverse amplification is performed on the gate lines (G1000 row and G1001 row) where Vcom ripple occurs, in order to quickly pull back the Vcom signal and return it to the original voltage value before the pixel TFT of the gate line (G1000 row and G1001 row) is turned off.

[0189] For example, in the embodiment of this application, at the instant from row Gn+1 to row Gn+2 (row Gn+2 is the Excel spreadsheet boundary), the data voltage changes. R2, B2, and G4 are pulled down from Vdata+ to Vcom voltage, while G2, R4, and B4 are pulled up from Vdata- to Vcom voltage. This results in three columns of data signals being pulled up and three columns of data signals being pulled down, canceling each other out, and Vcom remains almost unaffected by data signal coupling. Similarly, at the instant from row Gn+2 (row Gn+2 is the Excel spreadsheet boundary) to row Gn+3, the data voltage changes. R2, B2, and G4 are pulled up from Vcom voltage to Vdata+ voltage, while G2, R4, and B4 are pulled down from Vcom to Vdata- voltage. Again, three columns of data signals are pulled up and three columns of data signals are pulled down, and the Vcom signal remains unaffected by data signal coupling.

[0190] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by an electronic device, implements the compensation method for the display panel as described above.

[0191] This application provides a computer-readable storage medium applicable to various optional embodiments of the compensation method for the display panel provided in the above-described embodiments of this application, which will not be elaborated further here.

[0192] This application also provides a computer program product, including a computer program that, when executed by an electronic device, can implement the steps and corresponding content of the aforementioned method embodiments.

[0193] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0194] In this embodiment, the logic integrated circuit is connected to the common electrode, and the common electrode feeds back the common electrode signal to the logic integrated circuit. The logic integrated circuit is configured to monitor the common electrode signal of the current frame display panel and determine at which gate lines the common electrode voltage fluctuates. The compensation structure is connected to the common electrode, and the common electrode feeds back the common electrode signal to the compensation structure. The compensation structure is connected to the logic integrated circuit, and the compensation structure feeds back the received data signal to the logic integrated circuit so that the logic integrated circuit can analyze the data signal.

[0195] In this embodiment of the application, the logic integrated circuit is further configured to issue a first determination signal based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, or it is further configured to detect the data signals of each data line and issue a second determination signal based on the detection result and the gate line information of the target gate line.

[0196] When the logic integrated circuit issues a first determination signal, the compensation structure is configured to acquire the first determination signal and the common electrode signal. Furthermore, the compensation structure is also configured to compensate for the fluctuating common electrode voltage in the next frame based on the acquired first determination signal and the common electrode signal, so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line. The compensation structure is also connected to the data line, and the compensation structure provides the acquired data signal to the data line.

[0197] When the logic integrated circuit issues a second determination signal, the compensation structure is configured to acquire the second determination signal and the data signal. Furthermore, the compensation structure is also configured to adjust the polarity of the data signal of a portion of the data lines in the next frame based on the acquired second determination signal and the data signal, so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line. The compensation structure is connected to the common electrode, and the compensation structure provides the acquired common electrode signal to the common electrode.

[0198] By using the above settings, the fluctuating common electrode voltage can be compensated in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. Alternatively, the polarity of the data signal of some data lines can be adjusted in the next frame so that the fluctuations in the data voltage of each data line at least partially cancel each other out at the target gate line. This can reduce or even eliminate the phenomenon of ripple fluctuations in the common electrode voltage, solve the technical problem of display abnormality, and avoid weak lines or crosstalk.

[0199] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0200] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0201] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0202] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0203] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0204] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0205] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A display device, characterized in that, include: The display panel has a display area, and the display panel includes a plurality of data lines and a plurality of gate lines arranged in a cross manner, as well as a common electrode; A logic integrated circuit, connected to the common electrode, is configured to monitor the common electrode signal of the current frame display panel, determine the fluctuation of the common electrode voltage and the target gate line, wherein the position of the target gate line corresponds to the position where the common electrode voltage fluctuates; Based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, a first determination signal is issued; Alternatively, the data signals of each data line can be detected, and a second determination signal can be issued based on the detection results and the gate line information of the target gate line. The compensation structure is connected to the data line, the common electrode, and the logic integrated circuit, respectively. It is configured to acquire the data signal, the common electrode signal fed back by the common electrode, and the first determination signal or the second determination signal emitted by the logic integrated circuit. Based on the acquired first determination signal and the common electrode signal, it compensates for the fluctuating common electrode voltage in the next frame so that the fluctuation of the common electrode voltage in the next frame at least partially cancels each other out at the target gate line. Alternatively, based on the second determination signal and the data signal, the polarity of the data signals of some data lines is adjusted in the next frame so that the data voltage fluctuations of each data line at the target gate line at least partially cancel each other out; The first determination signal includes the amplitude information of the fluctuation of the common electrode voltage and the gate line information of the target gate line; The compensation structure includes a power supply integrated circuit, which is connected to the common electrode and the logic integrated circuit respectively. It is configured to receive the first determination signal emitted by the logic integrated circuit and the common electrode signal fed back by the common electrode, and based on the first determination signal and the common electrode signal, to perform inverse compensation on the fluctuating common electrode voltage in the next frame, so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. The second determination signal includes data line information of the first target data line and gate line information of the target gate line, wherein the first target data line is a data line whose polarity needs to be reversed; The compensation structure includes a timing controller and a data driving circuit. The timing controller is connected to the logic integrated circuit and the data driving circuit, respectively. The data driving circuit is connected to the logic integrated circuit and the data line, respectively. The timing controller is configured to receive the second determination signal emitted by the logic integrated circuit and output a polarity reversal signal and a data signal to the data driving circuit; the data driving circuit is configured to output the received data signal to the logic integrated circuit and, based on the received polarity reversal signal and the data signal, adjust the polarity of the data signal of the first target data line in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line; the logic integrated circuit is configured to determine the voltage value and polarity of the data signal of each data line according to the received data signal, determine the second target data line, the voltage value and / or polarity of the data signal of the second target data line changes at the target gate line, and determine the first target data line according to the second target data line, the first target data line including at least one second target data line.

2. The display device according to claim 1, characterized in that, The compensation structure includes a power integrated circuit, a data driving circuit, and a timing controller. The power integrated circuit is connected to the common electrode and the logic integrated circuit, respectively. The power integrated circuit is also connected to the data driving circuit and the timing controller to supply power to the data driving circuit and the timing controller, respectively. The timing controller is connected to the logic integrated circuit and the data driving circuit, respectively. The data driving circuit is connected to the data line and the logic integrated circuit, respectively.

3. The display device according to claim 1, characterized in that, The first determination signal also includes inverting amplifier information, which includes the amplification factor of the inverting amplifier, and the amplification factor of the inverting amplifier is adapted to the magnitude of the fluctuation amplitude of the common electrode voltage. The power supply integrated circuit includes multiple inverting amplifiers, and the multiple inverting amplifiers have different amplification factors; The power integrated circuit is configured to receive the first determination signal and the common electrode signal, and based on the first determination signal, determine an inverting amplifier, and use the inverting amplifier in the next frame to perform inverting amplification compensation on the common electrode voltage of the common electrode signal.

4. The display device according to claim 3, characterized in that, The amplification factor of the selected inverting amplifier is proportional to the amplitude of the fluctuation in the common electrode voltage; and / or, The amplification factor of multiple inverting amplifiers is greater than or equal to 5 and less than or equal to 50.

5. The display device according to claim 3, characterized in that, The inverting amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a reference electrode voltage. The common electrode is connected to the inverting input terminal to input a common electrode signal. The output terminal is connected to the common electrode and is configured to output a common electrode compensation signal amplified by inversion to the common electrode.

6. An electronic device, characterized in that, The display device includes any one of claims 1 to 5.

7. A compensation method for a display panel, characterized in that, include: The common electrode signal of the display panel in the current frame is monitored to determine the fluctuation of the common electrode voltage and the target gate line, wherein the position of the target gate line corresponds to the position where the common electrode voltage fluctuates; Based on the fluctuation of the common electrode voltage and the gate line information of the target gate line, a first determination signal is issued; based on the acquired first determination signal and the common electrode signal, the fluctuating common electrode voltage is compensated in the next frame so that the fluctuation of the common electrode voltage in the next frame at the target gate line at least partially cancels each other out. or, The data signals of each data line are detected, and a second determination signal is issued based on the detection results and the gate line information of the target gate line. Based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuations of each data line at the target gate line at least partially cancel each other out. The first determination signal includes the amplitude information of the fluctuation of the common electrode voltage and the gate line information of the target gate line; The step of compensating for fluctuating common electrode voltage in the next frame based on the acquired first determination signal and the common electrode signal includes: performing inverse compensation for fluctuating common electrode voltage in the next frame based on the first determination signal and the common electrode signal. The second determination signal includes data line information of the first target data line and gate line information of the target gate line, wherein the first target data line is a data line whose polarity needs to be reversed; the step of adjusting the polarity of the data signal of some data lines in the next frame based on the second determination signal and the data signal includes: adjusting the polarity of the data signal of the first target data line in the next frame based on the second determination signal, the polarity reversal signal and the data signal, so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line; determining the voltage value and polarity of the data signal of each data line according to the data signal, determining the second target data line, wherein the voltage value and / or polarity of the data signal of the second target data line changes at the target gate line, and determining the first target data line according to the second target data line, wherein the first target data line includes at least one second target data line.

8. The compensation method according to claim 7, characterized in that, The step of monitoring the common electrode signal of the current frame display panel to determine the fluctuation of the common electrode voltage and the target gate line, wherein the position of the target gate line corresponds to the position of the common electrode voltage fluctuation, includes: Obtain the common electrode signal of the display panel in the current frame; If the common electrode voltage of the current frame display panel is pulled up or pulled down relative to the reference electrode voltage at the moment when at least one row of gate lines is turned on, the common electrode voltage fluctuates at the at least one row of gate lines, which is the target gate line. Otherwise, the common electrode signal of the display panel in the current frame does not fluctuate.

9. The compensation method according to claim 8, characterized in that, The variation of the voltage value of the data signal at each data line at the target gate line characterizes the fluctuation of the common electrode voltage at the target gate line relative to the reference electrode voltage, including: If the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is greater than 0, then the common electrode voltage is pulled up relative to the reference electrode voltage at the target gate line; or, If the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is less than 0, then the common electrode voltage is pulled down relative to the reference electrode voltage at the target gate line; or, If the sum of the voltage changes of the data signals of each data line from the previous row of gate lines to the target gate line is equal to 0, then the common electrode voltage does not fluctuate relative to the reference electrode voltage at the target gate line.

10. The compensation method according to claim 7, characterized in that, The detection of data signals on each data line includes: Obtain the data signals of each data line on the display panel in the current frame; Determine the voltage value and polarity of the data signal for each data line.

11. The compensation method according to claim 7, characterized in that, Based on the acquired first determination signal and the common electrode signal, compensation is performed on the fluctuating common electrode voltage in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line, including: Determine the magnitude of the fluctuation in the common electrode voltage that is fluctuating; Depending on the magnitude of the fluctuation, the common electrode voltage that fluctuates is inverted in the next frame so that the fluctuations in the common electrode voltage in the next frame at least partially cancel each other out at the target gate line. And / or, Based on the second determination signal and the data signal, the polarity of the data signals of some data lines is adjusted in the next frame so that the data voltage fluctuations of each data line at least partially cancel each other out at the target gate line, including: Determine the data line information of the first target data line, wherein the first target data line includes a data line whose polarity needs to be reversed, and the data line whose polarity needs to be reversed includes at least one data signal whose voltage value or polarity changes at the target gate line; In the next frame, the polarity of the data signal of the first target data line is adjusted so that the data voltage fluctuations of each data line at the target gate line at least partially cancel each other out.

12. The compensation method according to claim 7, characterized in that, If the common electrode voltage of the current frame display panel fluctuates relative to the reference electrode voltage at multiple gate lines, then the common electrode voltage is compensated at each of the multiple gate lines. Based on the first determination signal and the common electrode signal, compensation is performed on the fluctuating common electrode voltage in the next frame so that the fluctuation of the common electrode voltage in the next frame is at least partially canceled out at multiple target gate lines; or, based on the second determination signal and the data signal, the polarity of the data signal of some data lines is adjusted in the next frame so that the data voltage fluctuation of each data line is at least partially canceled out at multiple target gate lines.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, when executed by an electronic device, the computer program implements the compensation method for a display panel as described in any one of claims 7 to 12.

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