Field effect transistor with electric field modulation structure and manufacturing method thereof

Abstract

The present invention discloses a field effect transistor with an electric field modulation structure and a manufacturing method thereof. The field effect transistor includes: a first conductive type drift region and a second conductive type well region located in a second conductive type epitaxial layer, and a first conductive type source region located in the second conductive type well region; an insulating layer and a first conductive type drain region located in the first conductive type drift region, and the insulating layer is located between the first conductive type source region and the first conductive type drain region; a stepped conductive material located in the insulating layer, the stepped conductive material including N-level conductive materials, and the depth decreases from the first-level conductive material to the N-th-level conductive material; the present invention integrates an electric field modulation structure in a semiconductor body without affecting the frequency characteristics of the device, which can not only effectively modulate the electric field distribution and improve the blocking characteristics, but also increase the doping concentration of the drift region, thereby improving the conduction characteristics.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a field effect transistor with an electric field modulation structure and a manufacturing method thereof. Background Art

[0002] The lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) is a common switching device characterized by a wide, lightly doped drift region in the drain region. This region allows it to withstand higher voltages, resulting in improved blocking characteristics. The LDMOS manufacturing process is fully compatible with standard CMOS processes and is primarily used in various power circuits. Excellent frequency characteristics are a fundamental requirement for LDMOS. Furthermore, with the expansion of its application, the industry is placing increasingly stringent demands on both its blocking and conduction characteristics.

[0003] A field plate structure is typically formed by a metal layer (or polysilicon) covering an oxide layer. When the PN junction is reverse biased, the longitudinal electric field between the metal and semiconductor causes the region beneath the field plate to enter a depletion state. This depletion region connects to the PN junction depletion layer, widening the depletion layer and distributing the electric field at the junction edge to the field plate, reducing the peak electric field at the junction edge and improving the device's withstand voltage. Field plate structures are widely used in power MOSFET terminal protection and LDMOS structures.

[0004] The existing field plate protection structures of LDMOS currently include source field plates, drain field plates, and gate field plates, and the field plate structure close to the source side is the most critical. Multilayer field plate technology can reduce the electric field peak in the reverse blocking state by setting a multilayer field plate or a stepped field plate on the semiconductor surface close to the source side, and increase the doping concentration of the drift region as much as possible while ensuring that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device. However, the manufacturing process of the multilayer field plate structure is complex and requires consideration of multilayer dielectric isolation, which increases the process cost and increases the risk of long-term application of the device. In addition, the existing multilayer field plate structure often requires an extension of the gate length, which significantly reduces the distance between the gate and the drain, and the influence of the gate-drain capacitance on the frequency characteristics of the device also increases, thereby damaging the frequency characteristics of the device. Summary of the Invention

[0005] In response to the shortcomings of the above-mentioned LDMOS multi-layer field plate technology, the present invention provides a field-effect transistor with an electric field modulation structure and a manufacturing method thereof. Without affecting the frequency characteristics of the device, the electric field modulation structure is integrated into the semiconductor body, which can not only effectively modulate the electric field distribution and improve the blocking characteristics, but also increase the doping concentration of the drift region, thereby improving the conduction characteristics.

[0006] The present invention discloses a field effect transistor with an electric field modulation structure, comprising:

[0007] A second conductive type substrate; a second conductive type epitaxial layer located on the second conductive type substrate;

[0008] A first conductivity type drift region and a second conductivity type well region are located in the second conductivity type epitaxial layer, and the first conductivity type drift region and the second conductivity type well region are adjacent to each other;

[0009] a first conductivity type source region located in the second conductivity type well region;

[0010] An insulating layer and a first conductive type drain region are located in the first conductive type drift region, the insulating layer and the first conductive type drain region are adjacent to each other, and the insulating layer is located between the first conductive type source region and the first conductive type drain region;

[0011] The stepped conductive material is located in the insulating layer. The stepped conductive material includes N levels. The first level conductive material is close to the gate, and the N level conductive material is close to the first conductive type drain region. The depth of the first level conductive material to the N level conductive material decreases. The distance between the bottom of the first level conductive material and the bottom of the insulating layer is D1, the distance between the bottom of the second level conductive material and the bottom of the insulating layer is D2, and so on. The distance between the bottom of the N level conductive material and the bottom of the insulating layer is D N , D1 <D2<……<D N , the difference between D1 and D2 is 0.1µm~1.0µm, the difference between D2 and D3 is 0.1µm~1.0µm, ..., D N-1 With D N The difference is 0.1µm~1.0µm;

[0012] A gate dielectric located on the interface between the first conductivity type drift region and the second conductivity type well region, with one side of the gate dielectric projection located on the first conductivity type source region and the other side located on the first conductivity type drift region;

[0013] A gate located on the gate dielectric, wherein the width of the gate is smaller than the width of the gate dielectric;

[0014] Isolation dielectrics located on both sides of and above the gate dielectric and the gate;

[0015] A source electrode is located on one side of the isolation medium, covering part of the second conductive type well region and part of the first conductive type source region; a drain electrode is located on the other side of the isolation medium, covering part of the insulating layer and the first conductive type drain region.

[0016] The present invention also discloses a method for manufacturing a field effect transistor having an electric field modulation structure, which is used to manufacture the field effect transistor having the electric field modulation structure described above, comprising the following steps:

[0017] forming a second conductive type epitaxial layer on a second conductive type substrate;

[0018] forming a first conductivity type drift region in the second conductivity type epitaxial layer;

[0019] etching a portion of the first conductive type drift region to form a first trench;

[0020] forming an insulating layer that completely fills the first trench;

[0021] The insulating layer is etched to form a stepped trench, and a stepped conductive material is formed that completely fills the stepped trench; the stepped conductive material includes N levels, the first level conductive material is close to the gate, the N level conductive material is close to the first conductive type drain region, the depth of the first level conductive material to the N level conductive material decreases, the distance between the bottom of the first level conductive material and the bottom surface of the insulating layer is D1, the distance between the bottom of the second level conductive material and the bottom surface of the insulating layer is D2, and so on, the distance between the bottom of the N level conductive material and the bottom surface of the insulating layer is D N , D1 <D2<……<D N , the difference between D1 and D2 is 0.1µm~1.0µm, the difference between D2 and D3 is 0.1µm~1.0µm, ..., D N-1 With D N The difference is 0.1µm~1.0µm;

[0022] forming a second conductivity type well region adjacent to the first conductivity type drift region in the second conductivity type epitaxial layer, forming a first conductivity type source region in the second conductivity type well region, and forming a first conductivity type drain region adjacent to the insulating layer in the first conductivity type drift region;

[0023] forming a gate dielectric on the interface between the first conductive type drift region and the second conductive type well region, and forming a gate on the gate dielectric;

[0024] An isolation dielectric is formed on both sides and above the gate dielectric and the gate, a source is formed on one side of the isolation dielectric, covering a portion of the second conductive type well region and a portion of the first conductive type source region, and a drain is formed on the other side of the isolation dielectric, covering a portion of the insulating layer and the first conductive type drain region.

[0025] The present invention adopts the above technical solution and has the following beneficial effects:

[0026] The field effect transistor with an electric field modulation structure proposed in the present invention forms an electric field modulation structure composed of a step-shaped conductive material, an insulating layer and a first conductive type drift region within the semiconductor material. In the off state, the electric field modulation structure can further uniformize the electric field distribution in the drift region, thereby significantly improving the blocking characteristics of the device. In the forward conduction state, the charge controlled by the first conductive type drift region with a higher concentration and the step-shaped conductive material can effectively increase the current density and reduce the on-resistance. The gate dielectric process and gate process of the present invention are completely consistent with the conventional LDMOS process, avoiding the damage to the device frequency characteristics caused by traditional multi-layer field plate technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a field effect transistor with an electric field modulation structure according to Example 1;

[0028] Figure 2 A schematic diagram of a field effect transistor with an electric field modulation structure according to Example 2;

[0029] Figures 3 to 14 This is a flow chart of a method for manufacturing a field effect transistor with an electric field modulation structure according to Example 1;

[0030] Explanation of the accompanying drawings: 1. Second conductive type substrate; 2. Second conductive type epitaxial layer; 3. First conductive type drift region; 4. Second conductive type well region; 5. Insulating layer; 6. First conductive type source region; 7. First conductive type drain region; 8. Step-shaped conductive material; 9. Gate dielectric; 10. Gate; 11. Isolation dielectric; 12. Source; 13. Drain; 14. Second conductive type electrical connection layer; 101. First trench; 102. Second trench; 103. Third trench; 104. Fourth trench. DETAILED DESCRIPTION

[0031] The present invention is further described below with reference to examples. The examples are only used to illustrate the present invention and do not constitute a limitation to the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0032] Furthermore, in the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the present invention and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Example 1

[0033] like Figure 1 As shown, a field effect transistor with an electric field modulation structure according to this embodiment includes:

[0034] A second conductive type substrate 1; a second conductive type epitaxial layer 2 located on the second conductive type substrate 1;

[0035] A first conductivity type drift region 3 and a second conductivity type well region 4 are located in the second conductivity type epitaxial layer 2 , and the first conductivity type drift region 3 and the second conductivity type well region 4 are adjacent to each other;

[0036] a first conductivity type source region 6 located in the second conductivity type well region 4;

[0037] The insulating layer 5 and the first conductive type drain region 7 are located in the first conductive type drift region 3 , the insulating layer 5 and the first conductive type drain region 7 are adjacent to each other, and the insulating layer 5 is located between the first conductive type source region 6 and the first conductive type drain region 7 ;

[0038] The stepped conductive material is located in the insulating layer. The stepped conductive material includes N levels. The first level conductive material is close to the gate, and the N level conductive material is close to the first conductive type drain region. The depth of the first level conductive material to the N level conductive material decreases. The distance between the bottom of the first level conductive material and the bottom of the insulating layer is D1, the distance between the bottom of the second level conductive material and the bottom of the insulating layer is D2, and so on. The distance between the bottom of the N level conductive material and the bottom of the insulating layer is D N , the spacing is strongly related to the electric field modulation effect, and the present invention defines D1 <D2<……<D N , the difference between D1 and D2 is 0.1µm~1.0µm, the difference between D2 and D3 is 0.1µm~1.0µm, ..., D N-1 With D NThe difference is 0.1µm~1.0µm; in the off state, the electric field modulation structure can make the electric field distribution in the drift region more uniform, thereby significantly improving the blocking characteristics of the device. The depth of the first-level conductive material to the N-th level conductive material decreases; wherein, the depth range of the insulating layer 5 is 0.5µm~4.0µm, and in the stepped conductive material 8, the depth range of the first-level conductive material is 0.4µm~3.5µm, the range of D1 is 0.1µm~0.5µm, and the distance between the left boundary of the first-level conductive material and the left boundary of the insulating layer 5 is 0.1µm~0.5µm; the difference in depth between two adjacent levels of conductive materials is 0.1µm~1.0µm, 2≤N≤6, and it is a natural number; in this embodiment, the stepped conductive material 8 includes three levels;

[0039] A gate dielectric 9 located on the interface between the first conductivity type drift region 3 and the second conductivity type well region 4, with one side of the gate dielectric 9 projected above the first conductivity type source region 6 and the other side above the first conductivity type drift region 3. The distance between the side above the first conductivity type drift region 3 and the second conductivity type well region 4 is in the range of 0.1µm to 0.8µm.

[0040] A gate 10 is located on the gate dielectric 9. The width of the gate 10 is smaller than the width of the gate dielectric 9. One side of the projection of the gate 10 is located on the first conductivity type source region 6, and the other side is located on the first conductivity type drift region 3.

[0041] Isolation dielectrics 11 located on both sides of and above the gate dielectric 9 and the gate electrode 10;

[0042] The source 12 is located on one side of the isolation medium, covering part of the second conductivity type well region 4 and part of the first conductivity type source region 6; the drain 13 is located on the other side of the isolation medium, covering part of the insulating layer 5 and the first conductivity type drain region 7.

[0043] The distance between the insulating layer 5 and the second conductive type well region 4 is in the range of 0.4µm to 2.0µm.

[0044] A method for manufacturing a field effect transistor with an electric field modulation structure according to this embodiment is as follows: Figures 2 to 9 The specific process steps are described, including the following steps:

[0045] Step 1: forming a second conductive type epitaxial layer 2 on a second conductive type substrate 1; Figure 3 、 Figure 4 As shown, a second conductive type epitaxial layer 2 is formed on a second conductive type substrate 1 by epitaxial growth, and the doping concentration of the second conductive type substrate 1 is 1e18cm -3 ~5e20cm -3The doping concentration of the second conductivity type epitaxial layer 2 is 1e14cm -3 ~ 1e17cm -3 ;

[0046] Step 2: forming a first conductivity type drift region 3 in the second conductivity type epitaxial layer 2; Figure 5 As shown, an ion implantation mask layer is formed on the surface of the first conductive type epitaxial layer 2 by a chemical vapor deposition process, and a first conductive type drift region 3 is formed in the second conductive type epitaxial layer 2 by photolithography, implantation, and annealing processes. The first conductive type drift region 3 has a depth range of 1.0µm to 5.0µm, a width range of 1µm to 20µm, and a doping concentration of 1e14cm -3 ~ 1e18cm -3 In the present invention, the doping concentration of the first conductive type drift region 3 is higher than that of the drift region in the conventional structure. In the forward conduction state, the charge controlled by the first conductive type drift region with a higher concentration and the step-shaped conductive material can effectively increase the current density and reduce the on-resistance.

[0047] Step 3: etching a portion of the first conductive type drift region 3 to form a first trench 101; Figure 6 As shown, an ICP (Inductive Coupled Plasma) etching process is performed on the first conductive type drift region 3 through photolithography and etching processes. The etching gas used can be one or a combination of gases such as HBr and Cl2, to form a first trench 101. The depth of the first trench 101 ranges from 0.5µm to 4.0µm, that is, the first trench 101 does not penetrate the first conductive type drift region 3.

[0048] Step 4: forming an insulating layer 5 that completely fills the first trench 101; Figure 7 As shown, an insulating layer 5 is formed in the first trench 101 by a chemical vapor deposition process. The insulating layer 5 completely fills the first trench 101. The insulating layer 5 is made of a material selected from one or more combinations of materials such as SiO2 and Si3N4.

[0049] Step 5: etching a portion of the insulating layer 5 to form a second trench 102; Figure 8 As shown, the insulating layer 5 is etched by photolithography and etching processes. The etching gas used can be one or more combinations of gases such as CF4 and Cl2 to form a second trench 102. The depth of the second trench 102 ranges from 0.4µm to 3.5µm.

[0050] Step 6: etching a portion of the insulating layer 5 to form a third trench 103 communicating with the second trench 102; Figure 9As shown, the insulating layer 5 is etched by photolithography and etching processes, and the etching gas used can be one or more gases such as CF4 and Cl2 to form a third trench 103. The depth of the third trench 103 ranges from 0.3µm to 3.0µm.

[0051] Step 7: etching a portion of the insulating layer 5 to form a fourth trench 104 communicating with the third trench 103; Figure 10 As shown, the insulating layer 5 is etched by photolithography and etching processes. The etching gas used may be one or more combinations of gases such as CF4 and Cl2, to form a fourth trench 104. The depth of the fourth trench 104 ranges from 0.2µm to 2.5µm. The second trench 102, the third trench 103, and the fourth trench 104 constitute a stepped trench. The stepped trench is located in the insulating layer 5, i.e., the total width of the stepped trench is less than the width of the insulating layer 5, and the maximum depth of the stepped trench is less than the depth of the insulating layer 5.

[0052] Step 8: depositing a step-shaped conductive material 8 in the step trench; Figure 11 As shown, a step-shaped conductive material 8 is formed in the stepped trenches, namely the second trench 102, the third trench 103, and the fourth trench 104, through a chemical vapor deposition process, and the device surface is flattened through a chemical mechanical polishing process. The step-shaped conductive material 8 fills the entire step-shaped trench. Corresponding to the step-shaped trench, the step-shaped conductive material 8 includes three levels. The step-shaped conductive material can be polycrystalline silicon, amorphous silicon, or metal. The present invention forms the step-shaped conductive material 8 in the trench 101 and utilizes the different thicknesses of the insulating layer 5 between the different levels of the conductive material of the step-shaped conductive material 8 and the drift region 3 to achieve different adjustment capabilities of the step-shaped conductive material 8 at different locations. Within a certain range, that is, 2≤N≤6, and when taking a natural number, the higher the number of levels of the step-shaped conductive material 8, the better the electric field modulation of the step-shaped conductive material 8. However, if the number of levels is too high, that is, N>6, the electric field modulation effect tends to remain unchanged.

[0053] Step 9: forming a second conductivity type well region 4 adjacent to the first conductivity type drift region 3 in the second conductivity type epitaxial layer 2, forming a first conductivity type source region 6 in the second conductivity type well region 4, and forming a first conductivity type drain region 7 adjacent to the insulating layer 5 in the first conductivity type drift region 3; Figure 12As shown, through photolithography, implantation and annealing processes, a second conductive type well region 4 is formed in the second conductive type epitaxial layer 2, a first conductive type source region 6 is formed in the second conductive type well region 4, and a first conductive type drain region 7 is formed in the first conductive type drift region 3, and the first conductive type drain region 7 is aligned with the boundary of the insulating layer 5; wherein, the second conductive type well region 4 is adjacent to the first conductive type drift region 3 in the second conductive type epitaxial layer 2, and the depth of the second conductive type well region 4 is greater than the depth of the first conductive type drift region 3; the first conductive type drain region 7 is adjacent to the insulating layer 5 in the first conductive type drift region 3, and the depth of the first conductive type drain region 7 is greater than the depth of the insulating layer 5; the depth range of the second conductive type well region 4 is 0.7µm ~ 4.0µm, and the doping concentration is 1e16cm -3 ~ 5e18cm -3 The depth of the first conductive type source region 6 is in the range of 0.2µm to 1.0µm, and the doping concentration is 5e18cm -3 ~ 5e19cm -3 The depth of the first conductive type drain region 7 is in the range of 0.2µm to 1.0µm, and the doping concentration is 5e18cm -3 ~5e19cm -3 .

[0054] Step 9: forming a gate dielectric 9 on the interface between the first conductive type drift region 3 and the second conductive type well region 4, and forming a gate 10 on the gate dielectric 9; Figure 13 As shown, a gate dielectric 9 is formed on the surface of the second conductive type epitaxial layer 2 by a thermal oxidation process. After high-temperature annealing, a gate 10 is formed on the gate dielectric 9 by a chemical vapor deposition process. The gate dielectric 9 is located on a portion of the first conductive type source region 6, a portion of the second conductive type well region 4, and a portion of the first conductive type drift region 3, and is not covered by the insulating layer 5 and the step-shaped conductive material 8. That is, one side of the projection of the gate dielectric 9 is located on the first conductive type source region 6, and the other side is located on the first conductive type drift region 3, and the distance between the side located on the first conductive type drift region 3 and the second conductive type well region 4 is in the range of 0.1µm to 0.8µm. The width of the gate 10 is smaller than the width of the gate dielectric 9, and one side of the projection of the gate 10 is located on the first conductive type source region 6, and the other side is located on the first conductive type drift region 3. The thickness of the gate dielectric 9 is in the range of 30nm to 100nm. The material of the gate 10 can be metal or doped polysilicon.

[0055] Step 10: forming an isolation dielectric 11 on both sides and on top of the gate dielectric 9 and the gate 10; forming a source electrode 12 on one side of the isolation dielectric 11, covering a portion of the second conductivity type well region 4 and a portion of the first conductivity type source region 6; and forming a drain electrode 13 on the other side of the isolation dielectric 11, covering a portion of the insulating layer 5 and the first conductivity type drain region 7; Figure 14 As shown, an isolation dielectric 11 is formed by chemical vapor deposition, contact holes are formed by multiple photolithography and etching processes, metal is deposited and reverse-etched to form a source 12 and a drain 13. Isolation dielectric 11 is located on both sides and above gate dielectric 9, on both sides and above gate 10, on a portion of first conductivity type source region 6, on a portion of insulating layer 5, and on stepped conductive material 8, but does not cover first conductivity type drain region 7. Source 12 is located on one side of isolation dielectric 11, on a portion of second conductivity type well region 4, and on a portion of first conductivity type source region 6. Drain 13 is located on the other side of isolation dielectric 11, on insulating layer 5, and on a portion of first conductivity type drain region 7. Isolation dielectric 11 can be made of silicon dioxide, nitride, or a composite of silicon dioxide and nitride. Source and drain materials can be one or more combinations of metals such as Ti, Al, Ni, and Pt.

[0056] In this embodiment, the stepped trench may be etched using an ICP (Inductive Coupled Plasma) etching process, and the etching gas used may be one or a combination of gases such as CF 4 and Cl 2 .

[0057] In this embodiment, the first conductivity type is N-type or P-type, the second conductivity type is P-type or N-type, and the semiconductor material used in the device, that is, the material of the second conductivity type substrate 1 and the second conductivity type epitaxial layer 2 can be one of Si, SiC and other materials. Example 2

[0058] A field effect transistor with an electric field modulation structure according to this embodiment, such as Figure 2 As shown, the difference from Example 1 is that a second conductive type electrical connection layer 14 is formed in the second conductive type well region 4 and on one side of the first conductive type source region 6. The second conductive type electrical connection layer 14 is adjacent to the first conductive type source region 6 and is away from the first conductive type drift region 3. The bottom of the second conductive type electrical connection layer 14 is flush with or not flush with the bottom of the first conductive type source region 6. The doping concentration of the second conductive type electrical connection layer 14 is 1e18cm -3 ~ 5e19cm -3 The second conductive type electrical connection layer 14 can achieve good contact between the second conductive type well region 4 and the source electrode 12, so that the potential of the second conductive type well region 4 is more stable.

[0059] The manufacturing method of a field effect transistor with an electric field modulation structure in this embodiment refers to Example 1, and the difference from Example 1 is that in step 9, a process of forming a second conductive type electrical connection layer 14 is additionally added, that is, through lithography, injection and annealing processes, a second conductive type electrical connection layer 14 is formed in the second conductive type well region 4 and on one side of the first conductive type source region 6.

[0060] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A field effect transistor having an electric field modulation structure, characterized in that: include: a second conductive type substrate; a second conductive type epitaxial layer located on a second conductive type substrate; A first conductivity type drift region and a second conductivity type well region are located in the second conductivity type epitaxial layer, the first conductivity type drift region and the second conductivity type well region are adjacent to each other; the depth of the second conductivity type well region is greater than the depth of the first conductivity type drift region; a first conductivity type source region located in the second conductivity type well region; An insulating layer and a first conductivity type drain region are located within the first conductivity type drift region, the insulating layer and the first conductivity type drain region are adjacent to each other, and the depth of the first conductivity type drain region is greater than the depth of the insulating layer; the insulating layer is located between the first conductivity type source region and the first conductivity type drain region; the depth of the insulating layer ranges from 0.5µm to 4.0µm, and the distance between the insulating layer and the second conductivity type well region ranges from 0.4µm to 2.0µm; The stepped conductive material is located in the insulating layer. The stepped conductive material includes N levels. The first level conductive material is close to the gate, and the N level conductive material is close to the first conductive type drain region. The depth of the first level conductive material to the N level conductive material decreases. The distance between the bottom of the first level conductive material and the bottom of the insulating layer is D1, the distance between the bottom of the second level conductive material and the bottom of the insulating layer is D2, and so on. The distance between the bottom of the N level conductive material and the bottom of the insulating layer is D N , D1< D2<…… <D N , the difference between D1 and D2 is 0.1µm~1.0µm, the difference between D2 and D3 is 0.1µm~1.0µm, ..., D N-1 With D N The difference is 0.1µm~1.0µm; A gate dielectric located on the interface between the first conductivity type drift region and the second conductivity type well region, with one side of the gate dielectric projection located on the first conductivity type source region and the other side located on the first conductivity type drift region; A gate located on the gate dielectric, wherein the width of the gate is smaller than the width of the gate dielectric; Isolation dielectrics located on both sides of and above the gate dielectric and the gate; A source electrode located on one side of the isolation medium and covering a portion of the second conductive type well region and a portion of the first conductive type source region; A drain electrode is located on the other side of the isolation medium and covers a portion of the insulating layer and the first conductive type drain region.

2. The field effect transistor with an electric field modulation structure according to claim 1, characterized in that: 2≤N≤6, and it must be a natural number.

3. The field effect transistor with an electric field modulation structure according to claim 1, characterized in that: In the stepped conductive material, the depth of the first level conductive material ranges from 0.4µm to 3.5µm.

4. The field effect transistor with an electric field modulation structure according to claim 1, characterized in that: The distance between the side of the gate dielectric projection located above the first conductive type drift region and the second conductive type well region is in the range of 0.1µm to 0.8µm.

5. The field effect transistor with an electric field modulation structure according to claim 1, characterized in that: The depth of the first conductivity type drift region ranges from 1.0µm to 5.0µm, and the doping concentration is 1e14cm -3 ~ 1e18cm -3 ; The step-shaped conductive material is polysilicon, amorphous silicon or metal.

6. The field effect transistor with an electric field modulation structure according to claim 1, characterized in that: The depth of the second conductivity type well region ranges from 0.7µm to 4.0µm, and the doping concentration is 1e16cm -3 ~ 5e18cm -3 The depth of the first conductivity type source region ranges from 0.2µm to 1.0µm, and the doping concentration is 5e18cm -3 ~ 5e19cm -3 The depth of the first conductivity type drain region ranges from 0.2µm to 1.0µm, and the doping concentration is 5e18cm -3 ~ 5e19cm -3 .

7. The field effect transistor with an electric field modulation structure according to claim 1, characterized in that: The system further includes a second conductive type electrical connection layer, which is located in the second conductive type well region and adjacent to the first conductive type source region.

8. A method for manufacturing a field effect transistor with an electric field modulation structure, for manufacturing a field effect transistor with an electric field modulation structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: forming a second conductive type epitaxial layer on a second conductive type substrate; forming a first conductivity type drift region in the second conductivity type epitaxial layer; etching a portion of the first conductive type drift region to form a first trench; forming an insulating layer that completely fills the first trench; etching the insulating layer to form a stepped trench, thereby forming a stepped conductive material that completely fills the stepped trench; The stepped conductive material includes N levels, the first level conductive material is close to the gate, the N level conductive material is close to the first conductive type drain region, the depth of the first level conductive material to the N level conductive material decreases, the distance between the bottom of the first level conductive material and the bottom of the insulating layer is D1, the distance between the bottom of the second level conductive material and the bottom of the insulating layer is D2, and so on, the distance between the bottom of the N level conductive material and the bottom of the insulating layer is D N , D1< D2<…… <D N , the difference between D1 and D2 is 0.1µm~1.0µm, the difference between D2 and D3 is 0.1µm~1.0µm, ..., D N-1 With D N The difference is 0.1µm~1.0µm; forming a second conductivity type well region adjacent to the first conductivity type drift region in the second conductivity type epitaxial layer, forming a first conductivity type source region in the second conductivity type well region, and forming a first conductivity type drain region adjacent to the insulating layer in the first conductivity type drift region; the depth of the second conductivity type well region is greater than the depth of the first conductivity type drift region; and the depth of the first conductivity type drain region is greater than the depth of the insulating layer; forming a gate dielectric on the interface between the first conductive type drift region and the second conductive type well region, and forming a gate on the gate dielectric; An isolation dielectric is formed on both sides and above the gate dielectric and the gate, a source is formed on one side of the isolation dielectric, covering a portion of the second conductive type well region and a portion of the first conductive type source region, and a drain is formed on the other side of the isolation dielectric, covering a portion of the insulating layer and the first conductive type drain region.

9. The method for manufacturing a field effect transistor with an electric field modulation structure according to claim 8, characterized in that: The method further includes forming a second conductive type electrical connection layer in the second conductive type well region, wherein the second conductive type electrical connection layer is adjacent to the first conductive type source region.

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