Driving circuit and display device

Abstract

The present application discloses a driving circuit and a display device; the driving circuit comprises a connected control module, a plurality of switch modules, a plurality of light-emitting modules and a plurality of driving modules, each switch module comprises a plurality of switch circuits, the switch circuits are used to output switch signals, the light-emitting module comprises a plurality of light-emitting elements receiving switch signals, the plurality of switch circuits comprises at least a first switch circuit, in the same signal frame, the starting time of the switch signals output by at least two first switch circuits are different; the present application makes the switch signals received by the light-emitting elements connected to the same switch circuit have a phase difference, thereby avoiding that a plurality of light-emitting elements are simultaneously lit when the driving chip drives the light-emitting elements to light up, eliminating the technical problem of superposition of a plurality of drive signals of the same frequency, and improving the electromagnetic interference phenomenon in the driving circuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit display device. Background Art

[0002] Mini LED display panels have significant advantages such as higher brightness, better luminous efficiency and lower power consumption. The backlight of the Mini LED display panel supports multi-zone dynamic dimming and can achieve a contrast ratio of millions. It has become the focus of research in the display panel industry.

[0003] In order to achieve the independent dimming effect of multiple backlight zones, the lamp beads of each zone need to be controlled independently. When the number of zones exceeds the upper limit of the number of channels of the driver chip, multiple driver chips are required to drive the backlight. When multiple driver chips are driving the lamp beads to light up, when a certain number of lamp beads are turned on or off at the same time, multiple driving signals of the same frequency are superimposed together, and there will be strong harmonics at the frequency doubling, resulting in serious electromagnetic interference, which will cause serious interference to the display panel. Summary of the invention

[0004] The present application provides a driving circuit and a display device to alleviate the technical problem of electromagnetic interference in the existing driving circuit.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a driving circuit, which includes

[0007] Control module;

[0008] A plurality of switch modules connected to the control module, each of the switch modules comprising a plurality of switch circuits, and the switch circuits are used to output switch signals;

[0009] A plurality of light-emitting modules, used to receive the switch signal, one of the light-emitting modules is connected to one of the switch modules, and the light-emitting modules include a plurality of light-emitting elements;

[0010] A plurality of driving modules, wherein one of the driving modules is connected to one of the light emitting modules and the control module;

[0011] The plurality of switch circuits include at least a first switch circuit, and in the same signal frame, the start times of the switch signals output by at least two of the first switch circuits are different.

[0012] The present application also proposes a display device, which includes the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0014] Figure 1 It is a timing diagram of a driving circuit under PWM dimming in the prior art;

[0015] Figure 2 It is a timing diagram of a driving circuit under DC dimming in the prior art;

[0016] Figure 3 It is a timing diagram of a driving circuit under time-sharing row scanning in the prior art;

[0017] Figure 4 This is a structural diagram of the driving circuit of this application;

[0018] Figure 5 This is a structural diagram of a switch circuit in the driving circuit of this application;

[0019] Figure 6 for Figure 5 Timing diagram of each node in;

[0020] Figure 7 is a time distribution diagram of the potential of the internal node in the delay unit with different resistance and capacitance;

[0021] Figure 8 A timing diagram of switch signals output by different switch circuits in an existing drive circuit;

[0022] Fig. 9 A timing diagram of switch signals output by different switch circuits in the driving circuit of the present application;

[0023] Fig.10 for Figure 4 A brief timing diagram of the drive circuit in the figure;

[0024] Fig.11 This is a working diagram of the time-sharing and frequency-staggered driving circuit of this application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] In current technology, in order to achieve the independent dimming effect of multiple backlight zones, it is necessary to independently control the lamp beads of each zone. When the number of zones exceeds the upper limit of the number of channels of the driver chip, multiple driver chips are required to drive the backlight. The driver chip usually dims the lamp beads by adjusting the duty cycle of the switch (PWM) dimming and adjusting the direct current (DC) dimming. For example, Figure 1 and attached Figure 2 .

[0027] As for PWM dimming, when multiple driver chips are driving the lamp beads to light up, when a certain number of lamp beads are turned on or off at the same time, multiple driving signals of the same frequency are superimposed together, and there will be strong harmonics at the frequency doubling, generating more serious electromagnetic interference, which will cause serious interference to the display panel; at the same time, for example Figure 3 When using line scanning, switching electromagnetic interference noise will also be generated when opening and closing the line scanning device. Therefore, the present application proposes a driving circuit based on the above technical problem.

[0028] See also Figure 4 The present application provides a driving circuit 10, which may include a control module 100, multiple switch modules 200, multiple light-emitting modules 300 and multiple driving modules 400, multiple switch modules 200 are connected to the control module 100, one light-emitting module 300 is connected to one switch module 200, and one driving module 400 is connected to one light-emitting module 300, that is, the driving modules 400 correspond to the switch modules 200 one by one, and multiple driving modules 400 are connected to the control module 100 at the same time.

[0029] In this embodiment, each switch module 200 includes a plurality of switch circuits 210 for outputting switch signals, and the light emitting module 300 includes a plurality of light emitting elements D for receiving the switch signals output by the switch circuits 210 .

[0030] In this embodiment, the plurality of switch circuits 210 at least include a first switch circuit 210a. In the same signal frame, the start times of the switch signals output by at least two first switch circuits 210a are different.

[0031] It should be noted that the starting time of the switching signal in the present application refers to the time when the switching signal reaches a high level, or the end time of the rising edge of the waveform of the switching signal.

[0032] The present application makes the switching signals received by the light-emitting elements D connected to the same switching circuit 210 have a phase difference, thereby avoiding the situation where multiple light-emitting elements D are lit up at the same time when the driving chip drives the light-emitting elements D to light up, eliminating the technical problem of superposition of multiple driving signals of the same frequency, and improving the electromagnetic interference phenomenon in the driving circuit 10.

[0033] It should be noted that the number of the switch modules 200, the number of the light emitting modules 300 and the number of the driving modules 400 are all equal. Figure 4 The driving circuit 10 is illustrated by taking two switch modules 200, two light-emitting modules 300 and two driving modules 400 as an example; at the same time, the number of switch circuits 210 in each light-emitting module 300 can be the same or different. Each light-emitting module 300 of the present application can be provided with three switch circuits 210, and the output end of the switch circuit 210 is connected to the anode of the corresponding light-emitting element D.

[0034] It should be noted that the light-emitting element D of the present application may be LED, Mini LED or Micro LED.

[0035] It should be noted that a plurality of driving output terminals 410 are provided on the driving module 400, and one driving output terminal 410 can be connected to a column of light-emitting elements D in a light-emitting module 300, and one switching circuit 210 can be connected to a row of light-emitting elements D in a light-emitting module 300. For example, in the present application, two driving output terminals 410 can be provided on a driving module 400, and a light-emitting module 300 is provided with six light-emitting elements D distributed in 3*2, namely D1 to D6, each switching circuit 210 is simultaneously connected to the anodes of two light-emitting elements D located in the same row, and each signal output terminal is electrically connected to the cathodes of three light-emitting elements D located in the same column.

[0036] It should be noted that the driving module 400 can be a driving chip, and one driving module 400 is used to drive one light-emitting module 300; the control module 100 can be an FPGA (Field Programmable Gate Array), and the control module 100 is used to output a control signal to the switching circuit 210 in the switching module 200, and the switching circuit 210 receives the control signal and transmits an anode voltage to the anode of the light-emitting element D, and the driving module 400 transmits a cathode voltage to the light-emitting element D.

[0037] In the driving circuit 10 of the present application, the structures of the switch circuits 210 may be the same or different. The following description will be made by taking the example that the structures of each switch circuit 210 are the same.

[0038] See also Figure 5The switch circuit 210 may include a first delay unit 211, a second delay unit 212, a third delay unit 213, a first transistor T1, a second transistor T2, a third transistor T3 and a voltage dividing resistor R0.

[0039] In the present embodiment, the first delay unit 211 has a first internal node P1, a first end of the first delay unit 211 is connected to the first control node Q1, and a second end of the first delay unit 211 is connected to the first potential line Vgl; the gate of the first transistor T1 is connected to the first internal node P1, the first electrode of the first transistor T1 is connected to the second control node Q2, and the second electrode of the first transistor T1 is connected to the first potential line Vgl; the gate of the second transistor T2 is connected to the second control node Q2, and the first electrode of the second transistor T2 is connected to the first control node Q1; the second delay unit 212 has a second internal node P2, and the second electrode of the second transistor T2 is connected to the first control node Q1. Connected to the second internal node P2, the first end and the second end of the second delay unit 212 are both connected to the first potential line Vgl; the gate of the third transistor T3 is connected to the second internal node P2, and the first electrode of the third transistor T3 is connected to the second potential line Vgh; the third delay unit 213 has a third internal node P3, the first end of the third delay unit 213 is connected to the second electrode of the third transistor T3, the second end of the third delay unit 213 is connected to the first potential line Vgl, and the third internal node P3 is connected to the anode of the light-emitting element D; the first end of the voltage-dividing resistor R0 is connected to the first control node Q1, and the second end of the voltage-dividing resistor R0 is connected to the second control node Q2.

[0040] In this embodiment, the first delay unit 211 includes a first resistor R1 and a first capacitor C1 connected to the first internal node P1, one end of the first resistor R1 away from the first capacitor C1 is connected to the first control node Q1, and one end of the first capacitor C1 away from the first resistor R1 is connected to the first potential line Vgl; the second delay unit 212 includes a second resistor R2 and a second capacitor C2, one end of the second resistor R2 and the second capacitor C2 is connected to the second internal node P2, and the other end of the second resistor R2 and the second capacitor C2 is connected to the first potential line Vgl; the third delay unit 213 includes a third resistor R3 and a third capacitor C3 connected to the third internal node P3, one end of the third resistor R3 away from the third capacitor C3 is connected to the second electrode of the third transistor T3, and one end of the third capacitor C3 away from the third resistor R3 is connected to the first potential line Vgl.

[0041] In the driving circuit 10 of the present application, the first transistor T1 can be an N-type transistor or a P-type transistor, and the second transistor T2 and the third transistor T3 can be an N-type transistor or the other of the P-type transistors. The following is an example in which the first transistor T1 is an N-type transistor and the second transistor T2 and the third transistor T3 are P-type transistors.

[0042] In this embodiment, the first potential line Vgl may be a constant voltage low level line, such as a ground line; and the second potential line Vgh may be a constant voltage high level line.

[0043] In this embodiment, the resistance value of the voltage divider resistor R0 can be 10 5 Ohm to 10 6 ohm.

[0044] In this embodiment, the output terminal of the control module 100 is connected to the first control node Q1.

[0045] According to the following Figure 6 The timing diagram of Figure 5 The working process of the switching circuit 210 is described below.

[0046] In the first stage, when the control signal output by the control module 100 is at a high level, that is, the potential of the first control node Q1 is at a high level, the first internal node P1 and the first control node Q1 are connected in series, so the first internal node P1 is at a high level; since the first transistor T1 is an N-type transistor, that is, the first transistor T1 is turned on by the high level of the first internal node P1, the second control node Q2 will be connected to the first potential line Vgl, and since the voltage-dividing resistor R0 is a resistor with a large resistance, the voltage of the first control node Q1 is divided by the voltage-dividing resistor R0, so the second control node Q2 is at a low level; since the second transistor T2 is a P-type transistor, the second transistor T2 is turned on by the low level of the second control node Q2, the second internal node P2 will be connected to the first control node Q1, and the potential of the second internal node P2 is at a high level; and since the third transistor T3 is a P-type transistor, the third transistor T3 is cut off, the third internal node P3 outputs a low level to the corresponding light-emitting element D, and the light-emitting element D does not emit light.

[0047] In the second stage, when the control signal output by the control module 100 is at a high level, that is, the potential of the first control node Q1 is at a low level, the first internal node P1 and the first control node Q1 are connected in series, and due to the existence of the first capacitor C1, the discharge of the first capacitor C1 maintains the first internal node P1 at a high level for a period of time, and then the potential of the first internal node P1 gradually decreases, and when the voltage difference between the potential of the first internal node P1 and the first potential line Vgl is less than the threshold voltage of the first transistor T1, the first transistor T1 is turned off, and the potential of the first internal node P1 gradually decreases; at the same time, when the second control node Q2 is at a low level, the potential of the second internal node P2 is pulled down by the low potential of the first control node Q1, and due to the second capacitor C2 Discharging, the second internal node P2 continues to be at a high level for a period of time after the first control node Q1 becomes a low level, and the potential of the second internal node P2 continues to be pulled down. When the potential of the second internal node P2 is as low as the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the third internal node P3 will be connected to the second potential line Vgh. Due to the existence of the third capacitor C3, the stretching of the potential of the third internal node P3 will be delayed from the moment when the second internal node P2 is at a low level. As the third capacitor C3 is charged, the potential of the third internal node P3 will gradually increase until the potential of the third internal node P3 is equal to the voltage of the second potential line Vgh, and the third internal node P3 outputs a high level to the corresponding light-emitting element D, and the light-emitting element D emits light.

[0048] In the third stage, when the control signal output by the control module 100 is at a high level, that is, the potential of the first control node Q1 is at a high level, the first internal node P1 and the first control node Q1 are connected in series, and due to the existence of the first capacitor C1, the first capacitor C1 is charged, and the potential of the first internal node P1 gradually increases; and when the first transistor T1 is turned off, since the resistance of the first transistor T1 is greater than the resistance of the voltage-dividing resistor R0, the potential of the second control node Q2 is the same as that of the first control node Q1, and the potential of the second control node Q2 is at a high level, that is, the second transistor T2 is turned off, at this time, the second internal node P2 is connected to the first potential line Vgl through the second resistor R2, and the second internal node P2 is continuously at a low level, the third transistor T3 is turned on, and the potential of the third internal node P3 is the same as the voltage of the second potential line Vgh, and the third internal node P3 outputs a high level to the corresponding light-emitting element D, and the light-emitting element D emits light; as the potential of the first internal node P1 increases To a high level, the first transistor T1 is turned on by the high level of the first internal node P1, and the second control node Q2 will be connected to the first potential line Vgl, and because the voltage-dividing resistor R0 is a resistor with a larger resistance, the voltage of the first control node Q1 is divided by the voltage-dividing resistor R0, so the second control node Q2 is a low level, so the second transistor T2 is turned on by the low level of the second control node Q2, and the second internal node P2 will be connected to the first control node Q1, and due to the existence of the second capacitor C2, the potential of the second internal node P2 gradually increases to a high level, when the potential of the second internal node P2 is greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned off, the third internal node P3 and the second potential line Vgh are disconnected, the third capacitor C3 discharges to maintain the high potential of the third internal node P3 for a period of time, and then the potential of the third internal node P3 gradually decreases to a low level, the third internal node P3 outputs a low level to the corresponding light-emitting element D, and the light-emitting element D does not emit light.

[0049] exist Figure 5 and Figure 6 In the structure, the combination of the first resistor R1 and the first capacitor C1, the combination of the second resistor R2 and the second capacitor C2, and the combination of the third resistor R3 and the third capacitor C3 each constitute a resistor-capacitor delay circuit. Figure 6 The absolute value of the slope of the rising edge or falling edge of the first internal node P1, the second internal node P2 and the third internal node P3 is negatively correlated with the product of the corresponding resistance and capacitance.

[0050] For example, the product of the resistance of the first resistor R1 and the capacitance of the first capacitor C1 is the first product, the product of the resistance of the second resistor R2 and the capacitance of the second capacitor C2 is the second product, and the product of the resistance of the third resistor R3 and the capacitance of the third capacitor C3 is the third product. When the first product, the second product and the third product are all equal, the absolute values ​​of the slopes of the rising edges or falling edges of the first internal node P1, the second internal node P2 and the third internal node P3 are all equal. When the first product is minimum and the third product is maximum, the absolute value of the slope of the rising edge or falling edge of the first internal node P1 is maximum, and the absolute value of the slope of the rising edge or falling edge of the third internal node P3 is minimum.

[0051] Similarly, see Figure 7 , Figure 7 The distribution diagram of the potential of the internal node in the delay unit with different resistance and capacitance over time, the horizontal axis is time, the vertical axis is voltage value, Figure 7 There are 9 curves in total. In the direction from curve A to curve B, the product of the resistance and capacitance in the delay unit gradually increases, and the absolute value of the slope of the rising edge or falling edge of the waveform gradually decreases, that is, the rising edge or falling edge of the same curve gradually slows down.

[0052] In this embodiment, the product of the resistance of the first resistor R1 and the capacitance of the first capacitor C1 may be smaller than the product of the resistance of the third resistor R3 and the capacitance of the third capacitor C3, and the product of the resistance of the second resistor R2 and the capacitance of the second capacitor C2 may be smaller than the product of the resistance of the third resistor R3 and the capacitance of the third capacitor C3. That is, the absolute value of the slope of the waveform of the third internal node P3 of the present application at the rising edge or the falling edge is the smallest, and the rising edge or the falling edge is the slowest, so as to reduce the radiation energy of the light-emitting element D due to instantaneous opening.

[0053] In this embodiment, the plurality of switch modules 200 include a first switch module 200a and a second switch module 200b. The first switch module 200a and the second switch module 200b each include at least a first switch circuit 210a.

[0054] In this embodiment, the control module 100 may include multiple switch output terminals, and one switch output terminal is connected to a switch circuit 210 in each switch module 200; for example, the control module 100 includes at least a first switch output terminal 101, and the first switch output terminal 101 is connected to the first control node Q1 of the first switch circuit 210a in the first switch module 200a and the second switch module 200b. In the same signal frame, the rising edge of the waveform of the switch signal output by the first switch circuit 210a in the first switch module 200a has a first slope, and the rising edge of the waveform of the switch signal output by the first switch circuit 210a in the second switch module 200b has a second slope, and the first slope and the second slope are different.

[0055] For example, Figure 4 In the structure, the first switch module 200a and the second switch module 200b may include a first switch circuit 210a, a second switch circuit 210b and a third switch circuit 210c, the multiple light-emitting modules 300 may include a first light-emitting module 300a and a second light-emitting module 300b, and the control module 100 may be provided with a first switch output terminal 101, a second switch output terminal 102 and a third switch output terminal 103, that is, the first switch output terminal 101 is connected to the first control node Q1 of the first switch circuit 210a in the first switch module 200a and the second switch module 200b, the second switch output terminal 102 is connected to the first control node Q1 of the second switch circuit 210b in the first switch module 200a and the second switch module 200b, and the third switch output terminal 103 is connected to the first control node Q1 of the third switch circuit 210c in the first switch module 200a and the second switch module 200b. The following description only takes the first switch output terminal 101 and the first switch circuit 210a as an example.

[0056] In the prior art, see Figure 8 When the control module receives the start signal Vs, it transmits the control signal to the first switch circuit 210a in the first switch module 200a and the second switch module 200b through the first switch output terminal 101 at the same time. The switch signal SW1 transmitted by the first switch circuit 210a to the light-emitting element D is a high level, that is, the high level reaches the light-emitting element D connected to the first switch circuit 210a in each switch module 200 at the same time, and the light-emitting element D will be turned on at the same time, resulting in relatively large noise.

[0057] In this example, see Fig. 9 In the first switch module 200a, the rising edge of the waveform of the switching signal output by the first switch circuit 210a has a first slope, and in the second switch module 200b, the rising edge of the waveform of the switching signal output by the first switch circuit 210a has a second slope. Since the first slope and the second slope are different, the moment when the third internal node P3 in the first switch circuit 210a in the first switch module 200a reaches a high level is different from the moment when the third internal node P3 in the first switch circuit 210a in the second switch module 200b reaches a high level, and the two are staggered with each other, thereby avoiding the light-emitting element D from being turned on at the same time, eliminating the technical problem of superposition of multiple driving signals of the same frequency, and improving the electromagnetic interference phenomenon in the driving circuit 10.

[0058] It should be noted that Fig. 9For the sake of convenience in description, the difference in slope of the rising edge of the third internal node P3 in different switch modules 200 is not included, and only the starting time when the third internal node P3 reaches a high level is differentiated. The actual situation is that the starting time of the rising edge of the third internal node P3 in different switch modules 200 is the same, and the cut-off time when it reaches a high level is different.

[0059] It should be noted that the attached Figure 8 and Fig. 9 The SWn signal in is the switch signal transmitted by the nth switch circuit 210 in the switch module 200 .

[0060] In this embodiment, the third capacitor C3 of the first switch circuit 210a in the first switch module 200a can be the same as the third capacitor C3 of the first switch circuit 210a in the second switch module 200b, and the resistance value of the third resistor R3 of the first switch circuit 210a in the first switch module 200a is less than the resistance value of the third resistor R3 of the first switch circuit 210a in the second switch module 200b; or, the third resistor R3 of the first switch circuit 210a in the first switch module 200a can be the third resistor R3 of the first switch circuit 210a in the second switch module 200b. The third resistors R3 of the switch circuits 210a are the same, and the capacitance of the third capacitor C3 of the first switch circuit 210a in the first switch module 200a is smaller than the capacitance of the third capacitor C3 of the first switch circuit 210a in the second switch module 200b; or, the product of the resistance value of the third resistor R3 of the first switch circuit 210a in the first switch module 200a and the capacitance value of the third capacitor C3 is smaller than the product of the resistance value of the third resistor R3 of the first switch circuit 210a in the second switch module 200b and the capacitance value of the third capacitor C3.

[0061] In this embodiment, in addition to adjusting the third resistor R3 and the third capacitor C3, the present application can also make the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 of the first switch circuit 210a in the first switch module 200a smaller than the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 of the first switch circuit 210a in the second switch module 200b; or / and the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2 of the first switch circuit 210a in the first switch module 200a is smaller than the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2 of the first switch circuit 210a in the second switch module 200b.

[0062] Therefore, the adjustment of the third resistor R3 and the third capacitor C3 is to adjust the cut-off time when the rising edge of the third internal node P3 reaches a high level, and the adjustment of the first resistor R1 and the first capacitor C1, that is, the adjustment of the second resistor R2 and the second capacitor C2 is to adjust the difference in the starting time of the rising edge of the third internal node P3, that is, the present application can make the slope of the rising edge of the third internal node P3 in different switch modules 200 the same, but the starting time of the rising edge is designed differently to avoid the light-emitting element D from being turned on at the same time, eliminating the technical problem of superposition of multiple driving signals of the same frequency.

[0063] See also Figure 4 , the multiple light-emitting elements D include at least a first light-emitting element and a second light-emitting element, the anode of the first light-emitting element and the anode of the second light-emitting element are both connected to the third internal node P3 of the same first switch circuit 210a; the driving module 400 includes at least a first driving output terminal 410a and a second driving output terminal 410b, the cathode of the first light-emitting element is connected to the first driving output terminal 410a, and the cathode of the second light-emitting element is connected to the second driving output terminal 410b. In a signal frame, the driving signal output by the first driving output terminal 410a is different from the driving signal output by the second driving output terminal 410b.

[0064] In this embodiment, for example, the first light-emitting element may be the light-emitting element D1 in the light-emitting module 300, the second light-emitting element may be the light-emitting element D2 in the light-emitting module 300, the driving module 400 may include n driving output terminals 410, and this application only takes two driving output terminals 410 as an example for illustration, the first driving output terminal 410a is connected to the first column of light-emitting elements D1 to D3, and the second driving output terminal 410b is connected to the second column of light-emitting elements D4 to D6.

[0065] In this embodiment, the control module 100 also includes a brightness output terminal 120a and a synchronization output terminal 120b, and each driving module 400 includes a brightness receiving terminal 420a and a synchronization receiving terminal 420b. The brightness output terminal 120a is connected to the brightness receiving terminal 420a in each driving module 400, and the synchronization output terminal 120b is connected to the synchronization receiving terminal 420b in each driving module 400.

[0066] For details, please refer to the attached Fig.10As shown in the timing diagram, before each signal frame is turned on, the brightness output terminal 120a outputs a brightness signal to the brightness receiving terminal 420a, and the driving module 400 outputs the same or different cathode voltages to the light-emitting elements D in different columns through each driving output terminal 410 according to the brightness signal; at the same time, the synchronization output terminal 120b outputs a synchronization signal to the synchronization receiving terminal 420b. For example, the control module 100 has 4 or more built-in scanning frequencies, and the control module 100 can select a suitable scanning frequency according to the display state of the display device. The scanning frequency of the present application is mainly adjusted by the frequency of the control signal output by the switch output terminal in the control module 100; taking PWM dimming and a scanning frequency of 480HZ as an example, within 1 / 480s, the light-emitting elements D1 to D3 need to be lit once each, and the driving output terminal 410 needs to synchronously transmit the cathode signal to the corresponding light-emitting element D.

[0067] For the specific working process, please refer to the attached Fig.11 Before each signal frame is started, the control module 100 first selects a suitable scanning frequency according to the display state of the display device to configure the frequency; secondly, the control module 100 configures the driving current to transmit and output the same or different cathode voltages to the driving module 400; thirdly, the synchronization output terminal 120b of the control module 100 outputs a synchronization signal to the synchronization receiving terminal 420b of the driving module 400; finally, the control module 100 outputs a control signal to the first control node of the switch module 200.

[0068] It should be noted that, during the next scanning frame, the control module of the present application can be configured with different scanning frequencies. For example, when the control module 100 has four built-in scanning frequencies, four different scanning frequencies can be configured in four scanning stages to achieve time-sharing staggered frequency scanning, avoid frequency concentration of scanning energy, and further reduce the technical problem of electromagnetic interference.

[0069] For example, see Figure 4The first switch output terminal simultaneously outputs the same first control signal S1 to the first switch circuit 210a of the first switch module 200a and the second switch module 200b, and the first switch circuit 210a of the first switch module 200a and the second switch module 200b outputs the first switch signal K1 to the light-emitting elements D1 and D4 in the light-emitting module 300 according to the first control signal S1; the second switch output terminal simultaneously outputs the same second control signal S2 to the second switch circuit 210b of the first switch module 200a and the second switch module 200b, and the first switch module 200a and the second switch circuit 210b output the first switch signal K1 to the light-emitting elements D1 and D4 in the light-emitting module 300. 0a and the second switch circuit 210b of the second switch module 200b output the second switch signal K2 to the light-emitting elements D2 and D5 in the light-emitting module 300 according to the second control signal S2; the third switch output end simultaneously outputs the same third control signal S3 to the third switch circuit 210c of the first switch module 200a and the second switch module 200b, and the third switch circuit 210c of the first switch module 200a and the second switch module 200b outputs the third switch signal K3 to the light-emitting elements D3 and D6 in the light-emitting module 300 according to the third control signal S3.

[0070] In this embodiment, in each switch module 200 , the switching signals output by the multiple switch circuits 210 in the same scanning frame have the same frequency, and the switching signals output by the multiple switch circuits 210 in two adjacent scanning frames have different frequencies.

[0071] For example, in the first scanning frame, the control module 100 outputs the first control signal S1, the second control signal S2 and the third control signal S3 having the first frequency to the corresponding switch circuit 210 through the switch output terminal, and the switch circuit 210 outputs the first switch signal K1, the second switch signal K2 and the third switch signal K3 respectively according to the corresponding first control signal S1, the second control signal S2 and the third control signal S3. Since the frequencies of the first control signal S1, the second control signal S2 and the third control signal S3 are the same, the frequencies of the first switch signal K1, the second switch signal K2 and the third switch signal K3 are The rates may be the same; similarly, in the second scanning frame, the control module 100 outputs the first control signal S1, the second control signal S2 and the third control signal S3 having a second frequency to the corresponding switching circuit 210 through the switch output terminal, and the frequencies of the first switching signal K1, the second switching signal K2 and the third switching signal K3 may be the same. At the same time, the first frequency and the second frequency of the present application may be different, so as to realize that the switching signal output by the switching circuit 210 in different scanning frames has different frequencies, so as to realize time-sharing staggered frequency scanning of the driving circuit, avoid the frequency concentration of the scanning energy, and reduce the technical problem of electromagnetic interference.

[0072] Similarly, when the control module 100 has four built-in scanning frequencies and has four or more switch modules 200, the four scanning frequencies are used to configure different scanning frequencies in four consecutive scanning stages; for example, in the first scanning frame, the control module 100 can configure a first control signal S1 with a first frequency to all switch circuits 210, in the second scanning frame, the control module 100 can configure a second control signal S2 with a second frequency to all switch circuits 210, in the third scanning frame, the control module 100 can configure a third control signal S3 with a third frequency to all switch circuits 210, in the fourth scanning frame, the control module 100 can configure a fourth control signal (not shown) with a fourth frequency to all switch circuits 210, and in the fifth scanning frame, the control module 100 can configure the first control signal S1 with the first frequency to all switch circuits 210, and subsequent scanning frames can configure the scanning frequencies according to the above scanning method.

[0073] It should be noted that, in the present application, a scanning frame is the time required for all light-emitting elements in the driving circuit to complete a scan.

[0074] In this embodiment, in each switch module 200, the frequencies of the switch signals output by two adjacent switch circuits 210 are different. Figure 4 In each scanning phase, the control module 100 outputs a first control signal S1 having a first frequency to the first switch circuit 210a through the first switch output terminal 101, and the first switch circuit 210a outputs a first switch signal K1 according to the first control signal S1; the control module 100 outputs a second control signal S2 having a second frequency to the second switch circuit 210b through the second switch output terminal 102, and the second switch circuit 210b outputs a second switch signal K2 according to the second control signal S2; the control module 100 outputs a second control signal S2 having a second frequency to the third switch circuit 210c through the third switch output terminal 103, and the second switch circuit 210c outputs a second switch signal K2 according to the second control signal S2. A third control signal S3 having a third frequency is output, and the third switch circuit 210c outputs a third switch signal K3 according to the third control signal S3; since the frequencies of the first control signal S1, the second control signal S2 and the third control signal S3 are all different, the frequencies of the first switch signal K1, the second switch signal K2 and the third switch signal K3 are all different, so that the switch signals output by two adjacent switch circuits 210 in the same scanning frame have different frequencies, so as to realize time-sharing staggered frequency scanning of the driving circuit 10, avoid the frequency concentration of the scanning energy, and reduce the technical problem of electromagnetic interference.

[0075] Similarly, when the control module 100 has four built-in scanning frequencies and the switch module 200 has four or more switch circuits 210, the four scanning frequencies are used to configure different scanning frequencies in four consecutive switch circuits 210; for example, in the first signal frame, the control module 100 can configure a first control signal S1 with a first frequency to all first switch circuits 210a, in the second signal frame, the control module 100 can configure a second control signal S2 with a second frequency to all second switch circuits 210b, in the third signal frame, the control module 100 can configure a third control signal S3 with a third frequency to all third switch circuits 210c, in the fourth signal frame, the control module 100 can configure a fourth control signal (not shown) with a fourth frequency to all fourth switch circuits (not shown), and in the fifth signal frame, the control module 100 can configure the first control signal S1 with a first frequency to all fifth switch circuits (not shown), and subsequent signal frames can configure the scanning frequencies in the above-mentioned scanning manner.

[0076] It should be noted that, in the present application, a signal frame is the time required for all light-emitting elements connected to the same switch output terminal in the driving circuit to complete a scan.

[0077] The present application also proposes a display device, which includes the above-mentioned driving circuit, and the display device can be a liquid crystal display panel or a direct display panel. The display device can include electronic devices such as mobile phones, televisions, and laptops.

[0078] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0079] The above is a detailed introduction to a driving circuit and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, characterized in that: include Control module; A plurality of switch modules connected to the control module, each of the switch modules comprising a plurality of switch circuits, the switch circuits being used to output switch signals, the plurality of switch circuits comprising at least a first switch circuit, and in the same signal frame, the start time of the switch signals output by the first switch circuits of at least two of the switch modules being different; A plurality of light-emitting modules, used for receiving the switch signal, the light-emitting modules are connected to the switch modules in a one-to-one correspondence, and the light-emitting modules include a plurality of light-emitting elements; A plurality of driving modules, wherein the driving modules correspond to the switch modules one by one, the driving modules are connected to the light emitting modules one by one, and the control module is connected to the plurality of driving modules; Wherein, the switch circuit comprises: A first delay unit has a first internal node, a first end of the first delay unit is connected to a first control node, and a second end of the first delay unit is connected to a first potential line; a first transistor, wherein a gate of the first transistor is connected to the first internal node, a first electrode of the first transistor is connected to a second control node, and a second electrode of the first transistor is connected to the first potential line; a second transistor, wherein a gate of the second transistor is connected to the second control node, and a first electrode of the second transistor is connected to the first control node; A second delay unit has a second internal node, a second electrode of the second transistor is connected to the second internal node, and a first end and a second end of the second delay unit are both connected to the first potential line; a third transistor, wherein a gate of the third transistor is connected to the second internal node, and a first electrode of the third transistor is connected to a second potential line; a third delay unit having a third internal node, a first end of the third delay unit connected to the second electrode of the third transistor, a second end of the third delay unit connected to the first potential line, and the third internal node connected to the anode of the light emitting element; and A voltage-dividing resistor, wherein a first end of the voltage-dividing resistor is connected to the first control node, and a second end of the voltage-dividing resistor is connected to the second control node.

2. The driving circuit according to claim 1, characterized in that: The first delay unit comprises a first resistor and a first capacitor connected to the first internal node, an end of the first resistor away from the first capacitor is connected to the first control node, and an end of the first capacitor away from the first resistor is connected to the first potential line; The second delay unit comprises a second resistor and a second capacitor, one end of the second resistor and the second capacitor are connected to the second internal node, and the other end of the second resistor and the second capacitor are connected to the first potential line; The third delay unit includes a third resistor and a third capacitor connected to the third internal node, one end of the third resistor away from the third capacitor is connected to the second electrode of the third transistor, and one end of the third capacitor away from the third resistor is connected to the first potential line.

3. The driving circuit according to claim 2, characterized in that: The product of the resistance value of the first resistor and the capacitance of the first capacitor is smaller than the product of the resistance value of the third resistor and the capacitance of the third capacitor, and the product of the resistance value of the second resistor and the capacitance of the second capacitor is smaller than the product of the resistance value of the third resistor and the capacitance of the third capacitor.

4. The driving circuit according to claim 2, characterized in that: The plurality of switch modules include a first switch module and a second switch module, and the first switch module and the second switch module both include at least the first switch circuit; Wherein, the control module at least includes a first switch output terminal, and the first switch output terminal is connected to the first control node of the first switch circuit in the first switch module and the second switch module; The product of the resistance value of the first resistor of the first switch circuit in the first switch module and the capacitance value of the first capacitor is less than the product of the resistance value of the first resistor of the first switch circuit in the second switch module and the capacitance value of the first capacitor; or / and The product of the resistance value of the second resistor of the first switch circuit in the first switch module and the capacitance value of the second capacitor is less than the product of the resistance value of the second resistor of the first switch circuit in the second switch module and the capacitance value of the second capacitor; or / and The product of the resistance value of the third resistor and the capacitance value of the third capacitor of the first switch circuit in the first switch module is smaller than the product of the resistance value of the third resistor and the capacitance value of the third capacitor of the first switch circuit in the second switch module.

5. The driving circuit according to claim 4, characterized in that: In the same signal frame, the rising edge of the waveform of the switching signal output by the first switching circuit in the first switching module has a first slope, and the rising edge of the waveform of the switching signal output by the first switching circuit in the second switching module has a second slope, and the first slope and the second slope are different.

6. The driving circuit according to claim 4, characterized in that: The resistance value of the third resistor of the first switch circuit in the first switch module is smaller than the resistance value of the third resistor of the first switch circuit in the second switch module; or, The capacitance of the third capacitor of the first switch circuit in the first switch module is smaller than the capacitance of the third capacitor of the first switch circuit in the second switch module.

7. The driving circuit according to claim 1, characterized in that: The plurality of light-emitting elements at least include a first light-emitting element and a second light-emitting element, and an anode of the first light-emitting element and an anode of the second light-emitting element are both connected to the third internal node of the same first switch circuit; The driving module at least includes a first driving output terminal and a second driving output terminal, the cathode of the first light-emitting element is connected to the first driving output terminal, and the cathode of the second light-emitting element is connected to the second driving output terminal. In a signal frame, the driving signal output by the first driving output terminal is different from the driving signal output by the second driving output terminal.

8. The driving circuit according to claim 1, characterized in that: The first transistor is one of an N-type transistor and a P-type transistor, and the second transistor and the third transistor are the other of the N-type transistor and the P-type transistor.

9. The driving circuit according to any one of claims 1 to 8, characterized in that: The control module comprises a plurality of switch output terminals, one of the switch output terminals being connected to one of the switch circuits in each of the switch modules; Among the plurality of switch modules, the switching signals output by the switch circuits connected to the same switch output terminal have the same frequency.

10. The driving circuit according to claim 9, characterized in that: In each of the switch modules, the switching signals output by the multiple switch circuits in the same scanning frame have the same frequency, and the switching signals output by the multiple switch circuits in two adjacent scanning frames have different frequencies.

11. The driving circuit according to claim 9, characterized in that: In each of the switch modules, the frequencies of the switch signals output by two adjacent switch circuits are different.

12. A display device, characterized in that: The display device comprises the driving circuit according to any one of claims 1 to 11.

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