Semiconductor test structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor test structure and a preparation method thereof, and belongs to the technical field of semiconductors. In the semiconductor test structure, the conductive structure comprises a conductive layer on a substrate and at least one conductive plug between the conductive layer and the substrate, and the conductive layer is electrically connected to the substrate through the at least one conductive plug; a plurality of interlayer conductive strips extend along a first direction, are arranged at intervals along a second direction, and are circumferentially surrounded by the conductive layer; and an isolation side wall is arranged between the interlayer conductive strips and the conductive layer. At least the electrical defects of the presence of capacitance in the chip can be detected in time and conveniently.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor testing structure and its fabrication method. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] For semiconductor chips, as device size shrinks and storage capacity and density continue to increase, the probability of leakage paths between adjacent capacitors increases, posing a challenge to the detection of electrical defects in capacitors. Summary of the Invention

[0004] Based on this, this disclosure provides a semiconductor test structure and its fabrication method, which can at least detect the presence of electrical defects in the capacitor in a chip in a timely and convenient manner.

[0005] To address the aforementioned technical problems and other issues, according to some embodiments, a first aspect of this disclosure provides a semiconductor test structure disposed on a substrate. The semiconductor test structure includes a conductive structure, isolation sidewalls, and multiple interlayer conductive strips. The conductive structure includes a conductive layer located on the substrate and at least one conductive plug located between the conductive layer and the substrate. The conductive layer is electrically connected to the substrate via the at least one conductive plug. The multiple interlayer conductive strips extend along a first direction, are spaced apart along a second direction, and circumferentially surround the conductive layer. Isolation sidewalls are also disposed between the interlayer conductive strips and the conductive layer.

[0006] In some embodiments, the semiconductor test structure further includes an interlayer dielectric layer located between the substrate and the conductive layer, wherein at least one conductive plug extends through the interlayer dielectric layer and into the substrate in a direction perpendicular to the substrate.

[0007] In some embodiments, multiple conductive plugs are spaced apart around multiple interlayer conductive strips.

[0008] In some embodiments, the conductive layer includes a first sub-conductive layer and a second sub-conductive layer. The first sub-conductive layer extends along a first direction and is alternately arranged with interlayer conductive strips along a second direction. The second sub-conductive layer is disposed around the first sub-conductive layer and is electrically connected to the substrate via at least one conductive plug.

[0009] In some embodiments, the semiconductor test structure includes a plurality of first capacitors and a plurality of second capacitors; a row of first capacitors spaced apart along a first direction is disposed on a first sub-conductive layer; and a row of second capacitors spaced apart along the first direction is disposed on an interlayer conductive strip.

[0010] In some embodiments, the substrate includes an array region and a diced region, the diced region being located on the periphery of the array region and the semiconductor test structure being located within the diced region.

[0011] In some embodiments, the array region includes multiple bit line structures, multiple node contact structures, and multiple storage capacitors. The multiple bit line structures are disposed on the substrate at intervals. The multiple node contact structures are disposed on the substrate and alternate with the bit line structures. The multiple storage capacitors are located on the node contact structures and are electrically connected to the substrate.

[0012] In some embodiments, the node contact structure includes a capacitive contact node and an interconnect structure located between the capacitive contact node and the substrate; the capacitive contact node is electrically connected to the substrate via the interconnect structure.

[0013] According to some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor test structure, comprising:

[0014] A substrate is provided, and an initial conductive structure is formed on the substrate. The initial conductive structure includes an initial conductive layer on the substrate and at least one conductive plug between the initial conductive layer and the substrate. The initial conductive layer is electrically connected to the substrate via the at least one conductive plug.

[0015] An initial conductive layer is patterned to obtain a conductive layer and multiple interlayer conductive strips; wherein, the multiple interlayer conductive strips extend along a first direction, are spaced apart along a second direction, and surround the conductive layer circumferentially; the conductive layer and at least one conductive plug are used to jointly constitute a conductive structure; an isolation sidewall is also formed between the interlayer conductive strips and the conductive layer.

[0016] In some embodiments, the substrate includes an array region and a diced region located around the array region, and an initial conductive layer is located in the array region and the diced region; patterning the initial conductive layer includes:

[0017] The initial conductive layer on the array region is patterned twice to form multiple spaced capacitor contact nodes on the substrate of the array region.

[0018] The initial conductive layer is patterned on the cutting area to form a conductive layer and multiple interlayer conductive strips within the cutting area; wherein the initial patterning and any one of the two patterning processes share the same photomask. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a top view schematic diagram of a chip including a semiconductor test structure according to an embodiment of the present disclosure;

[0021] Figure 2a for Figure 1 A top view of the first semiconductor test structure;

[0022] Figure 2b In one embodiment, the semiconductor test structure along... Figure 2a Schematic diagram of the longitudinal section structure obtained in the PP' direction;

[0023] Figure 3 for Figure 1 A top view of the second semiconductor test structure;

[0024] Figure 4 This is a schematic flowchart of a semiconductor test structure fabrication method according to an embodiment of the present disclosure;

[0025] Figure 5 This is a top view schematic diagram of the active region, bit line and word line in the array region of an embodiment of the present disclosure;

[0026] Figures 6-16 , Figures 17a-17b This is a schematic diagram of the longitudinal section of the array region and the cutting region of the structure obtained in different process steps in the semiconductor test structure fabrication method of this disclosure; wherein, the AA' direction is... Figure 5 The directions shown are AA' and BB'. Figure 5 The direction of BB' shown;

[0027] Figures 18-21 This is a top view schematic diagram of the photomask during the two patterning processes in different embodiments to form the node contact structure in the array region.

[0028] Figure 22 This is a schematic diagram of defect detection in a semiconductor test structure according to an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100, Substrate; 1000, Semiconductor Test Structure; 1000a, First Semiconductor Test Structure; 1000b, Second Semiconductor Test Structure; 10, Cutting Region; 20, Array Region; 21, Node Contact Structure; 11, Conductive Structure; 12, Interlayer Conductive Pillar; 111, Conductive Layer; 1111, First Sub-Conductive Layer; 1112, Second Sub-Conductive Layer; 112, Conductive Plug; 121, Interlayer Conductive Strip; 122, Isolation Sidewall; 13, Interlayer Dielectric Layer; 101, Active Region; 102, Trench Isolation Structure; 14. Conductive pad; 22. Word line structure; 23. Bit line structure; 201. Node contact window; 211. Interconnect structure; 212. Capacitor contact node; 203a / 203b. Isolation pillar; 241. Dielectric material layer; 24 / 24a / 24b. First dielectric layer; 11a. Initial conductive structure; 111'. Initial conductive layer; 25. Protective sidewall; 26. Organic dielectric layer; 1121. Plug trench; SN1. First capacitor; SN2. Second capacitor; 18. Storage node; 19a / 19b. Groove. Detailed Implementation

[0031] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0037] Please note that the mutual insulation between the two components described in this disclosure includes, but is not limited to, the presence of one or more of an insulating material, insulating fumes, or gaps between them. The vertical substrate is the top surface of the vertical substrate.

[0038] This disclosure aims to provide a semiconductor test structure and its fabrication method, which can at least detect the presence of electrical defects in capacitors in a chip in a timely and convenient manner, thereby effectively improving the chip yield.

[0039] Please refer to Figure 1 A semiconductor test structure is disposed on a substrate 100, the substrate 100 including an array region 20 and a dicing region 10 located around the array region 20, and the semiconductor test structure 1000 is located in the dicing region 10.

[0040] Please refer to Figure 2a , Figure 2b In some embodiments, a semiconductor test structure 1000 includes a conductive structure 11, an isolation sidewall 122, and a plurality of interlayer conductive strips 121. The conductive structure 11 includes a conductive layer 111 located on a substrate 100, and at least one conductive plug 112 located between the conductive layer 111 and the substrate 100. The conductive layer 111 is electrically connected to the substrate 100 via the at least one conductive plug 112. The plurality of interlayer conductive strips 121 extend along a first direction (e.g., the om direction), are spaced apart along a second direction (e.g., the on direction), and surround the conductive layer 111 circumferentially. An isolation sidewall 122 is also provided between the interlayer conductive strips 121 and the conductive layer 111.

[0041] It should be noted that, Figure 2b In one embodiment, the semiconductor test structure along... Figure 2a The schematic diagram of the longitudinal cross-section structure obtained in the PP' direction is intended to illustrate the specific implementation principle of the embodiments of this disclosure by means of an exemplary implementable structure of a semiconductor test structure.

[0042] As an example, please continue to refer to Figure 2bThe semiconductor test structure 1000 further includes an interlayer dielectric layer 13, a portion of which is located between the substrate 100 and the conductive layer 111, and a portion of which is located between the substrate 100 and the interlayer conductive pillar 12. At least one conductive plug 112 extends through the interlayer dielectric layer 13 and into the substrate 100 along a direction perpendicular to the substrate 100. For example, the conductive plug 112 extends into an active region 101 within the substrate 100 along a direction perpendicular to the substrate 100. A plurality of trench isolation structures 102 are formed in the substrate 100, defining a plurality of active regions 101, which are arranged in a spaced array.

[0043] As an example, please continue to refer to Figure 2a Multiple conductive plugs 112 are spaced apart around the multiple interlayer conductive strips 121 to increase the conductivity between the conductive layer 111 and the active region 101, reduce the connection impedance, and prevent the conductive plugs 112 from adversely affecting the multiple interlayer conductive strips 121. The conductive layer 111 includes a first sub-conductive layer 1111 and a second sub-conductive layer 1112. The first sub-conductive layer 1111 extends along a first direction and is alternately arranged with the interlayer conductive strips 121 along a second direction. The second sub-conductive layer 1112 is disposed around the first sub-conductive layer 1111 and is electrically connected to the substrate 100 via at least one conductive plug 112.

[0044] As an example, please continue to refer to Figure 2a The semiconductor test structure 1000 includes multiple first capacitors SN1 and multiple second capacitors SN2; a row of first capacitors SN1 are arranged at intervals along a first direction on the first sub-conductive layer 1111; a row of second capacitors SN2 are arranged at intervals along the first direction on the interlayer conductive strip 121. For example, please refer to [reference needed]. Figure 2b The semiconductor test structure also includes a conductive pad 14, through which the conductive plug 112 is electrically connected to the active region 101 in the substrate 100 via a conductive pad 14 below it. The conductive pad 14 can increase the conductivity between the conductive layer 111 and the active region 101 and reduce the connection impedance.

[0045] As an example, please continue to refer to Figures 1-3 A test structure includes a first semiconductor test structure 1000a, an array region 20, and a second semiconductor test structure 1000b; both the first semiconductor test structure 1000a and the second semiconductor test structure 1000b include the semiconductor test structure 1000 in any embodiment of this disclosure.

[0046] In some embodiments, a defect detection method includes:

[0047] Step S300: Provide a test structure according to any embodiment of this disclosure;

[0048] Step S400: Use an electron beam defect detection device to inspect the aforementioned test structure and obtain inspection information;

[0049] Step S500: Determine whether there are electrical defects in the capacitors in the array area within the chip based on the detection information.

[0050] In some embodiments, the detection information includes a voltage contrast image; step 500, determining whether there are electrical defects in the capacitors of the array region within the chip based on the detection information, includes:

[0051] Step S501: Compare the voltage contrast image with a preset standard image;

[0052] Step S502: Based on the comparison results, determine whether the capacitors in the array area have electrical defects, locate the position of the electrical defects, and determine the type of electrical defects.

[0053] It should be understood that electron beam defect detection equipment uses a low-energy electron beam as the incident source during the detection process. When the electron beam strikes the surface of the semiconductor test structure, it excites secondary electrons, back-emitter electrons, and penetrating electrons. The collected image is then presented by an image processing system, and this image is the voltage contrast image. In the voltage contrast image, areas with a higher amount of secondary electrons can be observed as a bright field, while areas with a lower amount of secondary electrons can be observed as a dark field. Therefore, the distribution of bright / dark fields can be used as a basis for defect detection.

[0054] Furthermore, by comparing the voltage contrast image of the semiconductor test structure detected by the electron beam defect detection equipment with a preset standard image, it is possible to determine whether the capacitor has an electrical defect and to locate the position of the electrical defect. Specifically, this is done by comparing the distribution of bright / dark fields in the voltage contrast image and the preset standard image to determine whether the capacitor has an electrical defect and to locate the position of the electrical defect. When the distribution of bright / dark fields in the voltage contrast image and the preset standard image are the same, it can be determined that the capacitor has no electrical defect; when the distribution of bright / dark fields in the voltage contrast image and the preset standard image are different, it can be determined that the capacitor has an electrical defect. Therefore, based on the position of the capacitor with an electrical defect in the semiconductor test structure, the position of the electrical defect in the array region can be determined.

[0055] It should be understood that the device structure in the substrate of the semiconductor test structure can be equivalent to a MOS transistor. The capacitor located above the interlayer conductive strip is in a floating state. When the electron beam defect detection equipment emits an electron beam onto the floating capacitor, the charge in the capacitor is difficult to transfer, resulting in a large accumulation of charge and secondary electrons, which appears as a bright field at the corresponding position in the preset standard image. On the other hand, the capacitor located above the conductive layer is grounded. When the electron beam defect detection equipment emits an electron beam onto the grounded capacitor, the charge in the capacitor transfers, resulting in less charge accumulation and less secondary electrons, which appears as a dark field at the corresponding position in the preset standard image.

[0056] In some embodiments, the categories of electrical defects include open-circuit defects and / or short-circuit defects.

[0057] As an example, please continue to refer to Figure 2a or Figure 3 Taking capacitors as an example, the principle of determining specific electrical defect categories will be illustrated. Under normal circumstances, the first capacitors SN1 located on the first sub-conductive layer 1111 are all grounded, and the second capacitors SN2 located on the interlayer conductive strip 121 are all in a floating state. Therefore, the position corresponding to the first capacitor SN1 in the preset standard image presents a dark field, and the position corresponding to the floating second capacitor SN2 presents a bright field. The bright field and dark field are arranged alternately.

[0058] In some embodiments, the comparison result includes a comparison result of the bright / dark field distribution in the voltage contrast image and a preset standard image; step S502, determining whether the capacitors in the array region have electrical defects based on the comparison result, includes:

[0059] Step S5021: Based on the comparison results of bright field / dark field distribution, determine whether the capacitors in the array area have electrical defects, locate the position of the electrical defects, and determine the type of electrical defects.

[0060] As an example, please continue to refer to Figure 2a , Figure 2a In the preset standard image corresponding to the first semiconductor test structure 1000a, the position corresponding to the first capacitor SN1 is dark, and the position corresponding to the floating second capacitor SN2 is bright. The bright and dark fields are arranged alternately. The positions corresponding to adjacent capacitors along the first direction are all either bright or dark. Specifically, the positions corresponding to the second capacitor SN2 located on the interlayer conductive strip 121 are all bright, and the positions corresponding to the first capacitor SN1 located on the first sub-conductive layer 1111 are all dark. The voltage contrast image of the first semiconductor test structure 1000a is compared with the bright / dark field distribution in the corresponding preset standard image. Based on the comparison results, it is determined whether the capacitors in the array region have electrical defects. If... Figure 2aThe bright field at the location corresponding to the first capacitor SN1 marked in the image indicates an electrical defect. Figure 2a The dark field at the location corresponding to the second capacitor SN2 marked in the image indicates an electrical defect.

[0061] As an example, please continue to refer to Figure 3 , Figure 3 In the preset standard image corresponding to the second semiconductor test structure 1000b, the position corresponding to the first capacitor SN1 is dark, and the position corresponding to the floating second capacitor SN2 is bright. The bright and dark fields are alternately arranged. Along the second direction, the positions corresponding to adjacent capacitors are either bright or dark. Specifically, the positions corresponding to the second capacitor SN2 located on the interlayer conductive strip 121 are all bright, and the positions corresponding to the first capacitor located on the first sub-conductive layer 1111 are all dark. The voltage contrast image of the detected second semiconductor test structure 1000b is compared with the bright / dark field distribution in the corresponding preset standard image. Based on the comparison results, it is determined whether the capacitors in the array region have electrical defects. It can be determined that capacitors at different positions in the comparison results have electrical defects. Figure 3 The bright field at the location corresponding to the first capacitor SN1 marked in the image indicates a circuit defect. Figure 3 The dark field at the location corresponding to the second capacitor SN2 marked in the image indicates a circuit defect.

[0062] Furthermore, Figure 2a and Figure 3 By comparing the results at the same location, it can be further determined whether there are electrical defects in the capacitor at the same location in the corresponding array region. For details, please refer to [link to relevant documentation]. Figure 22 An electrical defect Q1 was found in the left cutting area 10, and an electrical defect Q2 was found in the right cutting area 10. Based on the locations of electrical defects Q1 and Q2, it can be deduced that an electrical defect may also occur at the same location Q3 in array area 20. This method is used to locate the electrical defects and improve the accuracy of their location.

[0063] Please refer to Figure 4 In some embodiments, a method for fabricating a semiconductor test structure includes:

[0064] Step S20: Provide a substrate and form an initial conductive structure on the substrate. The initial conductive structure includes an initial conductive layer on the substrate and at least one conductive plug between the initial conductive layer and the substrate. The initial conductive layer is electrically connected to the substrate via the at least one conductive plug.

[0065] Step S40: Pattern the initial conductive layer to obtain a conductive layer and multiple interlayer conductive strips; wherein, the multiple interlayer conductive strips extend along a first direction, are spaced apart along a second direction, and surround the conductive layer circumferentially; the conductive layer and at least one conductive plug are used to jointly constitute a conductive structure; an isolation sidewall is also formed between the interlayer conductive strips and the conductive layer.

[0066] For example, please refer to Figure 5 , Figure 6 The substrate 100 provided in step S20 includes a trench isolation structure 102 and active regions 101 arranged in a spaced array defined by the trench isolation structure 102. The substrate 100 may be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 100 may be a single-layer structure or a multi-layer structure. In some embodiments, a patterning process may be used to form shallow trenches in the substrate 100, and then an isolation material may be filled in the shallow trenches to form the trench isolation structure 102; for example, the above patterning process includes, but is not limited to, self-aligned double patterning (SADP) process, self-aligned quadruple patterning (SAQP) process, etc.

[0067] As an example, please continue to refer to Figure 5 The array region 20 includes multiple word line structures 22 located within the substrate 100 and multiple bit line structures 23 located on the substrate; wherein, the multiple word line structures 22 and multiple bit line structures 23 can jointly define multiple node contact windows (not shown) corresponding to multiple node contact structures (not shown); the node contact structures are located within the corresponding node contact windows and are electrically connected to the active region 101 below the node contact windows, so that capacitors or storage nodes are electrically connected to the active region 101 via the node contact structures below them.

[0068] For example, please refer to Figure 6 A spin-on dielectric layer is deposited on the array region 20 and the cutting region 10. The spin-on dielectric layer (SOD) covers multiple bit line structures 23 and fills the gaps between adjacent bit line structures 23. The top surface of the spin-on dielectric layer SOD is planarized. The planarization process may include, but is not limited to, at least one of chemical mechanical polishing, dry etching, and planarization processes.

[0069] For example, please refer to Figure 7 After a hard mask layer and a photoresist layer are sequentially formed on the spin-coated dielectric layer, a series of processes such as photolithography and etching are performed to obtain spaced isolation pillars 203a in the array region 20 and spaced isolation pillars 203b in the cutting region 10.

[0070] For example, please refer to Figures 8-9A dielectric material layer 241 is deposited on the sidewalls and top surface of the isolation pillars 203a and 203b. The dielectric material layer 241 fills the gap between adjacent isolation pillars 203a and the gap between adjacent isolation pillars 203b. Then, the top surface of the dielectric material layer 241 is planarized to obtain the first dielectric layer 24. Then, a mask layer mask1 is formed on the top surface of the first dielectric layer 24 in the cutting area 10.

[0071] For example, a plasma-enhanced deposition process can be used to form a dielectric material layer 241, which may include plasma-enhanced silicon nitride.

[0072] For example, please refer to Figure 10 The first dielectric layer 24 in the array region 20 is removed to obtain the spaced bit line structure 23 and the spaced first dielectric layer 24a. The first dielectric layer 24a can be located above an embedded word line WL, so that the first dielectric layer 24a and the bit line structure 23 together define multiple node contact windows 201 arranged in a spaced array. The first dielectric layer 24b located in the cutting region 10 and the isolation pillar 203b together constitute the interlayer dielectric layer 13.

[0073] For example, please refer to Figure 11 After removing the mask layer mask1 of the dicing region 10, a conductive material is deposited on the resulting semiconductor structure to obtain a conductive material layer 2111 whose top surface is higher than the top surface of the bit line structure 23 and the top surface of the interlayer dielectric layer 13. The material of the conductive material layer 2111 can be selected from single crystal silicon, doped polycrystalline silicon, germanium silicon, and combinations thereof.

[0074] For example, please refer to Figure 12 The conductive material layer 2111 is then etched back. At this point, the remaining conductive material layer 2111 in the array region 20 forms an interconnect structure 211 and exposes the node contact windows 201 arranged in a spaced array. The top surface of the interconnect structure 211 can be flush with the top surface of the interlayer dielectric layer 13.

[0075] For example, please refer to Figure 13 At least a protective sidewall 25 is formed on the outer sidewall of the bit line structure 23 to seal and protect the bit line BL inside the bit line structure 23, so as to avoid the generation of a current leakage path between the bit line BL and the capacitor contact node formed subsequently.

[0076] For example, please refer to Figures 14-15 ,At Figure 13 Organic dielectric layer 26 and photomask layer PR are deposited sequentially on the top surface and sidewalls of the structure shown. The organic dielectric layer 26 and interlayer dielectric layer 13 located in the cutting region 10 are etched using the photomask layer PR as a mask to obtain the plug trench 1121 that exposes the active region 101 in the cutting region 10. The remaining organic dielectric layer 26 and photomask layer PR are removed.

[0077] For example, please refer to Figures 16-17b Conductive pads 14 are formed within node contact windows 201 and plug trenches 1121 in the array region 20. Capacitive contact nodes 212 are then formed within node contact windows 201 in the array region 20, and conductive plugs 112 are formed within plug trenches 1121. The conductive plugs 112 are electrically connected to the active region 101 in the substrate 100 via a conductive pad 14 beneath them. The conductive pads 14 increase the conductivity between the conductive layer 111 and the active region 101, reducing the connection impedance. The material of the conductive pads 14 is selected from titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, or metal silicides and combinations thereof. The planarization process may include, but is not limited to, at least one of chemical mechanical polishing, dry etching, and planarization processes.

[0078] For example, please refer to Figures 16-17b After forming the conductive pads 14, a conductive material can be formed using a deposition process to obtain an initial conductive layer 111' whose top surface is higher than the top surface of the interlayer dielectric layer 13. The initial conductive layer 111' and at least one conductive plug 112 located between the initial conductive layer 111' and the substrate 100 are used to jointly constitute the initial conductive structure 11a. The initial conductive layer 111' is electrically connected to the substrate 100 via at least one conductive plug 112. The deposition process may include, but is not limited to, at least one of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0079] As an example, please continue to refer to Figure 1 , Figure 17a , Figure 17b , Figures 18-19 The substrate 100 includes an array region 20 and a dicing region 10 located around the array region 20. An initial conductive layer 111' is located in the array region 20 and the dicing region 10. Patterning the initial conductive layer 111' includes: providing a photomask, patterning the initial conductive layer 111' located in the array region 20 and the dicing region 10, and then patterning the initial conductive layer 111' located in the array region 20 again. Thus, the array region 20 is patterned twice, while the dicing region 10 is patterned once each. The first patterning and either of the two patternings share the same photomask.

[0080] In other embodiments, the initial conductive layer 111' located in the array region 20 may be patterned first, and then the initial conductive layer 111' located in the array region 20 and the dicing region 10 may be patterned simultaneously while a photomask is provided.

[0081] In other embodiments, please continue to refer to Figure 1 , Figure 17a , Figure 17b , Figures 20-21 The substrate 100 includes an array region 20 and a dicing region 10 located around the array region 20. An initial conductive layer 111' is located in the array region 20 and the dicing region 10. Patterning the initial conductive layer 111' includes: providing a photomask to pattern the initial conductive layer 111' located in the array region 20 and the dicing region 10 on one side of the array region 20; and patterning the initial conductive layer 111' located in the array region 20 and the dicing region 10 on the other side of the array region 20. Thus, the array region 20 is patterned twice, while the dicing regions 10 on both sides are patterned once each.

[0082] As an example, please continue to refer to Figures 17a-17b A portion of the initial conductive layer 111' in the array region 20 and the dicing region 10 is removed to form a storage node 18 in the array region 20 and a groove 19a located between the storage nodes 18. A first sub-conductive layer 1111 and an interlayer conductive layer 121 are formed in the dicing region 10, and a groove 19b is located between the first sub-conductive layer 1111 and the interlayer conductive layer 121. An isolation sidewall 122 is formed in the array region 20 and the dicing region 10, filling the grooves 19a and 19b. The isolation sidewall 122 is selected from silicon oxide, silicon nitride, or other insulating materials. Finally, a storage capacitor is formed on the storage node 18, a first capacitor is formed on the first sub-conductive layer 1111, and a second capacitor is formed on the interlayer conductive layer 121.

[0083] For chip manufacturing, to detect electrical defects in the capacitors, it's generally necessary to arrange the capacitors in an array region in a regular pattern to easily pinpoint the location of capacitors with electrical defects. During the fabrication of the capacitors in the array region, capacitors corresponding to those in the array region and arranged in a regular array can be fabricated in a cutting area surrounding the array region. The presence of electrical defects in the array region can then be determined based on the detection electrical signals from the capacitors in the cutting area. Since the capacitors in the cutting area can be fabricated simultaneously during the fabrication of the array region, without adding extra process flow or photomask design costs, this method offers excellent practicality and promising application prospects.

[0084] It should be understood that, although Figure 4The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, although... Figure 4 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0085] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0086] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above embodiments are merely illustrative of several implementation methods of this disclosure, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A semiconductor test structure disposed on a substrate, wherein, The semiconductor testing structure includes: A conductive structure includes a conductive layer on the substrate and at least one conductive plug located between the conductive layer and the substrate; Multiple interlayer conductive strips extend along a first direction, are spaced apart along a second direction, and surround the conductive layer circumferentially. An isolation sidewall is also provided between the interlayer conductive strips and the conductive layer. The conductive layer includes: Multiple first sub-conductive layers extend along the first direction and are alternately arranged with the interlayer conductive strips along the second direction; A second sub-conductive layer is disposed around the first sub-conductive layer and is in direct contact with the first sub-conductive layer. The second sub-conductive layer is electrically connected to the substrate via at least one of the conductive plugs. Multiple first capacitors, with a row of first capacitors arranged at intervals along the first direction on the first sub-conductive layer; Multiple second capacitors are provided, and a row of second capacitors are arranged at intervals along the first direction on the interlayer conductive strip, and the first capacitors and second capacitors are arranged alternately along the second direction.

2. The semiconductor test structure according to claim 1, wherein, Also includes: An interlayer dielectric layer is located between the substrate and the conductive layer, wherein the at least one conductive plug extends through the interlayer dielectric layer and into the substrate in a direction perpendicular to the substrate.

3. The semiconductor test structure according to claim 1, wherein, Multiple conductive plugs are spaced apart around the periphery of the multiple interlayer conductive strips.

4. The semiconductor test structure according to claim 1, wherein, Also includes: A conductive pad, wherein the conductive plug is electrically connected to an active region within the substrate via a conductive pad below it.

5. The semiconductor test structure according to claim 4, wherein, The isolation sidewall is located on the sidewall of the interlayer conductive strip and surrounds the interlayer conductive strip in the circumferential direction.

6. The semiconductor test structure according to claim 1, wherein, The substrate includes: Array area; The dicing region is located on the periphery of the array region, and the semiconductor test structure is located within the dicing region.

7. The semiconductor test structure according to claim 6, wherein, The array region includes: Multiple bit line structures are disposed on the substrate at intervals; Multiple node contact structures are disposed on the substrate and alternately disposed with the bit line structure; Multiple storage capacitors are located on the node contact structure and are electrically connected to the substrate.

8. The semiconductor test structure according to claim 7, wherein, The node contact structure includes a capacitive contact node and an interconnect structure located between the capacitive contact node and the substrate; The capacitor contact node is electrically connected to the substrate via the interconnect structure.

9. A method for fabricating a semiconductor test structure, wherein, include: A substrate is provided, on which an initial conductive structure is formed, the initial conductive structure including an initial conductive layer on the substrate and at least one conductive plug between the initial conductive layer and the substrate, the initial conductive layer being electrically connected to the substrate via the at least one conductive plug; The initial conductive layer is patterned to obtain a conductive layer and a plurality of interlayer conductive strips; wherein the plurality of interlayer conductive strips extend along a first direction, are spaced apart along a second direction, and circumferentially surround the conductive layer; the conductive layer and the at least one conductive plug are used to jointly constitute a conductive structure; an isolation sidewall is also formed between the interlayer conductive strips and the conductive layer; the conductive layer includes a plurality of first sub-conductive layers and a second sub-conductive layer, the plurality of first sub-conductive layers extend along the first direction and are alternately arranged with the interlayer conductive strips along the second direction; the second sub-conductive layer is disposed around the first sub-conductive layer and is in direct contact with the first sub-conductive layer, and the second sub-conductive layer is electrically connected to the substrate via at least one of the conductive plugs; During the process of forming a plurality of first capacitors spaced apart along the first direction on the conductive layer, a plurality of second capacitors spaced apart along the first direction are formed on the interlayer conductive strip, and the first capacitors and the second capacitors are alternately arranged along the second direction.

10. The method for fabricating a semiconductor test structure according to claim 9, wherein, The substrate includes an array region and a diced region located around the array region, and the initial conductive layer is located in the array region and the diced region; The patterning of the initial conductive layer includes: The initial conductive layer located on the array region is patterned twice to form a plurality of spaced-apart capacitive contact nodes on the substrate of the array region; The initial conductive layer located on the cutting area is patterned in one step to form the conductive layer and the plurality of interlayer conductive strips within the cutting area; wherein the first patterning and any one of the two patternings share the same photomask.

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